LINER LT8601 42v triple monolithic synchronous step-down regulator Datasheet

LT8601
42V Triple Monolithic
Synchronous Step-Down Regulator
Features
Description
Flexible Power Supply System Providing Three
Outputs Over a Wide Input Voltage Range
nn Two High Voltage Synchronous Buck Regulators
nn 3V to 42V Input Voltage Range
nn Output Currents Up to 2.5A and 1.5A
nn High Efficiency Up to 93%
nn One Low Voltage Synchronous Buck Regulator
nn 2.6V to 5.5V Input Voltage Range
nn Output Current Up to 1.8A and 95% Efficiency
nn Resistor Programmable and Synchronizable
from 250kHz to 2.2MHz Switching Frequency
nn Low Ripple Burst Mode® Operation
nn 30µA I at 12V to 3.3V
Q
IN
OUT2
nn Output Ripple < 15mV
nn Programmable Power-On Reset
nn Power Good Indicators
nn 2-Phase Clock Reduces Input Current Ripple
nn Available in Thermally Enhanced 40-Lead QFN
(6mm × 6mm) Package
The LT®8601 is a triple channel, current mode, monolithic
buck switching regulator with a programmable power-on
reset. All regulators are synchronized to a single oscillator
with an adjustable frequency from 250kHz to 2.2MHz. The
LT8601 can be configured for micropower Burst Mode or
pulse-skipping operation at light load. Micropower operation results in quiescent current of 30µA with all three
regulators operating as shown in the application below
with no load applied.
nn
The high voltage channels are synchronous buck regulators that operate from an input of 3.0V to 42V. The output
currents are up to 1.5A (OUT1) and 2.5A (OUT2). The
low voltage channel operates from an input of 2.6V to
5.5V. Internal synchronous power switches provide high
efficiency with output currents up to 1.8A. The LT8601
uses a 2-phase clock with channel 1 operating 180° from
channels 2 and 3 to reduce input ripple current on both
HV and LV inputs. All channels have cycle-by-cycle current limit, providing protection against shorted outputs.
Thermal shutdown provides additional protection.
Applications
The LT8601 is available in a 40-lead 6mm × 6mm QFN
package.
Automotive Systems
nn Distributed Supply Regulation
nn Industrial Controls and Power Supplies
nn
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Analog Devices, Inc. All other trademarks are the property of their respective owners.
Typical Application
Automotive Input Stepped Down to 5V, 3.3V and 1.8V Outputs at 2MHz
BST1
PVIN2
SW1
FB1
PVIN1 LT8601
EN/UVLO
3.3μH
22μF
POREN
3
BST2
OUT2
3.3V, 1A*
47μF
INTVCC
CPOR
2
TRKSS1, 2
SW3
FB3
RT
SYNC
100
90
1.8
90
1.6
80
1.4
70
0.7
60
0.6
50
0.5
EFFICIENCY
1μH
OUT3
1.8V, 1.8A
22μF
GND
8601 TA01a
*IMAX = 2.5A – IPVIN3 – IBIAS
VIN = 12V
70
60
1.2
50
1.0
40
0.8
POWER
LOSS
30
0.6
0.9
EFFICIENCY
40
0.8
0.4
POWER
LOSS
30
0.3
20
0.4
20
0.2
10
fSW = 1MHz 0.2
fSW = 2MHz
0
1.2
1.5
10
fSW = 1MHz 0.1
fSW = 2MHz
0
0.6
0.9
1.2
1.5
1.8
LOAD CURRENT (A)
0
0
0.3
0.6
0.9
LOAD CURRENT (A)
8601 TA01b
0
0
0.3
POWER LOSS (W)
SW2
FB2
BIAS
PVIN3
1μH
1.0
2.0
POWER LOSS (W)
PG1-3
LV Channel Efficiency, VOUT3 = 1.8V
100
80
RST
RUN3
OUT2
HV Channel Efficiency, VOUT1 = 5V
OUT1
5V, 1.5A
EFFICIENCY (%)
VIN
EFFICIENCY (%)
IN
6V TO 24V,
TRANSIENTS
TO 42V
8601 TA01c
8601fa
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1
LT8601
Pin Configuration
(Note 1)
CPOR
RST
SYNC
GND
GND
NC
GND
POREN
TOP VIEW
GND
Supply Voltages
VIN, PVIN1,2............................................. –0.3V to 42V
PVIN3........................................................ –0.3V to 6V
PG1-3, SYNC, TRKSS1-2,
RUN3, RST Voltages....................................................6V
RT, FB1-3, CPOR, POREN Voltages...........................3.6V
EN/UVLO Voltage.......................................................42V
BIAS Voltage............................................... –0.3V to 15V
Operating Junction Temperature (Notes 2 and 3)
LT8601E.............................................. –40°C to 125°C
LT8601I............................................... –40°C to 125°C
Storage Temperature Range............... –65°C to 150°C
PVIN1
Absolute Maximum Ratings
40 39 38 37 36 35 34 33 32 31
PG1 1
30 GND
GND 2
29 RT
SW1 3
28 INTVCC
BST1 4
27 GND
BST2 5
26 FB1
41
GND
SW2 6
25 FB2
SW2 7
24 FB3
GND 8
23 VIN
GND 9
22 EN/UVLO
BIAS 10
21 TRKSS1
TRKSS2
NC
RUN3
PVIN3
GND
SW3
PVIN2
GND
PG3
PG2
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
θJA = 33°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
Order Information
http://www.linear.com/product/LT8601#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT8601EUJ#PBF
LT8601EUJ#TRPBF
LT8601
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
LT8601IUJ#PBF
LT8601IUJ#TRPBF
LT8601
40-Lead (6mm × 6mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
8601fa
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LT8601
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = 3.3V unless otherwise
noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Operating Voltage
l
2.7
3
V
Minimum Operating Voltage to Start
l
3.1
3.5
V
1
VIN Quiescent Current, Shutdown
EN/UVLO = 0.4V
0.1
VIN Quiescent Current, Operating
All Channels Active, No Load (Note 4)
All Channels Active,100µA on VOUT2 (Note 4)
30
70
EN/UVLO Threshold
EN/UVLO Rising
EN/UVLO Falling
EN/UVLO Input Current
EN/UVLO = 1.2V, VIN = 42V
l
l
1.15
1.0
1.2
1.15
−40
µA
µA
µA
1.25
1.2
V
V
40
nA
Oscillator
Switching Frequency
RT = 28.7k
l
1.8
2
2.2
MHz
RT = 254k
l
0.225
0.25
0.275
MHz
0.25
2.2
MHz
0.3
V
100
nA
SYNC Input Frequency Range
l
SYNC Input Voltage Low
l
SYNC Input Voltage High
l
SYNC Input Current
1.2
V
−100
Channel 1
Feedback Voltage
l
0.988
Input Current FB1
l
−100
FB1 Voltage Line Regulation
VIN = 3V to 42V
SW1 Peak Current Limit
VIN = PVIN1 = PVIN2 = 6V
2.3
SW1 Leakage Current
1
1.012
V
100
nA
0.002
0.01
%/V
2.7
3.0
A
0.1
1
µA
SW1 Top On Resistance
ISW1 = 1A
240
mΩ
SW1 Bottom On Resistance
ISW1 = 1A
170
mΩ
Lower FB1 Power Good Threshold
Percentage of VFB1
l
89
92
95
%
Upper FB1 Power Good Threshold
Percentage of VFB1
l
105
108
111
%
0.13
0.3
V
30
μA
3.1
μA
PG1 Output Voltage Low
IPG1 = –350μA
l
PG1 Leakage Current
PG1 = 5V, FB1 = 1V
l
TRKSS1 Pull-Up Current
TRKSS1 = 0.2V
Minimum Switch-On Time
ISW1 = 1A
60
ns
Minimum Switch-Off Time
ISW1 = 1A
70
ns
1.5
2.4
Channel 2
Feedback Voltage
Input Current FB2
FB2 Voltage Line Regulation
VIN = 3V to 42V
SW2 Peak Current Limit
VIN = PVIN1 = PVIN2 = 6V
l
0.988
l
−100
3.5
SW2 Leakage Current
SW2 Top On Resistance
ISW2 = 1A
SW2 Bottom On Resistance
ISW2 = 1A
Lower FB2 Power Good Threshold
Percentage of VFB2
l
89
Upper FB2 Power Good Threshold
Percentage of VFB2
l
105
PG2 Output Voltage Low
IPG2 = –350µA
l
1
1.012
100
nA
0.002
0.01
%/V
4.0
4.5
A
0.1
1
µA
150
V
mΩ
100
mΩ
92
95
%
108
111
%
0.13
0.3
V
8601fa
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3
LT8601
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = 3.3V unless otherwise
noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
30
µA
1.5
2.4
3.1
µA
PG2 Leakage Current
PG2 = 5V, FB2 = 1V
TRKSS2 Pull-Up Current
TRKSS2 = 0.2V
Minimum Switch-On Time
ISW2 = 2A
55
ns
Minimum Switch-Off Time
ISW2 = 2A
70
ns
l
Channel 3
2.6
Operating Voltage
l
Feedback Voltage
l
790
Input Current FB3
l
–100
FB3 Voltage Line Regulation
VIN = 3V to 42V
SW3 Current Limit
V
810
mV
100
nA
0.002
0.01
%/V
3.2
3.8
A
PVIN3 = 5.5V
0.1
1
µA
SW3 PMOS On Resistance
ISW3 = 1A
150
mΩ
SW3 NMOS On Resistance
ISW3 = 1A
120
mΩ
SW3 Leakage
2.6
800
5.5
Lower FB3 Power Good Threshold
Percentage of VFB3
l
89
92
95
%
Upper FB3 Power Good Threshold
Percentage of VFB3
l
105
108
111
%
PG3 Output Voltage Low
IPG3 = –350μA
l
0.13
0.3
V
PG3 Leakage Current
PG3 = 5V, FB3 = 0.8V
l
30
µA
RUN3 Threshold Voltage
RUN3 Input Current
RUN3 = 3.3V
Soft-Start Time
l
0.695
l
–100
l
0.7
0.72
1
0.74
V
100
nA
1.3
ms
Minimum Switch-On Time
ISW3 = 1A
70
ns
Minimum Switch-Off Time
ISW3 = 1A
70
ns
PVIN3 UVLO
2.35
l
2.6
V
35.2
39.4
ms
0.1
0.2
Power-On Reset
CPOR Pull-Up Current
CPOR = 0V
POR Delay Time
CPOR = 1000pF
l
2
l
RST Output Voltage Low
IRST = –100μA
RST Pull-Up Current
POR Timed Out, RST = 0V
RST Leakage Current
RST = 6V, EN/UVLO = 0V
POREN Threshold
POREN Pull-Up Current
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8601E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8601I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. High junction temperatures degrade
4
μA
20
–40
l
POREN = 0V
31
V
μA
40
nA
1.15
1.2
1.25
V
0.8
1.2
1.6
μA
operating lifetimes. Operating lifetime is derated at junction temperatures
above 125°C.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during overload conditions. Junction temperature will
exceed 150°C when overtemperature protection is active. Continuous
operation above the specified maximum junction temperature will reduce
lifetime.
Note 4: All three channels enabled as shown in the application circuit
titled, “Details of the Front Page Application” (using the 1MHz component
values) found in the Typical Application section.
8601fa
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LT8601
Typical Performance Characteristics
and PVIN3 = 3.3V, unless otherwise noted.
Channel 2 Efficiency vs Load
VVOUT2
3.3V, fSW = 2MHz
OUT2 == 3.3V,
90
80
80
3.2
80
70
70
2.8
70
60
2.4
EFFICIENCY (%)
60
50
40
30
Burst Mode OPERATION
PVIN1 = 12V
PVIN1 = 28V
PVIN1 = 42V
10
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
50
2.0
PVIN2 = 5.5V
PVIN2 = 12V
PVIN2 = 24V
40
30
1.6
1.2
10
0.4
10
90
90
80
80
70
70
0.5
1
1.5
LOAD CURRENT (A)
2
40
30
Burst Mode OPERATION
20
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
50
50
40
30
Burst Mode OPERATION
PVIN3 = 2.6V
PVIN3 = 3.3V
PVIN3 = 5.5V
0
8601 G04
0.4
0.8
1.2
LOAD CURRENT (A)
1.6
10
2
3.5
TOP FET CURRENT LIMIT (A)
4.5
TOP FET CURRENT LIMIT (A)
2.7
8601 G07
10
15
4.0
3.5
3.0
2.5
0
20
25 30
VIN (V)
35
40
45
8601 G06
Channel 3 Peak Current Limit vs
4.0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
5
Duty Cycle
5.0
0
3
20
3.0
1.5
1
30
Channel 2 Peak Current Limit
vs Duty Cycle
1.8
0.01
0.1
LOAD CURRENT (A)
Quiescent Current vs VIN
8601 G05
Channel 1 Peak Current Limit
Duty
Cycle
vs
Duty
Cycle
2.1
0.001
8601 G03
60
0
3
2.4
PVIN2 = 5.5V
PVIN2 = 12V
PVIN2 = 28V
40
10
1
Burst Mode OPERATION
0
0.0001
LV Channel Efficiency vs Load
VOUT3
OUT3 = 1.2V,fSW
SW = 2MHz
20
PVIN3 = 2.6V
PVIN3 = 3.3V
PVIN3 = 5.5V
10
0
2.5
IQ (µA)
EFFICIENCY (%)
EFFICIENCY (%)
100
50
30
8601 G02
LV Channel Efficiency vs Load
VOUT3
OUT3 = 1.8V, fSW = 1MHz
60
40
20
8601 G01
100
50
0.8
0
VOUT2 = 3.3V,
3.3V, ffSW
1MHz
SW == 1MHz
60
20
0
1 2
Burst Mode OPERATION
EFFICIENCY (%)
100
3.6
100
POWER LOSS (W)
4.0
90
20
TOP FET CURRENT LIMIT (A)
Channel 2 Efficiency vs Load
90
100
EFFICIENCY (%)
Channel 1 Efficiency vs Load
VOUT1
OUT1 = 8V, fSW = 2MHz
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
3.0
2.5
2.0
1.5
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
8601 G09
8601 G08
8601fa
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5
LT8601
Typical Performance Characteristics
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
and PVIN3 = 3.3V, unless otherwise noted.
Switching Frequency
vs Temperature
RT = 30k
RT = 60k
RT = 250k
8
6
TRKSS CURRENT (µA)
FREQUENCY CHANGE (%)
TRKSS Pull-Up Current vs Voltage
4
2
0
–2
–4
–6
RST Pull-Up Current vs Voltage
1
10
0
0
RST CURRENT (µA)
10
–1
–2
–10
–20
–8
10
–50 –30 –10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
–3
0
0.5
1
1.5
2
2.5
TRKSS VOLTAGE (V)
3
8601 G10
350
2.00
300
1.75
FREQUENCY (MHz)
150
0.50
8000
10000
0.25
8601 G13
VSW3
2V/DIV
8601 G14
VOUT
20mV/DIV
Minimum On-Time vs ISW
100
MINIMUM ON-TIME (ns)
90
5µs/DIV
CHANNEL 1
12VIN TO 5VOUT AT 10mA
VSYNC = 0V
8601 G16
80
CHANNEL 2
70
60
50
Minimum Off-Time vs ISW
90
CHANNEL 1
0
0.5
1
1.5
SWITCH CURRENT (A)
2
2.5
8601 G17
6
VOUT1 = 5V
VOUT2 = 3.3V
VOUT3 = 1.8V
25 50 75 100 125 150 175 200 225 250 275
RT (kΩ)
100
IL
0.5A/DIV
8601 G15
200ns/DIV
Light Load Waveforms
VSW
5V/DIV
3.5
VSW2
10V/DIV
1.00
50
4000
6000
CPOR (pF)
3
1.25
0.75
2000
1.5
2
2.5
RST VOLTAGE (V)
VSW1
10V/DIV
1.50
100
0
1
Full Frequency Waveforms
MINIMUM OFF-TIME (ns)
POR DELAY TIME (ms)
2.25
200
0.5
8601 G12
Switching Frequency vs RT
Power-On Reset Time vs CPOR
250
0
8601 G11
400
0
–30
3.5
80
CHANNEL 1
CHANNEL 2
70
60
50
0
0.5
1
1.5
2
SWITCH CURRENT (A)
2.5
8601 G18
8601fa
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LT8601
Typical Performance Characteristics
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
and PVIN3 = 3.3V, unless otherwise noted.
Minimum On-Time
vs Temperature
100
80
CHANNEL 1
70
60
CHANNEL 2
50
180
ISW = 1A
Channel 3 Minimum
On-Time
ISW
Channel vs
3 Minimum
On–Time vs ISW
162
90
144
MINIMUM ON–TIME (ns)
ISW = 1A
MINIMUM OFF-TIME (ns)
MINIMUM ON-TIME (ns)
90
Minimum Off-Time
vs Temperature
80
CHANNEL 1
70
CHANNEL 2
126
108
90
72
54
60
36
PVIN3 = 2.6V
PVIN3 = 3.3V
PVIN3 = 5.5V
18
40
–50 –25
0
50
–50 –25
25 50 75 100 125 150
TEMPERATURE (°C)
0
8601 G19
Channel 3 Minimum
Off-Time
ISW
Channel 3vsMinimum
Off–Time vs ISW
Channel 1 RDS(ON)
vs Temperature
500
88
70
64
58
400
ISW1 = 1A
TOP FET
300
0.6
0.8
1 1.2
ISW (A)
1.4
1.6
100
–50 –25
1.8
0
8601 G21
25 50 75 100 125 150
TEMPERATURE (°C)
8601 G24
EN/UVLO Current vs Voltage
1.010
0.810
1.005
0.805
3.0
200
TOP FET
150
CHANNEL 3
2.0
1.5
1.0
0.795
0.995
BOTTOM FET
0
0.800
1.000
100
50
CHANNELS 1, 2
IEN/UVLO (µA)
CHANNELS 1, 2 VFB (V)
2.5
CHANNEL 3 VFB (V)
RDSON (mΩ)
0
8601 G23
250
0
–50 –25
1.8
BOTTOM FET
0
–50 –25
Feedback Voltage vs Temperature
ISW3 = 1A
1.6
200
25 50 75 100 125 150
TEMPERATURE (°C)
8601 G22
Channel 3 RDS(ON)
vs Temperature
1.4
TOP FET
100
46
0.4
1 1.2
ISW (A)
ISW2 = 1A
BOTTOM FET
40
0.2
0.8
300
200
52
300
0.6
Channel 2 RDS(ON)
vs Temperature
400
82
RDSON (mΩ)
MINIMUM OFF–TIME (ns)
94
76
0.4
8601 G20
RDSON (mΩ)
100
0
0.2
25 50 75 100 125 150
TEMPERATURE (°C)
0.5
25 50 75 100 125 150
TEMPERATURE (°C)
8601 G25
0.990
–50 –25
0
0.790
25 50 75 100 125 150
TEMPERATURE (°C)
8601 G26
0.0
0
5
10
15
20 25 30
VEN/UVLO (V)
35
40
45
8601 G27
8601fa
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7
LT8601
Typical Performance Characteristics
TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V
and PVIN3 = 3.3V, unless otherwise noted.
Channel 1 Start-Up and Dropout,
RL = 20Ω
Channel 1 Start-Up and Dropout,
RL = 3.3Ω
VIN
VIN
VOUT1
2V/DIV
VOUT1
2V/DIV
100ms/DIV
100ms/DIV
8601 G28
Channel 2 Start-Up and Dropout,
RL = 20Ω
Channel 2 Start-Up and
Dropout, RL = 2Ω
VIN
VIN
VOUT2
100ms/DIV
45
RT = 28.7k
40
35
35
30
30
FULL FREQUENCY
REGION (2MHz)
VIN (V)
VIN (V)
Channel 2 Full Frequency VIN
vs
Current
VinLoad
vs Load
Current
40
20
VOUT = 3.3V
VOUT = 5V
15
10
8
6.0
5.0
4.5
25
FULL FREQUENCY
REGION (2MHz)
0.2
0.4
0.6
0.8 1
IOUT (A)
1.2
3.0
10
1.4
1.6
8601 G32
0
FULL FREQUENCY
REGION (2MHz)
4.0
3.5
2.5
5
0
RT = 28.7k, VOUT = 1.2V
5.5
VOUT = 3.3V
VOUT = 5V
20
8601 G31
Channel 3 Full Frequency VIN
vs
Current
VinLoad
vs Load
Current
RT = 28.7k
15
5
0
100ms/DIV
8601 G30
Channel 1 Full Frequency VIN
vs
Current
VinLoad
vs Load
Current
25
VOUT2
2V/DIV
VIN (V)
2V/DIV
45
8601 G29
0
0.3
0.7
1.0
1.3 1.6
IOUT (A)
1.9
2.3
2.6
8601 G33
2.0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0
IOUT (A)
8601 G34
8601fa
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LT8601
Typical Performance Characteristics
TA = 25°C
Radiated EMI Performance, CISPR25 Radiated Emission Tests with Class 5 Peak Limit.
AMPLITUDE (dBµV/m)
Vertical Polarization
60
55
50
45
40
35
30
25
20
15
10
5
0
–5
–10
–15
DETECTOR: +PEAK
CISPR25 RADIATED DISTURBANCES – ALSE
NOTES: DC2346A
CISPR25 CLASS 5 PEAK LIMIT
DATA
0
100
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
1000
8601 EMI 01a
AMPLITUDE (dBµV/m)
Horizontal Polarization
60
55
50
45
40
35
30
25
20
15
10
5
0
–5
–10
–15
DETECTOR: +PEAK
CISPR25 RADIATED DISTURBANCES – ALSE
NOTES: DC2346A
CISPR25 CLASS 5 PEAK LIMIT
DATA
0
100
200
300
400
500
600
FREQUENCY (MHz)
700
800
900
1000
8601 EMI 01a
Demo Board with EMI Filter Installed, 14VIN, 1A on All Outputs, fSW = 2MHz.
8601fa
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9
LT8601
Pin Functions
BIAS (Pin 10): Power to the Internal Regulator. Connect
to an output ≥ 3.2V when available. Decouple to ground
with a low ESR capacitor.
BST1, BST2 (Pins 4, 5): Boost Voltage for High Voltage
Channels. The Boost Voltage provides a drive voltage
higher than PVIN to the gate of the NMOS top switch.
CPOR (Pin 31): Power-On Reset Timer. Connect a capacitor from this pin to ground to program the power-on reset
timer. CPOR has a 2μA (typical) pull-up current.
EN/UVLO (Pin 22): Enable/Undervoltage Lockout Input.
The LT8601 is in low power shutdown when this pin is
≤ 0.4V. A precision threshold at 1.20V (rising) enables
the switching regulator’s output switching stages. This
allows the EN/UVLO pin to be used as an input undervoltage lockout by connecting to a resistor divider between
VIN and GND. When the EN/UVLO voltage is between 0.4V
and 1.2V, the LT8601 input current will depend on the
mode selected, the VIN voltage, and the EN/UVLO voltage.
Connect this pin to VIN if the UVLO function is not needed.
FB1, FB2 (Pins 26, 25): Feedback Input Pins for the High
Voltage Converters. The converters regulate the corresponding feedback pin to the lesser of 1V or the voltage
on the associated TRKSS pin.
FB3 (Pin 24): Feedback Input Pin for the Low Voltage
Converter. The converter regulates the corresponding
feedback pin to 800mV.
GND (Pins 2, 8, 9, 13, 16, 27, 30, 34, 35, 38, 40, 41):
Ground. These pins must be soldered to PCB ground.
The exposed pad must also be soldered to PCB ground.
INTVCC (Pin 28): Internal Regulator Bypass. Do not load
the INTVCC pin with external circuitry. INTVCC is 3.1V
when BIAS < 3.1V, 3.4V when BIAS > 3.4V, and approximately equal to BIAS when BIAS is between 3.1V and
3.4V. Decouple to ground with a low ESR, 4.7μF capacitor.
PG1, PG2 (Pins 1, 11): Power Good Indicators for Channels
1 and 2. Open-drain logic output pulls down until the corresponding FB pin rises above 0.92V but remains below 1.08V.
PG3 (Pin 12): Power Good Indicator for Channel 3. Opendrain logic output pulls down until the corresponding FB
pin rises above 0.736V but remains below 0.864V.
POREN (Pin 39): Power-On Reset Enable. This is a logic
input that starts the ramp on the POR timing capacitor.
10
PVIN1, PVIN2 (Pins 37, 14): Input Supply Voltage to High
Voltage Channels 1 and 2, respectively. These pins are
independent and can be powered from different sources
if necessary. Bypass each input with a low ESR capacitor
to the adjacent GND pin.
PVIN3 (Pin 17): Input Supply Voltage to Low Voltage
Channel 3. This pin is typically connected to one of the
high voltage converter outputs and should be locally
bypassed with a low ESR capacitor.
RST (Pin 32): Power-On Reset Output. CMOS output with
weak pull-up, this pin is held low until the POR times out.
RT (Pin 29): Frequency Programming Resistor. Connect
a resistor from this pin to ground to set the internal oscillator frequency.
RUN3 (Pin 18): Run Input for the Low Voltage Converter.
Channel 3 is enabled when the voltage on this pin exceeds
0.72V (typical).
SW1 (Pin 3): Channel 1 Switch Node. This is the output
of the internal power switches for channel 1.
SW2 (Pins 6, 7): Channel 2 Switch Node. This is the output of the internal power switches for channel 2. These
pins must be connected together.
SW3 (Pin 15): Channel 3 Switch Node. This is the output
of the internal power switches for channel 3.
SYNC (Pin 33): Clock Synchronization and Mode Select
Input. Connect this pin to ground to enable low ripple
Burst Mode operation. Connect this pin to INTVCC to
enable pulse skip operation. Apply a digital clock input to
synchronize the LT8601 switching frequency to a reference clock. When an external clock is applied, the LT8601
will operate in pulse-skipping mode.
TRKSS1, TRKSS2 (Pins 21, 20): Track/Soft-Start Inputs
for the High Voltage Converters. When this pin is below
1V, the converter regulates the FB pin to the TRKSS voltage instead of the internal reference. The TRKSS pin has
a 2.4μA (typical) pull-up current.
VIN (Pin 23): Input Supply Voltage to Internal Functions.
This pin is independent from any PVIN pin and can be
powered from different sources if necessary. VIN must
be above 3V for the part to operate.
For more information www.linear.com/LT8601
8601fa
LT8601
Block Diagram
POREN
RST
VIN
INTVCC
RT
SYNC
INTVCC
CPOR
POWER-ON
RESET
EN/UVLO
REGULATOR
OSCILLATOR
1V
REFERENCE
0.8V
CLK1
ENABLE
BIAS
CLK2
SS3
BST2
BST1
ILIM1
PVIN1
–
+
CLK1
CLK2
CURRENT
SENSE
COMPARATOR
LOGIC
DRIVER
–
+
+
2.4µA
LOOP
COMPENSATION
ILIM2
ILIM1
1.08V
PG1
–
+
–
+
ILIM3
PVIN3
FB2
–
+
+
LOOP
COMPENSATION
2.4µA
1V
0.92V
–
+
GND
ERROR
AMPLIFIER
1V
TRKSS1
–
+
REVERSE
CURRENT
COMPARATOR
REVERSE
CURRENT
COMPARATOR
ERROR
AMPLIFIER
FB1
PVIN2
SW2
LOGIC
DRIVER
–
+
–
+
CURRENT
SENSE
COMPARATOR
SW1
GND
ILIM2
TRKSS2
0.92V
1.08V
PG2
CLK2
CURRENT
SENSE
COMPARATOR
SW3
LOGIC
DRIVER
–
+
GND
REVERSE
CURRENT
COMPARATOR
ERROR
AMPLIFIER
FB3
–
+
+
SS3
LOOP
COMPENSATION
ILIM3
0.8V
0.74V
0.86V
–
+
PG3
GND
RUN3
8601 BD
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11
LT8601
Operation
The LT8601 is a triple channel, constant frequency, current mode, monolithic buck switching regulator with
power-on reset. All channels are synchronized to a single
oscillator. Two of the channels are high voltage capable
(up to 42V input) while the other is low voltage capable
(up to 5.5V input) and is typically powered from the high
voltage buck outputs.
Start-Up
When enabled by setting the EN/UVLO voltage above its
threshold, the LT8601 starts charging the INTVCC capacitor from VIN. If BIAS is higher than 3.2V, BIAS supplies
current to the INTVCC regulator to reduce VIN quiescent
current.
High Voltage Buck Regulators
Each high voltage channel is a synchronous buck regulator that operates from an independent PVIN pin. The
internal top power MOSFET is turned on at the beginning
of each oscillator cycle, and turned off when the current
flowing through the top MOSFET reaches a level determined by the error amplifier. The error amplifier measures
the output voltage through an external resistor divider
tied to the FB pin to control the peak current in the top
switch. The reference of the error amplifier is determined
by the lower of the internal 1V reference and the voltage
at its TRKSS pin.
While the top MOSFET is off, the bottom MOSFET is
turned on for the remainder of the oscillator cycle or until
the inductor current starts to reverse. If overload conditions result in more than 2A for channel 1 or 3.3A for
channel 2 flowing through the bottom switch, the next
clock cycle will be delayed until switch current returns
to a safe level.
Low Voltage Buck Regulator
The low voltage channel is a synchronous buck regulator
that operates from an independent PVIN pin. The PVIN pin
has an undervoltage lockout set at 2.35V (typical). Each
internal top power MOSFET is turned on at the beginning
of each oscillator cycle, and turned off when the current
flowing through the top MOSFET reaches a level determined by the error amplifier. The error amplifier measures
the output voltage through an external resistor divider tied
12
to the FB pin to control the peak current in the top switch.
The reference of the error amplifier is an internal 800mV
reference. The low voltage channel has a RUN pin to allow
power sequencing and an internal soft-start circuit ramps
the output voltage up in 1ms.
While the top MOSFET is off, the bottom MOSFET is
turned on for the remainder of the oscillator cycle or until
the inductor current starts to reverse. If overload conditions result in more than 2.4A flowing through the bottom
switch, the next clock cycle will be delayed until switch
current returns to a safe level.
Multiphase Switching
The oscillator generates two clock signals 180° out of
phase. Channel 1 operates from CLK1, while channels
2 and 3 operate from CLK2. Since a buck regulator only
draws input current during the top switch on-cycle, multiphase operation reduces peak input current and doubles
the input current frequency. These effects reduce input
current ripple and reduce the input capacitance required.
Light Load Operation
At light load, the regulators operate in low ripple Burst
Mode operation. Low ripple Burst Mode operation shuts
down most internal circuitry between switch on-cycles
to conserve power while still retaining low ripple at the
output.
Undervoltage Lockout
The EN/UVLO pin is used to put the LT8601 in shutdown,
reducing the input current to less than 1μA. The accurate
1.2V (rising) threshold of the EN/UVLO pin provides a programmable VIN undervoltage lockout through an external
resistor divider tied to the EN/UVLO pin. A 50mV (typical)
hysteresis voltage on the EN/UVLO pin prevents switching noise from inadvertently shutting down the LT8601.
Power Good Comparators
Each channel has a power good comparator that trips
when the feedback pin is above or below its reference
voltage by more than 8%. The PG output pins are opendrain. The PG pin for each channel is pulled low when the
corresponding output is out of regulation. The PG outputs
are not valid until INTVCC rises to 2.7V
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8601fa
LT8601
Operation
Power-On Reset Timer
The LT8601 includes a power-on reset timer. The poweron reset timeout period is adjustable using an external
capacitor on the CPOR pin as described in the Applications
Information section. The timer is initiated when the
POREN pin is higher than 1.2V (typical).
The output of the POR timer, the RST pin, is an open-drain
output with a weak internal pull-up of 100kΩ (typical) to
approximately 2V. RST is held low until the expiration of
the POR timer. The RST pin is only valid when the LT8601
is enabled and INTVCC is above 2.7V.
Applications Information
Setting the Output Voltages
VOUTx
SWx
The output voltages are set by the resistor dividers on the
outputs as shown in Figure 1. The formula used is:
COUT
LT8601
R1
Cff
OPTIONAL
FBx
R2
⎛V
⎞
R1=R2 • ⎜⎜⎜ OUTx – 1⎟⎟⎟
⎝ VFB
⎠
8601 F01
Figure 1. Feedback Resistor Divider
where VOUTx is the output voltage of regulator x and VFB
is the feedback reference voltage. VFB is 1V for the high
voltage regulators (1 and 2) and 800mV for the low voltage
channel. R2 should be 200k or less to avoid noise problems.
To improve the frequency response, a feedforward capacitor Cff may also be used. Typical values are 10pF to 100pF.
Great care should be taken to route the FB node away from
noise sources, such as an inductor or a SW line.
Switching Frequency
The LT8601 uses a constant frequency architecture that can
be programmed from 250kHz to 2.2MHz by tying a resistor
from the RT pin to ground. Table 1 shows the closest 1%
resistor value of RT for common switching frequencies.
Table 1. Switching Frequency vs RT Value
The following equation approximates the values shown
in Table 1:
RT =
61.9
– 1.9
fS – 0.009
where RT is in kΩ and fS is in MHz.
Selection of the operating frequency is mainly a trade-off
between efficiency and component size. The advantage
of high frequency operation is that smaller inductor and
capacitor values may be used. The advantage of low frequency operation is higher efficiency.
The high switching frequency also decreases the duty
cycle range because of finite minimum on- and off-times
independent of the switching frequency. The minimum
and maximum duty cycles are:
SWITCHING FREQUENCY (MHz)
RT (kΩ)
0.25
255
DCMIN = fS • tON(MIN)
0.35
178
0.5
124
DCMAX = 1 – fS • tOFF(MIN)
0.75
80.6
1.0
60.4
1.25
47.5
1.5
39.2
1.75
33.2
2.0
28.7
2.2
26.1
where fS is the switching frequency, tON(MIN) is the
minimum switch on-time, and tOFF(MIN) is the minimum
switch off-time. These equations illustrate how duty cycle
range increases when switching frequency decreases.
Information about individual channel minimum on and
off times can be found in the Electrical Characteristics
table and Typical Performance curves section.
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13
LT8601
Applications Information
The internal oscillator of the LT8601 can be synchronized
to an external 250kHz to 2.2MHz clock signal on the SYNC
pin.
VIN Voltage Range
The LT8601’s minimum operating voltage is 3V. To program a higher minimum operating voltage, use a resistor divider between the VIN pin and the EN/UVLO pin. The
EN/UVLO threshold is 1.2V. The EN/UVLO pin has 50mV
of hysteresis to prevent glitches from falsely disabling
the LT8601.
The UVLO circuit is shown in Figure 3, Reverse Protection
Diodes. The calculation for the lockout voltage is:
VIN(UVLO) =
where DCMIN is the minimum duty cycle (refer to
Switching Frequency section) for that channel. If PVIN
is above the calculated maximum voltage, the channel
starts to skip switch on-cycles (pulse-skipping). In this
case, the channel switching frequency will no longer be
the programmed frequency. The output will continue to
regulate, but the peak inductor current and output ripple
will increase significantly.
Inductor Selection
Inductor selection involves inductance, saturation current,
series resistance (DCR) and magnetic loss.
A good starting point for the inductance values are:
RUV1 +RUV2
•1.2V
RUV2
Lx =Kx •
PVIN Voltage Range
Each switching regulator channel operates from its own
PVIN pin (PVIN1 to PVIN3). The PVIN pin can be connected
to either an independent voltage supply or a high voltage
channel output. The PVIN1 and PVIN2 voltage range is 3.0V
to 42V. The PVIN3 voltage range is 2.6V to 5.5V.
where fS is the switching frequency in MHz, Lx is in µH,
VOUTx is the channel output voltage and K1 = 1.7, K2 = 1.0
and K3 = 1.4.
Once the inductance is selected, the inductor current
ripple and peak current can be calculated:
⎛
VOUTx ⎞
⎟⎟
• ⎜⎜1–
PV
INx(MAX) ⎠
⎝
ΔI
ILx(PEAK) =IOUTx(MAX) + Lx
2
ΔILx =
The minimum PVIN voltage to regulate output voltage at
full frequency is:
PVINx(MIN) =
VOUTx
DCMAX
where DCMAX is the maximum duty cycle (refer to
Switching Frequency section) for that channel. If PVIN
is below the calculated minimum voltage, the channel
starts to skip switch off-cycles. At low input voltages,
the part will turn on the top switch for longer than a full
switch cycle in order to extend the effective duty cycle.
When the part is extending the effective duty cycle, the
switching frequency will drop to one half (or less) of the
programmed frequency.
The maximum PVIN voltage to regulate output voltage at
full frequency is:
V
PVINx(MAX) = OUTx
DCMIN
14
VOUTx PVINx – VOUTx
•
PVINx
fS
VOUTx
Lx • fS
To guarantee sufficient output current, peak inductor current must be lower than the switch current limit (ILIM).
To keep the efficiency high, the inductor series resistance
(DCR) should be as small as possible (must be < 0.1Ω
channels 1 and 3; < 0.06 Ω channel 2), and the core material should be intended for the chosen switching frequency.
Table 2 lists several vendors and suitable inductor series.
Table 2. Inductor Vendors
VENDOR
SERIES
WEBSITE
TDK
SLF, VLC, VLF
www.tdk.com
Sumida
CDRH, CDR, CDMC
www.sumida.com
Coilcraft
XAL, XFL, MSS
www.coilcraft.com
NIC
NPIM, NPIS
www.niccomp.com
Würth
TPC, SPC, PD, PDF, PD3
www.we-online.com
8601fa
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LT8601
Applications Information
Of course, such a simple design guide will not always
result in the optimum inductors for the applications. A
larger value inductor provides a slightly higher maximum
load current and will reduce the output voltage ripple.
A larger value inductor can result in higher efficiency if
the DCR and magnetic losses are the same. However, for
inductors of the same dimensions, the larger value inductor has higher DCR. The trade-off between inductance
and DCR is not always obvious. Use experiments to find
optimum inductors.
Low inductance may result in discontinuous mode operation, which is acceptable, but reduces maximum load
current. For details of maximum output current and discontinuous mode operation, see the Linear Technology
Application Note 44. For duty cycles greater than 50%,
there is a minimum inductance required to avoid subharmonic oscillations.
1.05 • ( VOUTx + VBOTx )
LMINx =
, chs 1 and 3
fS
LMINx =
0.70 • ( VOUTx + VBOTx )
, ch 2
fS
where VOUTx is the output voltage; VBOTx is the voltage
across the bottom switch; fS is the switching frequency
in MHz and LMINx is in µH. If the frequency is synchronized over a range, use the lowest frequency to determine
LMINx.
Shorted Output Protection
If the bottom MOSFET current exceeds the valley current
limit at the start of a clock cycle, the top MOSFET is kept
off until the overcurrent situation clears. This prevents
the buildup of inductor current during a shorted output. Further, during overload or short-circuit conditions,
the LT8601 safely tolerates operation with a saturated
inductor.
Input Capacitor Selection
Bypass each PVIN pin of the LT8601 with a ceramic capacitor of X7R or X5R type.
Step-down converters draw current from the input supply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT8601 input and to force this switching current
into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency
to do this effectively and it must have an adequate ripple
current rating.
The worst case ripple current is when VOUT is one half of
PVIN. In this case, the ripple current is:
ICIN(RMS) =
IOUT
2
A reasonable value for the input capacitor is:
4.7µF
, Chs 1 and 3
fS
10µF
, Ch 2
fS
where fS is the switching frequency in MHz.
Careful placement of CIN is essential to get the lowest
ripple and EMI. CIN should be placed as close to the PVIN
pin as possible and on the same side of the PC board. The
layer immediately below the component traces should be
an unbroken ground plane. The ground side of CIN should
have at least 2 vias to the ground plane as close to CIN
as possible. This provides a high frequency return path
directly under the PVIN to CIN trace. This minimizes loop
area of the high frequency, high current path from PVIN
to CIN and back to the GND exposed pad. See Figure 8,
Recommended PCB Layout.
A word of caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit back to the supply. If power is applied quickly (for
example by plugging the circuit into a live power source),
this tank can ring, as much as doubling the input voltage. The solution is to either clamp the input voltage or
dampen the tank circuit by adding a lossy capacitor in
parallel with the ceramic capacitor. For details, see Linear
Technology Application Note 88.
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LT8601
Applications Information
Output Capacitor Selection
The output capacitor performs two functions. First, it filters the inductor current to generate an output with low
voltage ripple. Second, it stores energy to minimize overshoot during transient loads. Because the LT8601 operates at a high frequency, minimal output capacitance is
necessary. The control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following
equations:
VRIPPLE =
ΔIL
, for ceramic
8 • fS •COUT
VRIPPLE = ∆IL • ESR, for aluminum or tantalum.
where VRIPPLE is the peak-to-peak output ripple, fS is the
switching frequency in MHz, ΔIL is the peak-to-peak ripple
current in the inductor, COUT is the output capacitor value
in µF and ESR is the output capacitor series resistance.
Another constraint on the output capacitor is that it must
have greater energy storage than the inductor. When the
load current steps from high to low, the stored energy
in the inductor transfers to the output and the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
2
⎛I
⎞
COUT ≥10 •L • ⎜ LIM ⎟
⎝ VOUT ⎠
where ILIM is the maximum switch current limit. For
applications that intend to operate near minimum ontime, larger output capacitance values may be required
to minimize output voltage ripple than described by the
equations in this section.
The low ESR and small size of ceramic capacitors make
them the preferred type for LT8601 applications. Not
all ceramic capacitors are the same, however. Many of
the higher value capacitors use poor dielectrics with
16
high temperature and voltage coefficients. In particular,
Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and at temperature extremes.
Because loop stability and transient response depend on
the value of COUT, this loss may be unacceptable. Use
X7R or X5R types.
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR, organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 3 lists
several capacitor vendors.
Table 3. Low ESR Capacitor Vendors
VENDOR
SERIES
TYPE
Murata
www.murata.com
Ceramic
TDK
www.tdk.com
Ceramic
Kemet
www.kemet.com
Ceramic
T494, T495
Tantalum
T510, T520, T525, T530 Tantalum Organic Polymer
A700
Alum. Organic Polymer
Panasonic
www.panasonic.com SP-CAP
Ceramic
Alum. Organic Polymer
AVX
www.avx.com
Ceramic
Tantalum
TPS, TES, TCH
BST and SW Pin Considerations
The high voltage channels require a voltage above PVIN
to drive the gates of the top NFET switches. Connect an
external capacitor between the BST and SW pins. An
internal MOS switch connects BST to the internal INTVCC
supply during the switch off-cycles. Then BST is boosted
to approximately 3.3V above SW during the switch oncycles. In most cases, a 0.1μF capacitor will work well.
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LT8601
Applications Information
Soft-Start
The LT8601 has a soft-start pin for each high voltage
channel and internal soft-start for each low voltage channel. The low voltage channel soft-start is set to 1ms.
On the high voltage channels, the feedback pin voltage
is regulated to the lower of the corresponding TRKSS
pin and the internal reference of 1V. A capacitor from the
TRKSS pin to ground is charged by an internal 2.4μA current source resulting in an output ramping linearly from
0V to the regulated voltage. The duration of the ramp is:
1V
2.4µA
where tSS is the ramping time in seconds and CTRKSS is
the capacitance on the TRKSS pin in F.
The TRKSS pin is pulled down through approximately
200Ω at start-up until INTVCC has reached operating voltage. It is also pulled down when an undervoltage condition is detected by either the internal lockout on PVIN or
the programmable EN/UVLO pin.
For applications with a startup sequence that requires a
PG pin be tied to a TRKSS input, a 10k or less resistor
must be used as an external pull-up. The soft-start time
with this configuration can be approximated by:
tSS = 0.5 • RPULLUP • CTRKSS
A more exact formula, that includes the dependence on
the pull-up voltage, VPULLUP, is given by:
⎛ V
⎞
tSS = RPULLUP • CTRKSS • Loge ⎜⎜⎜ PULLUP ⎟⎟⎟
⎝ VPULLUP – 1⎠
OUTPUT VOLTAGE
VOUT1
VOUT2
VOUT1
OUTPUT VOLTAGE
tSS = CTRKSS •
The TRKSS pin can be used to allow the output of one regulator to track the output of another regulator. To achieve
coincident tracking, connect a resistor divider, RTR1 and
RTR2, from the master output to ground and tie the RTR1,
RTR2 common node to the TRKSS pin of slave regulator.
To achieve ratiometric tracking, connect both TRKSS1 and
TRKSS2 to a single capacitor to ground. Figure 2 shows
the output waveforms for both coincident and ratiometric
tracking. Note: Pulling TRKSS1 and TRKSS2 to ground
does not guarantee the respective channel will never display a switching cycle.
VOUT2
TIME
TIME
(2a) Coincident Tracking
8601 F02
(2b) Ratiometric Tracking
Figure 2. Example Tracking Output Waveforms
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17
LT8601
Applications Information
Reverse Protection
In battery charging applications or in battery backup systems, an output will be held high by the battery when
the input to the LT8601 is absent. If the VIN and PVIN
pins are floated and the LT8601 is enabled, the internal
circuitry will pull its quiescent current through the SW
pin of the output that is held high. This is acceptable if
the system can tolerate a small current (< 100µA) in this
state. If the LT8601 is disabled, the SW pin current will
drop to essentially zero. However, if the VIN or PVIN pin is
grounded while the output is held high, an external diode
is required at the VIN/PVIN pin to prevent current being
pulled out of the VIN/PVIN pin. An example is shown in
Figure 3. In this case, both OUT1 and OUT3 are held high
by batteries. PVIN1 and PVIN3 must be diode protected if
they are connected to external supplies.
IN
RUV1
BST1
PVIN1
EN/UVLO
SW1
VSW3
2V/DIV
1µs/DIV
8601 F04
Figure 4. Burst Mode Operation SW Waveforms with Oscillator
Running
VERT
5V/DIV
VSW1
OUT1
+
–
FB1
VSW3
100ms/DIV
LT8601
SW3
OUT3
PVIN3
+
–
FB3
GND
8601 F03
Figure 3. Reverse Protection Diodes
Burst Mode Operation
To improve efficiency at light loads, the LT8601 automatically switches to Burst Mode operation which minimizes
the switching loss and keeps the output voltage ripple
small. In Burst Mode operation, most of the circuits are
shut down between switch-on bursts to minimize power
loss. If at least one channel remains full frequency, the
oscillator remains on and all bursts are synchronized to
the appropriate phase of the oscillator (Figure 4). If all
three channels go into Burst Mode operation, the oscillator will also shut off between bursts with a further savings
in power (Figure 5). Because the channels of the LT8601
may have different loads, channels can have different
switching frequencies when in Burst Mode operation.
18
VSW2
10V/DIV
VSW2
VIN
RUV2
IN3
VSW1
10v/DIV
8601 F05
Figure 5. Burst Mode Operation SW Waveforms with All
Channels in Burst Mode Operation
Mode Selection and Synchronization
To select low ripple Burst Mode operation, the SYNC
pin should be connected to a voltage below 0.3V such
as ground. To select pulse-skipping operation, connect
the SYNC pin to an available voltage above 1.2V such as
INTVCC.
To synchronize the LT8601 to an external frequency, drive
the SYNC pin with a square wave between 20% and 80%
duty cycle with a high voltage above 1.2V and a low voltage below 0.3V. If the negative or positive pulse widths
are less than 140ns, use a high voltage above 1.4V and a
low voltage below 0.2V. The LT8601 will not enter Burst
Mode operation at low output loads while synchronized
to an external clock but instead will pulse skip to maintain regulation. The LT8601 may be synchronized over
a 250kHz to 2.2MHz range. The RT resistor should be
chosen to set the LT8601 switching frequency equal to
the synchronization input. If a range of frequencies is
8601fa
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LT8601
Applications Information
used, set RT to the center of the range. For example, if
the synchronization signal will be 400kHz to 600kHz, the
RT should be selected for 500kHz.
For some applications it is desirable for the LT8601 to
operate in pulse-skipping mode, offering two major differences from Burst Mode operation. First, in pulse-skipping
mode the clock stays awake at all times and all switching
cycles are aligned to the clock. Second, full frequency
switching is reached at a lower output load in pulse-skipping than Burst Mode operation. These two differences
come at the expense of increased quiescent current for
pulse-skipping. To enable pulse-skipping mode, the SYNC
pin is tied high either to a logic output or to the INTVCC
pin.
Do not leave the SYNC pin floating.
Power Good Comparators
Each channel of the LT8601 has a power good comparator that monitors their corresponding feedback voltage
when the LT8601 is enabled. The threshold of power good
comparator is 0.92V to 1.08V for the high voltage channels, and 736mV to 864mV for the low voltage channel.
The PG outputs are open-drain and have a recommended
external pull-up resistance value of 20k or less. An appropriate pull-up resistance value will take into consideration
the specific application configuration and the leakage current of the PG pin.
Power-On Reset Timer
The power-on reset timer circuit provides a programmable reset timer. The POREN pin is the enable for the reset
timer and includes a 1μA (typical) internal pull-up. Once
enabled, the reset timer begins an internal clock counter
that terminates after 64 cycles. Upon counter termination,
the RST open-drain output releases allowing the pin to
transition high. The RST output includes a weak, 100kΩ,
internal pull-up resistor to approximately 2V.
POREN
1V/DIV
CPOR
1V/DIV
RST
2V/DIV
1ms/DIV
8601 F06
Figure 6. Power-On Reset Timing
where CPOR is in pF and tRST is in microseconds. For
example, using a capacitor value of 8.2nF gives a 289ms
reset timeout period. The accuracy of tRST will be determined by several factors including the accuracy and
temperature coefficient of the capacitor CPOR, parasitic
capacitance on the CPOR pin and board trace, and system noise. It is not recommended to use capacitor values
greater than 10nF for best accuracy. Figure 6 shows the
power-on reset timing.
Sequencing
The LT8601 provides great flexibility in sequencing the
3 channels and the power-on reset timer. Each channel
has a power good output (PG1 to PG3) and a controlling input (TRKSS1, TRKSS2 and RUN3). The POR has
a control input (POREN) and a reset output (RST). All
4 outputs (PG1-PG3, RST) are open-drain, and all 4 inputs
(TRKSS1/2, RUN3, POREN) have internal pull-up currents
to reduce external component counts when not driven by
a PG pin. The soft-start function on the TRKSS pins will
INTVCC
LT8601
RST
START
PG1
TRKSS2
PG2
RUN3
INTVCC
PG3
The power-on reset timeout period, tRST, can be programmed by connecting a capacitor, CPOR, between the
CPOR pin and ground. The value of tRST is calculated by:
POREN
TRKSS1
8601 F07
tRST = 35.2 • CPOR
Figure 7. Sequencing the Outputs and POR
8601fa
For more information www.linear.com/LT8601
19
LT8601
Applications Information
work when using sequencing; simply connect the capacitor to the TRKSS pin as usual, connect an external pullup resistor of value 10k or less, and use the desired PG
output to short the cap. A sequencing example is shown
in Figure 7.
In this example, channel 1 starts first, and soft-starts
according to the cap on TRKSS1. Once OUT1 has reached
regulation, channel 2 soft-starts. When OUT2 is good,
channel 3 starts up. When OUT3 is in regulation, then the
POR timer is started. One caution when connecting RUN
pins to TRKSS pins: the TRKSS channel will start ramping
immediately, but the RUN channel will not start until the
voltage reaches the RUN threshold.
The EN/UVLO has two thresholds enabling three regions
of operation. When EN/UVLO is below the shutdown
threshold, the LT8601 is in low power shutdown and
draws less than 1µA from VIN. The shutdown threshold
is typically between 0.4V and 1.1V. When the EN/UVLO is
above the shutdown threshold but below the undervoltage
threshold, the internal bias circuitry starts but the regulators' output switches are disabled. The input current
in this region typically ranges between 1µA and 400µA
depending on several factors including the mode selected
and the voltage at VIN. When the EN/UVLO is above the
undervoltage threshold, normal operation is active.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 8 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT8601’s PVIN pins, GND pins, and
the input capacitors. The loop formed by the input capacitor should be as small as possible by placing the capacitor
close to the PVIN pin and the adjacent GND pin. When
using a physically large input capacitor, the resulting loop
20
may become too large in which case using a small case/
value capacitor placed close to the PVIN and GND pins
plus a larger capacitor further away is preferred. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane under the application circuit on the layer closest to the surface layer. The SW and
BOOST nodes should be as small as possible. Finally, keep
the FB and RT nodes small so that the ground traces will
shield them from the SW and BOOST nodes. The exposed
pad on the bottom of the package must be soldered to
ground to provide a good electrical connection as well
as a good thermal connection so that the PCB can act as
a heat sink. To keep thermal resistance low, extend the
ground plane as much as possible, and add thermal vias
under and near the LT8601 to additional ground planes
within the circuit board and on the bottom side.
VOUT2
VOUT1
L2
L1
COUT2
COUT1
CBST2
COUT3
CBST1
CIN2
VOUT3
1
CIN1
L3
CIN3
8601 F08
Figure 8. Recommended PCB Layout
8601fa
For more information www.linear.com/LT8601
LT8601
Applications Information
Thermal Considerations
Care should be taken in the layout of the PCB to ensure
good heat sinking of the LT8601. The exposed pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to large copper layers
below with thermal vias; these layers will spread heat
dissipated by the LT8601. Recommended layer use for
a 4-layer board is:
Layer 1 (Components): use 2oz copper; unbroken high
frequency/high current routing (CIN loop, SW node, BST
node, inductor, COUT), high current DC routing, ground
plane on remainder
Layer 2 (Internal): Unbroken ground plane
Layer 3 (Internal): Signal routing, ground plane on
remainder
Layer 4 (Bottom): Use 2oz copper; high current DC routing (VIN, VOUT), ground plane on remainder
Placing additional vias can reduce thermal resistance further. Many small thermal vias are better than a few large
ones. Following these PCB design guidelines can reduce
θJA to 22°C/W.
Power dissipation within the LT8601 can be estimated by
adding the power dissipated in each channel. Calculate
each channel’s power loss from an efficiency measurement and subtract the inductor loss. The die temperature
is calculated by multiplying the total LT8601 power dissipation by the thermal resistance from junction to ambient
θJA, and adding the ambient temperature. The maximum
load current should be derated as the die temperature
approaches the maximum junction rating. The LT8601 will
stop switching if the internal temperature rises too high.
This thermal protection is above the maximum operating
temperature and is intended as a failsafe only.
Even with the best thermal practices, the LT8601 must be
derated at high ambient temperature. The thermal derating curves in Figure 9 show the front page application
(Ch1: 5V, Ch2: 3.3V, Ch3: 1.8V). The PCB layout is as
described above and the θJA is 22°C/W. The output currents are decreased uniformly as a percentage of maximum. Although derating is application dependent, this set
of curves is representative of typical applications with a
range of frequencies and input voltages.
Figure 10. Thermal Derating, E and I–Grade
% OF MAX LOAD CURRENT (%)
100
80
60
40
12VIN, 1MHz
12VIN, 2.2MHz
24VIN, 1MHz
24VIN, 2.2MHz
20
0
3.5in x 3.5in 4–LAYER BOARD
2oz Cu TOP AND BOTTOM
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
LIMITED BY MAXIMUM
JUNCTION TEMPERATURE
θ JA = 22°C/W
125
8601 F09
Figure 9. Thermal Derating, E- and I-Grade
8601fa
For more information www.linear.com/LT8601
21
LT8601
Typical Applications
Details of Front Page Application
VIN
6V TO 24V
TRANSIENTS
TO 42V
VIN
C12
4.7µF
BST1
PVIN1
SW1
LT8601
C11
10µF
PVIN2
EN/UVLO
SW2
TRKSS2
L2
1.0µH
R3
316k
R4
137k
PVIN3
C5
4.7µF
PG2
CFF1
10pF
OUT1
C1 5V, 1.5A
22µF
CFF2
22pF
OUT2
C2 3.3V, 1A
47µF
R2
113k
C8
0.1µF
FB2
PG1
OUT2
R1
453k
BIAS
RUN3
R10
20k
L1
3.3µH
FB1
BST2
TRKSS1
C13
2200pF
C7
0.1µF
THE MAX CURRENT ON OUT2 IS
I(OUT2) = 2.5A – IPVIN3 – IBIAS
PG3
SW3
SYNC
POREN
L3
1.0µH
FB3
RST
INTVCC
RT
GND
R5
249k
C3
22µF
OUT3
1.8V, 1.8A
R6
200k
CPOR
R9
28.7k
CFF3
10pF
C9
4.7µF
8601 TA02a
THE VALUES SHOWN ARE FOR 2MHz OPERATION. FOR 1MHz OPERATION, MAKE THE FOLLOWING CHANGES:
L1 = 6.2μH, CFF1 = 4.7pF, L2 = 2.7μH, L3 = 2.2μH, R9 = 60.4k.
AT 1MHz OPERATION, THE INPUT VOLTAGE RANGE IS 6V TO 42V.
Sequence
Start–UpStart-Up
Sequence
VOUT1
5V/DIV
VOUT2
5V/DIV
VOUT3
2V/DIV
200µs/DIV
22
8601 TA02b
8601fa
For more information www.linear.com/LT8601
LT8601
Typical Applications
Automotive Input Steps Down to 5V, 3.3V, 1.8V
VIN
6V TO 30V
TRANSIENTS
TO 42V
VIN
C12
4.7µF
BST1
PVIN1
SW1
LT8601
C11
10µF
R11
1.75M
UVLO = 5.4V
PVIN2
SW2
TRKSS1
C13
2700pF
R10
20k
OUT2
R8
20k
OUT2
TRKSS2
UP_START
R9
47.5k
L2
2.2µH
PVIN3
PG1
PG2
R1
453k
CFF2
22pF
R3
316k
SW3
C5
4.7µF
L3
1.5µH
FB3
CPOR
RT
INTVCC
GND
OUT2
C2 3.3V, 1A
47µF
R4
137k
THE MAX CURRENT
ON OUT2 IS
I(OUT2) = 2.5A – IPVIN3 – IBIAS
PG3
POREN
OUT1
C1 5V, 1.5A
22µF
R2
113k
C8
0.1µF
FB2
RST
C10
220pF
CFF1
4.7pF
BIAS
RUN3
SYNC
SYNC INPUT
L1
4.7µH
FB1
BST2
EN/UVLO
R12
499k
C7
0.1µF
CFF3
22pF
R5
249k
OUT3
C3 1.8V, 1.8A
22µF
R6
200k
C9
4.7µF
8601 TA03a
SWITCHING FREQUENCY = 1.25MHz
Start-Up Sequence
VOUT1
5V/DIV
VOUT2
2V/DIV
VOUT3
2V/DIV
RST
2V/DIV
1ms/DIV
8601 TA03b
START-UP SEQUENCE:
CH1 AND CH2 SOFT-START
RATIOMETRICALLY;
THEN CH3 TURNS ON;
THEN POR TIMER STARTS.
8601fa
For more information www.linear.com/LT8601
23
LT8601
Package Description
Please refer to http://www.linear.com/product/LT8601#packaging for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
24
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
8601fa
For more information www.linear.com/LT8601
LT8601
Revision History
REV
DATE
DESCRIPTION
A
06/17
Clarified Resitor Value for 2MHz Switching.
PAGE NUMBER
Clarified Channels 1, 2, 3 Feedback Voltage Limits.
3
3, 4
Clarified RUN3 Threshold Upper Limits.
4
Clarified RST Pull-Up Current.
4
Clarified RT Value on Bottom Graphs.
8
Clarified Conditions for EMI Performance Graphs.
9
Clarified INTVCC (Pin 28) Description.
10
Clarified BST and SW Pin Considerations Paragraph.
16
Clarified Mode Selection and Synchronization Paragraph.
18
Clarified Values in Power-On Reset Timer Paragraph.
19
Clarified Sequencing Paragraph.
20
8601fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LT8601
25
LT8601
Typical Application
Wide Range Input Stepped Down to 5V, 2.5V and 8V (Delayed)
VIN
10V TO 24V
TRANSIENTS
TO 42V
VIN
C12
4.7µF
BST1
PVIN1
SW1
LT8601
C11
10µF
R11
2M
UVLO = 9.6V
R12
287k
R10
20k
OUT2
EN/UVLO
SW2
TRKSS2
L2
2.2µH
RUN3
PVIN3
VOUT2
5V/DIV
OUT2
5V, 1A
C2
47µF
R3
549k
C5
4.7µF
SW3
L3
1µH
CFF3
10pF
FB3
VOUT3
2V/DIV
THE MAX CURRENT
ON OUT2 IS
I(OUT2) = 2.5A – IPVIN3 – IBIAS
R5
243k
C3
47µF
CPOR
VOUT1
5V/DIV
RST
2V/DIV
2ms/DIV
OUT3
2.5V, 1.8A
8601 TA04b
START-UP SEQUENCE:
CH2 SOFT-STARTS;
THEN CH3 TURNS ON;
THEN POR TIMER STARTS;
AFTER POR TIMES OUT, THEN
CH1 STARTS.
R6
115k
RST
R9
26.1k
Start-Up Sequence
PG2
SYNC
C10
330pF
CFF2
10pF
R4
137k
PG1
OUT1
C1 8V, 1.5A
47µF
R1
1000k
R2
143k
C8
0.1µF
FB2
POREN
C14
1000pF
CFF1
10pF
BIAS
PG3
R8
20k
L1
4.7µH
FB1
BST2
TRKSS1
C13
2700pF
INTVCC
PVIN2
C7
0.1µF
INTVCC
RT
C9
4.7µF
GND
8601 TA04
SWITCHING FREQUENCY = 2.2MHz
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT8602
VIN = 3V to 42V, VOUT(MIN)= 0.8V, IQ = 25µA, ISD < 1µA,
42V, Quad Output (2.5A+1.5A+1.8A+1.8A) 95% Efficiency, 2.2MHz
Synchronous Micropower Step-Down DC/DC Converter with IQ = 25µA 6mm × 6mm QFN-40 Package
LT3507/LT3507A
36V, 2.7A + 1.8A + 1.8A + LDO Controller, 2.5MHz, High Efficiency,
Triple Output Step-Down DC/DC Converter
VIN = 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD < 1µA,
5mm × 7mm QFN
LT8640
42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA,
ISD < 1µA, 3mm × 4mm QFN
LT8614
42V, 4A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA,
ISD < 1µA, 3mm × 4mm QFN
LT8612
42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA,
ISD < 1µA, 3mm × 6mm QFN
42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower
LT8610/LT8610A/
LT8610AB/LT8610AC Step-Down DC/DC Converter with IQ = 2.5µA
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA,
ISD < 1µA, MSOP-16E
LT8611
VIN = 3.4V to 42V, VOUT(MIN) = 0.985V , IQ = 2.5µA,
ISD < 1µA, 3mm × 5mm QFN-24
26
42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower
Step-Down DC/DC Converter with IQ = 2.5µA and Input/Output
Current Limit/Monitor
8601fa
LT 0617 REV A • PRINTED IN USA
For more information www.linear.com/LT8601
www.linear.com/LT8601
 LINEAR TECHNOLOGY CORPORATION 2016