STMicroelectronics M36LLR8760D1 256 128 mbit (multiple bank, multi-level, burst) flash memory 64 mbit (burst) psram, 1.8v supply, multi-chip package Datasheet

M36LLR8760T1, M36LLR8760D1
M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY
■
■
■
■
MULTI-CHIP PACKAGE
– 1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-Level, Burst) Flash Memory
– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM
SUPPLY VOLTAGE
– VDDF1 = VDDF2 = VCCP = VDDQF = 1.7 to
1.95V
– VPPF = 9V for fast program (12V tolerant)
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Configuration (Top + Top)
M36LLR8760T1: 880Dh + 88C4h
– Mixed Configuration (Bottom + Top)
M36LLR8760D1: 880Eh + 88C4h
– Mixed Configuration (Top + Bottom)
M36LLR8760M1: 880Dh + 88C5h
– Bottom Configuration (Bottom + Bottom)
M36LLR8760B1: 880Eh + 88C5h
PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
Figure 1. Package
FBGA
LFBGA88 (ZAQ)
8 x 10mm
■
■
■
■
■
FLASH MEMORIES
■
■
■
■
SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
SYNCHRONOUS BURST READ SUSPEND
PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
MEMORY ORGANIZATION
– Multiple Bank Memory Array:
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
– Parameter Blocks (at Top or Bottom)
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for Block Lock-Down
– Absolute Write Protection with VPPF = VSS
PSRAM
■
■
■
■
ACCESS TIME: 70ns
ASYNCHRONOUS PAGE READ
– Page Size: 16 words
– Subsequent read within page: 20ns
LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
SYNCHRONOUS BURST READ/WRITE
July 2005
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
1/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FLASH MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. LFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Chip Enable Inputs (EF1, EF2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Output Enable Inputs (GF1, GF2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PSRAM Chip Enable input (EP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSRAM Configuration Register Enable (CRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDF1/VDDF2 Supply Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VCCP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VDDQF Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Main Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 6.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash 1 DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Flash 2 DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash 1 and Flash 2 DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline . . . . 15
Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data. . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SUMMARY DESCRIPTION
The
M36LLR8760T1,
M36LLR8760D1,
M36LLR8760M1 and M36LLR8760B1 combine
three memory devices in a Multi-Chip Package:
■
a 256-Mbit, Multiple Bank Flash memory, the
M30L0R8000(T/B)0 (Flash 1)
■
a 128-Mbit, Multiple Bank Flash memory, the
M58LR128GT/B (Flash 2)
■
a 64-Mbit PseudoSRAM, the M69KB096AA.
For detailed information on how to use the memory components, refer to the M30L0R8000(T/B)0,
M58LR128GT/B and M69KB096AA datasheets
which are available from your local STMicroelectronics distributor and should be read in conjunction with the M36LLR8760x1 datasheet.
What differs between the M36LLR8760T1,
M36LLR8760D1 and M36LLR8760B1 is the configuration of the two Flash memories:
■
in the M36LLR8760T1, Flash 1 and Flash 2
both have a Top Configuration (Parameter
Blocks located at the top of the address
space).
■
in the M36LLR8760D1, Flash 1 has a Bottom
Configuration (Parameter Blocks at the
bottom of the address space) and Flash 2 has
a Top Configuration.
■
In the M36LLR8760M1, Flash 1 has a Top
Configuration and Flash 2 has a Bottom
Configuration.
■
In the M36LLR8760B1, both Flash 1 and
Flash 2 have a Bottom Configuration.
4/19
Recommended operating conditions do not allow
more than one memory to be active at the same
time.
The memories are offered in a Stacked LFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) package.
In addition to the standard version, the package is
also available in Lead-free version, in compliance
with JEDEC Std J-STD-020B, the ST ECOPACK
7191395 Specification, and the RoHS (Restriction
of Hazardous Substances) directive. All packages
are compliant with Lead-free soldering processes.
The memory is supplied with all the bits erased
(set to ‘1’).
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 2. Logic Diagram
VDDQF
Table 1. Signal Names
A0-A23(1)
VPPF
VDDF1 VDDF2
VCCP
Address Inputs
DQ0-DQ15 Common Data Input/Output
L
Common Flash and PSRAM Latch
Enable Input
K
Common Flash and PSRAM Burst Clock
WAIT
Wait Data in Burst Mode for both Flash
memories and PSRAM
VDDF1
Flash 1 Power Supply
VDDF2
Flash 2 Power Supply
VDDQF
Common Flash Supply for I/O Buffers
VPPF
Common Flash Optional Supply Voltage
for Fast Program & Erase
K
VSS
Common, Ground
EP
VCCP
PSRAM Power Supply
GP
NC
Not Connected Internally
WP
DU
Do Not Use as Internally Connected
24
16
A0-A23
DQ0-DQ15
EF1
GF1
EF2
GF2
WF
RPF
WPF
L
WAIT
M36LLR8760T1
M36LLR8760D1
M36LLR8760M1
M36LLR8760B1
CRP
Flash Memory Signals
UBP
LBP
VSS
AI10908b
EF1
Flash 1 Chip Enable Input
GF1
Flash 1 Output Enable Input
EF2
Flash 2 Chip Enable Input
GF2
Flash 2 Output Enable Input
WF
Common Flash Memory Write Enable
Input
RPF
Common Flash Memory Reset input
WPF
Common Flash Memory Write Protect
Input
PSRAM Signals
EP
Chip Enable Input
GP
Output Enable Input
WP
Write Enable Input
CRP
Configuration Register Enable Input
UBP
Upper Byte Enable Input
LBP
Lower Byte Enable Input
Note: 1. A22 is an Address Input for the two Flash memories only.
A23 is for the 256Mb Flash memory component only.
5/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Figure 3. LFBGA Connections (Top view through package)
A
DU
DU
B
A4
A18
A19
VSS
VDDF1
C
A5
LBP
A23
VSS
D
A3
A17
NC
E
A2
A7
F
A1
G
DU
DU
VDDF2
A21
A11
NC
K
A22
A12
VPPF
WP
EP
A9
A13
NC
WPF
L
A20
A10
A15
A6
UBP
RPF
WF
A8
A14
A16
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
EF2
H
GP
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
GF2
J
NC
GF1
DQ9
DQ11
DQ4
DQ6
DQ15
VDDQF
K
EF1
DU
DU
NC
VCCP
VDDF2
VDDQF
CRP
L
VSS
VSS
VDDQF
VDDF1
VSS
VSS
VSS
VSS
M
DU
DU
DU
DU
AI10503b
Note: A22 is an Address Input for the two Flash memories only. A23 is for the 256Mb Flash memory component only.
6/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A23). Addresses A0-A21
are common inputs for the Flash memory and
PSRAM components. A22 is common to the two
Flash memory components whereas A23 is an address input for the 256 Mbit Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the
internal state machine. The Flash memories are
accessed through the Chip Enable signal (EF) and
through the Write Enable signal (W F), while the
PSRAM is accessed through the Chip Enable signal (EP) and the Write Enable signal (WP).
It is not allowed to have EF Low, and EP Low at the
same time.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address during a Bus Read operation or input a command or
the data to be programmed during a Bus Write operation.
For the PSRAM component, the upper Byte Data
Inputs/Outputs (DQ8-DQ15) carry the data to or
from the upper part of the selected address when
Upper Byte Enable (UBP) is driven Low. The lower
Byte Data Inputs/Outputs (DQ0-DQ7) carry the
data to or from the lower part of the selected address when Lower Byte Enable (LBP) is driven
Low. When both UBP and LBP are disabled, the
Data Inputs/ Outputs are high impedance.
Latch Enable (L). The Latch Enable pin is common to the Flash memory and PSRAM components.
For details of how the Latch Enable signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for
the PSRAM and M30L0R8000(T/B)0 and
M58LR128GT/B for Flash 1 and Flash 2, respectively.
Clock (K). The Clock input pin is common to the
Flash memory and PSRAM components.
For details of how the Clock signal behaves,
please refer to the datasheets of the respective
memory components: M69KB096AA for the
PSRAM
and
M30L0R8000(T/B)0
and
M58LR128GT/B for Flash 1 and Flash 2, respectively.
Wait (WAIT). WAIT is an output pin common to
the Flash memory and PSRAM components. However the WAIT signal does not behave in the same
way for the PSRAM and the Flash memories.
For details of how it behaves, please refer to the
M69KB096AA datasheet for the PSRAM and to
the M30L0R8000T/B0 and M58LR128GT/B
datasheets for Flash 1 and Flash 2, respectively.
Flash Chip Enable Inputs (EF1, EF2). The
Flash Chip Enable inputs activate the control logic,
input buffers, decoders and sense amplifiers of the
Flash memory component selected (EF1 is used to
select Flash 1, EF2 is used to select Flash 2).
When Chip Enable is Low, VIL, and Reset is High,
VIH, the device is in active mode. When Chip Enable is at VIH the corresponding Flash memory are
deselected, the outputs are high impedance and
the power consumption is reduced to the standby
level.
It is not allowed to have EF1 at VIL, EF2 at VIL and
EP at VIL at the same time. Only one memory component can be enabled at a time.
Flash Output Enable Inputs (GF1, GF2). The
Output Enable pins control the data outputs during
Flash memory Bus Read operations.
Flash Write Enable (WF). The Write Enable
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WPF). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, VIL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, VIH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (See the Lock Status Table in
the M30L0R8000(T/B)0 and M58LR128GT/B
datasheets).
Flash Reset (RPF). The Reset input provides a
hardware reset of the Flash memories. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current
consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash 1 DC Characteristics - Currents, for the value of IDD2. After Reset
all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the
device is in normal operation. Exiting Reset mode
the device enters Asynchronous Read mode, but
7/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH
(refer to Table 8., Flash 1 and Flash 2 DC Characteristics - Voltages).
PSRAM Chip Enable input (EP). The Chip Enable input activates the PSRAM when driven Low
(asserted). When deasserted (VIH), the device is
disabled, and goes automatically in low-power
Standby mode or Deep Power-down mode.
PSRAM Write Enable (WP). Write Enable, WP,
controls the Bus Write operation of the PSRAM.
When asserted (VIL), the device is in Write mode
and Write operations can be performed either to
the configuration registers or to the memory array.
Enable,
PSRAM Output Enable (GP). Output
GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the
common I/O data bus.
PSRAM Upper Byte Enable (UB P). The Upper
Byte En-able, UBP, gates the data on the Upper
Byte Data Inputs/Outputs (DQ8-DQ15) to or from
the upper part of the selected address during a
Write or Read operation.
PSRAM Lower Byte Enable (LBP). The Lower
Byte Enable, LBP, gates the data on the Lower
Byte Data Inputs/Outputs (DQ0-DQ7) to or from
the lower part of the selected address during a
Write or Read operation.
If both LBP and UBP are disabled (High) during an
operation, the device will disable the data bus from
receiving or transmitting data. Although the device
will seem to be deselected, it remains in an active
mode as long as EP remains Low.
PSRAM Configuration Register Enable (CR P).
When this signal is driven High, VIH, Write operations load either the value of the Refresh Configuration Register (RCR) or the Bus configuration
register (BCR).
and
VDDF1/VDDF2 Supply Voltages. VDDF1
VDDF2 provide the power supply to the internal
8/19
cores of Flash 1 and Flash 2, respectively. It is the
main power supply for all Flash memory operations (Read, Program and Erase).
VCCP Supply Voltage. VCCP provides the power
supply to the internal core of the PSRAM device. It
is the main power supply for all PSRAM operations.
VDDQF Supply Voltage. VDDQF provides the
power supply for the Flash memory. This allows all
Outputs to be powered independently of the Flash
memory and SRAM core power supplies, VDDF
and VCCP.
VPPF Program Supply Voltage. VPPF is both a
control input and a power supply pin for the Flash
memories. The two functions are selected by the
voltage range applied to the pin.
If VPPF is kept in a low voltage range (0V to VDDQF)
VPPF is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection
against Program or Erase, while VPPF > VPP1 enables these functions (see Tables 6 and 8, DC
Characteristics for the relevant values). VPPF is
only sampled at the beginning of a Program or
Erase; a change in its value after the operation has
started does not have any effect and Program or
Erase operations continue.
If VPPF is in the range of VPPH it acts as a power
supply pin. In this condition VPPF must be stable
until the Program/Erase algorithm is completed.
VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash
(core and I/O Buffers) and PSRAM chips. It must
be connected to the system ground.
Note: Each Flash memory device in a system
should have their supply voltage (VDDF) and
the program supply voltage VPPF decoupled
with a 0.1µF ceramic capacitor close to the pin
(high frequency, inherently low inductance capacitors should be as close as possible to the
package). See Figure 6., AC Measurement
Load Circuit. The PCB track widths should be
sufficient to carry the required VPPF program
and erase currents.
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
FUNCTIONAL DESCRIPTION
The PSRAM and Flash memory components have
separate power supplies but share the same
grounds. They are distinguished by three Chip Enable inputs: EF1 and EF2 for Flash 1 and Flash 2,
respectively, and EP for the PSRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read operations on one of the Flash memories and the
PSRAM which would result in a data bus contention. Therefore it is recommended to put the other
devices in the high impedance state when reading
the selected device.
Figure 4. Functional Block Diagram
VDDF1
A23
EF1
GF1
Flash 1
256 Mbit
Flash
Memory
A22
RPF
WPF
VDDF2 VPPF VDDQF
WF
A0-A21
EF2
Flash 2
GF2
128 Mbit
Flash
Memory
L
DQ0-DQ15
WAIT
K
VCCP
VSS
EP
GP
WP
64 Mbit
PSRAM
CRP
UBP
LBP
AI10909b
9/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 2. Main Operating Modes
Operation
EF(5) GF(5)
WF
LF
RPF
WAITF(4)
Flash Read
VIL
VIL
VIH
VIL(2)
VIH
Flash Write
VIL
VIH
VIL
VIL(2)
VIH
Flash Address
Latch
VIL
X
VIH
VIL
VIH
Flash Output
Disable
VIL
VIH
VIH
X
VIH
Flash Standby
VIH
X
X
X
VIH
Hi-Z
X
X
X
X
VIL
Hi-Z
Flash Reset
PSRAM Deep
Power-Down
Note: 1.
2.
3.
4.
GP
WP
LBP,UBP
PSRAM must be disabled.
Only one Flash memory can be
enabled at a time.
Both Flash memories must be disabled
PSRAM Write
Configuration
Register
PSRAM
Standby
CRP
DQ15-DQ0
Flash Data Out
PSRAM Read
PSRAM Write
EP
Any Flash memory mode is allowed. Only
one Flash memory can be enabled at a time
Any PSRAM mode is allowed.
Both Flash memories must be
disabled.
Flash Data In
Flash Data Out
or Hi-Z (3)
Hi-Z
Hi-Z
Hi-Z
VIL
VIL
VIL
VIH
VIL
PSRAM data
out
VIL
VIL
X
VIL
VIL
PSRAM data in
VIL
VIH
VIH
VIL
X
PSRAM data in
VIH
VIL
X
X
X
Hi-Z
VIH
X
X
X
X
Hi-Z
X = Don't care.
LF can be tied to VIH if the valid address has been previously latched.
Depends on GF.
WAIT signal polarity is configured using the Set Configuration Register command. See the M30L0R8000(T/B)0 and
M30L0R8000(T/B)0 datasheets for details.
5. EF is either EF1 or EF2, and GF is either GF1 or GF2 according to the Flash memory enabled. Only one Flash memory can be enabled
at a time.
10/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Value
Symbol
Parameter
Unit
Min
Max
Ambient Operating Temperature
–25
85
°C
TBIAS
Temperature Under Bias
–25
85
°C
TSTG
Storage Temperature
–65
125
°C
TLEAD
Lead Temperature During Soldering
(1)
°C
TA
VIO
VDDF1, VDDF2,
VDDQF, VCCP
VPPF
IO
tVPPFH
Input or Output Voltage
–0.5
3.6
V
Core and Input/Output Supply Voltages
–0.2
2.45
V
Flash Program Voltage
–0.2
12.6
V
Output Short Circuit Current
100
mA
Time for VPPF at VPPFH
100
hours
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 4., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Flash Memories
PSRAM
Parameter
Unit
Min
Max
Min
Max
1.7
1.95
–
–
V
VCCP Supply Voltage
–
–
1.7
1.95
V
VDDQF Supply Voltage
1.7
1.95
–
–
V
VPPF Supply Voltage (Factory environment)
8.5
9.5
–
–
V
VPPF Supply Voltage (Application environment)
–0.4
VDDQF +0.4
–
–
V
Ambient Operating Temperature
–25
85
–25
85
°C
VDDF1/VDDF2 Supply Voltages
Load Capacitance (CL)
Output Circuit Resistors (R1, R2)
30
30
pF
16.7
16.7
kΩ
Input Rise and Fall Times
5
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Figure 5. AC Measurement I/O Waveform
ns
0 to VDDQF
0 to VDDQF
V
VDDQF/2
VDDQF/2
V
Figure 6. AC Measurement Load Circuit
VDDQF
VDDQF
VDDF
VDDQF/2
VDDQF
R1
0V
DEVICE
UNDER
TEST
AI06161b
CL
0.1µF
R2
0.1µF
CL includes JIG capacitance
AI08364c
Table 5. Device Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Note: Sampled only, not 100% tested.
12/19
Test Condition
Min
Max
Unit
VIN = 0V
14
pF
VOUT = 0V
18
pF
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 6. Flash 1 DC Characteristics - Currents
Symbol
Parameter
Test Condition
Typ
Max
Unit
0V ≤ VIN ≤ VDDQF
±1
µA
±1
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
0V ≤ VOUT ≤ VDDQF
Supply Current
Asynchronous Read (f=5MHz)
EF1 = VIL, GF1 = VIH
13
15
mA
4 Word
16
18
mA
8 Word
18
20
mA
16 Word
23
25
mA
Continuous
25
27
mA
RPF = VSS ± 0.2V
50
110
µA
IDD1
Supply Current
Synchronous Read (f=54MHz)
IDD2
Supply Current
(Reset)
IDD3
Supply Current (Standby)
EF1 = VDDF1 ± 0.2V
50
110
µA
IDD4
Supply Current (Automatic Standby)
EF1 = VIL, GF1 = VIH
50
110
µA
VPPF = VPPH
8
20
mA
VPPF = VDDF1
10
25
mA
VPPF = VPPH
8
20
mA
VPPF = VDDF1
10
25
mA
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
40
mA
Program/Erase in one Bank,
Synchronous Read (Continuous
f=54MHz) in another Bank
35
52
mA
EF1 = VDDF1 ± 0.2V
50
110
µA
VPPF = VPPH
2
5
mA
VPPF = VDDF1
0.2
5
µA
VPPF = VPPH
2
5
mA
VPPF = VDDF1
0.2
5
µA
VPPF Supply Current (Read)
VPPF ≤ VDDF1
0.2
5
µA
VPPF Supply Current (Standby)
VPPF ≤ VDDF1
0.2
5
µA
Supply Current (Program)
IDD5 (1)
Supply Current (Erase)
Supply Current
IDD6 (1,2) (Dual Operations)
IDD7(1)
Supply Current Program/ Erase
Suspended (Standby)
VPPF Supply Current (Program)
IPP1(1)
VPPF Supply Current (Erase)
IPP2
IPP3(1)
Note: 1. Sampled only, not 100% tested.
2. VDDF1 Dual Operation current is the sum of read and program or erase currents.
13/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 7. Flash 2 DC Characteristics - Currents
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
Supply Current
Asynchronous Read (f=5MHz)
IDD1
Supply Current
Synchronous Read (f=54MHz)
Test Condition
Typ
Max
Unit
0V ≤ VIN ≤ VDDQF
±1
µA
0V ≤ VOUT ≤ VDDQF
±1
µA
E = VIL, G = VIH
13
15
mA
4 Word
16
18
mA
8 Word
18
20
mA
16 Word
23
25
mA
Continuous
25
27
mA
IDD2
Supply Current
(Reset)
RP = VSS ± 0.2V
25
70
µA
IDD3
Supply Current (Standby)
E = VDDQF ± 0.2V
K=VSS
25
70
µA
IDD4
Supply Current (Automatic Standby)
E = VIL, G = VIH
25
70
µA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
VPP = VPPH
8
20
mA
VPP = VDD
10
25
mA
Program/Erase in one Bank,
Asynchronous Read in another
Bank
23
40
mA
Program/Erase in one Bank,
Synchronous Read (Continuous
f=54MHz) in another Bank
35
52
mA
E = VDDQF ± 0.2V
K=VSS
25
70
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP = VPPH
2
5
mA
VPP = VDD
0.2
5
µA
VPP Supply Current (Read)
VPP ≤ VDD
0.2
5
µA
VPP Supply Current (Standby)
VPP ≤ VDD
0.2
5
µA
Supply Current (Program)
IDD5 (1)
Supply Current (Erase)
IDD6
(1,2)
IDD7(1)
Supply Current
(Dual Operations)
Supply Current Program/ Erase
Suspended (Standby)
VPP Supply Current (Program)
IPP1(1)
VPP Supply Current (Erase)
IPP2
IPP3(1)
Note: 1. Sampled only, not 100% tested.
2. VDDF2 Dual Operation current is the sum of read and program or erase currents.
14/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Table 8. Flash 1 and Flash 2 DC Characteristics - Voltages
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
VIL
Input Low Voltage
0
0.4
V
VIH
Input High Voltage
VDDQF –
0.4
VDDQF +
0.4
V
VOL
Output Low Voltage
IOL = 100µA
0.1
V
VOH
Output High Voltage
IOH = –100µA
VDDQF –
0.1
VPP1
VPPF Program Voltage-Logic
Program, Erase
1.1
1.8
3.3
V
VPPH
VPPF Program Voltage Factory
Program, Erase
8.5
9.0
9.5
V
VPPLK
Program or Erase Lockout
0.4
V
VLKO
VDDF1/F2 Lock Voltage
1
V
VRPH
RPF pin Extended High Voltage
3.3
V
V
Table 9. PSRAM DC Characteristics
Symbo
l
Max.
Uni
t
70ns
25
mA
70ns
15
mA
80MHz
35
mA
66MHz
30
mA
Operating Current:
Continuous Burst Read
80MHz
18
mA
66MHz
15
mA
ICC3W(1 Operating Current:
Continuous Burst Write
)
80MHz
35
mA
66MHz
30
mA
VCC = VCCQ or 0V,
E = VIH
120
µA
0V ≤ VIN ≤ VCC
1
µA
G = VIH or E = VIH
1
µA
Parameter
Test Condition
Operating Current: Asynchronous Random
ICC1 (1) Read/Write
ICC1P
(1)
Operating Current: Asynchronous Page Read
Operating Current:
ICC2 (1) Initial Access, Burst Read/Write
ICC3R(1)
ISB(2)
VCC Standby Current
VCC =VIH or VIL,
E = VIL,
IOUT = 0mA
Min.
Typ
ILI
Input Leakage Current
ILO
Output Leakage Current
IZZ
Deep-Power Down Current
VIH
Input High Voltage
1.4
VCCQ +
0.2
V
VIL
Input Low Voltage
−0.2
0.4
V
VOH
Output High Voltage
IOH = −0.2mA
VOL
Output Low Voltage
IOL = 0.2mA
VIN = VIH or VIL
10
µA
0.8VCC
V
Q
0.2VCCQ
V
Note: 1. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to
drive the output capacitance expected in the actual system.
2. ISB(Max) values are measured with RCR2 to RCR0 bits set to ‘000’ (full array refresh) and RCR6 to RCR5 bits set to ‘11’ (temperature compensated refresh threshold at +85°C). In order to achieve low standby current, all inputs must be driven either to VCCQ
or VSS.
3. The Operating Temperature is +25°C.
15/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PACKAGE MECHANICAL
Figure 7. LFBGA88 8x10mm, 8x10 ball array - 0.8mm pitch, Bottom View Package Outline
D
D1
e
SE
E
E2
E1
b
BALL "A1"
e
ddd
FE1 FE
FD
SD
A2
A
A1
BGA-Z45
Note: Drawing is not to scale.
Table 10. Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.400
A1
Max
0.0551
0.200
0.0079
A2
1.000
0.0394
b
0.350
0.300
0.400
0.0138
0.0118
0.0157
D
8.000
7.900
8.100
0.3150
0.3110
0.3189
D1
5.600
–
–
0.2205
–
–
ddd
16/19
Max
0.100
0.0039
E
10.000
9.900
10.100
0.3937
0.3898
0.3976
E1
7.200
–
–
0.2835
–
–
E2
8.800
–
–
0.3465
–
–
e
0.800
–
–
0.0315
–
–
FD
1.200
–
–
0.0472
–
–
FE
1.400
–
–
0.0551
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
FE1
0.600
–
–
0.0236
–
–
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
PART NUMBERING
Table 11. Ordering Information Scheme
Example:
M36 L L
R 8
7 6
0 T 1 ZAQ T
Device Type
M36 = Multi-Chip Package (Multiple Flash + RAM)
Flash 1 Architecture
L = Multi-Level, Multiple Bank, Burst mode
Flash 2 Architecture
L = Multi-Level, Multiple Bank, Burst mode
Operating Voltage
R = VDDF = VCCP = VDDQF = 1.7 to 1.95V
Flash 1 Density
8 = 256 Mbits
Flash 2 Density
7 = 128 Mbits
RAM 1 Density
6 = 64 Mbits
RAM 0 Density
0 = No Die
Parameter Blocks Location
T = Top Boot Block Flash
B = Bottom Boot Block Flash
D = Mixed (Flash 1 Bottom, Flash 2 Top)
M = Mixed (Flash 1 Top, Flash 2 Bottom)
Product Version
1 = 0.13µm Flash technology (2 Chip Enable inputs, one for each Flash memory), 85ns speed;
0.11µm PSRAM, 70ns speed, burst mode
Package
ZAQ = Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free and RoHS Standard packing
F = Lead-free and RoHS Tape & Reel packing
Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
17/19
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
REVISION HISTORY
Table 12. Document Revision History
Date
Version
29-Apr-2004
0.1
First Issue
01-Feb-2005
0.2
Part Number M69KB096A changed to M69KB096AA throughout document.
13-July-2005
0.3
VDDQ changed to VDDQF throughout the document. Table 6., Table 7., Table 8. and
Table 9. modified.
18/19
Revision Details
M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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19/19