LM5064 Negative Voltage System Power Management and Protection IC with PMBus General Description Features The LM5064 combines a high performance hot swap controller with a PMBus TM compliant SMBus/I2C interface to accurately measure, protect and control the electrical operating conditions of systems connected to a backplane power bus. The LM5064 continuously supplies real-time power, voltage, current, temperature and fault data to the system management host via the SMBus interface. The LM5064 control block includes a unique hot swap architecture that provides current and power limiting to protect sensitive circuitry during insertion of boards into a live system backplane, or any other "hot" power source. A fast acting circuit breaker prevents damage in the event of a short circuit on the output. The input under-voltage and over-voltage levels and hysteresis are configurable, as well as the insertion delay time and fault detection time. A temperature monitoring block on the LM5064 interfaces with a low-cost external diode for monitoring the temperature of the external MOSFET or other thermally sensitive components. The PGD output provides a fast indicator when the input and/or output voltages are outside their programmed ranges. The LM5064 monitoring circuit computes both the real-time and average values of subsystem operating parameters (VIN, IIN, PIN, VOUT) as well as the peak power. Accurate power averaging is accomplished by averaging the product of the input voltage and current. A black box (Telemetry/Fault Snapshot) function captures and stores telemetry data and device status in the event of a warning or a fault. ■ Input voltage range: -10V to -80V ■ Programmable 26 mV or 50 mV current limit threshold with power limiting (MOSFET power dissipation limiting) ■ Real time monitoring of VIN, VOUT, IIN, PIN, VAUX with 12-bit resolution and 1 kHz sampling rate ■ Configurable circuit breaker protection for hard shorts ■ Configurable under-voltage and over-voltage protection ■ Remote temperature sensing with programmable warning ■ ■ ■ ■ ■ ■ ■ ■ ■ and shutdown thresholds Detection and notification of damaged MOSFET condition Power measurement accuracy: ±4.5% over temperature True input power averages dynamic power readings Averaging of VIN, IIN, PIN, and VOUT over programmable interval ranging from 0.001 to 4 seconds Programmable WARN and FAULT thresholds with SMBA notification Black box capture of telemetry measurements and device status triggered by WARN or FAULT condition I2C/SMBus interface and PMBus compliant command structure Full featured application development software eTSSOP-28 package Applications ■ Base Station Power Distribution Systems ■ Intelligent Solid State Circuit Breaker ■ -24V/-48V Industrial Systems Typical Application Circuit 301584001 © 2012 Texas Instruments Incorporated 301584 SNVS718C www.ti.com LM5064 Negative Voltage System Power Management and Protection IC with PMBusTM October 22, 2011 LM5064 Connection Diagram 301584002 Top View 28-Lead eTSSOP 9.7 mm x 4.4 mm x 0.9 mm NS Package Number MXA28A Ordering Information Order Number Package Type NSC Package Drawing Supplied As LM5064PMH NOPB eTSSOP-28 MXA28A 48 units in anti-static rail LM5064PMHE NOPB 250 units in tape and reel LM5064PMHX NOPB 2,500 units in tape and reel www.ti.com 2 LM5064 Pin Descriptions Pin# Name 1 VCC Description 2 VAUXH 3 NC 4 GATE MOSFET gate control signal for fault control of the output. The GATE pin is clamped to VEE through a 12.6V internal zener diode. 5 UVLO/EN Under-voltage lockout threshold input. Connecting the UVLO pin to a resistor divider from VCC to VEE will set the under-voltage lockout threshold. After the UVLO pin voltage falls below 2.48V, an internal 20 µA current source is switched to provide a user settable hysteresis. The UVLO pin can be toggled directly to act as a precision enable. After the UVLO threshold voltage is exceeded, the output voltage will begin to transition to VVEE as the GATE pin supplies 52 µA to turn on the MOSFET. 6 OVLO Over-voltage lockout threshold input. Connecting the OVLO pin to a resistor divider from VCC to VEE will set the over-voltage lockout threshold. After the OVLO pin voltage exceeds 2.47V, an internal 21 µA current source is switched to provide a user settable hysteresis. If the OVLO threshold is exceeded, the MOSFET will be immediately disabled to protect the output. 7 SENSE Current limit and power limit sense input. SENSE provides a direct connection to the MOSFET source and current sense resistor voltage to detect current limit and power limit events. This unfiltered signal will allow the LM5064 to quickly respond during over-current or over-power events. 8 SENSE_K Current telemetry Kelvin sense positive input. SENSE_K is the positive input to a precision differential current sense amplifier. Connecting SENSE_K to the positive terminal of the current sense resistor will provide an accurate current telemetry signal. 9 VEE_K Current telemetry Kelvin sense negative input. The VEE_K pin is the negative input to a precision differential current sense amplifier. Connecting VEE_K to the negative terminal of the current sense resistor will provide an accurate current signal. 10 VEE Negative supply input. Connect the VEE pin to the negative voltage supply rail. Use a small ceramic bypass capacitor (0.1 µF) from the VEE pin to the VCC pin to suppress transient current spikes when the load switch is turned off. The operational voltage range for the VEE pin is -10V to -80V. The VEE pin absolute maximum voltage is -100V. 11 SDAI SMBus data input. The SDAI pin is designed to read PMBus commands using the SMBus communication protocol. SDAI can be connected to SDAO if desired. 12 SDAO SMBus data output. The SDAO pin is designed to transmit PMBus commands using the SMBus communication protocol. SDAO can be connected to SDAI if desired. Positive supply input. Connect the VCC pin to the positive voltage rail. High voltage auxiliary input. VCC with respect to VEE is measured by connecting the VAUXH pin to the VCC rail. No connect. This pin is not internally connected and should not be connected to any signal or power rail. 13 SCL 14 SMBA SMBus clock input. SMBus alert. This pin is connected to an open drain MOSFET which pulls the pin to VEE if a fault is detected. 15 VREF Internal ADC reference output. Connect a 1 µF capacitor from the VREF pin to VEE to filter noise imposed on the internal reference output. 16 DIODE Positive diode sense. The DIODE pin should be connected to the anode of a diode whose cathode is connected to VEE for temperature monitoring. 17 VAUX Auxiliary pin allows voltage telemetry from an external source. Full scale input of 2.97V. 18 ADR2 Address pin 2. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the LM5064. 19 ADR1 Address pin 1 The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the LM5064. 20 ADR0 Address pin 0. The address pins can be connected to VDD, VEE, or left open to set the PMBus address of the LM5064. 21 VDD Internal 4.9V sub-regulator output. VDD must be connected and closely coupled to VEE through a 1 µF ceramic bypass capacitor. 22 CL Current limit threshold input. The LM5064 detects current limit events by sensing the voltage across a series resistor. The current limit threshold is set to 26 mV by connecting CL to VDD and 50 mV when CL is connected to VEE. 23 RETRY Retry selction pin. Connecting RETRY to VDD sets the LM5064 to lockout after a fault condition is detected. Connecting RETRY to VEE sets the LM5064 to retry after a fault condition. 3 www.ti.com LM5064 Pin# Name Description 24 TIMER Timing input. Set the insertion time delay and the fault timeout period by connecting a capacitor from the TIMER pin to VEE. The restart time is also set through the TIMER pin when in restart mode. 25 PWR Power limit input. Connecting a resistor from PWR to VEE sets the maximum power dissipation allowed in the external MOSFET switch. Power is calculated using the current information through the current sense resistor and voltage sensed across the MOSFET. 26 OUT Output voltage sense input. The OUT pin is used to sense the output voltage and calculate the power across the MOSFET switch. 27 NC 28 PGD EP EP www.ti.com No connect. This pin is not internally connected and should not be connected to any signal or power rail. Power good monitor output. Open-drain output pulls low during over-current, UVLO, and OVLO. An external pull-up resistor to VDD or external rail is required. Exposed pad. Connect to PCB VEE plane using multiple thermal vias. 4 If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VCC, UVLO/EN, OUT, VAUXH, PGD to VEE GATE to VEE OVLO, TIMER, PWR to VEE SENSE_K, SENSE, VEE_K to VEE SCL, SDAI, SDAO, SMBA, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY , VREF to VEE -0.3V to 100V Operating Ratings -0.3V to 16V -0.3V to 7V -0.3V to +0.3V -0.3V to 6V VCC supply voltage above VEE OUT voltage above VEE PGD off voltage above VEE Junction temperature 2 kV -65°C to 150°C 150°C 10V to +80V 0V to +80V 0V to +80V −40°C to + 125°C Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VCC-VEE = 48V. See (Note 1, Note 3) . Symbol Parameter Conditions Min Typ Max Units Input (VCC) IIN-EN Input current, enabled VCC - VEE = 48V, UVLO/EN = 5V 6 8 mA PORIT Threshold voltage to start insertion timer VCC - VEE increasing 8 9.2 V POREN Threshold voltage to enable all functions VCC - VEE increasing 8.7 9.9 V POREN hysteresis VCC - VEE decreasing 170 mV IOUT-EN OUT bias current, enabled Enabled, OUT = VEE -100 nA IOUT-DIS OUT bias current, disabled (Note 4) Disabled, OUT = VEE + 48V 135 µA UVLOTH UVLO/EN threshold UVLO/EN Falling UVLOHYS UVLO/EN hysteresis current UVLO/EN = VEE + 2V UVLODEL UVLO delay UVLOBIAS UVLO/EN bias current POREN-HYS Output (OUT) OVLO/UVLO 2.41 2.48 2.55 V 13 20 26 µA Delay to GATE high 9 Delay to GATE low 12 UVLO/EN = VEE + 5V OVLOTH OVLO threshold OVLOHYS OVLO hysteresis current OVLO = VEE + 2.8V OVLODEL OVLO delay Delay to GATE high 10 Delay to GATE low 12 OVLOBIAS OVLO bias current OVLO = 2.3V Power limit sense voltage (OUT-SENSE) OUT – SENSE = 48V, RPWR = 145 kΩ µs µs 1 µA 2.39 2.47 2.53 V -26 -21 -13 µA µs µs 1 µA 29.5 mV Power Limit (PWR) PWRLIM-1 PWRLIM-2 IPWR RSAT(PWR) 19.5 OUT - SENSE = 24V, RPWR = 75 kΩ 24.5 24.7 mV PWR pin current VPWR = 2.5V -18 µA PWR pin impedance when disabled UVLO/EN = 2.0V 140 Ω Gate Control (GATE) IGATE VGATE Source current Normal Operation -72 -52 -32 µA Sink current UVLO/EN < VEE+2V 3.4 4.1 5.3 mA SENSE - VEE =150 mV, VGATE =VEE+5V 50 111 180 mA Gate output voltage in normal GATE-VEE Voltage operation 5 12.6 V www.ti.com LM5064 ESD Rating Human Body Model(Note 2) Storage Temperature Junction Temperature Absolute Maximum Ratings (Note 1) LM5064 Symbol Parameter Conditions Min Typ Max Units VCL Current limit threshold voltage CL = VDD (Note 6) 23 26 30 mV VCL Current limit threshold voltage CL = VEE or FLOAT (Note 6) 47 50 53 mV tCL Response time SENSE-VEE stepped from 0 mV to 80 mV SENSE input current Current Limit ISENSE ISENSE_K IVEE_K 54 µs Enabled, OUT = VEE -5 µA Disabled, OUT = VCC -55 µA SENSE_K input current -10 µA VEE_K input current -10 µA Circuit Breaker RTCB Circuit breaker to current limit CB/CL ratio bit = 0, ILim = 50 mV ratio: (VSENSE-VVEE)/VCL CB/CL ratio bit = 1, ILim = 50 mV 1.45 1.9 2.22 2.8 3.7 4.9 CB/CL ratio bit = 0, ILim = 26 mV 1.8 CB/CL ratio bit = 1, ILim = 26 mV VCB tCB Circuit breaker threshold voltage: (VSENSE-VVEE) 3.6 CB/CL ratio bit = 0, ILim = 50 mV 72 93 116 mV CB/CL ratio bit = 1, ILim = 50 mV 144 187 230 mV CB/CL ratio bit = 0, ILim = 26 mV 37 49 59 mV CB/CL ratio bit = 1, ILim = 26 mV 72 93 116 mV Circuit breaker response time SENSE-VEE stepped from 0 mV to 150 mV, time to GATE = VEE 800 ns Timer (TIMER) VTMRH Upper threshold VTMRL Lower threshold ITIMER Restart cycles V 1.39 V 0.3 0.3 SENSE-VEE=VCL Fault sink current tFAULT 4.07 1.2 Re-enable threshold Sink current, end of insertion TIMER pin = VEE+2V time DCFAULT 3.9 1.09 End of 8th cycle Insertion time current Fault detection current 3.74 V -5.9 -4.8 -3.3 µA 1 1.5 2 mA -95 -74 -50 µA 1.7 2.4 3.2 µA Fault restart duty cycle Fault to GATE = VEE delay V TIMER pin reaches the upper threshold 0.5 % 15 µs Power Good (PGD) PGDTH Threshold measured at OUT OUT – SENSE Decreasing - SENSE OUT – SENSE Increasing PGDVOL Output low voltage ISINK = 2 mA PGDIOH Off leakage current VPGD = 80V 1.18 1.24 1.31 2.44 2.5 2.56 V V 50 150 mV 5 µA ADC and MUX Resolution INL tACQUIRE tRR Integral non-linearity ADC only Acquisition + conversion time Any Channel Acquisition round robin time Cycle all channels 12 Bits ±4 LSB 100 µs 1 ms Internal Reference VREF Reference voltage 2.93 2.97 3.02 V Telemetry Accuracy (Note 8) IINFSR Current input full scale range CL= VEE (Note 6) IINLSB Current input LSB www.ti.com 74.9 mV CL = VDD (Note 6) 38.1 mV CL= VEE (Note 6) 18.3 µV CL = VDD (Note 6) 9.3 µV 6 Parameter VAUXFSR VAUX input full scale range 2.96 V VAUXLSB VAUX input LSB 724 µV VAUXHFSR VAUXH input full scale range 88.9 V VAUXHLSB VAUXH input LSB 21.7 mV OUTLSB Conditions Min OUT pin LSB Typ Max 21.7 Units mV IINACC Input current accuracy SENSE_K-VEE_K = 50 mV, CL = VEE (Note 6) -3.0 3.0 % VACC VAUX, VAUXH, OUT VAUXH-VEE=48V,OUT - VEE= 48V, VAUX = 2.8V -2.7 2.7 % PINACC Input power accuracy VCC-VEE = 48V, SENSE_K-VEE_K = 50 mV, CL -4.5 = VDD 4.5 % Diode Temperature Sensor TACC IDIODE Temperature accuracy using TA = 25°C to 85°C local diode 2 °C Remote diode resolution 9 bits External diode current source High Level 250 Low Level 9.4 Diode current ratio 325 µA µA 25.9 VAUX IIN Input current VAUX = 3V VDD regulated output IDD = 0 mA 1 µA 5.15 V -42 mA VDD Regulation VDDOUT 4.6 IDD = -10 mA VDDILIM VDD current limit VDDPOR VDD voltage reset threshold VDD Rising 4.9 4.8 VDD = 0V -25 -30 V 4.1 V PMBus Pin Thresholds (SCL, SDAI/O, SMBA) (Note 7) VIL Data, clock input low voltage With respect to VEE VIH Data, clock input high voltage With respect to VEE VOL Data output low voltage ISINK = 3 mA ILEAK Input leakage current SDAI, SMBA, SCL = 5V above VEE 0.9 V 2.1 5.5 V 0 0.4 µA 1 µA Pin Strappable Thresholds (CL, RETRY) VIH ILEAK Input high voltage Input leakage current V 3 CL,RETRY = 5V 5 µA Thermal (Note 5) θJA Junction to ambient 30 °C/W θJC Junction to case 4 °C/W Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV rating for all pins except GATE and PGD which are rated at 1.5 kV and 1 kV respectively. Note 3: Current out of a pin is indicated as a negative value. Note 4: OUT bias current (disabled) due to leakage current through an internal 1 MΩ resistance from SENSE to OUT. Note 5: Junction to ambient thermal resistance is highly application and board layout dependent. Specified thermal resistance values for the package specified is based on a 4-layer, 4"x3", 2/1/1/2 oz. Cu board as per JEDEC standards is used. For detailed information on soldering plastic eTSSOP packages refer to the Packaging Data Book available from National Semiconductor Corporation. Note 6: CL bit High or Low is set by either the CL pin on startup (if CL = VDD, then High, if CL = VEE or FLOAT, then Low) or by the current limit setting bit in the device setup register. Note 7: PMBus communication clock rate at final test is 400 kHz. Note 8: Full scale range depends on both the VREF value and the gain/attenuation of the current/voltage channel. 7 www.ti.com LM5064 Symbol Unless otherwise specified the following conditions apply: TJ = 25°C, VCC-VEE = 48V. VCC Pin Current VEE_K Pin Current (Enabled) 6.2 -9.2 VCC = 80V 6.0 VEE_K PIN CURRENT (μA) VCC INPUT CURRENT (mA) 6.4 VCC = 48V 5.8 VCC = 9V 5.6 5.4 5.2 -50 -9.4 -9.6 -9.8 -10.0 -10.2 -10.4 -10.6 -25 0 25 50 75 TEMPERATURE (°C) 100 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584004 301584006 SENSE Pin Current OUT Pin Current (Disabled) 240 210 -4.75 OUT PIN CURRENT (μA) SENSE PIN CURRENT (μA) -4.70 -4.80 -4.84 -4.90 -4.95 -50 VCC = 80V 180 VCC = 48V 150 120 90 60 VCC = 9V 30 -5.00 0 -25 0 25 50 75 100 125 TEMPERATURE (°C) -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584005 301584008 SENSE_K Pin Current (Enabled) GATE Output Voltage (VGATE) -9.0 15 -9.3 14 -9.6 GATE PIN VOLTAGE (V) SENSE_K PIN CURRENT (μA) LM5064 Typical Performance Characteristics -9.9 -10.2 -10.5 -10.8 -11.1 -11.4 12 VCC - VEE = 48V 11 10 9 8 VCC - VEE = 9V 6 -25 0 25 50 75 100 125 TEMPERATURE (°C) -50 301584057 www.ti.com 13 7 -11.7 -12.0 -50 VCC - VEE = 80V -25 0 25 50 75 TEMPERATURE (°C) 100 125 301584009 8 UVLO Hysteresis Current UVLO HYSTERESIS CURRENT (μA) GATE PIN SOURCE CURRENT (μA) 20.4 -51.7 -51.8 -51.9 -52.0 -52.1 -52.2 -50 LM5064 GATE Pin Source Current -51.6 -25 0 25 50 75 100 125 TEMPERATURE (°C) 20.2 20.0 19.8 19.6 19.4 19.2 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584010 301584013 VSNS (SENSE_K-VEE_K) at Power Limit Threshold RPWR = 75 kΩ OVLO Threshold 2.480 30 OVLO THRESHOLD (V) VSNS VOLTAGE (mV) VCC-VEE=48V, CL = VEE 25 20 VCC-VEE=24V, CL = VDD 15 10 2.475 2.470 2.465 2.460 2.455 2.450 5 -50 -50 -25 0 25 50 75 TEMPERATURE (°C) -25 100 125 0 25 50 75 100 125 TEMPERATURE (°C) 301584014 OVLO Hysteresis Current 301584011 UVLO Threshold OVLO HYSTERESIS CURRENT (μA) 2.490 UVLO THRESHOLD (V) 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) -19.9 -20.0 -20.1 -20.2 -20.3 -20.4 -20.5 -20.6 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584015 301584012 9 www.ti.com LM5064 IIN Measurement Accuracy (SENSE_K-VEE_K = 50 mV) Current Limit Threshold 1.6 CL = VEE 50 1.2 CL=VEE 0.8 45 IIN ERROR (%) CURRENT LIMIT THRESHOLD (V) 55 40 35 30 CL = VDD 0.4 0.0 -0.4 -0.8 25 -1.2 20 -1.6 -50 -25 0 25 50 75 TEMPERATURE (°C) -50 100 125 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584018 301584058 PIN Measurement Accuracy (SENSE_K-VEE_K = 50 mV) 200 1.0 180 0.8 160 0.6 CL = VEE, CB/CL BIT = HIGH PIN ERROR (%) CIRCUIT BREAKER THRESHOLD (mV) Circuit Breaker Threshold 140 120 100 CL = VEE, CB/CL BIT = LOW 80 60 0.2 0.0 -0.2 -0.4 -0.6 CL = VDD, CB/CL BIT = LOW -0.8 -1.0 40 -50 CL=VEE 0.4 -25 0 25 50 75 TEMPERATURE (°C) -50 100 125 -25 0 25 50 75 100 125 TEMPERATURE (°C) 301584016 301584019 Startup (Insertion Delay) Reference Voltage 2.976 2.974 VREF (V) 2.972 2.970 2.968 2.966 2.964 2.962 -50 301584021 -25 40 ms/div 0 25 50 75 100 125 TEMPERATURE (°C) 301584017 www.ti.com 10 LM5064 Short Circuit VOUT Startup (PGD) 301584025 301584022 1s/div 400 ms/div Startup (1A Load) Current Limit Event (CL = VDD) 301584026 301584023 40 ms/div 4 ms/div Startup (UVLO/EN, OVLO) Circuit Breaker Event (CL = VDD) 301584027 400 µs/div 301584024 400 ms/div 11 www.ti.com LM5064 Retry Event (RETRY = VEE) Latch Off (RETRY = VDD) 301584028 301584029 400 ms/div www.ti.com 100 ms/div 12 LM5064 Block Diagram 301584003 FIGURE 1. Block Diagram 13 www.ti.com LM5064 301584096 FIGURE 2. Typical Application Circuit nals to the IC are referenced to the VEE voltage which acts as the effective return path for the IC. Functional Description The LM5064 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply and the dv/dt of the voltage applied to the load. The effect from the insertion event on other circuits in the system is minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM5064. In addition to a programmable current limit, the LM5064 monitors and limits the maximum power dissipation in the series pass device (Q1) to maintain operation within the device’s Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time (user defined) results in the shutdown of the series pass device. In this event, the LM5064 can latch off or repetitively retry based on the hardware setting of the RETRY pin. Once started, the number of retries can be set to 0, 1, 2, 4, 8, 16, or infinite. The circuit breaker function quickly switches off the series pass device upon detection of a severe over-current condition. Programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) circuits shut down the LM5064 when the system input voltage (VSYS) is outside the desired operating range. The telemetry capability of the LM5064 provides intelligent monitoring of the input voltage, output voltage, input current, input power, temperature, and an auxiliary input. The LM5064 also provides a peak capture of the input power and programmable hardware averaging of the input voltage, current, power, and output voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage, current, power and temperature via the PMBus interface. Additionally, the LM5064 is capable of detecting damage to the external MOSFET, Q1. Power Up Sequence Referring to Figure 2 and Figure 3, as the system voltage (VSYS) initially increases, the external N-channel MOSFET (Q1) is held off by an internal 111 mA pull-down current at the GATE pin. The strong pull-down current at the GATE pin prevents an inadvertent turn on as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at VEE. When the operating voltage of the LM5064 (VCC - VEE) reaches the PORIT threshold, the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8 µA current source, and Q1 is held off by a 4.1 mA pull-down current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing and transients on VSYS to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 3.9V. CT is then quickly discharged by an internal 1.5 mA pull-down current. The GATE pin then switches on Q1 when the operating voltage exceeds the UVLO threshold. If the operating voltage is above the UVLO threshold at the end of the insertion time,(t1 in Figure 3) the GATE pin sources 52 µA to charge the gate capacitance of Q1. The maximum voltage on GATE is limited by an internal 12.6V zener diode to VEE. As the voltage at the OUT pin transitions to VSYS, the LM5064 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the inrush limiting interval (t2 in Figure 3), an internal 74 µA fault timer current source charges CT. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 3.9V, the 74 µA current source is switched off, and CT is discharged by the internal 2.4 µA current sink (t3 in Figure 3). The in-rush limiting will no longer engage unless a current-limit condition occurs. If the TIMER pin voltage reaches 3.9V before in-rush current limiting or power limiting ceases during t2, a fault is declared Operating Voltage The LM5064 operating voltage is the voltage supplied between VCC and VEE (VCC-VEE) which has an operating range of 10V to 80V with a 100V transient capability. All sig- www.ti.com 14 The CONFIG_PRESET bit within the MFR_SPECIFIC_17 register (E1h) indicates default configuration of warning thresholds and device operation and will remain high until a CLEAR_FAULTS command is received. 301584031 FIGURE 3. Power Up Sequence rent or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 3.9V, the TIMER pin capacitor then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the TIMER pin reached 3.9V during t2, the GATE pin is then pulled low by the 4.1 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (RETRY pin to VDD), an automatic retry is attempted (RETRY pin to VEE or floating), or a PMBus ON/OFF command is intiated. See the Fault Timer & Restart section. If the operating voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 4.1 mA pull-down current to switch off Q1. Gate Control A current source provides the charge at the GATE pin to enhance the N-Channel MOSFET’s gate (Q1). During normal operating conditions (t3 in Figure 3) the gate of Q1 is held charged by an internal 52 µA current source. The GATE pin peak voltage is roughly 12.6V, which will force a VGS across Q1 of 12.6V under normal operation. When the system voltage is initially applied, the GATE pin is held low by a 111 mA pull-down current. This helps prevent an inadvertent turn on of Q1 through its drain-gate capacitance as the applied system voltage increases. During the insertion time (t1 in Figure 3), the GATE pin is held low by a 4.1 mA pull-down current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage on VSYS or UVLO/EN. Following the insertion time, during t2 in Figure 3, the gate voltage of Q1 is modulated to keep the cur15 www.ti.com LM5064 and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault mode. The LM5064 will assert the SMBA pin after the operating voltage has exceeded the POR threshold to indicate that the volatile memory and device settings are in their default state. LM5064 PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be asserted unless this feature is disabled using the ALERT_MASK (D8h) register. Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (SENSE to VEE) exceeds the internal voltage limit of 26 mV or 50 mV depending on whether the CL pin is connected to VDD or VEE, respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5064 resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper operation, the RS resistor value should be no higher than 200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h). Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the gate-tosource voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, a 74 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 3(Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period before the TIMER pin reaches 3.9V, the LM5064 returns to the normal operating mode and CT is discharged by the 1.5 mA current sink. If the TIMER pin reaches 3.9V during the Fault Timeout Period, Q1 is switched off by a 4.1 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on the selected retry configuration. If the RETRY pin is high (VDD), the LM5064 latches the GATE pin low at the end of the Fault Timeout Period. CT is then discharged to VEE by the 2.4 µA fault current sink. The GATE pin is held low by the 4.1 mA pull-down current until a power up sequence is externally initiated by cycling the operating voltage (VCC-VEE), or momentarily pulling the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 4. The voltage at the TIMER pin must be <0.3V for the restart procedure to be effective. The TIMER_LATCHED_OFF bit in the DIAGNOSTIC_WORD (E1h) register will remain high while the latched off condition persists. Circuit Breaker If the load current increases rapidly (e.g., the load is short circuited), the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds 1.9x or 3.7x (CL = VEE) the current limit threshold, Q1 is quickly switched off by the 111 mA pull-down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below the circuit breaker (CB) threshold, the 111 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9V before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.1 mA pull-down current at the GATE pin as described in the Fault Timer & Restart section. A circuit breaker event will cause the CIRCUIT_BREAKER_FAULT bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers to be toggled high, and SMBA pin will be asserted unless this feature is disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits in the DEVICE_SETUP (D9h) register. 301584032 Power Limit FIGURE 4. Latched Fault Restart Control An important feature of the LM5064 is the MOSFET power limiting. The power limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5064 determines the power dissipation in Q1 by monitoring its drain-source voltage (OUT to SENSE), and the drain current through the RS (SENSE to VEE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the power limit condition persists for longer than the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/ www.ti.com The LM5064 provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9V and 1.2V eight times after the Fault Timeout Period, as shown in Figure 5. The period of each cycle is determined by the 74 µA charging current, and the 2.4 µA discharge current, and the value of the capacitor CT. When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 52 µA current source at the GATE pin turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The RETRY pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by setting the appropriate bits in the DEVICE_SETUP (D9h) register. 16 LM5064 301584033 FIGURE 5. Restart Sequence VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA pin will be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. Under-Voltage Lockout (UVLO) The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range defined by the programmable under-voltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically, the UVLO level at VSYS is set with a resistor divider (R1-R3) as shown in Figure 6. Referring to the Block Diagram when VSYS is below the UVLO level, the internal 20 µA current source at UVLO/EN is enabled, the current source at OVLO is off, and Q1 is held off by the 4.1 mA pull-down current at the GATE pin. As VSYS is increased, raising the voltage at UVLO/EN above its threshold with respect to VEE, the 20 µA current source at UVLO/ EN is switched off, increasing the voltage at UVLO/EN, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q1 is switched on by the 52 µA current source at the GATE pin if the insertion time delay has expired. See the Applications Section for a procedure to calculate the values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at VSYS can be set by connecting the UVLO/EN pin to VCC. In this case Q1 is enabled after the insertion time when the operating voltage (VCC-VEE) reaches the POR threshold. After power up an UVLO condition will cause the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin will be pulled low unless this feature is disabled using the ALERT_MASK (D8h) register. Shutdown Control The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open collector or open drain device, as shown in Figure 6. Upon releasing the UVLO/EN pin the LM5064 switches on the load current with in-rush current and power limiting. 301584034 FIGURE 6. Shutdown Control Over-Voltage Lockout (OVLO) Power Good Pin The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range defined by the programmable under-voltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If VSYS raises the OVLO pin voltage above its threshold (2.47V above VEE), Q1 is switched off by the 4.1 mA pull-down current at the GATE pin, denying power to the load. When the OVLO pin is above its threshold, the internal 21 µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When VSYS is reduced below the OVLO level Q1 is re-enabled. An OVLO condition will toggle the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h) register and the The Power Good output indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET. An external pullup resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin must be more positive than VEE, and can be up to 80V above VEE with transient capability to 100V. PGD is switched high at the end of the turn-on sequence when the voltage from OUT to SENSE (the external MOSFET’s VDS) decreases below 1.24V. PGD switches low if the MOSFET’s VDS increases passed 2.5V, if the system input voltage goes below the UVLO threshold or above the OVLO threshold, or if a fault is detected. However, the PGD output cannot stay low when the operating voltage (VCC-VEE) is less than 2V. 17 www.ti.com LM5064 could read a value higher than the OT_FAULT_LIMIT, and will trigger a fault, disabling Q1. In this case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION (01h) register. VDD Sub-Regulator The LM5064 contains an internal linear sub-regulator which steps down the VCC voltage to generate a 4.9V rail (above VEE) used for powering low voltage circuitry. The VDD subregulator should be used as the pull-up supply for the CL, RETRY, ADR2, ADR1, ADR0 pins if they are to be tied high. It may also be used as the pull-up supply for the PGD and the SMBus signals (SDA, SCL, SMBA). The VDD sub-regulator is not designed to drive high currents. Careful consideration of internal power dissipation should be practiced when VDD is loaded with other integrated circuits. The VDD pin is current limited to 30 mA in order to protect the LM5064 in the event of a short. The sub-regulator requires a ceramic bypass capacitance (terminated to VEE) having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows. Damaged MOSFET Detection The LM5064 is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h) registers will be toggled high and the SMBA pin will be asserted unless this feature is disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted because of damage present between the drain and gate and/or drain and source. Remote Temperature Sensing Enabling/Disabling and Resetting The LM5064 is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and collector of the MMBT3904 should be connected to the DIODE pin and the emitter to VEE. Place the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The temperature is measured by means of a change in the diode voltage in response to a step in current supplied by the DIODE pin. The DIODE pin sources a constant 9.4 µA but pulses 250 µA once every millisecond in order to measure the diode temperature. Care must be taken in the PCB layout to keep the parasitic resistance between the DIODE pin and the MMBT3904 low so as not to degrade the measurement. Additionally, a small 1000 pF bypass capacitor should be placed in parallel with the MMBT3904 (collector to emitter) to reduce the effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The default limits of the LM5064 will cause SMBA pin to be pulled low if the measured temperature exceeds 125°C and will disable Q1 if the temperature exceeds 150°C. These thresholds can be reprogrammed via the PMBus interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the LM5064 are not used, the DIODE pin should be connected to VEE. Erroneous temperature measurements may result when the device input voltage is below the minimum operating voltage (10V) due to VREF dropping out below the nominal voltage (2.97V). At higher ambient temperatures, this measurement www.ti.com The output can be disabled at any time during normal operation by either pulling the UVLO/EN pin to below its threshold or the OVLO pin above its threshold, causing the GATE voltage to be forced low with a pull-down strength of 4.1 mA. Toggling the UVLO/EN pin will also reset the LM5064 from a latched-off state due to an over-current or over-power limit condition which has caused the maximum allowed number of retries to be exceeded. While the UVLO/EN or OVLO pins can be used to disable the output they have no effect on the volatile memory or address location of the LM5064. User stored values for address, device operation, and warning and fault levels programmed via the SMBus are preserved while the LM5064 is powered regardless of the state of the UVLO/ EN and OVLO pins.The output may also be enabled or disabled by writing 80h or 0h to the OPERATION (01h) register. To re-enable after a fault, the fault condition should be cleared and the OPERATION (01h) register should be written with a 0h and then 80h. The SMBus address of the LM5064 is captured based on the states (VEE, NC, VDD) of the ADR0, ADR1, and ADR2 pins during turn-on and is latched into a volatile register once VDD has exceeded its POR threshold of 4.1V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to VEE. Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM5064. Once released, the VREF pin will charge up to its final value and the address will be latched into a volatile register once the voltage at the VREF exceeds 2.55V. 18 LM5064 Application Section 301584030 FIGURE 7. Typical Application Circuit occur when the circuit card, or adjacent cards, are inserted or removed. - The maximum continuous current rating should be based on the current limit threshold (e.g., 26 mV/RS for CL = VDD), not the maximum load current, since the circuit can operate near the current limit threshold continuously. - The Pulsed Drain Current spec (IDM) must be greater than the current threshold for the circuit breaker function (49/93/187 mV/RS, depending on CL and CB configuration). - The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine the maximum power dissipation threshold set by the RPWR resistor. The programmed maximum power dissipation should have a reasonable margin from the maximum power defined by the MOSFET’s SOA curve. If the device is set to infinitely retry, the MOSFET will be repeatedly stressed during fault restart cycles. The MOSFET manufacturer should be consulted for guidelines. - RDS(on) should be sufficiently low such that the power dissipation at maximum load current (ILIM2 x RDS(on)) does not raise its junction temperature above the manufacturer’s recommendation. - The gate-to-source voltage provided by the LM5064 can be as high as 12.6V. Q1 must be able to tolerate this voltage for its VGS rating. An additional zener diode can be added from GATE to VEE to lower this voltage and limit the peak VGS. DESIGN-IN PROCEDURE Refer to Figure 7 for Typical Application Circuit. The following is a step-by-step procedure for hardware design of the LM5064. This procedure refers to section numbers that provide detailed information on the following design steps. The recommended design-in procedure is as follows: MOSFET Selection: Determine the MOSFET based on breakdown voltage, current and power ratings. Current Limit, RS: Determine the current limit threshold (ILIM). This threshold must be higher than the normal maximum load current, allowing for tolerances in the current sense resistor value and the LM5064 Current Limit threshold voltage. Use (1) to determine the value for RS. Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q1), using the device’s SOA information. Use (2) to determine the value for RPWR. Note that many MOSFET manufacturers do not accurately specify the device SOA so it is usually beneficial to choose a conservative value when selecting RPWR. Turn-on Time and TIMER Capacitor, CT: Determine the value for the timing capacitor at the TIMER pin (CT) using equation 7 and 8. The fault timeout period (tFAULT) MUST be longer than the circuit’s turn-on time. The turn-on time can be estimated using the equations in the TURN-ON TIME section of this data sheet, but should be verified experimentally. Review the resulting insertion time and the restart timing if retry is enabled. UVLO, OVLO: Choose option A, B, C, or D from the UVLO, OVLO section of the Application Information to set the UVLO and OVLO thresholds and hysteresis. Use the procedure for the appropriate option to determine the resistor values at the UVLO/EN and OVLO pins. CURRENT LIMIT (RS) The LM5064 monitors the current in the external MOSFET Q1 by measuring the voltage across the sense resistor (RS), connected from SENSE to VEE. The required resistor value is calculated from: MOSFET SELECTION It is recommended that the external MOSFET (Q1) selection is based on the following criteria: - The BVDSS rating should be greater than the maximum system voltage (VSYS), plus ringing and transients which can where ILIM is the desired current limit threshold. If the voltage across RS reaches VCL, the current limit circuit modulates the gate of Q1 to regulate the current at ILIM. While the current (1) 19 www.ti.com LM5064 limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. For proper operation, RS must be less than 200 mΩ. VCL can be set to either 26 mV or 50 mV via hardware and/or software. This setting defaults to use of CL pin which, when connected to VDD is 26 mV, or VEE is 50 mV. The value, when powered, can be set via the PMBus with the DEVICE_SETUP (D9h) command, which defaults to the 26 mV setting. Once the desired setting is known, calculate the shunt based on that input voltage and maximum current. While the maximum load current in normal operation can be used to determine the required power rating for resistor RS, basing it on the current limit value provides a more reliable design since the circuit can operate near the current limit threshold continuously. The resistor’s surge capability must also be considered since the circuit breaker threshold is 1.9 or 3.7 times the current limit threshold. Connections from RS to the LM5064 should be made using Kelvin techniques. In the suggested layout of Figure 8 the small pads at the lower corners of the sense resistor connect only to the sense resistor terminals, and not to the traces carrying the high current. With this technique, only the voltage across the sense resistor is applied to SENSE_K, SENSE, and VEE_K, eliminating the voltage drop across the high current solder connections. 301584036 FIGURE 8. Sense Resistor Connections POWER LIMIT THRESHOLD The LM5064 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS) and the VDS of Q1 (OUT to SENSE pins). The resistor at the PWR pin (RPWR) sets the maximum power dissipation for Q1, and is calculated from the following equation: er dissipation limit is set. The reason for this caution is that the voltage across the sense resistor, which is monitored and regulated by the power limit circuit, is lowest at turn-on when the regulated current is at a minimum. The voltage across the sense resistor during power limit can be expressed as follows: (2) (3) where PMOSFET(LIM) is the desired power limit threshold for Q1, and RS is the current sense resistor described in the Current Limit section. For example, if RS is 3 mΩ, VIN = 48V, and the desired power limit threshold is 80W, RPWR calculates to 30.1 kΩ (standard 1% value). If Q1’s power dissipation reaches the threshold Q1’s gate is modulated to regulate the load current, keeping Q1’s power from exceeding the threshold. For proper operation of the power limiting feature, RPWR must be ≤150 kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart section. Typically, power limit is reached during startup, or if the output voltage falls due to a severe over-load or short circuit. The programmed maximum power dissipation should have a reasonable margin from the maximum power defined by the SOA chart, especially if retry is enabled, because the MOSFET will be repeatedly stressed during fault restart cycles. The MOSFET manufacturer should be consulted for guidelines. If the application does not require use of the power limit function the PWR pin can be left open. The accuracy of the power limit function at turn-on may degrade if a very low pow- where ILIM is the current in RS, and VDS is the voltage across Q1. For example, if the power limit is set at 80W with RS = 3 mΩ, and VDS = 48V the sense resistor voltage calculates to 5.0 mV, which is comfortably regulated by the LM5064. However, if the power limit is set lower (e.g., 25W), the sense resistor voltage calculates to 1.6 mV. At this low level noise and offsets within the LM5064 may degrade the power limit accuracy. To maintain accuracy, the sense resistor voltage should not be less than 3 mV. www.ti.com TURN-ON TIME The output turn-on time depends on whether the LM5064 operates in current limit, or in both power limit and current limit, during turn-on. A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor (RS). If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS the circuit operates only at the current limit threshold during turn-on. Referring to Figure 9(A), as the load current reaches ILIM, the gate-to20 (4) where CL is the load capacitance. For example, if VSYS = -48V, CL = 200 µF, and ILIM = 8.7A, tON calculates to 1.1 ms. The maximum instantaneous power dissipated in the MOSFET is 418W. This calculation assumes the time from t1 to t2 inFigure 10 (A) is small compared to tON, the load does not draw any (5) where RL is the load resistance. The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete. 301584040 B. Load Draws Current During Turn-On 301584039 A. No Load Current During Turn-On FIGURE 9. Current During Turn-On B) Turn-On with Power Limit and Current Limit: The maximum allowed power dissipation in Q1 (PMOSFET(LIM)) is defined by the resistor at the PWR pin, and the current sense resistor RS. See the Power Limit Threshold section. If the current limit threshold (ILIM) is higher than the current defined by the power limit threshold at maximum VDS (PMOSFET(LIM)/| VSYS|) the circuit operates initially in the power limit mode when the VDS of Q1 is high, and then transitions to current limit mode as the current increases to ILIM and VDS decreases. Assuming the load (RL) is not connected during turn-on, the time for the output voltage to reach its final value is approximately equal to: (6) For example, if VSYS = -48V, CL = 200 µF, ILIM = 8.7A, and PMOSFET(LIM) = 80W, tON calculates to ≊3.0 ms, and the initial current level (IP) is approximately 1.67A. The Fault Timeout Period must be set longer than tON. 301584075 FIGURE 10. MOSFET Power Up Waveforms 21 www.ti.com LM5064 current until after the output voltage has reached its final value, and PGD switches high (Figure 9 (A)). The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete. If the load draws current during the turn-on sequence (Figure 9 (B)), the turn-on time is longer than the above calculation, and is approximately equal to: source voltage is controlled at GATE to maintain the current at ILIM. As the output voltage reaches its final value (VDS ≊ 0V) the drain current reduces to its normal operating value. The time for the OUT pin voltage to transition from zero volts to VSYS is equal to: LM5064 nal circuitry. When the Fault Timeout Period of the LM5064 expires, a restart sequence starts as described below (Restart Timing). During consecutive cycles of the restart sequence, the fault timeout period is shorter than the initial fault time out period described above by approximately 8% since the voltage at the TIMER pin starts ramping up from 0.3V rather than VEE. Since the LM5064 normally operates in power limit and/or current limit during a power up sequence, the Fault Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See the Turn-On Time section. C) Restart Timing For the LM5064, after the Fault Timeout Period described above, CT is discharged by the 2.4 µA current sink to 1.2V. The TIMER pin then cycles through seven additional charge/discharge cycles between 1.2V and 3.9V as shown in Figure 5. The restart time ends when the TIMER pin voltage reaches 0.3V during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to: TIMER CAPACITOR, CT The TIMER pin capacitor (CT) sets the timing for the insertion time delay, fault timeout period, and the restart timing of the LM5064. A) Insertion Delay - Upon applying the system voltage (VSYS) to the circuit, the external MOSFET (Q1) is held off during the insertion time (t1 in Figure 3) to allow ringing and transients at VSYS to settle. Since each backplane’s response to a circuit card plug-in is unique, the worst case settling time must be determined for each application. The insertion time starts when VSYS reaches the POR threshold, at which time the internal 4.8 µA current source charges CT from 0V to 3.9V. The required capacitor value is calculated from: (7) For example, if the desired insertion delay is 125 ms, CT calculates to 0.15 µF. At the end of the insertion delay, CT is quickly discharged by a 1.5 mA current sink. B) Fault Timeout Period - During in-rush current limiting or upon detection of a fault condition where the current limit and/ or power limit circuits regulate the current through Q1, the fault timer current source (74 µA) is switched on to charge CT. The Fault Timeout Period is the time required for the TIMER pin voltage to reach 3.9V, at which time Q1 is switched off. The required capacitor value for the desired Fault Timeout Period tFAULT is calculated from: (9) = CT x 9.6 x 106 For example, if CT = 0.15 µF, tRESTART = 1.4 seconds. At the end of the restart time, Q1 is switched on. If the fault is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately 0.5% in this mode. UVLO, OVLO By programming the UVLO and OVLO thresholds the LM5064 enables the series pass device (Q1) when the input supply voltage (VSYS) is within the desired operational range. If VCC is below the UVLO threshold, or above the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold. (8) For example, if the desired Fault Timeout Period is 8 ms, CT calculates to 0.15 µF. CT is discharged by the 2.4 µA current sink at the end of the Fault Timeout Period. After the Fault Timeout Period, if RETRY = VDD, the LM5064 latches the GATE pin low until a power up sequence is initiated by exter- www.ti.com 22 LM5064 Option A: The configuration shown in Figure 11 requires three resistors (R1-R3) to set the thresholds. 301584044 FIGURE 11. UVLO and OVLO Thresholds Set By R1-R3 The procedure to calculate the resistor values is as follows: - Choose the upper UVLO threshold (VUVH), and the lower UVLO threshold (VUVL). - Choose the upper OVLO threshold (VOVH). - The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the values for R1R3 are determined. If VOVL must be accurately defined in addition to the other three thresholds, see Option B below. The resistors are calculated as follows: (15) (16) (10) Using standard values of R1 = 200 kΩ, R2 = 8.87 kΩ, and R3 = 7.87 kΩ, the lower OVLO threshold calculates to 56V, and the OVLO hysteresis is 4.4V. Note that the OVLO hysteresis is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following: (11) (17) (18) (12) VUV(HYS) = R1 x 20 µA The lower OVLO threshold is calculated from: (13) (19) As an example, assume the application requires the following thresholds: VUVH = 36V, VUVL = 32V, VOVH = 60V. (20) VOV(HYS) = (R1 + R2) x 21 µA (14) 23 www.ti.com LM5064 Option B: If all four thresholds must be accurately defined, the configuration in Figure 12 can be used. 301584065 FIGURE 12. Programming the Four Thresholds The four resistor values are calculated as follows: - Choose the upper and lower UVLO thresholds (VUVH) and (VUVL). R1 = 200 kΩ, R2 = 16.8 kΩ R3 = 190 kΩ, R4 = 8.2 kΩ When the R1-R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following: (21) (25) (22) - Choose the upper and lower OVLO threshold (VOVH) and (VOVL). (26) VUV(HYS) = R1 x 20 µA (23) (27) (24) (28) As an example, assume the application requires the following thresholds: VUVH = 36V, VUVL = 32V, VOVH = 60V, and VOVL = 56V. Therefore VUV(HYS) = 4V, and VOV(HYS) = 4V. The resistor values are: www.ti.com 24 301584074 FIGURE 13. UVLO/EN = POREN Option D: The OVLO function can be disabled by connecting the OVLO pin to VEE. The UVLO thresholds are set as described in Option B or Option C. CPG. Adding a diode across RPG2 (Figure 15 (C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge. POWER GOOD PIN (PGD) When the Q1 VDS voltage is below its threshold, the internal pull-down acting on the PGD pin is disabled, allowing PGD to rise to VPGD through the pull-up resistor, RPG, as shown in Figure 14. The pull-up voltage (VPGD) can be as high as 80V, and can be higher or lower than the voltages at VCC and OUT. VDD is a convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on PGD during power up. If a delay is required at PGD, suggested circuits are shown in Figure 15. In Figure 15(A), capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 15(B), the rising edge is delayed by RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and 301584053 FIGURE 14. Power Good Output 301584054 FIGURE 15. Adding Delay to the Power Good Output Pin 25 www.ti.com LM5064 POREN threshold (≊8.7V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B. Option C: The minimum UVLO level is obtained by connecting the UVLO/EN pin to VCC as shown in Figure 13. Q1 is switched on when the VCC-VEE voltage reaches the LM5064 (<2A), a capacitor may be sufficient to limit the voltage surge, however this comes at the expense of input surge current on card insertion. If the load powered by the LM5064 hot swap circuit has inductive characteristics, a Schottky diode (D1) is required across the LM5064’s output, along with some load capacitance (CL). The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off. If the OUT pin transitions more than 0.3V negative the LM5064 can be permanently damaged. See Figure 16. SYSTEM CONSIDERATIONS Continued proper operation of the LM5064 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS (Transient Voltage Suppressor)is ideal, as depicted in Figure 16 as Z1. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. If the TVS is not present, inductance in the supply lines will generate a voltage transient at shutdown which can exceed the absolute maximum rating of the LM5064, resulting in its destruction. For low current solutions 301584055 FIGURE 16. Output Diode Required for Inductive Loads pins so any voltage greater than 0.3V in either polarity will cause significant current flow through the diodes, which can result in device failure. - The sense resistor (RS) should be placed close to the LM5064. A trace should connect the VEE source pin and OUT drain pad of Q1 to the sense resistor to VEE_K and SENSE_K pins, respectively. Connect RS using the Kelvin techniques shown in Figure 8. - The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and close to each other to minimize loop inductance. - The termination connections for the various components around the LM5064 should be connected directly to each other, and to the LM5064’s VEE pin connection, and then connected to VSYS at one point. Do not connect the various component terminations to each other through the high current VSYS line. - Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and turn-off. - The board’s edge connector can be designed such that the LM5064 detects via the UVLO/EN pin that the board is being removed, and responds by turning off the load before the supply voltage is disconnected. For example, in Figure 17, the voltage at the UVLO/EN pin goes to VEE before VSYS is removed from the LM5064 as a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system voltage is applied to the LM5064’s VSYS pin before the UVLO voltage is taken high, thereby allowing the LM5064 to turn on the output in a controlled fashion. PC BOARD GUIDELINES The following guidelines should be followed when designing the PC board for the LM5064: - Place the LM5064 close to the board’s input connector to minimize trace inductance from the connector to the MOSFET (Q1). - Place a TVS (Z1), directly adjacent to the VCC and VEE pins of the LM5064 to help minimize voltage transients which may occur on the input supply line. The TVS should be chosen such that the peak VSYS is just lower the TVS reverse-bias voltage. Transients of 20 volts or greater over the nominal input voltage can easily occur when the load current is shut off. A small capacitor may be sufficient for low current sense applications (I < 2A). It is recommended to test the VSYS input voltage transient performance of the circuit by current limiting or shorting the load and measuring the peak input voltage transient. - Place a 1 µF ceramic capacitor as close as possible to VREF pin. - Place a 1 µF ceramic capacitor as close as possible to VDD pin. - Minimize the inductance between the SENSE, SENSE_K, VEE_K, and VEE pins. There are anti-parallel diodes between these pins so any voltage greater than 0.3V in either polarity will cause significant current flow through the diodes, which can result in device failure. Do not place any resistors between these nodes. - Minimize the impedance between the VEE_K and SENSE_K pins. There are anti-parallel diodes between these www.ti.com 26 LM5064 301584056 FIGURE 17. Recommended Board Connector Design 27 www.ti.com LM5064 telemetry on VIN (VIN = VAUXH = VVCC-VVEE), VOUT (VOUT = VVCC - VVOUT), IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 1. PMBus™ Command Support The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get TABLE 1. Supported PMBus Commands Code Name Function R/W Number Default Of Data Value Bytes 01h OPERATION Retrieves or stores the operation status. R/W 1 03h CLEAR_FAULTS Clears the status registers and re-arms the Black Box registers for updating. Send Byte 0 80h 19h CAPABILITY Retrieves the device capability. R 1 B0h 43h VOUT_UV_WARN_LIMIT Retrieves or stores output under-voltage warn limit threshold. R/W 2 0000h 4Fh OT_FAULT_LIMIT Retrieves or stores over-temperature fault limit threshold. R/W 2 0960h (150°C) 51h OT_WARN_LIMIT Retrieves or stores over-temperature warn limit threshold. R/W 2 07D0h (125°C) 57h VIN_OV_WARN_LIMIT Retrieves or stores input over-voltage warn limit threshold. R/W 2 0FFFh 58h VIN_UV_WARN_LIMIT Retrieves or stores input under-voltage warn limit threshold. R/W 2 0000h 78h STATUS_BYTE Retrieves information about the parts operating status. R 1 49h 79h STATUS_WORD Retrieves information about the parts operating status. R 2 3849h 7Ah STATUS_VOUT Retrieves information about output voltage status. R 1 00h 7Ch STATUS_INPUT Retrieves information about input status. R 1 10h 7Dh STATUS_TEMPERATURE Retrieves information about temperature status. R 1 00h 7Eh STATUS_CML Retrieves information about communications status. R 1 00h 80h STATUS_MFR_SPECIFIC Retrieves information about circuit breaker and MOSFET shorted status. R 1 10h 88h READ_VIN Retrieves input voltage measurement. R 2 0000h 8Bh READ_VOUT Retrieves output voltage measurement. R 2 0000h 8Dh READ_TEMPERATURE_1 Retrieves temperature measurement. R 2 0190h 99h MFR_ID Retrieves manufacturer ID in ASCII characters (NSC). R 3 4Eh 53h 43h 9Ah MFR_MODEL Retrieves Part number in ASCII characters. (LM5064\0\0). R 8 4Ch 4Dh 35h 30h 36h 36h 0h 0h 9Bh MFR_REVISION Retrieves part revision letter/number in ASCII (e.g., AA). R 2 41h 41h D0h MFR_SPECIFIC_00 READ_VAUX Retrieves auxiliary voltage measurement. R 2 0000h D1h MFR_SPECIFIC_01 MFR_READ_IIN Retrieves input current measurement. R 2 0000h D2h MFR_SPECIFIC_02 MFR_READ_PIN Retrieves input power measurement. R 2 0000h D3h MFR_SPECIFIC_03 MFR_IIN_OC_WARN_LIMIT Retrieves or stores input current limit warn threshold. R/W 2 0FFFh www.ti.com 28 Name Function R/W D4h MFR_SPECIFIC_04 MFR_PIN_OP_WARN_LIMIT Retrieves or stores input power limit warn threshold. R/W 2 0FFFh D5h MFR_SPECIFIC_05 READ_PIN_PEAK Retrieves measured peak input power measurement. R 2 0000h D6h MFR_SPECIFIC_06 CLEAR_PIN_PEAK Resets the contents of the peak input power register to zero. Send Byte 0 D7h MFR_SPECIFIC_07 GATE_MASK Allows the user to disable MOSFET gate shutdown for various fault conditions. R/W 1 0000h D8h MFR_SPECIFIC_08 ALERT_MASK Retrieves or stores user SMBA fault mask. R/W 2 0820h D9h MFR_SPECIFIC_09 DEVICE_SETUP Retrieves or stores information about number of retry attempts. R/W 1 0000h DAh MFR_SPECIFIC_10 BLOCK_READ Retrieves most recent diagnostic and telemetry information in a single transaction. R 12 0190h 0000h 0000h 0000h 0000h 0000h DBh MFR_SPECIFIC_11 SAMPLES_FOR_AVG Exponent value AVGN for number of samples to be averaged (N = 2AVGN), range = 00h to 0Ch . R/W 1 00h DCh MFR_SPECIFIC_12 READ_AVG_VIN Retrieves averaged input voltage measurement. R 2 0000h DDh MFR_SPECIFIC_13 READ_AVG_VOUT Retrieves averaged output voltage measurement. R 2 0000h DEh MFR_SPECIFIC_14 READ_AVG_IIN Retrieves averaged input current measurement. R 2 0000h DFh MFR_SPECIFIC_15 READ_AVG_PIN Retrieves averaged input power measurement. R 2 0000h E0h MFR_SPECIFIC_16 BLACK_BOX_READ Captures diagnostic and telemetry information which are latched when the first SMBA event after faults are cleared. R 12 0000h 0000h 0000h 0000h 0000h 0000h MFR_SPECIFIC_17 Manufacturer-specific parallel of the STATUS_WORD to DIAGNOSTIC_WORD_READ convey all FAULT/WARN data in a single transaction. R 2 08E0h R 12 0000h 0000h 0000h 0000h 0000h 0000h E1h E2h MFR_SPECIFIC_18 AVG_BLOCK_READ Retrieves most recent average telemetry and diagnostic information in a single transaction. 29 www.ti.com LM5064 Number Default Of Data Value Bytes Code LM5064 TABLE 4. VOUT_UV_WARN_LIMIT Register Standard PMBus Commands OPERATION (01h) The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command may be used to switch the MOSFET ON and OFF under host control. It is also used to re-enable the MOSFET after a fault triggered shutdown. Writing an OFF command, followed by an ON command, will clear all faults and re-enable the device. Writing only an ON after a fault-triggered shutdown will not clear the fault registers or re-enable the device. The OPERATION command is issued with the write byte protocol. Value Meaning Default Switch ON 80h 00h Switch OFF n/a Meaning Default 1h – 0FFFh VOUT UnderVoltage Warning detection threshold 0000h (disabled) 0000h VOUT UnderVoltage Warning disabled n/a OT_FAULT_LIMIT (4Fh) The OT_FAULT_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the over-temperature fault detection. Reading and writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an overtemperature fault is triggered and the MOSFET is switched off, OT FAULT flags set, and the SMBA signal asserted. After the measured temperature falls below the value in this register, the MOSFET may be switched back on with the OPERATION command. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature fault detection time is 16 ms. TABLE 2. Recognized OPERATION Command Values 80h Value CLEAR FAULTS (03h) The CLEAR_FAULTS command is a standard PMBus command that resets all stored warning and fault flags and the SMBA signal. If a fault or warning condition still exists when the CLEAR_FAULTS command is issued, the SMBA signal may not clear or will re-assert almost immediately. Issuing a CLEAR_FAULTS command will not cause the MOSFET to switch back on in the event of a fault turnoff - that must be done by issuing an OPERATION command after the fault condition is cleared. This command uses the PMBus send byte protocol. TABLE 5. OT_FAULT_LIMIT Register CAPABILITY (19h) The CAPABILITY command is a standard PMBus command that returns information about the PMBus functions supported by the LM5064. This command is read with the PMBus read byte protocol. Value Meaning 0h – 0FFEh Over-temperature 0960h (150°C) Fault threshold value Default 0FFFh Over-temperature n/a Fault detection disabled TABLE 3. CAPABILITY Register Value Meaning Default B0h Supports Packet Error Check, 400Kbits/sec, Supports SMBus Alert B0h OT_WARN_LIMIT (51h) The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the over-temperature warning detection. Reading and writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write word protocol. If the measured temperature exceeds this value, an over-temperature warning is triggered and the OT WARN flags set in the respective registers and the SMBA signal asserted. A single temperature measurement is an average of 16 round-robin cycles; therefore, the minimum temperature warn detection time is 16 ms. VOUT_UV_WARN_LIMIT (43h) The VOUT_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VOUT under-voltage Warning detection. Reading and writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VOUT falls below the value in this register, VOUT UV Warn flags are set and the SMBA signal is asserted. www.ti.com TABLE 6. OT_WARN_LIMIT Register 30 Value Meaning 0h – 0FFEh Over-Temperature 07D0h (125°C) Warn Threshold Value Default 0FFFh Over-Temperature n/a Warn detection disabled TABLE 8. VIN_UV_WARN_LIMIT Register Value Meaning 1h – 0FFFh VIN Under-Voltage 0000h (disabled) Warning detection threshold 0000h VIN Under-Voltage n/a Warning disabled TABLE 7. VIN_OV_WARN_LIMIT Register Value Meaning 0h – 0FFEh VIN Over-Voltage 0FFFh (disabled) Warning detection threshold Default 0FFFh VIN Over-Voltage Warning disabled Default STATUS_BYTE (78h) The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5064. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued. n/a VIN_UV_WARN_LIMIT (58h) The VIN_UV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN under-voltage warning detection. Reading and writing TABLE 9. STATUS_BYTE Definitions Bit NAME Meaning Default 7 BUSY Not Supported, always 0 0 6 OFF This bit is asserted if the MOSFET is not switched on for any reason. 1 5 VOUT OV Not Supported, always 0 0 4 IOUT OC Not Supported, always 0 0 3 VIN UV Fault A VIN Under-Voltage Fault has occurred 1 2 TEMPERATURE A Temperature Fault or Warning has occurred 0 1 CML A Communication Fault has occurred 0 0 None of the Above A fault or warning not listed in bits [7:1] has occurred 1 the underlying fault should be removed and a CLEAR _FAULTS command issued. The INPUT and VIN UV flags will default to 1 on startup, however, they will be cleared to 0 after the first time the input voltage exceeds the resistor-programmed UVLO threshold. STATUS_WORD (79h) The STATUS_WORD command is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5064. Accesses to this command should use the PMBus read word protocol. To clear bits in this register, TABLE 10. STATUS_WORD Definitions Bit NAME Meaning Default 15 VOUT An output voltage fault or warning has occurred 0 14 IOUT/POUT Not Supported, always 0 0 13 INPUT An input voltage or current fault has occurred 1 12 MFR A Manufacturer Specific Fault or Warning has occurred 1 11 POWER GOOD The Power Good signal has been negated 1 10 FANS Not Supported, always 0 0 9 OTHER Not Supported, always 0 0 8 UNKNOWN Not Supported, always 0 0 7 BUSY Not Supported, always 0 0 6 OFF This bit is asserted if the MOSFET is not switched on for any reason. 1 5 VOUT OV Not Supported, always 0 0 4 IOUT OC Not Supported, always 0 0 31 www.ti.com LM5064 to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN falls below the value in this register, VIN UV Warn flags are set in the respective register, and the SMBA signal is asserted. VIN_OV_WARN_LIMIT (57h) The VIN_OV_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the VIN over-voltage warning detection. Reading and writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read or write word protocol. If the measured value of VIN falls below the value in this register, VIN OV Warn flags are set in the respective registers and the SMBA signal is asserted. LM5064 Bit NAME Meaning Default 3 VIN UV A VIN Under-Voltage Fault has occurred 1 2 TEMPERATURE A Temperature Fault or Warning has occurred 0 1 CML A Communication Fault has occurred 0 0 None of the Above A fault or warning not listed in bits [7:1] has occurred 1 Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. STATUS_VOUT (7Ah) The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV Warn flag. TABLE 11. STATUS_VOUT Definitions Bit NAME Meaning Default 7 VOUT OV Fault Not Supported, always 0 0 6 VOUT OV Warn Not Supported, always 0 0 5 VOUT UV Warn A VOUT Under-Voltage Warning has occurred 0 4 VOUT UV Fault Not Supported, always 0 0 3 VOUT Max Not Supported, always 0 0 2 TON Max Fault Not Supported, always 0 0 1 TOFF Max Fault Not Supported, always 0 0 0 VOUT Tracking Error Not Supported, always 0 0 register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. The VIN UV Warn flag will default to 1 on startup, however, it will be cleared to 0 after the first time the input voltage increases above the resistorprogrammed UVLO threshold. STATUS_INPUT (7Ch) The STATUS_INPUT command is a standard PMBus command that returns the value of a number of flags related to input voltage, current, and power. Accesses to this command should use the PMBus read byte protocol. To clear bits in this TABLE 12. STATUS_INPUT Definitions Bit NAME Meaning Default 7 VIN OV Fault A VIN Over-Voltage Fault has occurred 0 6 VIN OV Warn A VIN Over-Voltage Warning has occurred 0 5 VIN UV Warn A VIN Under-Voltage Warning has occurred 1 4 VIN UV Fault A VIN Under-Voltage Fault has occurred 0 3 Insufficient Voltage Not Supported, always 0 0 2 IIN OC Fault An IIN Over-Current Fault has occurred 0 1 IIN OC Warn An IIN Over-Current Warning has occurred 0 0 PIN OP Warn A PIN Over-Power Warning has occurred 0 mand should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. STATUS_TEMPERATURE (7dh) The STATUS_TEMPERATURE is a standard PMBus command that returns the value of the of a number of flags related to the temperature telemetry value. Accesses to this com- TABLE 13. STATUS_TEMPERATURE Definitions Bit www.ti.com NAME Meaning Default 7 Overtemp Fault An Over-Temperature Fault has occurred 0 6 Overtemp Warn An Over-Temperature Warning has occurred 0 5 Undertemp Warn Not Supported, always 0 0 4 Undertemp Fault Not Supported, always 0 0 3 reserved Not Supported, always 0 0 2 reserved Not Supported, always 0 0 1 reserved Not Supported, always 0 0 0 reserved Not Supported, always 0 0 32 TABLE 14. STATUS_CML Definitions Bit NAME Default 7 Invalid or unsupported command received 0 6 Invalid or unsupported data received 0 5 Packet Error Check failed 0 4 Not supported, always 0 0 3 Not supported, always 0 0 2 Not supported, always 0 0 1 Miscellaneous communications fault has occurred 0 0 Not supported, always 0 0 TABLE 17. READ_VOUT Register STATUS_MFR_SPECIFIC (80h) The STATUS_MFR_SPECIFIC command is a standard PMBus command that contains manufacturer specific status information. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed and a CLEAR_FAULTS command should be issued. Meaning Default 7 Circuit breaker fault 0 6 Ext. MOSFET shorted fault 0 5 Not Supported, Always 0 0 4 Defaults loaded 1 3 Not supported: Always 0 0 2 Not supported: Always 0 0 1 Not supported: Always 0 0 0 Not supported: Always 0 0 Meaning Default 0h – 0FFFh Measured value for VOUT 0000h READ_TEMPERATURE_1 (8Dh) The READ_TEMPERATURE_1 command is a standard PMBus command that returns the signed value of the temperature measured by the external temperature sense diode. Reading this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the Over-Temperature Fault and Warning detection. This data has a range of -256°C to + 255°C after the coefficients are applied. TABLE 15. STATUS_MFR_SPECIFIC Definitions Bit Value TABLE 18. READ_TEMPERATURE_1 Register READ_VIN (88h) The READ_VIN command is a standard PMBus command that returns the 12-bit measured value of the input voltage. Reading this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VIN Over and Under-Voltage Warning detection. Value Meaning Default 0h – 0FFFh Measured value for TEMPERATURE 0000h MFR_ID (99h) The MFR_ID command is a standard PMBus command that returns the identification of the manufacturer. To read the MFR_ID, use the PMBus block read protocol. TABLE 19. MFR_ID Register TABLE 16. READ_VIN Register Byte Name 0 Number of bytes Value 03h 4Eh ‘N’ Value Meaning Default 1 MFR ID-1 0h – 0FFFh Measured value for VIN 0000h 2 MFR ID-2 53h ‘S’ 3 MFR ID-3 43h ‘C’ READ_VOUT (8Bh) The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the output voltage. Reading this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VOUT Under-Voltage Warning detection. MFR_MODEL (9Ah) The MFR_MODEL command is a standard PMBus command that returns the part number of the chip. To read the MFR_MODEL, use the PMBus block read protocol. 33 www.ti.com LM5064 faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, a CLEAR_FAULTS command should be issued. STATUS_CML (7Eh) The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to communication LM5064 TABLE 20. MFR_MODEL Register Byte Name 0 Number of bytes 08h 1 MFR ID-1 4Ch ‘L’ 2 MFR ID-2 4Dh ‘M’ 3 MFR ID-3 35h ‘5’ 4 MFR ID-4 30h ‘0’ 5 www.ti.com MFR ID-5 MFR_REVISION (9Bh) The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To read the MFR_REVISION, use the PMBus block read protocol. Value TABLE 21. MFR_REVISION Register 36h ‘6’ 6 MFR ID-6 36h ‘4’ 7 MFR ID-7 00h 8 MFR ID-8 00h 34 Byte Name Value 0 Number of bytes 02h 1 MFR ID-1 41h ‘A’ 2 MFR ID-2 41h ‘A’ Value Meaning Default 0h – 0FFEh Value for input over-current warn limit 0FFFh MFR_SPECIFIC_00: READ_VAUX (D0h) The READ_VAUX command will report the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to 2.97V to VEE will be reported at plus full scale (0FFFh). Voltages less than or equal to 0V referenced to VEE will be reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus Read Word protocol. 0FFFh Input over-current n/a warning disabled MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h) The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN overpower flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus Read/Write Word protocol. Reading/ writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. TABLE 22. READ_VAUX Register Value Meaning Default 0h – 0FFFh Measured value for VAUX input 0000h MFR_SPECIFIC_01: MFR_READ_IIN (D1h) The MFR_READ_IIN command will report the 12-bit ADC measured current sense voltage. To read data from the MFR_READ_IIN command, use the PMBus Read Word protocol. Reading this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Please see the section on coefficient calculations to calculate the values to use. TABLE 26. MFR_PIN_OPWARN_LIMIT Register TABLE 23. MFR_READ_IIN Register Value Meaning Default 0h – 0FFFh Measured value for input current sense voltage 0000h Meaning Default Value for input current x input voltage 0000h Default Value for input over-power warn limit 0FFFh 0FFFh Input over-power warning disabled n/a TABLE 27. READ_PIN_PEAK Register TABLE 24. MFR_READ_PIN Register 0h – 0FFFh Meaning 0h – 0FFEh MFR_SPECIFIC_05: READ_PIN_PEAK (D5h) The READ_PIN_PEAK command will report the maximum input power measured since a Power On reset or the last CLEAR_PIN_PEAK command. To access the READ_PIN_PEAK command, use the PMBus Read Word protocol. Use the coefficients shown in the Telemetry and Warning Coefficients Table. MFR_SPECIFIC_02: MFR_READ_PIN (D2h) The MFR_READ_PIN command will report the upper 12 bits of the VIN x IIN product as measured by the 12-bit ADC. To read data from the MFR_READ_PIN command, use the PMBus Read Word protocol. Reading this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Please see the section on coefficient calculations to calculate the values to use. Value Value Value Meaning 0h – 0FFEh Maximum Value 0h for input current x input voltage since reset or last clear Default MFR_SPECIFIC_06: CLEAR_PIN_PEAK (D6h) The CLEAR_PIN_PEAK command will clear the PIN PEAK register. This command uses the PMBus Send Byte protocol. MFR_SPECIFIC_03: MFR_IN_OC_WARN_LIMIT (D3h) The MFR_IIN_OC_WARN_LIMIT PMBus command sets the input over-current warning threshold. In the event that the input current rises above the value set in this register, the IIN over-current flags are set in the respective registers and the SMBA is asserted. To access the MFR_IIN_OC_WARN_LIMIT register, use the PMBus Read/Write Word protocol. Reading/writing to this register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. MFR_SPECIFIC_07: GATE_MASK (D7h) The GATE_MASK register allows the hardware to prevent fault conditions from switching off the MOSFET. When the bit is high, the corresponding FAULT has no control over the MOSFET gate. All status registers will still be updated (STATUS, DIAGNOSTIC) and an SMBA will still be asserted. This register is accessed with the PMBus Read / Write Byte protocol. Warning: Inhibiting the MOSFET switch off in response to over-current or circuit breaker fault conditions will likely result in the destruction of the MOSFET! This functionality should be used with great care and supervision! 35 www.ti.com LM5064 TABLE 25. MFR_IIN_OC_WARN_LIMIT Register Manufacturer Specific PMBus™ Commands LM5064 TABLE 28. MFR_SPECIFIC_07 GATE MASK Definitions Bit NAME Default 7 Not used, always 0 0 6 Not used, always 0 0 5 VIN UV FAULT 0 4 VIN OV FAULT 0 3 IIN/PFET FAULT 0 2 OVERTEMP FAULT 0 1 Not used, always 0 0 0 CIRCUIT BREAKER FAULT 0 MFR_SPECIFIC_08: ALERT_MASK (D8h) The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an SMBA being asserted. When the corresponding bit is high, that condition will not cause the SMBA to be asserted. If that condition occurs, the registers where that condition is captured will still be updated (STATUS registers, DIAGNOSTIC_WORD) and the external MOSFET gate control will still be active (VIN_OV_FAULT, VIN_UV_FAULT, IIN/PFET_FAULT, CB_FAULT, OT_FAULT). This register is accessed with the PMBus Read / Write Word protocol. The VIN UNDERVOLTAGE FAULT flag will default to 1 on startup, however, it will be cleared to 0 after the first time the input voltage increases above the resistor-programmed UVLO threshold. The IIN/PFET Fault refers to the input current fault and the MOSFET power dissipation fault. There is no input power fault detection; only input power warning detection. TABLE 29. ALERT_MASK Definitions BIT NAME DEFAULT 15 VOUT UNDERVOLTAGE WARN 0 14 IIN LIMIT Warn 0 13 VIN UNDERVOLTAGE WARN 0 12 VIN OVERVOLTAGE WARN 0 11 POWER GOOD 1 10 OVERTEMP WARN 0 9 Not Used 0 8 OVERPOWER LIMIT WARN 0 7 Not Used 0 6 EXT_MOSFET_SHORTED 0 5 VIN UNDERVOLTAGE FAULT 1 4 VIN OVERVOLTAGE FAULT 0 3 IIN/PFET FAULT 0 2 OVERTEMPERATURE FAULT 0 1 CML FAULT (Communications Fault) 0 0 CIRCUIT BREAKER FAULT 0 Bit Name MFR_SPECIFIC_09: DEVICE_SETUP (D9h) The DEVICE_SETUP command may be used to override pin settings to define operation of the LM5064 under host control. This command is accessed with the PMBus read / write byte protocol. 3 CB/CL Ratio 2 Current Limit Configuration TABLE 30. DEVICE_SETUP Byte Format 1 Unused 0 Unused Bit Name Meaning 7:5 Retry setting 111 = Unlimited retries 100 = Retry 4 times 011 = Retry 2 times 010 = Retry 1 time 001 = No retries 000 = Pin configured retries 0 = High setting (50 mV) 1 = Low setting (26 mV) www.ti.com 0 = Use pin settings 1 = Use SMBus settings In order to configure the Current Limit Setting via this register, it is necessary to set the Current Limit Configuration bit (2) to 1 to enable the register to control the current limit function and the Current Limit Setting bit (4) to select the desired setting. If the Current Limit Configuration bit is not set, the pin setting will be used. The Circuit Breaker to Current Limit ratio value is set by the CB / CL Ratio bit (3). Note that if the Current Limit Configuration is changed, the samples for the telemetry averaging function will not be reset. It is recommeded to allow a full averaging update period with the new Current Limit Configuration before processing the averaged data. Note that the Current Limit Configuration affects the coefficients used for the Current and Power measurements and warning registers. 101 = Retry 8 times Current limit setting 0 = Low setting (1.9x) 1 = High setting (3.9x) 110 = Retry 16 times 4 Meaning 36 (1 byte) DIAGNOSTIC_WORD (1 Word) IIN_BLOCK (1 Word) VOUT_BLOCK (1 Word) VIN_BLOCK (1 Word) PIN_BLOCK (1 Word) TEMP_BLOCK (1 Word) N = 2AVGN Averaging/Register Update Period (ms) 1000 256 256 1001 512 512 1010 1024 1024 1011 2048 2048 1100 4096 4096 Note that a change in the SAMPLES_FOR_AVG register will not be reflected in the average telemetry measurements until the present averaging interval has completed. The default setting for AVGN is 0000, therefore, the average telemetry will mirror the instantaneous telemetry until a value higher than zero is programmed. The SAMPLES_FOR_AVG register is accessed via the PMBus read / write byte protocol. TABLE 33. SAMPLES_FOR_AVG Register TABLE 31. BLOCK_READ Register Format Byte Count (always 12) AVGN Value Meaning 0h – 0Ch Exponent (AVGN) 00h for number of samples to average over Default MFR_SPECIFIC_12: READ_AVG_VIN (DCh) The READ_AVG_VIN command will report the 12-bit ADC measured input average voltage. If the data is not ready, the returned value will be the previous averaged data. However, if there is no previously averaged data, the default value (0000h) will be returned. This data is read with the PMBus Read Word protocol. This register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. MFR_SPECIFIC_11: SAMPLES_FOR_AVG (DBh) The SAMPLES_FOR_AVG command is a manufacturer specific command for setting the number of samples used in computing the average values for IIN, VIN, VOUT, PIN. The decimal equivalent of the AVGN nibble is the power of 2 samples, (e.g. AVGN=12 equates to N=4096 samples used in computing the average). The LM5064 supports average numbers of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096. The SAMPLES_FOR_AVG number applies to average values of IIN, VIN, VOUT, PIN simultaneously. The LM5064 uses simple averaging. This is accomplished by summing consecutive results up to the number programmed, then dividing by the number of samples. Averaging is calculated according to the following sequence: TABLE 34. READ_AVG_VIN Register Value Meaning Default 0h – 0FFFh Average of measured values for input voltage 0000h MFR_SPECIFIC_13: READ_AVG_VOUT (DDh) The READ_AVG_VOUT command will report the 12-bit ADC measured OUT pin average voltage. The returned value will be the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus Read Word protocol. This register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. Y = (X(N) + X(N-1) + ... + X(0)) / N When the averaging has reached the end of a sequence (for example, 4096 samples are averaged), then a whole new sequence begins that will require the same number of samples (in this example, 4096) to be taken before the new average is ready. TABLE 32. SAMPLES_FOR_AVG Register AVGN N = 2AVGN TABLE 35. READ_AVG_VOUT Register Averaging/Register Update Period (ms) 0000 1 1 0001 2 2 0010 4 4 0011 8 8 0100 16 16 0101 32 32 0110 64 64 0111 128 128 Value Meaning Default 0h – 0FFFh Average of measured values for output voltage 0000h MFR_SPECIFIC_14: READ_AVG_IIN (DEh) The READ_AVG_IIN command will report the 12-bit ADC measured VAUXH average voltage. The returned value will be the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus Read 37 www.ti.com LM5064 MFR_SPECIFIC_10: BLOCK_READ (DAh) The BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output telemetry information (IIN, VOUT, VIN, PIN) as well as READ_TEMPERATURE_1 to capture all of the operating information of the LM5064 in a single SMBus transaction. The block is 12 bytes long with telemetry information being sent out in the same manner as if an individual READ_XXX command had been issued (shown below). The contents of the block read register are updated every clock cycle (85ns) as long as the SMBus interface is idle. BLOCK_READ also guarantees that the VIN, VOUT, IIN and PIN measurements are all time-aligned. If separate commands are used, individual samples may not be time-aligned, because of the delay necessary for the communication protocol. The Block Read command is read via the PMBus block read protocol. LM5064 Word protocol. This register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. TABLE 37. READ_AVG_PIN Register TABLE 36. READ_AVG_IIN Register Value Meaning Default 0h – 0FFFh Average of measured values for current sense voltage 0000h Meaning Default 0h – 0FFFh Average of 0000h measured value for input voltage x input current sense voltage MFR_SPECIFIC_16: BLACK_BOX_READ (E0h) The BLACK BOX READ command retrieves the BLOCK READ data which was latched in at the first assertion of SMBA by the LM5064. It is re-armed with the CLEAR_FAULTS command. It is the same format as the BLOCK_READ registers, the only difference being that its contents are updated with the SMBA edge rather than the internal clock edge. This command is read with the PMBus Block Read protocol. MFR_SPECIFIC_15: READ_AVG_PIN The READ_AVG_PIN command will report the upper 12-bits of the average VIN x IIN product as measured by the 12-bit ADC. You will read the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus Read Word protocol. This register should use the coefficients shown in the Telemetry and Warning Conversion Coefficients Table. www.ti.com Value 38 TABLE 38. DIAGNOSTIC_WORD Format Bit Meaning Default 15 VOUT_UNDERVOLTAGE_WARN 0 14 IIN_OP_WARN 0 13 VIN_UNDERVOLTAGE_WARN 0 12 VIN_OVERVOLTAGE_WARN 0 11 POWER GOOD 1 10 OVER_TEMPERATURE_WARN 0 9 TIMER_LATCHED_OFF 0 8 EXT_MOSFET_SHORTED 0 7 CONFIG_PRESET 1 6 DEVICE_OFF 1 5 VIN_UNDERVOLTAGE_FAULT 1 4 VIN_OVERVOLTAGE_FAULT 0 3 IIN_OC/PFET_OP_FAULT 0 2 OVER_TEMPERATURE_FAULT 0 1 CML_FAULT 0 0 CIRCUIT_BREAKER_FAULT 0 TABLE 39. AVG_BLOCK_READ Register Format MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h) The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, PIN) as well as temperature to capture all of the operating information of the part in a single PMBus transaction. The block is 12 bytes long with telemetry information being sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown below). AVG_BLOCK_READ also guarantees that the VIN, VOUT, and IIN measurements are all time-aligned whereas there is a chance they may not be if read with individual PMBus commands. To read data from the AVG_BLOCK_READ command, use the SMBus Block Read protocol. 39 Byte Count (always 12) (1 byte) DIAGNOSTIC_W ORD (1 word) AVG_IIN (1 word) AVG_VOUT (1 word) AVG_VIN (1 word) AVG_PIN (1 word) TEMPERATURE (1 word) www.ti.com LM5064 DIAGNOSTIC_WORD register. The READ_DIAGNOSTIC_WORD command should be read with the PMBus Read Word protocol. The READ_DIAGNOSTIC_WORD is also returned in the BLOCK_READ, BLACK_BOX_READ, and AVG_BLOCK_READ operations. MFR_SPECIFIC_17: READ_DIAGNOSTIC_WORD (E1h) The READ_DIAGNOSTIC_WORD PMBus command will report all of the LM5064 faults and warnings in a single read operation. The standard response to the assertion of the SMBA signal of issuing multiple read requests to various status registers can be replaced by a single word read to the LM5064 301584076 FIGURE 18. Command/Register and Alert Flow Diagram www.ti.com 40 All measured telemetry data and user programmed warning thresholds are communicated in 12-bit two’s compliment binary numbers read/written in 2 byte increments conforming to the Direct format as described in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part TABLE 40. Telemetry and Warning Word Format Byte B7 B6 B5 B4 B3 B2 B1 B0 1 Bit_7 Bit_6 Bit_5 Bit_4 Bit_3 Bit_2 Bit_1 Bit_0 2 0 0 0 0 Bit_11 Bit_10 Bit_9 Bit_8 Conversion from direct format to real-world dimensions of current, voltage, power, and temperature is accomplished by determining appropriate coefficients as described in section 7.2.1 of the PMBus Power System Management Protocol Specification 1.1 (Part II). According to this specification, the host system converts the values received into a reading of volts, amperes, watts, or other units using the following relationship: Where: X: the calculated "real-world" value (volts, amps, watt, etc.) m: the slope coefficient Y: a two byte two's complement integer received from device b: the offset, a two byte, two's complement integer R: the exponent, a one byte two's complement integer R is only necessary in systems where m is required to be an integer (for example, where m may be stored in a register in an integrated circuit). In those cases, R only needs to be large enough to yield the desired accuracy. TABLE 41. Telemetry and Warning Conversion Coefficients Commands Condition Format Number of Data Bytes m b R Units READ_VIN, READ_AVG_VIN VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT DIRECT 2 4611 -642 -2 V READ_VOUT, READ_AVG_VOUT VOUT_UV_WARN_LIMIT DIRECT 2 4621 423 -2 V DIRECT 2 13808 0 -1 V *READ_IIN, READ_AVG_IIN MFR_IIN_OC_WARN_LIMIT READ_VAUX CL = VDD DIRECT 2 10742 1552 -2 A *READ_IN, READ_AVG_IN MFR_IIN_OC_WARN_LIMIT CL = VEE DIRECT 2 5456 2118 -2 A *READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = VDD DIRECT 2 1204 8524 -3 W *READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = VEE DIRECT 2 612 11202 -3 W DIRECT 2 16000 0 -3 °C READ_TEMPERATURE_1 OT_WARN_LIMIT OT_FAULT_LIMIT * The coefficients relating to current/power measurements and warning thresholds shown in Table 41 are normalized to a sense resistor (RS) value of 1 mΩ. In general, the current/power coefficients can be calculated using the relationships shown in Table 42. 41 www.ti.com LM5064 II). The organization of the bits in the telemetry or warning word is shown in Table 40, where Bit_11 is the most significant bit (MSB) and Bit_0 is the least significant bit (LSB). The decimal equivalent of all warning and telemetry words are constrained to be within the range of 0 to 4095, with the exception of temperature. The decimal equivalent value of the temperature word ranges from 0 to 65535. Reading and Writing Telemetry Data and Warning Thresholds LM5064 TABLE 42. Current and Power Telemetry and Warning Conversion Coefficients (RS in mΩ) Commands Condition Format Number of Data Bytes m b R Units *READ_IIN, READ_AVG_IIN MFR_IIN_OC_WARN_LIMIT CL = VDD DIRECT 2 10742 x RS 1552 -2 A *READ_IIN, READ_AVG_IIN MFR_IIN_OC_WARN_LIMIT CL = VEE DIRECT 2 5456 x RS 2118 -2 A *READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = VDD DIRECT 2 1204 x RS 8524 -3 W *READ_PIN, READ_AVG_PIN, READ_PIN_PEAK MFR_PIN_OP_WARN_LIMIT CL = VEE DIRECT 2 612 x RS 11202 -3 W Care must be taken to adjust the exponent coefficient, R, such that the value of m remains within the range of -32768 to +32767. For example, if a 5 mΩ sense resistor is used, the correct coefficients for the READ_IIN command with CL = VDD would be m = 5371, b = 155, R = -1. www.ti.com A Note on the "b" Coefficient Since b coefficients represent offset, for simplification b is set to zero in the following discussions. 42 The current register actually displays a value equivalent to a voltage across the user specified sense resistor, RS. The coefficients enable the data output to be converted to amps. The Step 1. Determine full scale current and shunt value based on 38.1 mV across shunt at full scale: Example Example: 8.7A application with 3 mΩ shunt. or: 2. Determine m': 3. Determine exponent R necessary to set m' to integer value m: Select R to provide 16 bit accuracy for the integer value of m: R = -1 4. Final values m = 3224 R = -1 b=0 43 www.ti.com LM5064 values shown in the example are based on having the device programmed for a 26 mV current limit threshold (CL = VDD). In the 26 mV range, the LSB value is 9.3 µV and the full scale range is 38.1 mV. In the 50 mV range (CL = VEE), the LSB value is 18.3 µV and the full scale range is 74.9 mV. Reading Current LM5064 VIN_UV_WARN_LIMIT). Input and output voltage values are read/written in Direct format with 12-bit resolution and a 21.7 mV LSB. An example of calculating the PMBus coefficients for input voltage is shown below. Reading Input and Output Voltage Coefficients for VIN and VOUT are fixed and are consistent between read telemetry measurements (e.g., READ_VIN, READ_AVG_VIN) and warning thresholds (e.g., Step Example 1. Determine m' based on full scale analog input and full scale digital range: 2. Determine exponent R necessary to set m' to integer value m Select R to provide 16 bit accuracy for the integer value of m: with desired accuracy: (4606 in this example): R = -2 3. Final values m = 4606 R = -2 b =0 For this reason power coefficients will also vary depending on the shunt value and must be calculated for each application. The power LSB will vary depending on shunt value according to 830 µW/Rsense for the 26 mV range or 1.63 mW/Rsense for the 50 mV range. Reading Power The power calculation of the LM5064 is a relative power calculation meaning that full scale of the power register corresponds to simultaneous full scale values in the current register and voltage register such that the power register has the following relationship based on decimal equivalents of the register contents: Step Example 1. Determine full scale power from known full scale of input current and input voltage: PIN_MAX = VIN_MAX x IIN_MAX Example: 8.7A application with 3 mΩ shunt. PIN_MAX = (88.9V) x (38.1 mV / 3 mΩ) = 1129W 2. Determine m': 3. Optional: Determine exponent R necessary to set m' to integer Select R to provide 16 bit accuracy for the integer value of m : value m with desired accuracy: R = -4 4. Final values m = 36271 R = -4 b=0 www.ti.com 44 The coefficients for telemetry measurements and warning thresholds presented in Table 41 are adequate for the majority of applications. Current and power coefficients must be calculated per application as they are dependent on the value of the sense resistor, RS, used. Table 42 provides the equations necessary for calculating the current and power coefficients for the general case. The small signal nature of the current measurement make it and the power measurement more susceptible to PCB parasitics than other telemetry channels. This may cause slight variations in the optimum coefficients (m, b, R) for converting from Direct format digital values to real-world values (e.g., Amps and Watts). The optimum coefficients can be determined empirically for a specific application and PCB layout using two or more measurements of the telemetry channel of interest. The current coefficients can be determined using the following method: 1. While the LM5064 is in normal operation measure the voltage across the sense resistor using kelvin test points and a high accuracy DVM while controlling the load current. Record the integer value returned by the READ_AVG_IIN command (with the SAMPLES_FOR_AVG set to a value greater than 0) for two or more voltages across the sense resistor. For best results, the individual READ_AVG_IIN measurements should span nearly the full scale range of the current (For example, voltage across RS of 5 mV and 20 mV). 2. Convert the measured voltages to currents by dividing them by the value of RS. For best accuracy the value of RS should be measured. Table 43 assumes a sense resistor value of 5mΩ. 5. Where: X: the calculated "real-world" value (volts, amps, watts, temperature) m: the slope coefficient, is the two byte, two's complement integer Y: a two byte two's complement integer received from device b: the offset, a two byte, two's complement integer R: the exponent, a one byte two's complement integer The above procedure can be repeated to determine the coefficients of any telemetry channel simply by substituting measured current for some other parameter (e.g., power, voltage, etc.). Writing Telemetry Data TABLE 43. Measurements for linear fit determination of current coefficients: Measured voltage Measured Current across (A) RS (V) 3. There are several locations that will require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using this method as prescribed by the PMBus revision section 7.2.2 "Sending a Value" READ_AVG_IIN (integer value) 0.005 1 568 0.01 2 1108 0.02 4 2185 To determine the ‘m’ coefficient, simply shift the decimal point of the calculated slope to arrive at at integer with a suitable number of significant digits for accuracy (typically 4) while staying with the range of -32768 to +32767. This shift in the decimal point equates to the ‘R’ coefficient. For the slope value shown above, the decimal point would be shifted to the right once hence R = -1. Once the ‘R’ coefficient has been determined, the ‘b’ coefficient is found by multiplying the y-intercept by 10-R. In this case the value of b = 295. Calculated Current Coefficients: m = 5389 b = 295 R = -1 Y = (mX + b) x 10R Where: X: the calculated "real-world" value (volts, amps, watts, temperature) m: the slope coefficient, is the two byte, two's complement integer Y: a two byte two's complement integer received from device b: the offset, a two byte, two's complement integer R: the exponent, a one byte two's complement integer Using the spreadsheet or math program of your choice determine the slope and the y-intercept of the data returned by the READ_AVG_IIN command versus the measured current. For the data shown in Table 42: READ_AVG_IN value = slope x (Measured Current) + (yintercept) slope = 538.9 y-intercept = 29.5 45 www.ti.com LM5064 4. Determining Telemetry Coefficients Empirically with Linear Fit LM5064 for communicating with the LM5064. Table 44 depicts 7-bit addresses (eighth bit is read/write bit): PMBus™ Address Lines (ADR0, ADR1, ADR2) The three address lines are to be set high (connect to VDD), low (connect to VEE), or open to select one of 27 addresses TABLE 44. Device Addressing www.ti.com ADR2 ADR1 ADR0 Decoded Address Z Z Z 40h Z Z 0 41h Z Z 1 42h Z 0 Z 43h Z 0 0 44h Z 0 1 45h Z 1 Z 46h Z 1 0 47h Z 1 1 10h 0 Z Z 11h 0 Z 0 12h 0 Z 1 13h 0 0 Z 14h 0 0 0 15h 0 0 1 16h 0 1 Z 17h 0 1 0 50h 0 1 1 51h 1 Z Z 52h 1 Z 0 53h 1 Z 1 54h 1 0 Z 55h 1 0 0 56h 1 0 1 57h 1 1 Z 58h 1 1 0 59h 1 1 1 5Ah 46 LM5064 SMBus Communications Timing Requirements 301584094 FIGURE 19. SMBus Timing Diagram TABLE 45. SMBus Timing Definition Symbol Parameter Limits Units Min Max FSMB SMBus Operating Frequency 10 400 TBUF Bus free time between Stop and Start Condition 1.3 µs THD:STA Hold time after (Repeated) Start Condition. After this period, the first clock is generated. 0.6 µs TSU:STA Repeated Start Condition setup time 0.6 µs TSU:STO Stop Condition setup time 0.6 µs THD:DAT Data hold time 85 ns TSU:DAT Data setup time 100 TTIMEOUT Clock low time-out 25 Comments kHz ns 35 ms (Note 9) TLOW Clock low period 1.5 µs THIGH Clock high period 0.6 µs (Note 10) TLOW:SEXT Cumulative clock low extend time (slave device) 25 ms (Note 11) TLOW:MEXT Cumulative low extend time (master device) 10 ms (Note 12) TF Clock or Data Fall Time 20 300 ns (Note 13) TR Clock or Data Rise Time 20 300 ns (Note 13) Note 9: Devices participating in a transfer will timeout when any clock low exceeds the value of TTIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than TTIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms). Note 10: THIGH MAX provides a simple method for devices to detect bus idle conditions. Note 11: TLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself. Note 12: TLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ackto-ack, or ack-to-stop. Note 13: Rise and fall time is defined as follows: • TR = ( VILMAX – 0.15) to (VIHMIN + 0.15) • TF = 0.9 VDD to (VILMAX – 0.15) 47 www.ti.com LM5064 the last part on the bus that has an SMBA set has successfully reported its address, the SMBA signal will de-assert. The way that the LM5064 releases the SMBA signal is by setting the ARA Automatic mask bit for all fault conditions present at the time of the ARA read. All status registers will still show the fault condition, but it will not generate and SMBA on that fault again until the ARA Automatic mask is cleared by the host issuing a CLEAR_FAULTS command to this part. This should be done as a routine part of servicing an SMBA condition on a part, even if the ARA read is not done. Figure 20 depicts a schematic version of this flow. SMBA Response The SMBA effectively has two masks: 1. The Alert Mask Register at D8h, and 2. The ARA Automatic Mask. The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that THIS part was the one that returned its address. When a part responds to the ARA read, it releases the SMBA signal. When 301584095 FIGURE 20. Typical Flow Schematic for SMBA Fault www.ti.com 48 LM5064 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead eTSSOP Package NS Package Number MXA28A 49 www.ti.com LM5064 Negative Voltage System Power Management and Protection IC with PMBusTM Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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