MCP2021/2/1P/2P LIN Transceiver with Voltage Regulator Features: Description: • The MCP2021/2/1P/2P are Compliant with LIN Bus Specifications 1.3, 2.1 and are Compliant to SAE J2602-2 • Support Baud Rates up to 20 kBaudwith LIN-compatible Output Driver • 43V Load Dump Protected • Very Low EMI Meets Stringent OEM Requirements • Wide Supply Voltage, 6.0V-18.0V Continuous: - Maximum input voltage of 30V • Extended Temperature Range: -40 to +125°C • Interface to PIC® EUSART and Standard USARTs • Local Interconnect Network (LIN) Bus Pin: - Internal pull-up resistor and diode - Protected against ground shorts - Protected against loss of ground - High-current drive • Automatic Thermal Shutdown • On-Chip Voltage Regulator: - Output voltage of 5.0V with tolerances of ±3% overtemperature range - Available with alternate output voltage of 3.3V with tolerances of ±3% overtemperature range - Maximum continuous input voltage of 30V - Internal thermal overload protection - Internal short circuit current limit - External components limited to filter capacitor and load capacitor • Two Low-Power modes: - Receiver On, Transmitter Off, Voltage Regulator On ( 85 µA) - Receiver Monitoring Bus, Transmitter Off, Voltage Regulator Off ( 16 µA) The MCP2021/2/1P/2P provides a bidirectional, halfduplex communication physical interface to automotive and industrial LIN systems that meets the LIN bus specification Revision 2.1 and SAE J2602-2. The devices incorporate a voltage regulator with 5V at 50 mA or 3.3V at 50 mA regulated power-supply outputs. 2005-2014 Microchip Technology Inc. The regulator is short-circuit protected, and is protected by an internal thermal shutdown circuit. The device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. The MCP2021/2/1P/2P family of devices includes the following packages. 8-pin PDIP, DFN and SOIC packages: • MCP2021-330, LIN-compatible driver, 8-pin, 3.3V regulator, wake up on dominant level of LBUS • MCP2021-500, LIN-compatible driver, 8-pin, 5.0V regulator, wake up on dominant level of LBUS • MCP2021P-330, LIN-compatible driver, 8-pin, 3.3V regulator, wake up at falling edge of LBUS voltage • MCP2021P-500, LIN-compatible driver, 8-pin, 5.0V regulator, wake up at falling edge of LBUS voltage 14-pin PDIP, TSSOP and SOIC packages with RESET output: • MCP2022-330, LIN-compatible driver, 14-pin, 3.3V regulator, RESET output, wake up on dominant level of LBUS • MCP2022-500, LIN-compatible driver, 14-pin, 5.0V regulator, RESET output, wake up on dominant level of LBUS • MCP2022P-330, LIN-compatible driver, 14-pin, 3.3V regulator, RESET output, wake up at falling edge of LBUS voltage • MCP2022P-500, LIN-compatible driver, 14-pin, 5.0V regulator, RESET output, wake up at falling edge of LBUS voltage DS20002018H-page 1 MCP2021/2/1P/2P Package Types MCP2021, 6x5 DFN-S* MCP2021, MCP2021P 4x4 DFN* RXD 1 CS/LWAKE 2 VREG 3 TXD 4 EP 9 8 FAULT/TXE 7 VBB 6 LBUS 5 VSS RXD 1 CS/LWAKE 2 VREG TXD RXD 1 8 2 7 3 6 4 5 EP 9 3 4 7 VBB 6 LBUS 5 VSS MCP2022, MCP2022P PDIP, SOIC, TSSOP MCP2021, MCP2021P PDIP, SOIC CS/LWAKE VREG TXD FAULT/TXE 8 FAULT/TXE VBB LBUS VSS RXD CS/LWAKE 1 14 2 13 VREG TXD 3 12 4 5 11 10 6 9 7 8 RESET NC NC * Includes Exposed Thermal Pad (EP); see Table 1-2. FAULT/TXE VBB LBUS VSS NC NC NC MCP2021/2 Block Diagram Short Circuit Protection Thermal Protection RESET (MCP2022 ONLY) Voltage Regulator VREG Internal Circuits VBB Ratiometric Reference Wake-Up Logic and Power Control – RXD + ~30 kΩ CS/LWAKE TXD LBUS OC FAULT/TXE VSS Thermal Protection DS20002018H-page 2 Short Circuit Protection 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P MCP2021P/2P Block Diagram Short-Circuit Protection RESET (MCP2022P ONLY) Thermal Protection Voltage Regulator VREG Internal Circuits Ratiometric Reference Wake-Up Logic and Power Control – RXD + CS/LWAKE TXD VBB ~30 kΩ OC LBUS FAULT/TXE VSS Thermal and Short-Circuit Protection 2005-2014 Microchip Technology Inc. Short-Circuit Protection DS20002018H-page 3 MCP2021/2/1P/2P NOTES: DS20002018H-page 4 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 1.0 DEVICE OVERVIEW EQUATION 1-1: RTP (VBBmin - 5.5) / 250 mA. 5.5V = VUVLO + 1.0V, 250 mA is the peak current at Power-On when VBB = 5.5V The MCP2021/2/1P/2P provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. The MCP2021/2/1P/2P provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN-level logic, and vice versa. The LIN specification 2.0 requires that the transceiver(s) of all nodes in the system be connected via the LIN pin, referenced to ground, and with a maximum external termination resistance load of 510Ω from LIN bus to battery supply. The 510Ωcorresponds to one Master and sixteen Slave nodes. The MCP2021/2/1P/2P-500 provides a +5V, 50 mA, regulated power output. The regulator uses an LDO design, is short-circuit protected, and will turn the regulator output off if it falls below 3.5V. The MCP2021/2/1P/2P thermal-shutdown protection. also includes The regulator is specifically designed to operate in the automotive environment and will survive +43V load dump transients, double-battery jumps, and reverse battery connections when a reverse blocking diode is used. The other members of the MCP2021/2/1P/2P-330 family output +3.3V at 50 mA with a turn-off voltage of 2.5V. (See Section 1.6 “Internal Voltage Regulator”). MCP2021/2 wakes from Power-Down mode on a dominant level on LBUS. MCP2021P/2P wakes at a transition from recessive level to dominant level on LBUS. 1.1 1.1.1 1.2 1.2.1 Internal Protection ESD PROTECTION For component-level ESD ratings, please refer to the Section 2.1 “Absolute Maximum Ratings†”. 1.2.2 GROUND LOSS PROTECTION The LIN Bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a high-impedance level. 1.2.3 THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator if it detects a thermal overload. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions: • Voltage regulator overload • LIN bus output overload • Increase in die temperature due to increase in environmental temperature Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (i.e., RXD = low, TXD = high) or a thermal overload condition (i.e., RXD = high, TXD = low). Optional External Protection REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode should be used to provide polarity protection (see Figure 1-6). 1.1.2 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 43V transient suppressor (TVS) diode, between VBB and ground, with a 50Ω transient protection resistor (RTP) in series with the battery supply and the VBB pin, protect the device from power transients (see Figure 1-6) and ESD events. While this protection is optional, it is considered good engineering practice. The resistor value is chosen according to Equation 1-1. 2005-2014 Microchip Technology Inc. DS20002018H-page 5 MCP2021/2/1P/2P FIGURE 1-1: THERMAL SHUTDOWN STATE DIAGRAMS LBUS Overload to VBB Output Overload Voltage Regulator Shutdown Operation Mode Temperature <SHUTDOWNTEMP 1.3 Modes of Operation For an overview of all operational modes, please refer to Table 1-1. 1.3.1 POWER-ON RESET MODE Upon application of VBB, the device enters Power-On Reset mode (POR). During this mode, the part maintains the digital section in a Reset mode and waits until the voltage on pin VBB rises above the “ON” threshold (typically 5.75V) to enter to the Ready mode. If during the operation, the voltage on pin VBB falls below the “OFF” threshold (typically 4.25V), the part comes back to the POR mode. 1.3.2 POWER-DOWN MODE In Power-Down mode, the transmitter and the voltage regulator are off. Only the receiver wake-up from the LIN bus section, and the CS/LWAKE pin wake-up circuits, are in operation. This is the lowest power mode. If pin CS/LWAKE goes to a high level during Power-Down mode, the device immediately enters Ready mode and enables the voltage regulator; and after the output has stabilized (approximately 0.3 ms to 1.2 ms), the device goes to Operation mode or Transmitter-Off mode (see Figure 1-2 for MCP2021/2 and Figure 1-4 for MCP2021P/2P). Note: The above time interval <1.2 ms assumes 12V VBB input and no thermal shutdown event. DS20002018H-page 6 Transmitter Shutdown Temperature <SHUTDOWNTEMP LIN bus activity will also change the device from Power-Down mode to Ready mode. MCP2021/2 wakes up on the dominant level of the LIN bus, and MCP2021P/2P on a falling edge that follows a dominant level lasting 20 µs of time. The Power-Down mode can be reached through either Operation mode or Transmitter-Off mode. 1.3.3 READY MODE Upon entering Ready mode, the voltage regulator and receiver-threshold-detect circuit are powered up. The transmitter remains in an OFF state. The device is ready to receive data as soon as the regulator is stabilized, but not to transmit. If a microcontroller is being driven by the voltage regulator output, it will go through a POR and initialization sequence. The LIN pin is in the recessive state for MCP2021/2 and in floating state for MCP2021P/2P. The device will stay in Ready mode until the output of the voltage regulator has stabilized and the CS/LWAKE pin is true (‘1’). After VREG is stable and CS/LWAKE is high, MCP2021/2 will enter Operation mode; and MCP2021P/2P will enter either Operation mode or Transmitter-Off mode, depending on the level of the FAULT/TXE pin (refer to Figure 1-4). 1.3.4 OPERATION MODE In this mode, all internal modules are operational. The device will go into the Power-Down mode on the falling edge of CS/LWAKE. For the MCP2021P/2P devices, the pull-up resistor is switched on only in this mode. 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 1.3.5 TRANSMITTER-OFF MODE Whenever the FAULT/TXE signal is low, or permanent dominant on TXD/LBUS is detected, the LBUS transmitter is off. The transmitter may be re-enabled whenever the FAULT/TXE signal returns high, either by removing the internal Fault condition or when the CPU returns the FAULT/TXE high. The transmitter will not be enabled if the FAULT/TXE pin is brought high when the internal fault is still present. If TX-OFF mode is caused by TXD/LBUS permanent dominant level, the transmitter can recover when the permanent dominant status disappears. The transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. This prevents unwanted disruption of the bus during times of uncertain operation. 1.3.6 REMOTE WAKE-UP The Remote Wake-Up sub-module observes the LBUS in order to detect bus activity. Bus activity is detected when the voltage on the LBUS stays below a threshold of approximately 0.4 VBB for a typical duration of at least 20 µs. The MCP2021/2 device is level sensitive to LBUS. Dominant level longer than 20 µs will cause the device to leave the Power-Down mode. The MCP2021P/2P device is falling-edge sensitive to LBUS. Only the LBUS transition from recessive to dominant, followed by at least 20 µs dominant level, can wake up the device. Putting CS/LWAKE to high level also wakes up the device. Refer to Figure 1-2 and Figure 1-3. 1.3.7 DIFFERENCE DETAILS BETWEEN MCP2021/2 AND MCP2021P/2P The MCP202XP is a minor variation of the MCP202X device that adds improved state machine control, as well as the ability to disconnect the internal 30kΩ pull-up between LIN and VBB in all modes except normal operation. These changes allow the system designer to better handle Fault conditions and reduce the overall system current consumption. The differences between the two device versions are as follows: 1. Because of this, if the LIN bus becomes permanently shorted, it becomes impossible to place the MCP202X in a low-power state. 3. State Machine Options: The MCP202XP device is able to enter Transmitter Off mode from Ready mode without transitioning through Operation mode. The MCP202X device must enter Operation mode from Ready mode. (see State Machine Diagrams, Figure 1-2 and Figure 1-3 for details). This capability allows the system designer to monitor the bus in Ready mode to determine if the system should transition to normal operation and connect the internal pull-up, or if Ready mode was reached due to an invalid condition. In the case of an invalid condition, the MCP202XP device can be placed into Power-Down mode without connecting the internal pull-up and waking other nodes on the LIN Bus network. Note: To enter Transmitter Off, the system must set TXE ‘low’ before pulling CS high (see Figure 1-5). Otherwise, if CS is pulled high first, the MCP202XP will enter Operation mode due to the internal pull-up on TXE. To properly take advantage of the device differences, the system designer is required to implement some microcontroller code to the power-up routine. This code will monitor the status of the LIN bus to determine how to respond to the dominant signal. It will also determine if the local LIN node needs to respond or can ‘Listen Only’. If the local LIN node does not need to respond, it can enter Transmitter Off mode, disconnecting the 30 kΩ pull-up, reducing module current while still maintaining the ability to properly receive all valid LIN messages. Switchable LIN-VBB Pull-Up Resistor: On the MCP202XP device, the internal 30kΩ pull-up resistor is disconnected in all modes except Operation mode. On the MCP202X device, this pull-up resistor is always connected. (See the MCP2021/2 Block Diagram and the MCP2021P/2P Block Diagram for details.) 2. Power-Down Wake-up on LIN Traffic: The MCP202XP device requires a LIN falling edge to generate a valid Wake condition, due to bus traffic. The MCP202X device will generate a Wake anytime LIN is at a valid dominant level. 2005-2014 Microchip Technology Inc. DS20002018H-page 7 MCP2021/2/1P/2P FIGURE 1-2: MCP2021/2 OPERATIONAL MODES STATE DIAGRAM Power-Down TX: OFF RX: OFF VREG: OFF CS/LWAKE = 0 CS/LWAKE = 0 Operation TX: ON RX: ON VREG: ON FAULT/TXE = 0 Or Faults* CS/LWAKE = 1 or dominant level on LBUS CS/LWAKE = 1& VREG_OK = 1 FAULT/TXE = 1 &No Faults* Ready TX: OFF RX: ON VREG: ON Transmitter Off TX: OFF RX: ON VREG: ON VBAT > 5.75V POR TX: OFF RX: OFF VREG: OFF Start *Fault: thermal shutdown and TXD/LBUS permanent dominant Note: While the device is in shutdown, TXD should not be actively driven high or it may power internal logic through the ESD diodes and may damage the device. FIGURE 1-3: MCP2021P/2P OPERATIONAL MODES DIAGRAMS Power-Down TX: OFF RX: OFF VREG: OFF CS/LWAKE = 0 CS/LWAKE = 0 Operation TX: ON RX: ON VREG: ON FAULT/TXE = 0 Or Faults* FAULT/TXE = 1 &No Faults* CS/LWAKE = 1 or Falling edge on LBUS CS/LWAKE = 1& VREG_OK = 1& FAULT/TXE = 1 Ready TX: OFF RX: ON VREG: ON Transmitter Off TX: OFF RX: ON VREG: ON CS = 1& VREG_OK = 1 &FAULT/TXE = 0 VBAT > 5.75V POR TX: OFF RX: OFF VREG: OFF Start *Fault: thermal shutdown and TXD/LBUS permanent dominant DS20002018H-page 8 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-4: MCP2021P/2P WAKE-UP DUE TO BUS DISCONNECTING CSLWAKE 0 VREG FAULTTXE LBUS 0 State 2005-2014 Microchip Technology Inc. Sleep Ready DS20002018H-page 9 MCP2021/2/1P/2P FIGURE 1-5: FORCED POWER-DOWN MODE SEQUENCE FOR MCP2021P/2P tCSactive> = 2V CS/LWAKE VREG FAULT/TXE = 1 Forced internally FAULT/TXE = 0 Forced externally FAULT/TXE LBUS disconnected; e.g., Master pull-up & internal resistor off; LBUS floating. LBUS STATE Operation Mode Transmitter-Off Mode Power-Down Mode Forced Power-Down Mode after BUS-OFF instruction or a longer LIN-Bus inactivity ( > = 4 sec according to LIN specification) DS20002018H-page 10 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P TABLE 1-1: OVERVIEW OF OPERATIONAL MODES Transmitter Receiver Voltage Regulator POR OFF OFF OFF Read VBB; if VBB > 5.75V, proceed to Ready mode Ready OFF ON ON Bus OFF MCP2021/2: If CS/LWAKE is high level, then proceed to state Operation mode. MCP2021P/2P: If CS/LWAKE is high level and FAULT/TXE is high level, then proceed to Operation mode. If CS/LWAKE is high level and FAULT/TXE is low level, then proceed to TXOFF mode. Operation ON ON ON If CS/LWAKE is low level, then proceed to Power-Down mode. If FAULT/TXE is low level or TXD/LBUS permanent dominant is detected, then proceed to Transmitter-Off mode. Normal Operation mode Power-Down OFF Activity Detect OFF On LIN bus falling, go to Ready mode. On CS/LWAKE high level, go through Ready mode; then, to either operation or Transmitter-Off mode (refer to Figure 1-2 and Figure 1-3). Low-Power mode Transmitter-Off OFF ON ON If CS/LWAKE is low level, then proceed to Power-Down mode. If FAULT/TXE is high, then proceed to Operation mode. State 2005-2014 Microchip Technology Inc. Operation Comments DS20002018H-page 11 MCP2021/2/1P/2P 1.4 Pin Descriptions TABLE 1-2: PINOUT DESCRIPTIONS Devices Pin Name Function 8-Pin PDIP, SOIC 4x4 DFN 6x5 DFN-S 14-Pin PDIP, SOIC, TSSOP Pin Type Normal Operation RXD 1 1 1 O CS/LWAKE 2 2 2 TTL Receive Data Output (CMOS) VREG 3 3 3 O Power Output TXD 4 4 4 I Transmit Data Input (TTL) VSS 5 5 11 P LBUS 6 6 12 I/O NC — — 6 – 10 — No Connection VBB 7 7 13 P Battery Supply Chip Select (TTL) Ground LIN bus (Bidirectional) FAULT/TXE 8 8 14 OD Fault Detect Output, Transmitter Enable (OD) RESET — — 5 OD RESET Signal Output (OD) EP — 9 — — Exposed Thermal Pad Legend: O = Output, P = Power, I = Input, TTL = TTL input buffer, OD = Open-Drain Output 1.4.1 RECEIVE DATA OUTPUT (RXD) 1.4.3 POWER OUTPUT (VREG) The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin. Positive Supply Voltage Regulator Output pin. 1.4.2 The Transmit Data Input pin has an internal pull-up to VREG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. CHIP SELECT PIN (CS/LWAKE) An internal pull-down resistor will keep the CS/LWAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a POR and I/O initialization sequence. The pin must see a high level to activate the transmitter. If CS/LWAKE = 0 when the VBB supply is turned on, the device stays in Ready mode (Low-Power mode). In Ready mode, both the receiver and the voltage regulator are on and the LIN transmitter driver is off. If CS/LWAKE = 1 when the VBB supply is turned on, the device will proceed to either Operation or Transmitter-Off mode (refer to Figure 1-2 and Figure 1-3) after the VREG output has stabilized. This pin may also be used as a local wake-up input (see Figure 1-6). In this implementation, the microcontroller will set the I/O pin that controls the CS/LWAKE as an high-impedance input. The internal pull-down resistor will keep the input low. An external switch, or other source, can then wake up the transceiver and the microcontroller. Note: CS/LWAKE should not be tied directly to VREG as this could force the MCP202X into Operation mode before the microcontroller is initialized. 1.4.4 TRANSMIT DATA INPUT (TXD) For extra bus security, TXD is internally forced to ‘1’ when VREG is less than 1.8V (typical). If the thermal protection detects an overtemperature condition while the signal TXD is low, the transmitter is shut down. The recovery from the thermal shutdown is equal to adequate cooling time. 1.4.5 GROUND PIN (VSS) Ground pin. 1.4.6 LIN BUS PIN (LBUS) The bidirectional LIN bus Interface pin is the driver unit for the LIN pin and is controlled by the signal TXD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled. To further reduce radiated emissions, the LBUS pin has corner-rounding control for both falling and rising edges. The internal LIN receiver observes the activities on the LIN bus, and generates output signal RXD that follows the state of the LBUS. A 1st degree with 1 µs time constant (160 kHz), low-pass input filter is placed to maintain EMI immunity. 1.4.7 NO CONNECTION (NC) No internal connection. DS20002018H-page 12 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 1.4.8 BATTERY POSITIVE SUPPLY VOLTAGE (VBB) Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator. 1.4.9 This pin has an internal pull-up resistor of approximately 750 kΩ. The internal pull-up resistor may be too weak for some applications. We recommend adding a 10 kOhm external pull-up resistor to ensure a logic high level. FAULT/TXE Note 1: The FAULT/TXE pin is true (0) whenever the internal circuits have detected a short or thermal excursion and have disabled the LBUS output driver. Fault Detect Output and Transmitter Enable Input bidirectional pin. This pin is an open-drain output. Its state is defined as shown in Table 1-3. The transmitter driver is disabled whenever this pin is low (‘0’), either from an internal Fault condition or by external drive. This allows the transmitter to be placed in an OFF state and still allow the voltage regulator to operate. Refer to Table 1-1. 2: FAULT/TXE is true (0) when VREG not OK and has disabled the LBUS output driver. The FAULT/TXE pin sampled at a rate faster than every 10 µs. The FAULT/TXE also signals a mismatch between the TXD input and the LBUS level. This can be used to detect a bus contention. Since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. TABLE 1-3: FAULT/TXE TRUTH TABLE FAULT/TXE TXD In RXD Out LINBUS I/O Thermal Override L H VBB H H External Input Driven Output Definition OFF H L FAULT, TXD driven low, LBUS shorted to VBB (Note 1) VBB OFF H H OK L L GND OFF H H OK H L GND OFF H H OK, data is being received from the LBUS x x VBB ON H L FAULT, transceiver in thermal shutdown x x VBB x L x NO FAULT, the CPU is commanding the transceiver to turn off the transmitter driver Legend: x = don’t care Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault reporting during bus propagation delays. 1.4.10 RESET RESET is an open-drain output pin. This pin reflects an internal signal that tracks the internal system voltage has reached a valid, stable level. 1.4.11 EXPOSED THERMAL PAD (EP) It is recommended to connect this pad to VSS to enhance electromagnetic immunity and thermal resistance. As long as the internal voltage is valid, this pin will keep high-impedance. When the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the RESET output to short to GND. A pull-up resistor is needed to change the output to high/low voltage. When connected to a microcontroller input, this can provide a warning that the voltage regulator is shutting down (see Figure 1-2). Alternately, it can act as an external brown-out by connecting the RESET output to MCLR (see Figure 1-2). In addition to monitoring the internal voltage, RESET is asserted immediately upon entering the Power-Down mode. 2005-2014 Microchip Technology Inc. DS20002018H-page 13 MCP2021/2/1P/2P 1.5 Typical Applications FIGURE 1-6: TYPICAL MCP2021/MCP2021P APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) Master Node Only CBAT +12 CREG 220 kΩ VDD VREG TXD TXD VBB 1 kΩ (6) RXD RXD I/O LBUS LIN Bus CS/LWAKE (3) MMBZ27V (4) FAULT/TXE I/O 220 pF VSS 100 nF VSS Note 1: Note CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 – 22 µF. See Figure 2-1 to select the correct ESR. 2: CBAT is the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/LWAKE is connected to the VBAT supply. 4: Transient suppressor diode. 5: These components are required for additional load dump protection above 43V. 6: An external 10 kΩ resistor is recommended for some applications. DS20002018H-page 14 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-7: TYPICAL MCP2022/MCP2022P APPLICATION +12 +12 RTP(5) WAKE-UP 43V(5) +12 VDD VREG TXD TXD RXD RXD VBB 1 kΩ LBUS LIN Bus CS/LWAKE (3) MMBZ27V (4) FAULT/TXE I/O INT or MCLR VSS Master Node Only CREG 220 kΩ I/O CBAT 220 pF RESET VSS 100 nF VDD (6) Note 1: Note CREG, the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 – 22 µF. See Figure 2-1 to select the correct ESR. 2: CF is the filter capacitor for the external voltage supply. 3: This diode is only needed if is connected to the VBAT supply. 4: Transient suppressor diode. 5: These components are required for additional load dump protection above 43V. 6: Required if CPU does not have internal pull-up. FIGURE 1-8: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBB LIN bus MCP202X LIN bus MCP202X Slave 1 (MCU) LIN bus MCP202X LIN bus MCP202X Slave 2 (MCU) Slave n <16 (MCU) Master (MCU) 2005-2014 Microchip Technology Inc. DS20002018H-page 15 MCP2021/2/1P/2P 1.6 1.6.1 Internal Voltage Regulator 5.0V REGULATOR The MCP2021 has a low-drop-out voltage, positive regulator capable of supplying 5.00 VDC ±3% at up to 50 mA of load current, over the entire operating temperature range of -40°C to +125°C. With a load current of 50 mA, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 100 µA with a full 50 mA load current when the input to output voltage differential is greater than +3.00V. Designed for automotive applications, the regulator will protect itself from double-battery jumps and up to +43V load dump transients. The voltage regulator has both short-circuit and thermal-shut-down protection built in. Regarding the correlation between VBB, VREG and IDD, please refer to Figure 1-10 and Figure 1-11. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the output VREG will track the input down to approximately 3.5V, at which point the regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the POR trip point. The MCP2021 will then monitor VBB and turn on the regulator when VBB rises above 5.75, again. When the input voltage (VBB) drops below the differential needed to provide stable regulation, the output VREG) will track the input down to approximately +4.25V. The regulator will turn off the output at this point. This will allow PIC microcontrollers with internal POR circuits to generate a clean arming of the POR trip point. The regulator output will stay off until VBB is above +5.75 VDC. DS20002018H-page 16 In the start phase, the device must detect at least 5.75V to initiate operation during power-up. In the Power-Down mode, the VBB monitor will be turned off. Note: The regulator has an overload current limiting of approximately 100 mA. During a short circuit, the VREG is monitored. If VREG is lower than 3.5V, the VREG will turn off. After a recovery time of about three milliseconds, the VREG will be checked again. If there is no short circuit (VREG >3.5V), the VREG will be switched back on. The regulator has a thermal shutdown. If the thermal protection circuit detects an overtemperature condition, and the signals TXD and RXD are Low, or TXD is High, the regulator will shut down. The recovery from the thermal shutdown is equal to adequate cooling time. The regulator requires an external output bypass capacitor for stability. See Figure 2-1 for correct capacity and ESR for stable operation. Note: A ceramic capacitor of at least 10 µF or a tantalum capacitor of at least 2.2 µF is recommended for stability. In worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. Therefore, in order to ensure stability, ceramic capacitors smaller than 10 µF may require a small series resistance to meet the ESR requirements, as shown in Table 1-4. TABLE 1-4: RECOMMENDED SERIES RESISTANCE FOR CERAMIC CAPACITORS Resistance Capacitor Ω 1 µF 0.47Ω 2.2 µF 0.22Ω 4.7 µF 0.1Ω 6.9 µF 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-9: VOLTAGE REGULATOR BLOCK DIAGRAM Pass Element VREG VBB Sampling Network Fast Transient Loop Buffer VSS VREF 2005-2014 Microchip Technology Inc. DS20002018H-page 17 MCP2021/2/1P/2P 1.6.2 3.3V REGULATOR A metal option provides for a alternate 3.30 VDC ±3% at up to 50 mA of load current over the entire operating temperature range of -40°C to +125°C. All specifications given above for the 5.0V operation apply except for any difference noted here. The same input tracking of 4.25V applies the 3.3V regulator. Note: The regulator has an overload current limiting of approximately 100 mA. If VREG is lower than 2.5V, the VREG will turn off. FIGURE 1-10: VOLTAGE REGULATOR OUTPUT ON POR 8 VBB V Minimum VBB to maintain regulation VON 6 VOFF 4 2 0 t VREG 5 V VREG-NOM 4 3 2 1 0 t (1) Note 1: 2: 3: 4: DS20002018H-page 18 (2) (3) (4) Start-up, VBB < VON, regulator off. VBB > VON, regulator on. VBB Minimum VBB to maintain regulation. VBB < VOFF, regulator will turn off. 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 1-11: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION IREG mA lLIM 0 t VREG 6 V 5 VREG-NOM 4 VSD 3 2 1 0 Note 1: 2: 1.7 t (1) (2) IREG less than lLIM, regulator on. After IREG exceeds lLIM, the voltage regulator output will be reduced until VSD is reached. ICSP™ Considerations The following should be considered when the MCP2021/2/1P/2P is connected to pins supporting in-circuit programming: • Power used for programming the microcontroller can be supplied from the programmer or from the MCP2021/2/1P/2P. • The voltage on VREG should not exceed the maximum output voltage of VREG. 2005-2014 Microchip Technology Inc. DS20002018H-page 19 MCP2021/2/1P/2P NOTES: DS20002018H-page 20 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on RXD and TXD .......................................................................................................... -0.3 to VREG+0.3V VIN DC Voltage on FAULT and RESET.........................................................................................................-0.3 to +5.5V VIN DC Voltage on CS/LWAKE.......................................................................................................................-0.3 to +43V VBB Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43V VBB Battery Voltage, transient ISO 7637 Test 1 ......................................................................................................-200V VBB Battery Voltage, transient ISO 7637 Test 2a ...................................................................................................+150V VBB Battery Voltage, transient ISO 7637 Test 3a ....................................................................................................-300V VBB Battery Voltage, transient ISO 7637 Test 3b ...................................................................................................+200V VBB Battery Voltage, continuous ....................................................................................................................-0.3 to +30V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +43V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBB (IEC 61000-4-2, 330 Ohm, 150 pF) (Note 3) .............................................. minimum ±9 kV ESD protection on LIN, VBB (Charge Device Model) (Note 2)..............................................................................±1500V ESD protection on LIN, VBB (Human Body Model, 1 kOhm, 100 pF) (Note 4) ....................................................... ±8 kV ESD protection on LIN, VBB (Machine Model) (Note 2) ..........................................................................................±800V ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................ > 4 kV Maximum Junction Temperature ............................................................................................................................. 150C Storage Temperature .................................................................................................................................. -55 to +150C Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. 3: According to IBEE, without bus filter. 4: Limited by Test Equipment. † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2005-2014 Microchip Technology Inc. DS20002018H-page 21 MCP2021/2/1P/2P 2.2 DC Specifications DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Parameter Sym. VBB Quiescent Operating Current IBBQ VBB Transmitter-Off Current IBBTO Min. Typ. Max. Units Conditions 115 210 µA IOUT = 0 mA, LBUS recessive Power — 120 215 µA VOUT = 3.3V — 90 190 µA With VREG on, transmitter off, receiver on, FAULT/TXE = VIL, CS = VIH — 95 210 µA VOUT = 3.3V IBBPD — 16 26 µA With VREG powered-off, receiver on and transmitter off, FAULT/TXE = VIH, TXD = VIH, CS = VIL) IBBNOGND -1 — 1 mA VBB = 12V, GND to VBB, VLIN = 0-18V High-Level Input Voltage (TXD, FAULT/TXE) VIH 2.0 or (0.25 VREG + 0.8) — VREG +0.3 V Low-Level Input Voltage (TXD, FAULT/TXE) VIL -0.3 — 0.15 VREG V High-Level Input Current (TXD, FAULT/TXE) IIH -2.5 — — µA Input voltage = 0.8*VREG Low-Level Input Current (TXD, FAULT/TXE) IIL -10 — — µA Input voltage = 0.2*VREG Pull-up Current on Input (TXD) IPUTXD -3.0 — — µA ~800 kΩ internal pull-up to VREG @ VIH = 0.7*VREG High-Level Input Voltage (CS/LWAKE) VIH 0.7 VREG — VBB V Through a current-limiting resistor Low-Level Input Voltage (CS/LWAKE) VIL -0.3 — 0.3VREG V High-Level Input Current (CS/LWAKE) IIH — — 7.0 µA Input voltage = 0.8*VREG Low-Level Input Current (CS/LWAKE) IIL — — 3.0 µA Input voltage = 0.2*VREG IPDCS — — 6.0 µA ~1.3 MΩ internal pull-down to VSS @ VIH = 3.5V VBB Power-Down Current VBB Current with VSS Floating Microcontroller Interface Pull-down Current on Input (CS/LWAKE) Note 1: 2: 3: Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS20002018H-page 22 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.2 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions High-Level Input Voltage VIH(LBUS) 0.6 VBB — 18 V Recessive state Low-Level Input Voltage VIL(LBUS) -8 — 0.4 VBB V Dominant state — Bus Interface VHYS — Input Hysteresis 0.175 VBB V Low-Level Output Current IOL(LBUS) 40 — 200 mA Output voltage = 0.1 VBB, VBB = 12V Pull-up Current on Input IPU(LBUS) 5 — 180 µA ~30 kΩ internal pull-up @ VIH (LBUS) = 0.7 VBB ISC 50 — 200 mA (Note 1) High-Level Output Voltage VOH(LBUS) 0.8 VBB — VBB V Low-Level Output Voltage VOLLO (LBUS) — — 0.2 VBB V Input Leakage Current (at the receiver during dominant bus level) IBUS_PAS_DOM -1 — — mA Driver off, VBUS = 0V, VBAT = 12V Leakage Current (disconnected from ground) IBUS_NO_GND -1 — +1 mA GNDDEVICE = VBAT, 0V < VBUS < 18V, VBAT = 12V Leakage Current (disconnected from VBAT) IBUS — — 10 µA VBAT = GND, 0 < VBUS < 18V, TA = -40°C to +85°C (Note 3) 50 µA TA = +85°C to +125°C Receiver Center Voltage VBUS_CNT 0.475 VBB 0.5 VBB 0.525 VBB V VBUS_CNT = (VIL (LBUS) + VIH (LBUS))/2 Rslave 20 30 47 k Short Circuit Current Limit Slave Termination VIH (LBUS) - VIL(LBUS) VOH (LBUS) must be at least 0.8 VBB Voltage Regulator – 5.0V Output Voltage Load Regulation Quiescent Current Power Supply Ripple Reject Note 1: 2: 3: VOUT 4.85 5.00 5.15 V 0 mA < IOUT < 50 mA, VOUT2 — 10 50 mV 5 mA < IOUT < 50 mA refer to Section 1.6 “Internal Voltage Regulator” IVRQ — — 25 µA IOUT = 0 mA, (Note 2) PSRR — — 50 dB 1 VPP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition. 2005-2014 Microchip Technology Inc. DS20002018H-page 23 MCP2021/2/1P/2P 2.2 DC Specifications (Continued) DC Specifications Parameter Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBB = 6.0V to 18.0V TA = -40°C to +125°C CREG = 10 µF Sym. Min. Typ. Max. Units Conditions Output Noise Voltage eN — — 100 µVRMS 10 Hz – 40 MHz CFILTER = 10 µf, CBP = 0.1 µf, CLOAD 10 µf, ILOAD = 50 mA Shutdown Voltage VSD 3.5 — 4.0 V Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V Output Voltage VOUT 3.20 3.30 3.40 V Line Regulation VOUT1 — 10 50 mV IOUT = 1 mA, 6.0V < VBB < 18V Load Regulation VOUT2 — 10 50 mV 5 mA < IOUT < 50 mA Refer to Section 1.6 “Internal Voltage Regulator” IVRQ — — 25 µA IOUT = 0 mA, (Note 2) Power Supply Ripple Reject PSRR — — 50 dB 1 VPP @10-20 kHz CLOAD = 10 µf, ILOAD = 50 mA Output Noise Voltage eN — — 100 Shutdown Voltage VSD 2.5 — 2.7 V Input Voltage to Maintain Regulation VBB 6.0 — 18.0 V Input Voltage to Turn Off Output VOFF 4.0 — 4.5 V Input Voltage to Turn On Output VON 5.5 — 6.0 V See Figure 1-11 (Note 2) Voltage Regulator – 3.3V Quiescent Current Note 1: 2: 3: 0 mA < IOUT < 50 mA µVRMS 10 Hz – 40 MHz /Hz CFILTER = 10 µf, CBP = 0.1 µf CLOAD = 10 µf, ILOAD = 50 mA See Figure 1-11 (Note 2) Internal current limited. 2.0 ms maximum recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBB). Characterized, not 100% tested. Node has to sustain the current that can flow under this condition; bus must be operational under this condition. DS20002018H-page 24 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P FIGURE 2-1: ESR CURVES FOR LOAD CAPACITOR SELECTION ESR Curves 10 Instable Unstable Stable only ESR [ohm] 1 with Tantalum or Electrolytic cap. Stable with Tantalum, Electrolytic and Ceramic cap. Instable Unstable 0.1 0.01 Unstable Instable 0.001 0.1 1 10 100 1000 Load Capacitance [µF] Load Capacitor [uF] Note: The graph shows the minimum required capacitance after derating due to tolerance, temperature and voltage. 2005-2014 Microchip Technology Inc. DS20002018H-page 25 MCP2021/2/1P/2P 2.3 AC Specification AC CHARACTERISTICS Parameter VBB = 6.0V to 18.0V; TA = -40°C to +125°C Sym. Min. Typ. Max. Units Test Conditions Bus Interface – Constant Slope Time Parameters Slope rising and falling edges tSLOPE 3.5 — 22.5 µs 7.3V <= VBB <= 18V Propagation Delay of Transmitter tTRANSPD — — 4.0 µs tTRANSPD = max (tTRANSPDR or tTRANSPDF) Propagation Delay of Receiver tRECPD — — 6.0 µs tRECPD = max (tRECPDR or tRECPDF) Symmetry of Propagation Delay of Receiver rising edge w.r.t. falling edge tRECSYM -2.0 — 2.0 µs tRECSYM = max (tRECPDF tRECPDR) Symmetry of Propagation Delay of Transmitter rising edge w.r.t. falling edge tTRANSSYM -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF tTRANSPDR) tFAULT — — 32.5 µs tFAULT = max (tTRANSPD + tSLOPE + tRECPD) Duty Cycle 1 @20.0 kbit/sec 39.6 — — %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω |10 nF; 500Ω THREC(MAX) = 0.744 x VBB, THDOM(MAX) = 0.581 x VBB, VBB =7.0V - 18V; tBIT = 50 µs. D1 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 2 @20.0 kbit/sec — — 58.1 %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω |10 nF; 500Ω THREC(MAX) = 0.284 x VBB, THDOM(MAX) = 0.422 x VBB, VBB =7.6V - 18V; tBIT = 50 µs. D2 = tBUS_REC(MAX) / 2 x tBIT) Duty Cycle 3 @10.4 kbit/sec 41.7 — — %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω |10 nF; 500ΩTHREC(MAX) = 0.778 x VBB, THDOM(MAX) = 0.616 x VBB, VBB =7.0V - 18V; tBIT = 96 µs. D3 = tBUS_REC(MIN) / 2 x tBIT) Duty Cycle 4 @10.4 kbit/sec — — 59.0 %tBIT CBUS;RBUS conditions: 1 nF; 1 kΩ | 6.8 nF; 660Ω |10 nF; 500Ω THREC(MAX) = 0.251 x VBB, THDOM(MAX) = 0.389 x VBB, VBB =7.6V - 18V; tBIT = 96 µs. D4 = tBUS_REC(MAX) / 2 x tBIT) Time to sample of FAULT/ TXE for bus conflict reporting Note 1: 2: Time depends on external capacitance and load. Test condition: CREG=4.7 µF, no resistive load. Characterized, not 100% tested. DS20002018H-page 26 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.3 AC Specification (Continued) AC CHARACTERISTICS VBB = 6.0V to 18.0V; TA = -40°C to +125°C Parameter Sym. Min. Typ. Max. Units Test Conditions tBDB 5 10 20 µs Bus debounce time tBACTVE 100 250 500 µs After bus debounce time Voltage Regulator Enabled to Ready tVEVR — — 1200 µs (Note 1) Chip Select to Operation Ready tCSR — — 500 µs Voltage Regulator Bus Activity Debounce Time Bus Activity to Voltage Regulator Enabled Chip Select to Power-Down tCSPD — — 80 µs Short-Circuit to Shut-Down tSHUTDOWN 20 — 100 µs VREG OK Detect to RESET Inactive tRPU — — 10.0 µs VREG OK Detect to RESET Active tRPD — — 10.0 µs (Note 2) RESET Timing Note 1: 2: 2.4 Time depends on external capacitance and load. Test condition: CREG=4.7 µF, no resistive load. Characterized, not 100% tested. Thermal Specifications (Note 1) THERMAL CHARACTERISTICS Parameter Symbol Typ. Max. Units Recovery Temperature RECOVERY +140 — C Shutdown Temperature SHUTDOWN +150 — C tTHERM 1.5 5.0 ms Thermal Resistance, 4x4 8L-DFN JA 48 — C/W Thermal Resistance, 8L-PDIP JA 89.3 — C/W Thermal Resistance, 8L-SOIC JA 149.5 — C/W Thermal Resistance, 14L-PDIP JA 70 — C/W Thermal Resistance, 14L-SOIC JA 90.8 — C/W Thermal Resistance, 14L-TSSOP JA 100 — C/W Short Circuit Recovery Time Test Conditions Thermal Package Resistances Note 1: The maximum power dissipation is a function of TJMAX, JA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)JA. If this dissipation is exceeded, the die temperature will rise above 150C and the MCP2021 will go into thermal shutdown. 2005-2014 Microchip Technology Inc. DS20002018H-page 27 MCP2021/2/1P/2P 2.5 Typical Performance Curves The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated, VBB = 6.0V to 18.0V; TA = -40°C to +125°C. 0.2 Voltage Regulator Load (mA) 60 0.1 VBB = 6V VBB = 7.3V VBB = 12V VBB = 14.4V VBB = 18V 0 -40C 25C 85C Temperature (°C) 18V SOIC 30 20 10 0 125C Temperature (°C) FIGURE 2-5: Operating Range. Typical IBBQ vs. 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 -40C 40 MCP2021-500 Safe 60 VBB = 6V VBB = 7.3V VBB = 12V VBB = 14.4V VBB = 18V 12V DFN 50 12V SOIC 18V DFN 40 30 18V SOIC 20 10 0 25C 85C 125C -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 mA FIGURE 2-2: Temperature. 12V SOIC 18V DFN -40 -34 -28 -22 -16 -10 -4 2 8 14 20 26 32 38 44 50 56 62 68 74 80 86 92 98 104 110 116 122 0.05 Voltage Regulator Load (mA) IBBQ (mA) 0.15 12V DFN 50 Temperature (°C) Temperature (°C) FIGURE 2-6: Operating Range. Typical IBBTO vs FIGURE 2-3: Temperature. MCP2021-330 Safe 0.025 IPD (mA) 0.02 0.015 0.01 VBB = 6V VBB = 7.3V VBB = 12V VBB = 14.4V VBB = 18V 0.005 0 -40C 25C 85C Temperature (°C) FIGURE 2-4: Temperature. DS20002018H-page 28 125C Typical IBBPD vs. 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 2.6 Timing Diagrams and Specifications FIGURE 2-7: BUS TIMING DIAGRAM TXD 50% 50% LBUS 0.95VLBUS 0.50VBB 0.4VBB 0.0V tTRANSPDR tTRANSPDF tRECPDF tRECPDR RXD 50% Internal TXD/RXD Compare Match 50% Match Match Match Match FAULT Sampling tFAULT tFAULT FAULT/TXE Output FIGURE 2-8: Stable Hold Value Stable Hold Value Stable REGULATOR BUS WAKE TIMING DIAGRAM tVEVR LBUS 0.4VBB tBDB + tBACTVE VREG VOUT 2005-2014 Microchip Technology Inc. DS20002018H-page 29 MCP2021/2/1P/2P FIGURE 2-9: RESET TIMING DIAGRAM 6.0V 5.0V VBB 5.0V 4.0V 3.5V VREG tRPD tRPD RESET tRPU FIGURE 2-10: tRPU CS/LWAKE TO RESET TIMING DIAGRAM CS/LWAKE tCSR tVEVR VREG-NOM VREG tRPD tRPU tCSPD RESET DS20002018H-page 30 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 3.0 PACKAGING INFORMATION 3.1 Package Marking Information 8-Lead DFN (4x4x0.9 mm) (MCP2021, MCP2021P) XXXXXX XXXXXX YYWW NNN PIN 1 Example 202150 3 E/MD e^^ 1426 256 PIN 1 OR 2021P3 3 E/MD e^^ 1426 256 8-Lead DFN-S (6x5x0.9 mm) (MCP2021) Example 2021330 3 E/MF e^^ 1426 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2005-2014 Microchip Technology Inc. DS20002018H-page 31 MCP2021/2/1P/2P 8-Lead PDIP (150 mil) (MCP2021) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) (MCP2021, MCP2021P) NNN Example 2021330 3 E/P e^^256 1426 Example 2021500E SN e^^1426 3 256 OR 2021P33E SN e^^1426 3 256 14-Lead PDIP (300 mil) (MCP2022) Example MCP2022-500 3 E/P e^^ 1426256 DS20002018H-page 32 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 14-Lead SOIC (150 mil) (MCP2022, MCP2022P) Example MCP2022-500 3 E/SL e^^ 1426256 OR 2022P-330 3 E/SL e^^ 1426256 14-Lead TSSOP (4.4 mm) (MCP2022, MCP2022P) XXXXXXXX YYWW NNN Example 2022500E 1426 256 OR 2022P33E 1426 256 2005-2014 Microchip Technology Inc. DS20002018H-page 33 MCP2021/2/1P/2P 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 1 of 2 DS20002018H-page 34 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-131E Sheet 2 of 2 2005-2014 Microchip Technology Inc. DS20002018H-page 35 MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002018H-page 36 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e D L b N N K E E2 EXPOSED PAD NOTE 1 1 2 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 1.27 BSC 0.85 1.00 Standoff A1 0.00 0.01 0.05 Contact Thickness A3 0.20 REF Overall Length D 5.00 BSC Overall Width E Exposed Pad Length D2 3.90 4.00 4.10 Exposed Pad Width E2 2.20 2.30 2.40 6.00 BSC Contact Width b 0.35 0.40 0.48 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. – Microchip Technology Drawing C04-122B 2005-2014 Microchip Technology Inc. DS20002018H-page 37 MCP2021/2/1P/2P ! " ())$$$ ) DS20002018H-page 38 # $ " % & " ' # 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 2005-2014 Microchip Technology Inc. DS20002018H-page 39 MCP2021/2/1P/2P 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (VENDOR DEPENDENT) DATUM A DATUM A b b e 2 e 2 e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness Upper Lead Width b1 b Lower Lead Width Overall Row Spacing eB § e MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-018D Sheet 2 of 2 DS20002018H-page 40 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2014 Microchip Technology Inc. DS20002018H-page 41 MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002018H-page 42 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P ! " #$%& ! " ())$$$ ) 2005-2014 Microchip Technology Inc. # $ " % & " ' # DS20002018H-page 43 MCP2021/2/1P/2P 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .735 .750 .775 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 b1 .045 .060 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-005B DS20002018H-page 44 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2014 Microchip Technology Inc. DS20002018H-page 45 MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002018H-page 46 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P ! " ())$$$ ) 2005-2014 Microchip Technology Inc. # $ " % & " ' # DS20002018H-page 47 MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002018H-page 48 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2014 Microchip Technology Inc. DS20002018H-page 49 MCP2021/2/1P/2P Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002018H-page 50 2005-2014 Microchip Technology Inc. MCP2021/2/1P/2P APPENDIX A: REVISION HISTORY Revision H (July 2014) Revision C (April 2008) The following is the list of modifications: 1. The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Updated Table 1-1. Updated Section 1.4, Pin Descriptions and Section 1.6.1 “5.0V Regulator”. Updated Figures 1-6 and 1-7. Updated Figures 1-10 and 1-11. Added Section 2.5, Typical Performance Curves. Updated Section 3.0, Packaging Information. Updated the Product Identification System section. Minor typographical changes. 2. 3. 4. 5. Added LIN2.1 and J2602 compliance statement to Features section. Added recommended RC network for CS/ LWAKE in Example 1-1. Updated 2.1 “Absolute Maximum Ratings†” to reflect current test results. Updated 2.2 “DC Specifications” and 2.3 “AC Specification” 2.3 AC Specifications to reflect current production device. Added 8-Lead SOIC Landing Pattern Outline drawing. Revision B (August 2007) The following is the list of modifications: Revision G (July 2013) The following has been modified: 1. 2. Added Note 2 in Section 2.3 “AC Specification”. Added pull up to nFAULT/TXE pin in Section 1.4 “Pin Descriptions” and Section 1.5 “Typical Applications”. Revision F (January 2012) The following has been modified: 1. Added the MCP2021P and MCP2022P options and related information throughout the document. Revision E (February 2009) 1. 2. 3. 4. 5. 6. Modified Block Diagram on page 2. Section 1.3.5 “Transmitter-OFF Mode”: Deleted text in 1st paragraph. Example 1-6: Removed +5V notation. Section 1.4 “Pin Descriptions”: Removed 10pin DFN, MSOP column from table. Section 1.4.9 “Fault/Txe”: Deleted text from 2nd paragraph. Section 3.0 “Packaging Information”: Added 8-lead 4x4 and 6x5 DFN and 14-lead TSSOP packages. Updated package outline drawings and added drawings for 8-lead DFN and 14-lead TSSOP drawings. Revision A (November 2005) Original Release of this Document. The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. Added Example 1-7 and Example 1-8. Updated Section 1.4.10 “RESET”. Updated Section 1.7 “ICSP™ Considerations”. Updated Section 2.1 “Absolute Maximum Ratings†”. Updated Section 2.2 “DC Specifications” and Section 2.3 “AC Specification”. Added Figure 2-1 in Section 2.0 “Electrical Characteristics” Updated the Product Identification System section. Revision D (July 2008) The following is the list of modifications: 1. 2. 3. Updated ESD specs under ‘Absolute DC’. Updated notes in Example 1-1. Updated Package Outline Drawings. 2005-2014 Microchip Technology Inc. DS20002018H-page 51 MCP2021/2/1P/2P PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. –XXX X /XX Device Voltage Temperature Range Package Device: Voltage: MCP2021: LIN Transceiver with Voltage Regulator; wakes up on dominant level of LIN bus. MCP2021T: LIN Transceiver with Voltage Regulator; wakes up on dominant level of LIN bus. (Tape and Reel) (SOIC only) MCP2022: LIN Transceiver with Voltage Regulator, and RESET pin; wakes up on dominant level of LIN bus. MCP2022T: LIN Transceiver with Voltage Regulator, and RESET pin; wakes up on dominant level of LIN bus. (Tape and Reel) (SOIC only) MCP2021P: LIN Transceiver with Voltage Regulator; wakes up at a falling edge of LIN bus level. MCP2021PT: LIN Transceiver with Voltage Regulator; wakes up at a falling edge of LIN bus level (Tape and Reel) (SOIC only) MCP2022P: LIN Transceiver with Voltage Regulator, and RESET pin; wakes up at a falling edge of LIN bus level. MCP2022PT: LIN Transceiver with Voltage Regulator, and RESET pin; wakes up at a falling edge of LIN bus level. (Tape and Reel) (SOIC only) 330 = 3.3V 500 = 5.0V Examples: a) b) c) d) e) f) g) h) i) a) b) c) d) e) Temperature Range: E = -40°C to +125°C (Extended) Package: MD = 8-Lead Plastic Dual Flat, No Lead – 4x4x0.9 mm Body (DFN) MF = 8-Lead Plastic Dual Flat, No Lead – 6x5 mm Body (DFN-S) P = 14-Lead Plastic Dual In Line – 300 mil Body (PDIP) SN = 8-Lead Plastic Small Outline – Narrow, 3.90 mm Body (SOIC) SL = 14-Lead Plastic Small Outline – Narrow, 3.90 mm Body (SOIC) ST = 14-Lead Plastic Thin Shrink Small Outline – Narrow, 4.4 mm (TSSOP) DS20002018H-page 52 f) g) MCP2021-500E/MD: 5.0V, Extended Temperature, 8L-DFN package. MCP2021T-500E/MD: Tape and Reel, 5.0V, Extended Temperature, 8L-DFN package. MCP2021-500E/MF: 5.0V, Extended Temperature, 8L-DFN-S package. MCP2021-330E/P: 3.3V, Extended Temperature, 8L-PDIP package. MCP2021-500E/P: 5.0V, Extended Temperature, 8L-PDIP package. MCP2021-330E/SN: 3.3V, Extended Temperature, 8L-SOIC package MCP2021T-330E/SN: Tape and Reel, 3.3V, Extended Temperature, 8L-SOIC package. MCP2021-500E/SN: 5.0V, Extended Temperature, 8L-SOIC package. MCP2021T-500E/SN: Tape and Reel, 5.0V, Extended Temperature, 8L-SOIC package. MCP2022-330E/P: 3.3V, Extended Temperature, 14L-PDIP package. MCP2022-500E/P: 5.0V, Extended Temperature, 14L-PDIP package. MCP2022-330E/SL: 3.3V, Extended Temperature, 14L-SOIC package. MCP2022T-330E/SL: Tape and Reel, 3.3V, Extended Temperature, 14L-SOIC package. MCP2022-500E/SL: 5.0V, Extended Temperature, 14L-SOIC package. MCP2022T-500E/SL: Tape and Reel, 5.0V, Extended Temperature, 14L-SOIC package. MCP2022T-500E/ST: Tape and Reel, 5.0V, Extended Temperature, 14L-TSSOP package. 2005-2014 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2014, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63276-401-0 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2005-2014 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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