Product Folder Sample & Buy Technical Documents Support & Community Tools & Software DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 DRV2511-Q1 8-A Automotive Haptic Driver for Solenoids and Voice Coils 1 Features 3 Description • • • • • The DRV2511-Q1 device is a high current haptic driver specifically designed for inductive loads, such as solenoids and voice coils. 1 • • • Wide Operating Voltage (4.5 V - 26 V) Capable of handling voltage of 30 V High Current Drive (8 A Peak) Low RDS(on), Full H-Bridge Output Integrated Fault Protection – Short-Circuit Protection – Over-temperature Protection – Over-Voltage and Under-Voltage Protection – Fault Reporting Analog Input Dedicated Interrupt Pin AEC-Q100 Qualified with the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C4B The output stage consists of a full H-bridge capable of delivering 8 A of peak current. The DRV2511-Q1 device provides protection functions such as undervoltage lockout, over-current protection and over-temperature protection. The DRV2511-Q1 device is automotive qualified. Device Information(1) PART NUMBER DRV2511-Q1 PACKAGE HTSSOP (32) BODY SIZE (NOM) 11 mm x 6.20 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic PVDD 2 Applications • • • Electromagnetic Actuator Driver – Voice Coil – Solenoid Mechanical Button Replacement Automotive Haptic Applications – Infotainment – Center-Console – Steering Wheel – Door-Panel – Seats AVDD BSTP OUT+ EN STDBY INTZ FS2 M Sole noid/ Voice-Coil FS1 FS0 IN+ INOUT± GAIN REG GND BSTN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 6 6 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 11 7.5 Programming........................................................... 11 8 Application and Implementation ........................ 12 8.1 Application Information............................................ 12 8.2 Typical Applications ................................................ 12 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Example .................................................... 16 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 Device Support .................................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2016) to Revision A • 2 Page Released as Production Data. ............................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 5 Pin Configuration and Functions DAP Package 32-Pin HTSSOP Top View GND 1 32 PVDD EN 2 31 PVDD INTZ 3 30 BSTP IN+ 4 29 OUT+ IN- 5 28 GND REG 6 27 OUT+ REG 7 26 BSTP GAIN 8 25 GND GND 9 24 BSTN GND 10 23 OUT- GND 11 22 GND STDBY 12 21 OUT- FS2 13 20 BSTN FS1 14 19 PVDD FS0 15 18 PVDD N/C 16 17 AVDD Pin Functions PIN TYPE DESCRIPTION NAME NO. GND 1, 9, 10, 11, 22, 25, 28 P Ground. EN 2 I Device enable pin. INTZ 3 O General fault reporting. Open drain. INTZ = High, normal operation INTZ = Low, fault condition IN+ 4 I Positive differential input. IN- 5 I Negative differential input. REG 6, 7 P Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the MODE resistor divider. GAIN 8 I Selects Gain. STDBY 12 I Standby pin. FS2 13 I Output switching frequency selection. FS1 14 I Output switching frequency selection. FS0 15 I Output switching frequency selection. N/C 16 N/C AVDD 17 P Analog Supply, can be connected to VBAT for single power supply operation. PVDD 18, 19, 31, 32 P Power supply. BSTN 20, 24 P Boot strap for negative output, connect to 220 nF X5R, or better ceramic cap to OUT-. OUT- 21, 23 O Negative output. BSTP 26, 30 P Boot strap for positive output, connect to 220 nF X5R, or better ceramic cap to OUT+. Pin should be left floating. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 3 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com Pin Functions (continued) PIN NAME NO. OUT+ 27, 29 TYPE Thermal Pad or PowerPAD™ DESCRIPTION O Positive output. G Connect to GND for best system performance. If not connected to GND, leave floating. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Input voltage, VI Current (1) MIN MAX UNIT PVDD, AVDD –0.3 30 V IN+, IN- –0.3 6.3 GAIN –0.3 VREG + 0.3 EN –0.3 PVDD + 0.3 –8 8 Operating free-air temperature, TA –40 125 Storage temperature range, Tstg –50 150 (1) DC current on PVDD, GND, OUT+, OUT- V A °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings V(ESD) (1) (2) Electrostatic discharge MIN MAX Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –2000 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –450 450 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM 4.5 MAX 26 UNIT VDD Supply voltage. PVDD, AVDD. VIH High-level input voltage. STDBY, EN, FS0, FS1, FS2. VIL Low-level input voltage. STDBY, EN, FS0, FS1, FS2. 0.8 V VOL Low-level output voltage. INTZ, RPULL-UP = 100 kΩ, PVDD = 26 V. 0.8 V IIH High-level input current. STDBY, EN, FS0, FS1, FS2. (VI = 2 V, PVDD = 26 V). 50 µA RL Minimum load Impedance. Lo Output-filter Inductance. 2 V V 1.65 1 Ω µH 6.4 Thermal Information DRV2511-Q1 THERMAL METRIC (1) DAP UNIT 32 PINS RθJA Junction-to-ambient thermal resistance 32.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 17.2 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 Thermal Information (continued) DRV2511-Q1 THERMAL METRIC (1) DAP UNIT 32 PINS RθJB Junction-to-board thermal resistance 17.3 °C/W ψJT Junction-to-top characterization parameter 0.4 °C/W ψJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1 °C/W Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 5 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com 6.5 Electrical Characteristics TA = 25°C, AVCC = PVDD = 12 V, RL = 5 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 15 UNIT | VOS | Output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB 1.5 IVDD Quiescent supply current No load or filter 20 mA IVDD(SD) Quiescent supply current in shutdown mode No load or filter 35 µA IVDD(STD Quiescent supply current in standby mode No load or filter 11 mA Drain-source on-state resistance, measured pin to pin TJ = 25°C 60 mΩ mV BY) rDS(on) G Gain R1 = open, R2 = 20 kΩ 19 20 21 R1 = 100 kΩ, R2 = 20 kΩ 25 26 27 R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 R1 = 75 kΩ, R2 = 47 kΩ 35 36 37 6.4 6.9 7.4 VREG Regulator voltage BW Full Power Bandwidth VO Output voltage (measured differentially) Measured at PVDD = 26V PSRR Power supply ripple rejection 200 mVpp ripple at 1 kHz, Gain = 20 dB CMRR Common-mode rejection ratio fOSC Oscillator frequency (with PWM duty cycle < 96%) 60 dB V kHz 50 V –70 dB –56 dB FS2 = 0, FS1 = 0, FS0 = 0 376 400 424 FS2 = 0, FS1 = 0, FS0 = 1 470 500 530 FS2 = 0, FS1 = 1, FS0 = 0 564 600 636 FS2 = 0, FS1 = 1, FS0 = 1 940 1000 1060 FS2 = 1, FS1 = 0, FS0 = 0 1128 1200 1278 Power-on threshold dB kHz 4.1 Power-off threshold V 28 V 150 °C Thermal hysteresis 15 °C Over-current trip point 13 A Over-voltage trip point 28 V Thermal trip point 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS ton-sd Turn-on time from shutdown to waveform EN = Low to High, STBY = Low tOFF-sd Turn-off time ton-stdby Turn-on time from standby to waveform 6 MIN TYP MAX UNIT 10 ms EN = High to Low 5 µs EN = High, STBY = High to Low 6 µs Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 6.7 Typical Characteristics 55.0 28.00 50.0 26.00 Standby Current (mA) Shutdown Current (mA) 45.0 40.0 35.0 30.0 25.0 24.00 22.00 20.00 18.00 16.00 20.0 14.00 15.0 10.0 12.00 4 6 8 10 12 14 16 18 20 VDD − Supply Voltage (V) 22 24 Figure 1. Shutdown Current vs VDD Voltage 26 4 6 8 10 12 14 16 18 20 VDD − Supply Voltage (V) 22 24 26 Figure 2. Standby Current vs VDD Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 7 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com 7 Detailed Description 7.1 Overview The DRV2511-Q1 device is a high current haptic driver specifically designed for inductive loads, such as solenoids and voice coils. The output stage consists of a full H-bridge capable of delivering 8 A of peak current. The design uses an ultra-efficient switching output technology developed by Texas Instruments, but with features added for the automotive industry. The DRV2511-Q1 device provides protection functions such as undervoltage lockout, over-current protection and over-temperature protection. This technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system. The DRV2511-Q1 device is automotive qualified. 7.2 Functional Block Diagram REG PVDD AVDD BSTP Reg PVDD Digital Cor e EN OUT+ Gate Drive POR Control STDBY INTZ Inte rrupt Control M OT Thermal Pro tection PVDD VDD VDD Sole noid/ Voice-Coil OVV UVLO Over-Curren t Pro tection Critical Condition Control OC Critical_Event Gate Drive OUT± OSC BSTN FS2 PWM Log ic FS1 FS0 IN+ INGAIN Gai n Control GND 8 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 7.3 Feature Description 7.3.1 Analog Input and Configurable Pre-amplifier The DRV2511-Q1 device features a differential input stage that cancels common-mode noise that appears on the inputs. The DRV2511-Q1 device also features four gain settings that are configurable via external resistors. Table 1. Gain Configuration Table GAIN R1 R2 INPUT IMPEDANCE 20 dB 5.6 kΩ open 60 kΩ 26 dB 20 kΩ 100 kΩ 30 kΩ 32 dB 39 kΩ 100 kΩ 15 kΩ 36 dB 47 kΩ 75 kΩ 9 kΩ REG R2 GAIN R1 GND Figure 3. Gain Configuration 7.3.2 Pulse-Width Modulator (PWM) The DRV2511-Q1 device features BD modulation scheme with high bandwidth, low noise, low distortion, and excellent stability. The BD modulation scheme allows for smaller ripple currents through the load. Each output switches from 0 V to the supply voltage. With no input, the OUT+ and OUT- pins are in phase with each other so that there is little or no current in the load. For positive differential inputs, the duty cycle of OUT+ is greater than 50% and the duty cycle of OUT- is lower than 50% for a positive differential output voltage. The opposite is true for negative differential inputs. The voltage accross the load sits at 0 V throughout most of the switching period, reducing the switching current, which reduces the I2R losses in the load. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 9 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com No Output OUT+ OUT- OUT+ - OUT- 0 V Solenoid Current 0 A Positive Output OUT+ OUT- OUT+ - OUT- 0 V Solenoid Current 0 A Negative Output OUT+ OUT- OUT+ - OUT- 0 V Solenoid Current 0 A Figure 4. BD Mode Modulation 7.3.3 Designed for low EMI The DRV2511-Q1 device design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that optimizes output transitions that causes EMI. Follow the recommended design requirements in the Design Requirements section. 7.3.4 Device Protection Systems The DRV2511-Q1 device features a complete set of protection circuits carefully designed to protect the device against permanent failures due to shorts, over-temperature, over-voltage, and under-voltage scenarios. The INTZ pin signals if an error is detected. 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 Table 2. Fault Reporting Table FAULT TRIGGERING CONDITION INTZ ACTION LATCH? Latched Over-current Output short or short to PVDD or GND pulled low output in high impedance Over-temperature Tj > 150 ºC pulled low output in high impedance Latched Under-voltage PVDD < 4.5 V - output in high impedance Self-clearing Over-voltage PVDD > 27 V - output in high impedance Self-clearing When the "Latched" conditions happen, the device must be reset with the EN signal in order to clear the fault. If automatic recovery from these conditions is desired, connect the INTZ pin directly to the EN pin. This allows the INTZ pin function to automatically drive the EN pin low which clears the latched condition. 7.4 Device Functional Modes The DRV2511-Q1 device has multiple power states to optimize power consumption. 7.4.1 Operation in Shutdown Mode The NRST pin of the DRV2511-Q1 device puts the device in a shutdown mode. When NRST is asserted (logic low), all internal blocks of the device are off to achieve ultra low power. 7.4.2 Operation in Standby Mode The STDBY pin of the DRV2511-Q1 device puts the device in a standby mode. When STDBY is asserted (logic high), some internal blocks of the device are off to achieve low power while preserving the ability to wake up quickly to achieve low latency waveform playback. 7.4.3 Operation in Active Mode The DRV2511-Q1 device is in active mode when it has a valid supply, and it is not in either shutdown or standby modes. In this mode the DRV2511-Q1 device is fully on and reproducing at the output the input times the gain. 7.5 Programming 7.5.1 Gain The DRV2511-Q1 device has a configurable gain that is controlled through external resistors. Please see the Analog Input and Configurable Pre-amplifier section for more details. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 11 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The DRV2511-Q1 device is a high-efficiency driver for inductive loads, such as solenoids and voice-coils. The typical use of the device is on haptic applications where short, strong waveforms are desired to create a haptic event that will be coming from the application processor. 8.2 Typical Applications 8.2.1 Single-Ended Source To use the DRV2511-Q1 with a single-ended source, apply either a voltage divider to bias INB to 3 V, tie to GND or use a 0.1-μF cap from INB to GND to have the device self bias. Apply the single-ended signal to the INA pin. PVDD C2 AVDD BSTP C1 Optiona l App lica tion Pro cessor L1 R(PU) OUT+ EN GPIO STDBY C7 GPIO R1 INTZ C4 GPIO FS2 GPIO M FS1 GPIO Sole noid/ Voice-Coil FS0 GPIO C5 IN+ PWM+ R2 LPF L2 IN- OUT± GAIN C9 REG R(GAIN) C8 C6 C3 GND BSTN Optiona l Figure 5. Typical Application Schematic 8.2.1.1 Design Requirements For most applications the following component values found in Table 3 below can be used. 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 Typical Applications (continued) Table 3. Component Requirements Table COMPONENT DESCRIPTION SPECIFICATION TYPICAL VALUE Supply capacitor Capacitance 22 µF and 0.1 µF for PVDD & AVDD C2/C3 Boost capacitor Capacitance 0.22 µF C4/C5 Output snubber capacitor Capacitance 470 pF C6 Regulator capacitor Capacitance 1 µF C9 Input decoupling capacitor Capacitance 0.1 µF R1/R2 Output snubber resistor Resistance 3.3 Ω R(PU) Pull-up resistor Resistance 100 kΩ C1 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Optional Components Note that in the diagrams, there are a few optional external components. These optional external components may be needed in the application to meet EMI/EMC standards and specifications by filters necessary frequency spectrums. 8.2.1.2.2 Capacitor Selection A bulk bypass capacitor should be mounted between VBAT and GND. The capacitance needs to be >22 uF with a X5R or better rating on the power pins to GND. Also include two ceramic capacitors in the ranges of 220 pF to 1 uF and 100 nF to 1 uF. The bootstrap capacitors, BSTA and BSTB, should be 220-nF ceramic capacitors of quality X5R or better rated for at least the maximum rating of the pin. 8.2.1.2.3 Solenoid Selection The DRV2511-Q1 solenoid driver can accommodate a variety of solenoids. Solenoids should have an equivalent resistance of 1.6 Ω or greater. Solenoids with lower resistances are prone to driving high currents. A maximum peak current of 8-A should not be exceeded. The DRV2511-Q1 will go into a shutdown mode to protect itself from overcurrent. 8.2.1.2.4 Output Filter Considerations The output filter is optional and is mainly for limiting peak currents. A second-order Butterworth low-pass filter with the cut-off frequency set to a few kilohertz should be sufficient. See Equation 2, Equation 3, and Equation 4 for example filter design. 1 H(s) = 2 s + 2s + 1 (1) Lx = 2 ´ RL 2wo (2) 2 RL ´ w0 2´ 2 w0 = 2p ´ ƒ 2 ´ CF = (3) (4) 8.2.1.3 Application Curves These application curves were taken using an HA200 solenoid with a 100-g mass, and the acceleration was measured using the DRV-AAC16-EVM accelerometer. The following scales apply to the graphs: • Output Differential Voltage scale is shown on the plots at 5-V/div • Acceleration scale is 5.85-G/div • Current scale is 2-A/div Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 13 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com Acceleration Input [OUT+] − [OUT−] Voltage (5V/div) Voltage (5V/div) Acceleration Current [OUT+] − [OUT−] 0 2m 4m 6m 8m 10m 12m Time (s) 14m 16m 18m 20m 0 Figure 6. Voltage and Acceleration vs Time (Input Square Wave) 2m 4m 6m 8m 10m 12m Time (s) 14m 16m 18m 20m Figure 7. Voltage and Acceleration vs Time (Square Wave) Voltage (5V/div) Acceleration Current [OUT+] − [OUT−] Voltage (5V/div) Acceleration Current [OUT+] − [OUT−] 0 2m 4m 6m 8m 10m 12m Time (s) 14m 16m 18m 20m Figure 8. Voltage and Acceleration vs Time (Ramp Wave) 0 2m 4m 6m 8m 10m 12m Time (s) 14m 16m 18m 20m Figure 9. Voltage and Acceleration vs Time (1/2 Sine Wave) 8.2.1.4 Differential Input Diagram To use the DRV2511-Q1 with a differential input source, apply both inputs differentially from a control source (GPIO, DAC, etc...). 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 PVDD C2 AVDD BSTP C1 Optiona l App lica tion Pro cessor L1 R(PU) OUT+ EN GPIO STDBY C7 GPIO R1 INTZ C4 GPIO FS2 GPIO M FS1 GPIO Sole noid/ Voice-Coil FS0 GPIO C5 IN+ PWM+ R2 LPF L2 IN- OUT± LPF PWM- GAIN REG C8 C6 R(GAIN) C3 GND BSTN Optiona l Figure 10. Typical Application Schematic Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 15 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com 9 Power Supply Recommendations The DRV2511-Q1 device operates from 4.5 V - 26 V and this supply should be able to handle high surge currents in order to meet the high currrent draws for haptics effects. Additionally the DRV2511-Q1 should have 22-µF and 0.1-µF ceramic capacitors near the PVDD & AVDD pins for additional decoupling from trace routing. 10 Layout 10.1 Layout Guidelines The EVM layout optimizes for thermal dissipation and EMC performance. The DRV2511-Q1 device has a thermal pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC performance. It is best practice to use the same/similiar layout as shown below in the DRV2511Q1EVM. 10.2 Layout Example Figure 11. DRV2511-Q1 EVM 16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 DRV2511-Q1 www.ti.com SLOS916A – JUNE 2016 – REVISED JULY 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Trademarks PowerPAD is a trademark of Texas Instruments. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 17 DRV2511-Q1 SLOS916A – JUNE 2016 – REVISED JULY 2016 www.ti.com 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: DRV2511-Q1 PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2016 PACKAGING INFORMATION Orderable Device Status (1) DRV2511QDAPRQ1 PREVIEW Package Type Package Pins Package Drawing Qty HTSSOP DAP 32 2000 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 125 DRV2511Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2016 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV2511QDAPRQ1 Package Package Pins Type Drawing SPQ HTSSOP 2000 DAP 32 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.5 1.6 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Jul-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV2511QDAPRQ1 HTSSOP DAP 32 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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