Altera EVB-ER3105DI 500ma wide vin synchronous buck regulator Datasheet

Enpirion® Power Datasheet
ER3105DI 500mA Wide VIN
Synchronous Buck Regulator
DS-1041
Datasheet
The Altera® Enpirion® ER3105DI is a 500mA Synchronous
buck regulator with an input range of 3V to 36V. It provides an
easy to use, high efficiency low BOM count solution for a
variety of applications.
Features
The ER3105DI integrates both high-side and low-side NMOS
FET's and features a PFM mode for improved efficiency at
light loads. This feature can be disabled if forced PWM mode
is desired. The part switches at a default frequency of 500kHz
but may also be programmed using an external resistor from
300kHz to 2MHz. The ER3105DI has the ability to utilize
internal or external compensation. By integrating both NMOS
devices and providing internal configuration options, minimal
external components are required, reducing BOM count and
complexity of design.
• No compensation required
With the wide VIN range and reduced BOM the part provides
an easy to implement design solution for a variety of
applications while giving superior performance. It provides a
very robust design for industrial, battery, and FPGA power
applications.
• Power-good and enable functions available.
The part is available in a small Pb free 4mmx3mm DFN
plastic package with an operation temperature range of
-40°C to +125°C
• Wide input voltage range 3V to 36V
• Synchronous Operation for high efficiency
• Integrated High-side and Low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal fixed (500kHz) or adjustable Switching frequency
300kHz to 2MHz
• Continuous output current up to 500mA
• Internal or external Soft-start
• Minimal external components required
Applications
• FPGA power
• Digital processor power
• Mixed-signal ASIC power
• Industrial control
• Medical devices
• Portable instrumentation
• Distributed Power supplies
• Cloud Infrastructure
100
VIN = 15V
95
VIN = 12V
VIN = 5V
1
2
3
CBOOT
100nF
CVIN
10µF
5
VOUT
COUT
10µF
4
L1
22µH
6
SS
FSW
COMP
SYNC
12
11
R2
10
BOOT
FB
GND
PVIN
9
AVINO
SW
R3
CAVINO
1µF
CFB
EFFICIENCY (%)
90
POK
PGND
85
80
75
70
VIN = 24V
65
VIN = 33V
60
EN
55
50
INTERNAL DEFAULT PARAMETER SELECTION
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION
101 Innovation Drive
San Jose, CA 95134
www.altera.com
March 2014
FIGURE 2. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
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www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed
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ISO
9001:2008
Registered
Altera Corporation
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09616
March 14, 2014
Rev A
Page 2
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ER3105DI
3105
EVB-ER3105DI
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(Pb-Free)
12 Ld DFN
PKG.
DWG. #
L12.4x3
NOTES:
1. Add “T” suffix for Tape and Reel.
2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
March 2014
March 14, 2014
Altera Corporation
Rev A
Page 3
Pin Configuration
ER3105DI
(12 LD 4X3 DFN)
TOP VIEW
12 FSW
SS 1
SYNC 2
11 COMP
BOOT 3
10 FB
PVIN 4
9
AVINO
SW 5
8
POK
7
EN
PGND 6
GND
Pin Descriptions
09616
PIN NUMBER
SYMBOL
PIN DESCRIPTION
1
SS
The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground
determines the output ramp rate. See “Soft Start” on page 16 for soft-start details. If the SS pin is tied
to AVINO, an internal soft-start of 2ms will be used.
2
SYNC
Synchronization and light load operational mode selection input. Connect to logic high or AVINO for
PWM mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to
automatically choose PFM or PWM operation. Connect to an external clock source for synchronization
with positive edge trigger. Sync source must be higher than the programmed IC frequency. There is an
internal 5M pull-down resistor to prevent an undefined logic state if SYNC is left floating.
3
BOOT
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor
from this pin to SW.
4
PVIN
The input supply for the power stage of the regulator and the source for the internal linear bias
regulator. Place a minimum of 4.7µF ceramic capacitance from PVIN to GND and close to the IC for
decoupling.
5
SW
6
PGND
7
EN
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground.
When the voltage on this pin rises above 1V, the chip is enabled. Connect this pin to PVIN for
automatic start-up. Do not connect EN pin to AVINO since the LDO is controlled by EN voltage.
8
POK
Open drain power-good output that is pulled to ground when the output voltage is below regulation
limits or during the soft-start interval. There is an internal 5M internal pull-up resistor.
9
AVINO
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the
pin.
10
FB
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is
the output of the error amplifier. The output voltage is set by an external resistor divider connected to
FB. In addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator
output voltage.
11
COMP
COMP is the output of the error amplifier. When it is tied to AVINO, internal compensation is used.
When only an RC network is connected from COMP to GND, external compensation is used. See
“Loop Compensation Design” on page 21 for more details.
12
FSW
Frequency selection pin. Tie to AVINO for 500kHz switching frequency. Connect a resistor to GND
for adjustable frequency from 300kHz to 2MHz.
EPAD
GND
Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage
levels are measured with respect to this pin. The EPAD MUST not float.
March 2014
Altera Corporation
Switch node output. It connects the switching FET’s with the external output inductor.
Power ground connection. Connect directly to the system GND plane.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 4
Typical Application Schematics
1
2
3
CBOOT
100nF
4
CVIN
10µF
5
VOUT
COUT
10µF
L1
22µH
6
FSW
SS
COMP
SYNC
12
11
R2
CFB
10
BOOT
FB
GND
PVIN
9
AVINO
SW
R3
CAVINO
1µF
POK
PGND
EN
FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION
1
CSS
SS
FSW
2
COMP
SYNC
3
CBOOT
100nF
4
CVIN
10µF
5
VOUT
L1
22µH
COUT
10µF
6
12
RFSW
11
R2
CFB
10
BOOT
FB
GND
9
PVIN
AVINO
SW
R3
CAVINO
1µF
POK
RCOMP
PGND
EN
CCOMP
FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION
TABLE 1. EXTERNAL COMPONENT SELECTION
VOUT
(V)
L1
(µH)
COUT
(µF)
R2
(k)
R3
(k)
CFB
(pF)
RFSW
(k)
RCOMP
(k)
CCOMP
(pF)
12
45
10
90.9
4.75
22
115
100
470
5
22
2 x 22
90.9
12.4
100
120
100
470
3.3
22
2 x 22
90.9
20
100
120
100
470
2.5
22
2 x 22
90.9
28.7
100
120
100
470
1.8
22
22
100
50
22
120
50
470
March 2014
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
March 14, 2014
Rev A
Page 5
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V
SW to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V (DC)
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 43V (20ns)
EN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V
BOOT to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FSW, POK, SYNC, SS, AVINO to GND . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
ESD Rating
Human Body Model (Tested per JESD22-A114). . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E) . . . . . 1.5kV
Machine Model (Tested per JESD22-A115) . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . 100mA
JC (°C/W)
Thermal Resistance
JA (°C/W)
DFN Package (Notes 3, 4) . . . . . . .
44
5.5
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +125°C
Operating Junction Temperature Range . . . . . . . . . -40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . —
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 36V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
TA = -40°C to +125°C, VIN = 3V to 36V, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the junction temperature range, -40°C to +125°C
PARAMETER
SYMBOL
MIN
(Note 7)
TEST CONDITIONS
TYP
MAX
(Note 7)
UNITS
SUPPLY VOLTAGE
VIN Voltage Range
VIN
3
36
VIN Quiescent Supply Current
IQ
VFB = 0.7V, SYNC = 0V, FSW =
AVINO
80
VIN Shutdown Supply Current
ISD
EN = 0V, VIN=36V (Note 5)
1.8
AVINO Voltage
AVINO
V
µA
2.5
µA
IOUT = 0mA
4.8
5.15
5.5
V
VIN = 6V; IOUT = 10mA
4.65
5
5.35
V
2.75
2.95
V
POWER-ON RESET
AVINO POR Threshold
Rising Edge
Falling Edge
2.4
2.6
V
FSW = AVINO
440
500
560
Resistor from FSW to GND = 340k
240
300
360
OSCILLATOR
Nominal Switching Frequency
FSW
kHz
kHz
Resistor from FSW to GND = 32.4k
2000
kHz
Minimum Off-Time
tOFF
VIN = 3V
150
ns
Minimum On-Time
tON
(Note 8)
90
ns
FSW Voltage
VFSW
Synchronization Frequency
SYNC
RFSW = 100kΩ
0.39
0.4
300
SYNC Pulse Width
0.41
V
2000
kHz
100
ns
ERROR AMPLIFIER
Error Amplifier
Transconductance Gain
gm
FB Voltage
March 2014
09616
165
Internal Compensation
230
295
50
VFB = 0.6V
FB Leakage Current
Current Sense Amplifier Gain
External Compensation
µA/V
µA/V
1
100
nA
0.54
0.6
0.66
V/A
TA = -40°C to +85°C
0.589
0.599
0.606
V
TA = -40°C to +125°C
0.589
0.599
0.609
V
RT
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 6
Electrical Specifications
TA = -40°C to +125°C, VIN = 3V to 36V, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the junction temperature range, -40°C to +125°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
90
94
%
POWER-GOOD
Lower POK Threshold - VFB
Rising
Lower POK Threshold - VFB
Falling
82.5
Upper POK Threshold - VFB
Rising
86
%
116.5
Upper POK Threshold - VFB
Falling
107
POK Propagation Delay
Percentage of the soft-start time
POK Low Voltage
ISINK = 3mA, EN = AVINO, VFB = 0V
120
%
112
%
10
%
0.05
0.3
V
1.5
2
2.5
µA
1.7
2.4
3.1
ms
TRACKING AND SOFT-START
Soft-Start Charging Current
ISS
Internal Soft-Start Ramp Time
EN/SS = AVINO
FAULT PROTECTION
Thermal Shutdown Temperature
TSD
Rising Threshold
150
°C
THYS
Hysteresis
20
°C
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart
Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
PFM Peak Current Limit
IPK_PFM
(Note 6)
0.8
0.9
1
A
0.26
0.3
0.34
A
-0.46
-0.40
-0.34
A
ISW = 100mA, AVINO = 5V
450
600
m
ISW = 100mA, AVINO = 5V
250
330
m
300
nA
Zero Cross Threshold
Negative Current Limit
10
INLIMIT
(Note 6)
mA
POWER MOSFET
High-side
RHDS
Low-side
RLDS
SW Leakage Current
SW Rise Time
EN = SW = 0V
tRISE
VIN = 36V
10
ns
EN/SYNC
Input Threshold
Falling Edge, Logic Low
0.4
Rising Edge, Logic High
1
V
1.2
1.4
V
EN Logic Input Leakage Current
EN = 0V/36V
0.5
µA
SYNC Logic Input Leakage
Current
SYNC = 0V
-0.5
10
100
nA
SYNC = 5V
1.0
1.3
µA
NOTES:
5. Test Condition: VIN = 36V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included.
6. Established by both current sense amplifier gain test and current sense amplifier output test @ IL = 0A.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
8. Minimum On-Time required to maintain loop stability.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
March 2014
March 14, 2014
Altera Corporation
Rev A
Page 7
Efficiency Curves
FSW = 800kHz, TA = +25°C
100
100
VIN = 6V
90
90
85
85
80
75
V
V
V
V
V
VIN = 33V
VIN = 24V
70
65
65
55
50
0
90
85
85
80
75
VIN = 33V
VIN = 24V
65
80
75
65
60
55
55
0
50
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
0.35 0.40 0.45
0.50
100
95
VIN = 15V
VIN = 12V
95
VIN = 5V
90
VIN = 15V
90
85
EFFICIENCY (%)
EFFICIENCY (%)
0.20 0.25 0.30
FIGURE 8. EFFICIENCY vs LOAD, PWM, VOUT = 3.3V
100
80
75
70
65
VIN = 24V
VIN = 33V
75
70
55
0.50
50
0
VIN = 33V
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
0.50
OUTPUT LOAD (A)
FIGURE 10. EFFICIENCY vs LOAD, PWM, VOUT = 1.8V
FIGURE 9. EFFICIENCY vs LOAD, PFM, VOUT = 1.8V
March 2014
VIN = 24V
65
55
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
VIN = 5V
80
60
0
VIN = 12V
85
60
OUTPUT LOAD (A)
09616
0.05 0.10 0.15
OUTPUT LOAD (A)
FIGURE 7. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
50
VIN = 33V
VIN = 24V
70
60
50
0.50
VIN = 5V
VIN = 12V
VIN = 15V
95
EFFICIENCY (%)
EFFICIENCY (%)
100
VIN = 5V
90
70
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
FIGURE 6. EFFICIENCY vs LOAD, PWM, VOUT = 5V
100
VIN = 12V
0.05
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD, PFM, VOUT = 5V
VIN = 15V
VIN = 33V
70
60
95
VIN = 6V
VIN = 24V
75
55
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
VIN = 12V
80
60
50
0
VIN = 15V
95
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 12V
VIN = 15V
95
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 8
Efficiency Curves
FSW = 800kHz, TA = +25°C (Continued)
5.018
5.020
VIN = 6V
5.012
5.010
VIN = 24V
5.008
5.010
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VIN = 12V
5.014
VIN = 33V
5.005
VIN = 24V
5.000
VIN = 15V
4.990
4.985
4.980
VIN = 33V
5.004
0
4.975
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD, PWM, VOUT = 5V
OUTPUT VOLTAGE (V)
3.332
VIN = 12V
VIN = 5V
3.330
3.328
3.326
VIN = 12V
VIN = 24V
VIN = 33V
3.335
VIN = 24V
3.330
VIN = 15V
3.325
3.320
3.315
VIN = 33V
0
3.310
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
0
OUTPUT LOAD (A)
FIGURE 13. VOUT REGULATION vs LOAD, PWM, VOUT = 3.3V
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 14. VOUT REGULATION vs LOAD, PFM, VOUT = 3.3V
1.777
1.785
1.776
1.780
VIN = 15V
1.775
1.774
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VIN = 5V
3.340
3.324
VIN = 12V
1.773
1.772
VIN = 5V
1.771
VIN = 5V
VIN = 15V
1.775
1.770
VIN = 12V
VIN = 24V
1.765
VIN = 33V
1.760
1.770
0
VIN = 33V
VIN = 24V
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 15. VOUT REGULATION vs LOAD, PWM, VOUT = 1.8V
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
3.345
VIN = 15V
3.334
3.322
0
FIGURE 12. VOUT REGULATION vs LOAD, PFM, VOUT = 5V
3.336
1.769
VIN = 12V
4.995
5.006
OUTPUT VOLTAGE (V)
VIN = 6V
5.015
VIN = 15V
5.016
1.755
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 16. VOUT REGULATION vs LOAD, PFM, VOUT = 1.8V
March 2014
March 14, 2014
Altera Corporation
Rev A
Page 9
Efficiency Curves
FSW = 500kHz, TA = +25°C
100
VIN = 12V
95
100
VIN = 6V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
90
85
VIN = 24V
80
VIN = 15V
75
VIN = 33V
70
65
60
90
85
VIN = 24V
80
75
VIN = 33V
70
65
55
0
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
0
OUTPUT LOAD (A)
FIGURE 17. EFFICIENCY vs LOAD, PFM, VOUT = 5V
100
VIN = 12V
95
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
VIN = 5V
90
85
80
VIN = 24V
75
70
VIN = 15V
VIN = 33V
65
85
80
70
60
55
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
VIN = 15V
VIN = 33V
65
55
0
VIN = 24V
75
60
FIGURE 19. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 20. EFFICIENCY vs LOAD, PWM, VOUT = 3.3V
100
100
95
95
85
80
75
VIN = 15V
70
VIN = 24V
65
60
80
75
70
VIN = 15V
VIN = 24V
65
60
VIN = 33V
55
50
50
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
VIN = 33V
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 22. EFFICIENCY vs LOAD, PWM, VOUT = 1.8V
FIGURE 21. EFFICIENCY vs LOAD, PFM, VOUT = 1.8V
March 2014
VIN = 5V
85
55
0
VIN = 12V
90
VIN = 5V
OUTPUT VOLTAGE (V)
VIN = 12V
90
OUTPUT VOLTAGE (V)
VIN = 12V
95
VIN = 5V
90
09616
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 18. EFFICIENCY vs LOAD, PWM, VOUT = 5V
100
50
VIN = 15V
60
55
50
VIN = 6V
VIN = 12V
95
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 10
Efficiency Curves
FSW = 500kHz, TA = +25°C (Continued)
100
100
VIN = 24V
90
90
85
85
80
75
70
65
80
75
70
65
60
60
55
55
50
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
VIN = 24V
95
EFFICIENCY (%)
EFFICIENCY (%)
95
50
0.1
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
OUTPUT LOAD (A)
FIGURE 23. EFFICIENCY vs LOAD, PFM, VOUT = 1.8V
FIGURE 24. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
5.022
100
VIN = 24V
95
5.020
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
90
85
80
75
70
65
60
5.018
5.016
VIN = 12V
VIN = 6V
5.014
5.012
5.010
VIN = 33V
5.008
55
50
0.1
OUTPUT LOAD (A)
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
5.006
0.1
VIN = 24V
0
OUTPUT LOAD (A)
FIGURE 25. EFFICIENCY vs LOAD, PFM, VOUT = 5V
VIN = 15V
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 26. VOUT REGULATION vs LOAD, PWM, VOUT = 5V
5.040
VIN = 12V
OUTPUT VOLTAGE (V)
5.030
VIN = 6V
5.020
5.010
5.000
VIN = 33V
VIN = 15V
VIN = 24V
4.990
4.980
4.970
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 27. VOUT REGULATION vs LOAD, PFM, VOUT = 5V
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
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March 2014
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Altera Corporation
Rev A
Page 11
Efficiency Curves
FSW = 500kHz, TA = +25°C (Continued)
3.360
3.350
VIN = 15V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.348
3.346
3.344
VIN = 12V
3.342
3.340
VIN = 33V
3.336
0
VIN = 15V
3.345
3.335
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
VIN = 5V
VIN = 24V
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 29. VOUT REGULATION vs LOAD, PFM, VOUT = 3.3V
1.812
1.820
1.811
1.818
OUTPUT VOLTAGE (V)
VIN = 15V
1.810
OUTPUT VOLTAGE (V)
3.350
VIN = 24V
FIGURE 28. VOUT REGULATION vs LOAD, PWM, VOUT = 3.3V
1.809
1.808
VIN = 12V
1.807
1.806
1.805
VIN = 5V
1.804
1.803
VIN = 12V
VIN = 33V
3.340
VIN = 5V
3.338
3.355
1.814
VIN = 12V
1.812
1.810
1.808
VIN = 33V
1.806
VIN = 5V
1.804
VIN = 33V
0
VIN = 15V
1.816
VIN = 24V
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 30. VOUT REGULATION vs LOAD, PWM, VOUT = 1.8V
1.802
VIN = 24V
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT LOAD (A)
FIGURE 31. VOUT REGULATION vs LOAD, PFM, VOUT = 1.8V
Typical Performance Curves
VIN = 24V, VOUT = 3.3V, FSW = 800kHz, TA = +25°C.
SW 20V/DIV
SW 20V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
POK 2V/DIV
POK 2V/DIV
5ms/DIV
5ms/DIV
FIGURE 32. START-UP AT NO LOAD, PFM
FIGURE 33. START-UP AT NO LOAD, PWM
March 2014
09616
VOUT 2V/DIV
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 12
Typical Performance Curves
VIN = 24V, VOUT = 3.3V, FSW = 800kHz, TA = +25°C. (Continued)
SW 20V/DIV
SW 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
POK 2V/DIV
POK 2V/DIV
500ms/DIV
500ms/DIV
FIGURE 34. SHUTDOWN IN NO LOAD, PFM
FIGURE 35. SHUTDOWN AT NO LOAD, PWM
SW 20V/DIV
SW 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 500mA/DIV
POK 2V/DIV
POK 2V/DIV
50µs/DIV
5ms/DIV
FIGURE 36. START-UP AT 500mA, PWM
FIGURE 37. SHUTDOWN AT 500mA, PWM
SW 20V/DIV
SW 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 500mA/DIV
POK 2V/DIV
POK 2V/DIV
5ms/DIV
50µs/DIV
FIGURE 38. START-UP AT 500mA, PFM
FIGURE 39. SHUTDOWN AT 500mA, PFM
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
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Altera Corporation
Rev A
Page 13
Typical Performance Curves
VIN = 24V, VOUT = 3.3V, FSW = 800kHz, TA = +25°C. (Continued)
SW 5V/DIV
SW 5V/DIV
50ns/DIV
50ns/DIV
FIGURE 40. JITTER AT NO LOAD, PWM
FIGURE 41. JITTER AT 500mA, PWM
SW 20V/DIV
SW 20V/DIV
VOUT 10mV/DIV
VOUT 10mV/DIV
IL 100mA/DIV
IL 200mA/DIV
5ms/DIV
500ns/DIV
FIGURE 42. STEADY STATE AT NO LOAD, PFM
FIGURE 43. STEADY STATE AT NO LOAD, PWM
SW 20V/DIV
SW 20V/DIV
VOUT 50mV/DIV
VOUT 10mV/DIV
IL 500mA/DIV
IL 200mA/DIV
1µs/DIV
10µs/DIV
FIGURE 44. STEADY STATE AT 500mA LOAD, PWM
FIGURE 45. LIGHT LOAD OPERATION AT 20mA, PFM
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Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 14
Typical Performance Curves
VIN = 24V, VOUT = 3.3V, FSW = 800kHz, TA = +25°C. (Continued)
SW 20V/DIV
VOUT 100mV/DIV
VOUT 10mV/DIV
IL 500mA/DIV
IL 100mA/DIV
1µs/DIV
200µs/DIV
FIGURE 46. LIGHT LOAD OPERATION AT 20mA, PWM
FIGURE 47. LOAD TRANSIENT, PFM
SW 20V/DIV
VOUT 50mV/DIV
VOUT 10mV/DIV
IL 500mA/DIV
IL 1A/DIV
2µs/DIV
200µs/DIV
FIGURE 49. PFM TO PWM TRANSITION
FIGURE 48. LOAD TRANSIENT, PWM
SW 20V/DIV
SW 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 1A/DIV
POK 2V/DIV
20µs/DIV
FIGURE 50. OVERCURRENT PROTECTION, PWM
FIGURE 51. OVERCURRENT PROTECTION HICCUP, PWM
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
POK 2V/DIV
50ms/DIV
March 2014
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Altera Corporation
Rev A
Page 15
Typical Performance Curves
VIN = 24V, VOUT = 3.3V, FSW = 800kHz, TA = +25°C. (Continued)
SW 20V/DIV
SW 20V/DIV
VOUT 5V/DIV
SYNC 2V/DIV
IL 0.5A/DIV
POK 2V/DIV
200ns/DIV
10µs/DIV
FIGURE 52. SYNC AT 500mA LOAD, PWM
FIGURE 53. NEGATIVE CURRENT LIMIT, PWM
SW 20V/DIV
VOUT 5V/DIV
VOUT 2V/DIV
IL 0.5A/DIV
POK 2V/DIV
POK 2V/DIV
500µs/DIV
200µs/DIV
FIGURE 54. NEGATIVE CURRENT LIMIT RECOVERY, PWM
March 2014
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Altera Corporation
FIGURE 55. OVER-TEMPERATURE PROTECTION, PWM
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 16
PVIN
POK
EN
SS
Functional Block Diagram
FB
POWER
GOOD
LOGIC
5M
AVINO
BIAS
LDO
EN/SOFT
START
FB
FAULT
LOGIC
600mV VREF
FSW
SYNC
600mV/Amp
Current Sense
OSCILLATOR
5M
PWM/PFM
SELECT LOGIC
PFM
CURRENT
SET
FB
BOOT
GATE
DRIVE
AND
PWM DEADTIME
PWM
s Q
R Q
Zero Current
Detection
SW
PGND
450mV/T Slope
Compensation
(PWM only)
gm
150k
PACKAGE
PADDLE
COMP
GND
Internal
54pF Compensation
Internal = 50µs
External = 230µs
Functional Description
The ER3105DI combines a synchronous buck PWM controller with integrated power switches. The buck controller drives internal
high-side and low-side N-channel MOSFETs to deliver load current up to 500mA. The buck regulator can operate from an
unregulated DC source, such as a battery, with a voltage ranging from +3V to +36V. An internal LDO provides bias to the low
voltage portions of the IC.
Peak current mode control is utilized to simplify feedback loop compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design. The ER3105DI switches at a default 500kHz.
The buck regulator is equipped with an internal current sensing circuit and the peak current limit threshold is typically set at 0.9A.
Power-On Reset
The ER3105DI automatically initializes upon receipt of the input power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold the IC is held in shutdown and consumes typically 1µA from the PVIN supply. If EN exceeds
its logic rising threshold, the regulator will enable the bias LDO and begin to monitor the AVINO pin voltage. When the AVINO
pin voltage clears its rising POR threshold the controller will initialize the switching regulator circuits. If AVINO never clears the
rising POR threshold, the controller will not allow the switching regulator to operate. If AVINO falls below its falling POR
threshold while the switching regulator is operating, the switching regulator will be shut down until AVINO returns.
Soft Start
To avoid large in-rush current, VOUT is slowly increased at startup to its final regulated value. Soft-start time is determined by the
SS pin connection. If SS is pulled to AVINO, an internal 2ms timer is selected for soft-start. For other soft-start times, simply
connect a capacitor from SS to GND. In this case, a 2µA current pulls up the SS voltage and the FB pin will follow this ramp until
it reaches the 600mV reference level. Soft-start time for this case is described by Equation 1:
Time  ms  = C  nF  0.3
(EQ. 1)
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
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Altera Corporation
Rev A
Page 17
Power-OK
POK is the open-drain output of a window comparator that continuously monitors the buck regulator output voltage via the FB pin.
POK is actively held low when EN is low and during the buck regulator soft-start period. After the soft-start period completes,
POK becomes high impedance provided the FB pin is within the range specified in the “Electrical Specifications” on page 3.
Should FB exit the specified window, POK will be pulled low until FB returns. Over-temperature faults also force POK low until
the fault condition is cleared by an attempt to soft-start. There is an internal 5M internal pull-up resistor.
PWM Control Scheme
The ER3105DI employs peak current-mode pulse-width modulation (PWM) control for fast transient response and pulse-by-pulse
current limiting, as shown in the “Functional Block Diagram” on page 16. The current loop consists of the current sensing circuit,
slope compensation ramp, PWM comparator, oscillator and latch. Current sense trans-resistance is typically 600mV/A and slope
compensation rate, Se, is typically 450mV/T where T is the switching cycle period. The control reference for the current loop
comes from the error amplifier’s output (VCOMP).
A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET is turned on. Current begins to ramp up in the upper
FET and inductor. This current is sensed (VCSA), converted to a voltage and summed with the slope compensation signal. This
combined signal is compared to VCOMP and when the signal is equal to VCOMP, the latch is reset. Upon latch reset the upper FET is
turned off and the lower FET turned on allowing current to ramp down in the inductor. The lower FET will remain on until the clock
initiates another PWM cycle. Figure 56 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate
the sum of the current sense and slope compensation signal.
Output voltage is regulated as the error amplifier varies VCOMP and thus output inductor current. The error amplifier is a
trans-conductance type and its output (COMP) is terminated with a series RC network to GND. This termination is internal
(150k/54pF) if the COMP pin is tied to AVINO. Additionally, the trans-conductance for COMP = AVINO is 50µs vs 220µs for
external RC connection. Its non-inverting input is internally connected to a 600mV reference voltage and its inverting input is
connected to the output voltage via the FB pin and its associated divider network.
VCOMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 56. PWM OPERATION WAVEFORMS
Light Load Operation
At light loads, converter efficiency may be improved by enabling variable frequency operation (PFM). Connecting the SYNC pin
to GND will allow the controller to choose such operation automatically when the load current is low. Figure 57 shows the DCM
operation. The IC enters the DCM mode of operation when 8 consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak inductor ripple current and set by the following Equation 2:
V OUT  1 – D 
I OUT = ----------------------------------2LF SW
(EQ. 2)
where D = duty cycle, FSW = switching frequency, L = inductor value, IOUT = output loading current, VOUT = output voltage.
While operating in PFM mode, the regulator controls the output voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The current pulses are approximately 300mA and are issued at a
frequency equal to the converters programmed PWM operating frequency.
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ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 18
PWM
DCM
PULSE SKIP
PWM
DCM
OCK
8 CYCLES
IL
LOAD CURRENT
0
VOUT
FIGURE 57. DCM MODE OPERATION WAVEFORMS
Due to the pulsed current nature of PFM mode, the converter can supply limited current to the load. Should load current rise
beyond the limit, VOUT will begin to decline. A second comparator signals an FB voltage 1% lower than the 600mV reference
and forces the converter to return to PWM operation.
Output Voltage Selection
The regulator output voltage is easily programmed using an external resistor divider to scale VOUT relative to the internal reference
voltage. The scaled voltage is applied to the inverting input of the error amplifier; refer to Figure 57.
The output voltage programming resistor, R3, depends on the value chosen for the feedback resistor, R2, and the desired output
voltage, VOUT, of the regulator. Equation 3 describes the relationship between VOUT and resistor values.
R 2 x0.6V
R 3 = ---------------------------------V OUT – 0.6V
(EQ. 3)
If the desired output voltage is 0.6V, then R3 is left unpopulated and R2 is 0Ω.
VOUT
FB
+
-
EA
R2
R3
0.6V
REFERENCE
FIGURE 58. EXTERNAL RESISTOR DIVIDER
Protection Features
The ER3105DI is protected from overcurrent, negative overcurrent and over-temperature. The protection circuits operate
automatically.
Overcurrent Protection
During PWM on-time, current through the upper FET is monitored and compared to a nominal 0.9A peak overcurrent limit. In the
event that current reaches the limit, the upper FET will be turned off until the next switching cycle. In this way, FET peak current
is always well limited.
If the overcurrent condition persists for 17 sequential clock cycles, the regulator will begin its hiccup sequence. In this case, both
FETS will be turned off and POK will be pulled low. This condition will be maintained for 8 soft-start periods after which, the
regulator will attempt a normal soft-start.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
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Page 19
Should the output fault persist, the regulator will repeat the hiccup sequence indefinitely. There is no danger even if the output is
shorted during soft-start.
If VOUT is shorted very quickly, FB may collapse below 5/8ths of its target value before 17 cycles of overcurrent are detected. The
ER3105DI recognizes this condition and will begin to lower its switching frequency proportional to the FB pin voltage. This
insures that under no circumstance (even with VOUT near 0V) will the inductor current run away.
Negative Current Limit
Should an external source somehow drive current into VOUT, the controller will attempt to regulate VOUT by reversing its inductor
current to absorb the externally sourced current. In the event that the external source is low impedance, current may be reversed to
unacceptable levels and the controller will initiate its negative current limit protection. Similar to normal overcurrent, the negative
current protection is realized by monitoring the current through the lower FET. When the valley point of the inductor current reaches
negative current limit, the lower FET is turned off and the upper FET is forced on until current reaches the POSITIVE current limit or
an internal clock signal is issued. At this point, the lower FET is allowed to operate. Should the current again be pulled to the negative
limit on the next cycle, the upper FET will again be forced on and current will be forced to 1/6th of the positive current limit. At this
point the controller will turn off both FET’s and wait for COMP to indicate return to normal operation. During this time, the controller
will apply a 100 load from SW to PGND and attempt to discharge the output. Negative current limit is a pulse-by-pulse style
operation and recovery is automatic. Negative current limit protection is disabled in PFM operating mode because reverse current is
not allowed to build due to the diode emulation behavior of the lower FET.
Over-Temperature Protection
Over-temperature protection limits maximum junction temperature in the ER3105DI. When junction temperature (TJ) exceeds
+150°C, both FET’s are turned off and the controller waits for temperature to decrease by approximately 20°C. During this time
POK is pulled low. When temperature is within an acceptable range, the controller will initiate a normal soft-start sequence. For
continuous operation, the +125°C junction temperature rating should not be exceeded.
Boot Undervoltage Protection
If the Boot capacitor voltage falls below 1.8V, the Boot undervoltage protection circuit will turn on the lower FET for 400ns to
recharge the capacitor. This operation may arise during long periods of no switching such as PFM no load situations. In PWM
operation near dropout (VIN near VOUT), the regulator may hold the upper FET on for multiple clock cycles. To prevent the boot
capacitor from discharging, the lower FET is forced on for approximately 200ns every 10 clock cycles.
Application Guidelines
Simplifying the Design
While the ER3105DI offers user programmed options for most parameters, the easiest implementation with fewest components
involves selecting internal settings for SS, COMP and FSW. Table 1 on page 4 provides component value selections for a variety
of output voltages and will allow the designer to implement solutions with a minimum of effort.
Operating Frequency
The ER3105DI operates at a default switching frequency of 500kHz if FSW is tied to AVINO. Tie a resistor from FSW to GND to
program the switching frequency from 300kHz to 2MHz, as shown in Equation 4.
R FSW  k  = 108.75k  t – 0.2s   1s
(EQ. 4)
Where:
t is the switching period in µs.
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Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 20
RFSW (kΩ)
300
200
100
0
500
750
1000
1250
1500
1750
2000
FSW (kHz)
FIGURE 59. RFSW SELECTION vs FSW
Synchronization Control
The frequency of operation can be synchronized up to 2MHz by an external signal applied to the SYNC pin. The rising edge on the
SYNC triggers the rising edge of SW. To properly sync, the external source must be at least 10% greater than the programmed free
running IC frequency.
Output Inductor Selection
The inductor value determines the converter’s ripple current. Choosing an inductor current requires a somewhat arbitrary choice of
ripple current, I. A reasonable starting point is 30% of total load current. The inductor value can then be calculated using
Equation 5:
L=
VIN - VOUT
FSW x DI
x
VOUT
(EQ. 5)
VIN
Increasing the value of inductance reduces the ripple current and thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient. The inductor current rating should be such that it will not saturate in
overcurrent conditions. For typical ER3105DI applications, inductor values generally lies in the 10µH to 47µH range. In general,
higher VOUT will mean higher inductance.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations on the PC board. Electrolytic and polymer capacitors may also be
used.
While ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered.
Ceramic capacitors are rated using large peak-to-peak voltage swings and with no DC bias. In the DC/DC converter application,
these conditions do not reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value.
Consult the manufacturers data sheet to determine the actual in-application capacitance. Most manufacturers publish capacitance
vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published, but an
assumption of ~20% further reduction will generally suffice. The result of these considerations may mean an effective capacitance
50% lower than nominal and this value should be used in all design calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely low ESR.
The following equations allow calculation of the required capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
I
V OUTripple = --------------------------------------8 F SW C OUT
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
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(EQ. 6)
March 2014
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Altera Corporation
Rev A
Page 21
where I is the inductor’s peak-to-peak ripple current, FSW is the switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 7)
Loop Compensation Design
When COMP is not connected to AVINO, the COMP pin is active for external loop compensation. The ER3105DI uses constant
frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current sensing pilot device
in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant, and the system becomes a single order system. It is much easier to
design a type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an
inherent input voltage feed-forward function to achieve good line regulation. Figure 60 shows the small signal model of the
synchronous buck regulator.
+
^
iin
^
Vin
ILd^ 1:D
^
iL
LP
vo^
RLP
Vin d^
+
Rc
GAIN (VLOOP (S(fi))
RT
Co
Ro
Ti(S)
d^
K
Fm
+
Tv(S)
He(S)
v^comp
-Av(S)
FIGURE 60. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK REGULATOR
Vo
R2
C3
VFB
R3
VREF
-
VCOMP
GM
+
R6
C7
C6
FIGURE 61. TYPE II COMPENSATOR
Figure 61 shows the type II compensator and its transfer function is expressed, as shown in Equation 8:
S
S 
 1 + ------------ 1 + -------------

 cz2
 cz1 
GM  R 3
v̂ COMP
A v  S  = -------------------- = -------------------------------------------------------- -------------------------------------------------------------- C6 + C7    R2 + R3  
S
S
v̂ FB
S 1 + -------------  1 + -------------





cp1
(EQ. 8)
cp2
where,
Compensator design goal:
High DC gain
March 2014
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Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 22
C6 + C7
R2 + R3
1
1
 cz1 = --------------- ,  cz2 = ---------------  cp1 = -----------------------  cp2 = ----------------------R6 C6 C7
C3 R2 R3
R6 C6
R2 C3
Choose Loop bandwidth fc less than 100kHz
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of fc has a unity gain. Therefore, the compensator resistance R6 is determined by Equation 9.
2f c V o C o R t
3
R 6 = ---------------------------------- = 27.3 10  f c V o C o
GM  V FB
(EQ. 9)
Where GM is the trans-conductance, gm, of the voltage error amplifier in each phase. Compensator capacitor C6 is then given by
Equation 10.
Ro Co Vo Co
Rc Co
1
C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------------)
R6
Io R6
R 6 f SW R 6
(EQ. 10)
Put one compensator pole at zero frequency to achieve high DC gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in Equation 10. An optional zero can boost the phase margin. CZ2 is a
zero due to R2 and C3
Put compensator zero 2 to 5 times fc
1
C 3 = ---------------f c R 2
(EQ. 11)
Example: VIN = 12V, VO = 5V, IO = 500mA, fSW = 500kHz, R2 = 90.9k, Co = 22µF/5mΩ, L = 39µH, fc = 50kHz, then
compensator resistance R6:
3
R 6 = 27.3 10  50kHz  5V  22F = 150.2k
(EQ. 12)
It is acceptable to use 150kas theclosest standard value for R6.
5V  22 F
C 6 = ------------------------------------------- = 1.46nF
500mA  150k
(EQ. 13)
 22F-,--------------------------------------------------1
C 7 = max (5m
--------------------------------) = (0.7pF,4.2pF) (EQ. 14)
150k
  500kHz  150k
It is also acceptable to use the closest standard values for C6 and C7. There is approximately 3pF parasitic capacitance from VCOMP to
GND; Therefore, C7 is optional. Use C6 = 1500pF and C7 = OPEN.
1
C 3 = -------------------------------------------------- = 70pF
  50kHz  90.9k
(EQ. 15)
Use C3 = 68pF. Note that C3 may increase the loop bandwidth from previous estimated value. Figure 62 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin. This can be accomplished by lowering R6 by 20% to 30%. In practice, ceramic
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
March 2014
March 14, 2014
Altera Corporation
Rev A
Page 23
capacitors have significant derating on voltage and temperature, depending on the type. Please refer to the ceramic capacitor
datasheet for more details.
60
45
GAIN (dB)
30
15
0
-15
-30
100
1k
10k
100k
1M
FREQUENCY (Hz)
180
150
PHASE (°)
120
90
60
30
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 62. SIMULATED LOOP GAIN
Layout Considerations
Proper layout of the power converter will minimize EMI and noise and insure first pass success of the design. PCB layouts are
available from Altera. In addition, Figure 63 will make clear the important points in PCB layout. In reality, PCB layout of the
ER3105DI is quite simple.
A multi-layer printed circuit board with GND plane is recommended. Figure 63 shows the connections of the critical components
in the converter. Note that capacitors CIN and COUT could each represent multiple physical capacitors. The most critical
connections are to tie the PGND pin to the package GND pad and then use vias to directly connect the GND pad to the system
GND plane. This connection of the GND pad to system plane insures a low impedance path for all return current, as well as an
excellent thermal path to dissipate heat. With this connection made, place the high frequency MLCC input capacitor near the PVIN
pin and use vias directly at the capacitor pad to tie the capacitor to the system GND plane.
The boot capacitor is easily placed on the PCB side opposite the controller IC and 2 vias directly connect the capacitor to BOOT
and SW.
Place a 1µF MLCC near the AVINO pin and directly connect its return with a via to the system GND plane.
Place the feedback divider close to the FB pin and do not route any feedback components near SW or BOOT. If external
components are used for SS, COMP or FSW the same advice applies.
March 2014
09616
Altera Corporation
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A
Page 24
CAV I NO
RFSW
FIGURE 63. PRINTED CIRCUIT BOARD POWER PLANES AND
Document Revision History
The table lists the revision history for this document.
Date
March 2014
Version
1.0
Changes
Initial release.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
09616
March 2014
March 14, 2014
Altera Corporation
Rev A
Page 25
Package Outline Drawing
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 7/10
3.30 +0.10/-0.15
4.00
6
PIN 1
INDEX AREA
2X 2.50
A
10X 0.50
PIN #1 INDEX AREA
B
6
1
12 X 0.40 ±0.10
6
1.70 +0.10/-0.15
3.00
(4X)
0.15
7
12
TOP VIEW
0.10M C A B
4 12 x 0.23 +0.07/-0.05
BOTTOM VIEW
SEE DETAIL "X"
( 3.30)
6
0.10 C
1
C
1.00 MAX
SEATING PLANE
0.08 C
SIDE VIEW
2.80
( 1.70 )
C
0.2 REF
5
12 X 0.60
7
12
0 . 00 MIN.
0 . 05 MAX.
( 12X 0.23 )
( 10X 0 . 5 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
March 2014
09616
Altera Corporation
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Compliant to JEDEC MO-229 V4030D-4 issue E.
ER3105DI 500mA Wide VIN Synchronous Buck Regulator
March 14, 2014
Rev A