IXYS IX2113G Outputs capable of sourcing and sinking 2a Datasheet

IX2113
600V High and Low Side
Gate Driver
INTEGRATED CIRCUITS DIVISION
Driver Characteristics
Parameter
Description
Rating
Units
VOFFSET
600
V
IO +/- (Source/Sink)
2/2
A
VOUT
10-20
V
ton/toff
113/100
ns
20
ns
Delay Matching (Max)
The IX2113 is a high voltage integrated circuit that can
drive high speed MOSFETs and IGBTs that operate at
up to +600V. The IX2113 is configured with
independent high-side and low-side referenced output
channels, both of which can source and sink 2A. The
floating high-side channel can drive an N-channel
power MOSFET or IGBT 600V from the common
reference.
Features
• Floating Channel for Bootstrap Operation to +600V
with Absolute Maximum Rating of +700V
• Outputs Capable of Sourcing and Sinking 2A
• Gate Drive Supply Range From 10V to 20V
• Enhanced Robustness due to SOI Process
• Tolerant to Negative Voltage Transients:
dV/dt Immune
• 3.3V Logic Compatible
• Undervoltage Lockout for Both High-side and
Low-Side Outputs
• Matched Propagation Delays
Manufactured on IXYS Integrated Circuits Division's
proprietary high-voltage BCDMOS on SOI (silicon on
insulator) process, the IX2113 is extremely robust, and
is virtually immune to negative transients. The UVLO
circuit prevents the turn-on of the MOSFET or IGBT
until there is sufficient VBS or VCC supply voltage.
Propagation delays are matched for use in high
frequency applications.
The IX2113 is available in a 14-pin DIP package and
in a 16-pin SOIC package.
Ordering Information
Part
Description
IX2113G
14-Pin DIP (25/Tube)
IX2113B
16-Pin SOIC (50/Tube)
IX2113BTR
16-Pin SOIC (1000/Reel)
IX2113 Functional Block Diagram
VDD
HIN
SD
Input Control Logic
&
Cycle-by-Cycle
Edge-Triggered
Shutdown
Level
Shift
VDD / VCC
VSS / COM
VB
High
Voltage
Level
Shift
Pulse
Generator
R
S
R
Q
Buffer
Level
Shift
VDD / VCC
VSS / COM
LS Delay
Control
HO
VS
VCC
UVLO
LIN
VSS
UVLO
Buffer
LO
COM
DS-IX2113-R03
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1
IX2113
INTEGRATED CIRCUITS DIVISION
1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Package Pinout: 16-Pin SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Pin Description: 16-Pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Package Pinout: 14-Pin DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Pin Description: 14-Pin DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Static Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Test Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
4
4
5
5
6
2. Typical Performance Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
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11
11
11
11
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R03
IX2113
INTEGRATED CIRCUITS DIVISION
1 Specifications
1.1 Package Pinout: 16-Pin SOIC Package
LO - 1
COM - 2
VCC - 3
4
5
VS - 6
VB - 7
HO - 8
1.3 Package Pinout: 14-Pin DIP Package
16
15 - VSS
14 - LIN
13 - SD
12 - HIN
11 - VDD
10
9
14
LO - 1
COM - 2
13 - VSS
VCC - 3
12 - LIN
4
11 - SD
VS - 5
10 - HIN
VB - 6
9 - VDD
8
HO - 7
1.2 Pin Description: 16-Pin SOIC Package
1.4 Pin Description: 14-Pin DIP Package
Pin#
Name
Low-Side Gate Drive Output
1
LO
COM
Low-Side Return
2
COM
Low-Side Return
3
VCC
Low-Side Supply
3
VCC
Low-Side Supply
4
-
No Connection
4
-
5
-
No Connection
5
VS
High-Side Floating Supply Return
6
VS
High-Side Floating Supply Return
6
VB
High-Side Floating Supply
7
VB
High-Side Floating Supply
7
HO
High-Side Gate Drive Output
8
HO
High-Side Gate Drive Output
8
-
9
-
No Connection
9
VDD
Logic Supply
10
-
No Connection
10
HIN
11
VDD
Logic Supply
Logic Input for High-Side Gate Driver
Output (HO), In-Phase
11
SD
Logic Input for Shutdown
HIN
Logic Input for High-Side Gate Driver
Output (HO), In-Phase
12
LIN
Logic Input for Low-Side Gate Driver
Output (LO), In-Phase
13
VSS
Logic Ground
14
-
Pin#
Name
1
LO
2
12
Description
13
SD
Logic Input for Shutdown
14
LIN
Logic Input for Low-Side Gate Driver
Output (LO), In-Phase
15
VSS
Logic Ground
16
-
R03
Description
Low-Side Gate Drive Output
No Connection
No Connection
No Connection
No Connection
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3
IX2113
INTEGRATED CIRCUITS DIVISION
1.5 Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board-mounted and still-air conditions.
Parameter
Symbol
Min
Max
Units
High-Side Floating Supply Voltage
VB
-0.3
700
V
High-Side Floating Supply Offset Voltage
VS
VB-20
VB+0.3
V
High-Side Floating Output Voltage
VHO
VS-0.3
VB+0.3
V
Low-Side Fixed Supply Voltage
VCC
-0.3
20
V
Low-Side Output Voltage
VLO
-0.3
VCC+0.3
V
Logic Supply Voltage
VDD
-0.3
VSS+20
V
Logic Supply Offset Voltage
VSS
VCC-20
VCC+0.3
V
VIN
VSS-0.3
VDD+0.3
V
dVS/dt
-
50
V/ns
-
1.25
Logic Input Voltage (HIN, LIN, SD)
Allowable Offset Supply Voltage Transient
Package Power Dissipation @ TA  25°C
Thermal Resistance, Junction to Ambient
16-Pin SOIC
14-Pin DIP
16-Pin SOIC
14-Pin DIP
PD
1.6
RJA
TJ
TS
TL
Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 Seconds)
-
100
75
-
150
W
°C/W
-55
150
°C
°C
-
300
°C
1.6 Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions. The VS and VSS offset ratings
are tested with all supplies biased at a 15V differential.
Parameter
Symbol
Min
Max
High-Side Floating Supply Absolute Voltage
VB
VS+10
VS+20
High-Side Floating Supply Offset Voltage
High-Side Floating Output Voltage
VS
-
600
VHO
VS
VB
Low-Side Fixed Supply Voltage
VCC
10
20
Low-Side Output Voltage
VLO
0
VCC
Logic Supply Voltage
VDD
VSS+3
VSS+20
Logic Supply Offset Voltage
Logic Input Voltage (HIN, LIN, SD)
VSS
-5
5
VIN
VSS
VDD
Ambient Temperature
TA
-40
+125
4
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Units
V
°C
R03
IX2113
INTEGRATED CIRCUITS DIVISION
1.7 Dynamic Electrical Characteristics
VBIAS (VCC, VBS, VDD)=15V, CL=1000 pF, TA=25°C, and VSS=COM unless otherwise specified.
Parameter
Turn-On propagation Delay
Turn-Off propagation Delay
Shutdown propagation Delay
Conditions
Symbol
Min
Typ
Max
VS=0V
ton
-
113
160
toff
-
100
150
tSD
-
94
160
VS=600V
Turn-On Rise Time
-
tr
-
9.4
35
Turn-Off Fall Time
-
tf
-
9.7
25
Delay Matching, HS & LS Turn-On/Off
-
MT
-
-
20
Units
ns
1.8 Static Electrical Characteristics
VBIAS (VCC, VBS, VDD)=15V, TA=25°C and VSS=COM unless otherwise specified. The VIN, VTH, and IIN parameters
are referenced to VSS and are applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters
are referenced to COM and are applicable to the respective output leads: HO or LO.
Parameter
Symbol
Min
Typ
Max
VIH
9.5
-
-
VIL
-
-
6
VIH
2.5
-
-
VIL
-
-
0.8
IO=0A
VOH
-
1.6
2.5
Low-Level Output Voltage, VO
IO=20mA
VOL
-
-
0.15
Offset Supply Leakage Current
VB=VS=600V
ILK
-
-
60
Quiescent VBS Supply Current
VIN=0V or VDD
IQBS
-
187
310
Quiescent VCC Supply Current
VIN=0V or VDD
IQCC
-
300
420
Quiescent VDD Supply Current
VIN=0V or VDD
IQDD
-
-
1
Logic “1” Input Bias Current
VIN=VDD
IIN+
-
22
40
Logic “0” Input Bias Current
VIN=0V
IIN-
-
-
5
VBB Supply Undervoltage Positive Going Threshold
-
VBSUV+
7.5
8.4
9.7
VBB Supply Undervoltage Negative Going Threshold
-
VBSUV-
7
7.8
9.4
VCC Supply Undervoltage Positive Going Threshold
-
VCCUV+
7.4
8.4
9.6
VCC Supply Undervoltage Negative Going Threshold
-
VCCUV-
7
7.8
9.4
Output High Short Circuit Pulsed Current
VO=0V, VIN=VDD , PW10s
IO+
2
2.5
-
Output Low Short Circuit Pulsed Current
VO=15V, VIN=0V, PW10s
IO-
2
2.5
-
Logic “1” Input Voltage
Logic “0” Input Voltage
Logic “1” Input Voltage
Logic “0” Input Voltage
High-Level Output Voltage, VBIAS-VO
R03
Conditions
VDD=15V
VDD=3V
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Units
V
V
V
A
A
V
A
5
IX2113
INTEGRATED CIRCUITS DIVISION
1.9 Test Waveforms
1.9.1 Switching Time Test Circuit
VCC=15V
VB
10µF
0.1µF
11
3
+
10µF 15V
7
0.1µF
-V
6
12
HIN
8
S
CL
HO
13
SD
LIN
10µF
1
14
(0 to 500V/600V)
LO
CL
15
1.9.2 Input/Output Timing Diagram
Note: Pin numbers shown
are for the SOIC package.
2
1.9.4 Shutdown Waveform Definitions
HIN
LIN
50%
SD
SD
tsd
HO
LO
HO
LO
1.9.3 Switching Time Waveform Definition
HIN
LIN
ton
50%
50%
tr
toff
90%
HO
LO
90%
1.9.5 Delay Matching Waveform Definitions
HIN
LIN
50%
tf
LO
50%
HO
90%
10%
10%
MT
10%
MT
90%
LO
6
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HO
R03
IX2113
INTEGRATED CIRCUITS DIVISION
2 Typical Performance Data
Turn-On Delay Time
vs. Temperature
250
200
150
100
50
200
150
100
50
25
50
75
Temperature (ºC)
100
150
100
50
0
-50
125
-25
0
25
50
75
Temperature (ºC)
100
125
Shutdown Delay Time
vs. Temperature
250
200
150
100
50
200
150
100
50
0
0
11
13
15
17
Supply Voltage (V)
19
-50
21
Shutdown Delay Time
vs. VDD Supply Voltage
-25
0
25
50
75
Temperature (ºC)
100
125
Turn-On Rise Time (ns)
250
200
150
100
50
40
30
20
10
0
5
10
15
VDD Supply Voltage (V)
20
21
Shutdown Delay Time
vs. VBIAS Supply Voltage
100
50
0
10
12
14
16
18
VBIAS Supply Voltage (V)
20
Turn-Off Fall Time vs. Temperature
50
40
30
20
10
0
0
0
19
150
Turn-On Rise Time vs. Temperature
300
13
15
17
Supply Voltage (V)
200
50
350
11
250
Turn-Off Fall Time (ns)
9
9
Shutdown Propagation Delay (ns)
0
Shutdown Delay Time (ns)
Turn-Off Delay Time (ns)
-25
Turn-Off Delay Time
vs. VBIAS Supply Voltage
250
Shutdown Delay Time (ns)
200
0
0
R03
250
Turn-On Delay Time (ns)
Turn-Off Delay Time (ns)
Turn-On Delay Time (ns)
250
-50
Turn-On Delay Time
vs. VBIAS Supply Voltage
Turn-Off Delay Time vs. Temperature
-50
-25
0
25
50
75
Temperature (ºC)
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100
125
-50
-25
0
25
50
75
Temperature (ºC)
100
125
7
IX2113
INTEGRATED CIRCUITS DIVISION
30
25
20
15
10
5
25
20
15
10
5
12
10
8
6
4
2
0
14
16
18
VBIAS Supply Voltage (V)
15
18
12
9
6
3
2.0
1.5
1.0
0.5
0.0
25
50
75
Temperature (ºC)
100
500
400
300
200
100
-25
0
25
50
75
Temperature (ºC)
100
0
25
50
75
Temperature (ºC)
100
125
15
18
21
6
3
-50
60
40
20
-25
0
25
50
75
Temperature (ºC)
100
125
VDD Supply Current vs. Temperature
20
15
10
5
0
0
-25
0
25
50
75
Temperature (ºC)
100
-50
125
VBS Supply Current vs. Temperature
400
300
200
100
-50
-25
0
25
50
75
Temperature (ºC)
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100
125
-25
0
25
50
75
Temperature (ºC)
100
125
VDD Supply Current vs. Voltage
1.0
0
-25
9
12
VDD (V)
9
125
80
500
6
12
100
-50
VCC Supply Current vs. Temperature
0
-50
3
15
Logic "1" Input Bias Current
vs. Temperature
125
VBS Supply Current (µA)
600
0
2
0
-50
Logic "1" Input Bias Current (µA)
2.5
-25
4
Logic "1" Input Threshold
vs. Temperature
15
21
3.0
-50
6
0
VDD Supply Current (µA)
9
12
VDD (V)
8
20
VDD Supply Current (µA)
6
Logic "0" Input Current
vs. Temperature
Logic "0" Input Current (µA)
12
0
3
10
Logic "0" Input Threshold
vs. Temperature
Logic “1” Input Threshold vs. VDD
0
VCC Supply Current (µA)
10
20
Logic "1" Input Threshold (V)
14
16
18
VBIAS Supply Voltage (V)
Logic "0" Input Threshold (V)
Logic “1” Input Threshold (V)
12
12
0
0
0
8
Logic “0” Input Threshold (V)
30
Turn-Off Fall Time (ns)
Turn-On Rise Time (ns)
35
10
Logic “0” Input Threshold vs. VDD
Turn-Off Fall Time vs. Voltage
Turn-On Rise Time vs. Voltage
35
0.8
0.6
0.4
0.2
0.0
0
5
10
15
VDD Logic Supply Voltage (V)
20
R03
IX2113
INTEGRATED CIRCUITS DIVISION
VCC Supply Current vs. Voltage
400
300
200
100
400
300
200
100
0
10
VCC Undervoltage Lockout+ (V)
300
200
100
0
100
200
300
400
VB Boost Voltage (V)
500
8
7
6
7
6
9
8
7
6
-50
125
-25
0
25
50
75
Temperature (ºC)
100
0.4
0.2
0.0
-25
0
25
50
75
Temperature (ºC)
100
125
125
125
8
7
6
-25
0
25
50
75
Temperature (ºC)
100
125
High Level Output Voltage
vs. Temperature
(IO=0mA)
5
4
3
2
1
0
-50
-25
0
25
50
75
Temperature (ºC)
100
125
100
125
Output Sink Current
vs. Temperature
5
4
3
2
1
0
-50
100
9
-50
Output Sink Current (A)
0.6
25
50
75
Temperature (ºC)
10
Output Source Current
vs. Temperature
0.8
0
11
125
10
Output Source Current (A)
Low Level Output Voltage (V)
100
5
-50
R03
25
50
75
Temperature (ºC)
11
Low Level Output Voltage
vs. Temperature
(IO=20mA)
1.0
0
High Level Output Voltage (V)
8
100
-25
-25
VCC Undervoltage Lockout (-)
vs. Temperature
9
-50
VBS Undervoltage Lockout- (V)
VBS Undervoltage Lockout+ (V)
9
25
50
75
Temperature (ºC)
0
-50
VBS Undervoltage Lockout (-)
vs. Temperature
10
0
10
20
10
600
11
-25
12
14
16
18
VBS Floating Supply Voltage (V)
11
VBS Undervoltage Lockout (+)
vs. Temperature
-50
20
VCC Undervoltage Lockout (+)
vs. Temperature
400
0
30
0
20
Offset Supply Leakage Current
vs. VB Boost Voltage
500
Leakage Current (µA)
12
14
16
18
VCC Fixed Supply Voltage (V)
40
VCC Undervoltage Lockout- (V)
10
50
Leakage Current (µA)
500
VBS Supply Current (µA)
VCC Supply Current (µA)
500
Offset Supply Leakage Current
vs. Temperature
VBS Supply Current vs. Voltage
4
3
2
1
0
-25
0
25
50
75
Temperature (ºC)
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100
125
-50
-25
0
25
50
75
Temperature (ºC)
9
IX2113
INTEGRATED CIRCUITS DIVISION
5
4
3
2
1
0
High Level Output Voltage (V)
5
Output Sink Current (A)
Output Source Current (A)
High Level Output Voltage
vs. Supply Voltage
Output Sink Current vs. Voltage
Output Source Current vs. Voltage
4
3
2
1
0
10
12
14
16
18
VBIAS Supply Voltage (V)
20
10
12
14
16
18
VBIAS Supply Voltage (V)
20
5
4
3
2
1
0
10
12
14
16
18
VBIAS Supply Voltage (V)
20
Low Level Output Voltage (mV)
Low Level Output Voltage
vs. Supply Voltage
200
160
120
80
40
0
10
12
14
16
18
VCC Supply Voltage (V)
20
Figure 1. Typical Connection Diagram
up to 600V
VDD
VDD
HO
VB
HIN
HIN
SD
SD
LIN
LIN
VS
LOAD
VCC
COM
VSS
VSS
LO
VCC
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IX2113
INTEGRATED CIRCUITS DIVISION
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
Device
Moisture Sensitivity Level (MSL) Rating
IX2113B, IX2113G
MSL 1
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
3.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
Device
Maximum Temperature x Time
IX2113B
IX2113G
260°C for 30 seconds
245°C for 30 seconds
3.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable, and the use of a short drying bake may be necessary. Chlorine-based or
Fluorine-based solvents or fluxes should not be used. Cleaning methods that employ ultrasonic energy should not be
used.
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IX2113
INTEGRATED CIRCUITS DIVISION
3.5 Mechanical Dimensions
3.5.1 IX2113B: 16-Pin SOIC Package
Recommended PCB Land Pattern
10.211 ± 0.254
(0.402 ± 0.010)
1.27
(0.050)
PIN 16
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
9.40
(0.370)
2.00
(0.079)
PIN 1
0.406 ± 0.076
(0.016 ± 0.003)
1.270 TYP
(0.050 TYP)
0.60
(0.024)
2.337 ± 0.051
(0.092 ± 0.002)
45º
0.649 ± 0.102
(0.026 ± 0.004)
0.203 ± 0.102
(0.008 ± 0.004)
0.889 ± 0.178
(0.035 ± 0.007)
0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
DIMENSIONS
mm
(inches)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
3.5.2 IX2113BTR: Tape & Reel Packaging for 16-Pin SOIC Package
330.2 DIA.
(13.00 DIA.)
W=16
(0.630)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
B0=10.70
(0.421)
K0=3.20
(0.126)
A0=10.90
(0.429)
P=12.00
(0.472)
K1=2.70
(0.106)
Embossed Carrier
Embossment
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NOTES:
1. All dimensions carry tolerances of EIA Standard 481-2
2. The tape complies with all “Notes” for constant dimensions
listed on page 5 of EIA-481-2
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Dimensions
mm
(inches)
R03
IX2113
INTEGRATED CIRCUITS DIVISION
3.5.3 IX2113G: 14-Pin DIP Through-Hole Package
18.542 / 19.050
(0.730 / 0.750)
See Note 2
PCB Hole Pattern
0º / 15º
7.62 BSC
(0.300 BSC)
Pin 1
2.542
(0.100)
8.509 / 9.525
(0.335 / 0.375)
See Note 3
7.62
(0.300)
1.35
(0.053)
2.54
(0.100)
1.524 typ
(0.06 typ)
Hole Size =
6.223 / 6.477
(0.245 / 0.255)
See Note 2
3.175 / 3.429
(0.125 / 0.135)
5.334 max
(0.210 max)
H
Seating Plane
2.921 / 3.810
(0.115 / 0.150)
0.381 min
(0.015 min)
0.457 typ
(0.018 typ)
NOTES:
1. JEDEC outline: MS-001 AA.
2. This dimension does not include mold flash or
protrusions. Mold flash or protrusions shall not
exceed 0.254 (0.010).
3. Measured at the lead tips with the leads
unconstrained.
4. Pointed or rounded lead tips are preferred to
ease insertion.
5. Distance between leads including dam bar
protrusions to be 0.127 (0.005).
6. Datum plane H coincident with the bottom of
lead where lead exits body.
0.85
(0.0335)
DIMENSIONS
(min / max)
mm
(inches)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-IX2113-R03
©Copyright 2014, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
6/9/2014
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