Product Folder Order Now Support & Community Tools & Software Technical Documents LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 LDC2112, LDC2114 Inductive Touch Solution for Low-Power HMI Button Applications 1 Features 3 Description • Inductive sensing technology enables touch button design for human machine interface (HMI) on a wide variety of materials such as metal, glass, plastic, and wood, by measuring small deflections of conductive targets. The sensor for an inductive touch system is a coil that can be implemented on a small PCB located behind the panel and protected from the environment. Inductive sensing solution is insensitive to humidity or non-conductive contaminants such as oil and dirt. It is able to automatically correct for any deformation in the conductive targets. 1 • • • • • • • • • Low Power Consumption: – One Button: 6 µA at 0.625 SPS – Two Buttons: 72 µA at 20 SPS Configurable Button Scan Rates: – 0.625 SPS to 80 SPS Force Level Measurement of Touch Buttons Independent Channel Operation: – Two Channels for LDC2112 – Four Channels for LDC2114 Integrated Algorithms to Enable: – Adjustable Force Threshold per Button – Environmental Shift Compensation – Simultaneous Button Press Detection Supports Independent Operation without MCU Robust EMI Performance: – Allows for CISPR 22 and CISPR 24 Compliance Operating Voltage Range: 1.8 V ± 5% Temperature Range: –40 °C to +85 °C Interface: – I2C – Dedicated Logic Output per Channel 2 Applications Touch Buttons and Force Level Measurements on Different Materials, Including Metal, Plastic, and Glass for: • • Consumer Electronics: – Smartphones – Smart Watches and Other Wearable Devices – Smart Speakers – Tablets/PCs – Virtual Reality Headsets – Sound Bars Industrial Applications: – Televisions – Handheld Devices – Home Appliances – HMI Panels and Keypads The LDC2112/LDC2114 is a multi-channel low-noise inductance to digital converter with integrated algorithms to implement inductive touch applications. The device employs an innovative LC resonator that offers high rejection of noise and interference. The LDC2112/LDC2114 can reliably detect material deflections of less than 200 nm. The LDC2112/LDC2114 includes an ultra-low power mode intended for power on/off buttons in battery powered applications. The LDC2112/LDC2114 is available in a 16-pin DSBGA or TSSOP package. The 0.4 mm pitch DSBGA package has a very small 1.6 × 1.6 mm nominal body size with a maximum height of 0.4 mm. The 0.65 mm pitch TSSOP package has a 5.0 × 4.4 mm nominal body size with a maximum height of 1.2 mm. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LDC2112/LDC2114 DSBGA (16) 1.6 mm × 1.6 mm LDC2112/LDC2114 TSSOP (16) 5.0 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VDD LDC2114 OUT0 Digital Algorithm IN0 OUT1 OUT2 OUT3 IN1 IN2 Resonant Circuit Driver Inductive Sensing Core INTB Logic LPWRB IN3 COM I2C SCL SDA GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 5 5 5 5 6 7 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Digital Interface ......................................................... I2C Interface .............................................................. Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 11 15 7.5 Register Maps ......................................................... 15 8 Application and Implementation ........................ 28 8.1 Application Information............................................ 28 8.2 Typical Application .................................................. 38 9 Power Supply Recommendations...................... 40 10 Layout................................................................... 40 10.1 Layout Guidelines ................................................. 40 10.2 Layout Example .................................................... 40 10.3 DSBGA Light Sensitivity ...................................... 41 11 Device and Documentation Support ................. 42 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Documentation Support ....................................... Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Export Control Notice ........................................... Glossary ................................................................ 42 42 42 42 42 42 42 43 12 Mechanical, Packaging, and Orderable Information ........................................................... 43 4 Revision History Changes from Revision A (January 2017) to Revision B Page • Changed unit of Data set-up time from µs to ns (typo) ......................................................................................................... 7 • Changed Multi-Channel and Single-Channel Operation ...................................................................................................... 11 • Added LDC2112 to Register EN – Address 0x0C Table...................................................................................................... 19 Changes from Original (December 2016) to Revision A • 2 Page Changed Advance Information to Production Data Release.................................................................................................. 1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 5 Pin Configuration and Functions LDC2112 16-Pin DSBGA Top View (Bumps Down) 1 A B C 2 NC NC 3 IN0 IN1 INTB ADDR LPW VDD LDC2112 16-Pin TSSOP Top View SDA 4 GND NC GND COM SCL 1 16 SCL GND 2 15 OUT0 LPWRB 3 14 SDA VDD 4 13 OUT1 LDC2112 OUT1 RB D COM INTB 5 12 NC NC 6 11 ADDR NC 7 10 GND IN1 8 9 IN0 OUT0 Pin Functions - LDC2112 PIN NAME DSBGA NO. TSSOP NO. C1 4 D1 2 A4 10 INTB B2 LPWRB VDD I/O (1) DESCRIPTION P Power supply G Ground (2) 5 O Interrupt output Polarity can be configured in Register 0x11. C2 3 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 1 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 9 A Channel 0 LC sensor input IN1 A2 8 A Channel 1 LC sensor input OUT0 D4 15 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 13 O Channel 1 logic output Polarity can be configured in Register 0x1C. ADDR B3 11 I I2C address When ADDR = Ground, I2C address = 0x2A. When ADDR = VDD, I2C address = 0x2B. SCL D3 16 I I2C clock SDA C3 14 I/O I2C data A1 7 B1 6 — No connect Leave them floating. B4 12 GND NC (1) (2) I = Input, O = Output, P=Power, G=Ground, A=Analog Both pins should be connected to the system ground on the PCB. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 3 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com LDC2114 16-Pin DSBGA Top View (Bumps Down) A B 1 2 3 4 IN2 IN1 IN0 GND IN3 OUT3 INTB LDC2114 16-Pin TSSOP Top View OUT2 COM 1 16 SCL GND 2 15 OUT0 LPWRB 3 14 SDA VDD 4 13 OUT1 LDC2114 C VDD LPW SDA OUT1 RB D GND COM SCL OUT0 INTB 5 12 OUT2 IN3 6 11 OUT3 IN2 7 10 GND IN1 8 9 IN0 Pin Functions - LDC2114 PIN NAME DSBGA NO. TSSOP NO. C1 4 D1 2 A4 10 INTB B2 LPWRB VDD I/O (1) DESCRIPTION P Power supply G Ground (2) 5 O Interrupt output Polarity can be configured in Register 0x11. C2 3 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 1 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 9 A Channel 0 LC sensor input IN1 A2 8 A Channel 1 LC sensor input IN2 A1 7 A Channel 2 LC sensor input IN3 B1 6 A Channel 3 LC sensor input OUT0 D4 15 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 13 O Channel 1 logic output Polarity can be configured in Register 0x1C. OUT2 B4 12 O Channel 2 logic output Polarity can be configured in Register 0x1C. OUT3 B3 11 O Channel 3 logic output Polarity can be configured in Register 0x1C. SCL D3 16 I I2C clock SDA C3 14 I/O GND (1) (2) 4 I2C data I2C address = 0x2A. I = Input, O = Output, P=Power, G=Ground, A=Analog Both pins should be connected to the system ground on the PCB. Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 6 Specifications 6.1 Absolute Maximum Ratings Over operating temperature range unless otherwise noted. (1) MIN VDD MAX UNIT 2.2 V V Supply voltage Voltage on SCL, SDA –0.3 3.6 Voltage on any other pin –0.3 2.2 (2) V TJ Junction temperature –40 85 ℃ TSTG Storage temperature –65 125 °C VI (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum voltage across any two pins (not including SCL or SDA) is VDD + 0.3 V. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) ±250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating temperature range unless otherwise noted. MIN NOM MAX UNIT VDD Supply voltage 1.71 1.89 V TJ Junction temperature –40 85 °C 6.4 Thermal Information LDC2112/LDC2114 THERMAL METRIC (1) DSBGA TSSOP UNIT 16 PINS 16 PINS RθJA Junction-to-ambient thermal resistance 81.8 105.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.4 40.3 °C/W RθJB Junction-to-board thermal resistance 18.2 50.2 °C/W ΨJT Junction-to-top characterization parameter 0.3 3.6 °C/W ΨJB Junction-to-board characterization parameter 18 49.6 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 5 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 6.5 Electrical Characteristics Over operating temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.71 1.8 1.89 V POWER VDD Supply voltage IDDNP Normal power mode supply current (4 channels) (1) (2) (3) 4 channels, 40 SPS per channel, 1 ms sampling window per channel, LPWRB = VDD IDDNP Normal power mode supply current (2 channels) (1) (2) 2 channels, 40 SPS per channel, 1 ms sampling window per channel, LPWRB = VDD 0.26 mA IDDLP Low power mode supply current (1) (2) 1 channel, 1.25 SPS per channel, 1 ms sampling window per channel, LPWRB = Ground 9 µA IDDSB Standby supply current No button active (EN = 0x00) 5 0.49 mA 7 µA SENSOR ISENSOR, MAX Registers SENSORn_CONFIG: RPn = 0 Sensor maximum current drive (4) 2.5 mA RP, MIN Sensor minimum parallel resonant impedance 350 Ω RP, MAX Sensor maximum parallel resonant impedance 10 kΩ fSENSOR Sensor resonant frequency QSENSOR, MIN Sensor minimum quality factor QSENSOR, MAX Sensor maximum quality factor VSENSOR, PP CIN 1 30 MHz 5 30 Sensor oscillation peak-to-peak voltage Measured on the INn reference to COM. (4) pins with Sensor input pin capacitance 0.9 V 17 pF CONVERTER SRNP, MIN Minimum normal power mode scan rate (5) LPWRB = VDD 7 10 13 SPS SRNP, MAX Maximum normal power mode scan rate (5) LPWRB = VDD 56 80 104 SPS SRLP, MIN Minimum low power mode scan rate (5) LPWRB = Ground 0.438 0.625 0.813 SPS SRLP, MAX Maximum low power mode scan rate (5) LPWRB = Ground 3.5 5 6.5 SPS Resolution Data code width (1) (2) (3) (4) (5) 6 12 Bits Sensor configuration: LSENSOR = 0.85 µH, CSENSOR = 58 pF, QSENSOR = 11, RP = 0.7 kΩ. I2C communication and pull-up resistors current is not included. Four-channel supply current is applicable to LDC2114 only. The italic n is the channel index, i.e., n = 0 or 1 for LDC2112; n = 0, 1, 2, or 3 for LDC2114. For typical distribution of the scan rates, refer to Figure 9. Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 6.6 Digital Interface Over operating temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C. Pins: LPWRB, INTB, OUT0, OUT1, OUT2, OUT3, and ADDR. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE LEVELS VIH Input high voltage VIL Input low voltage 0.8 × VDD VOH Output high voltage ISOURCE = 400 µA VOL Output low voltage ISINK = 400 µA IL Digital input leakage current V 0.2 × VDD 0.8 × VDD V V 0.2 × VDD V 500 nA MAX UNIT –500 6.7 I2C Interface MIN TYP VOLTAGE LEVELS VIH Input high voltage VIL Input low voltage VOL Output low voltage HYS Hysteresis (1) 0.7 × VDD V 3 mA sink current 0.3 × VDD V 0.2 × VDD V 0.05 × VDD V I2C TIMING CHARACTERISTICS fSCL Clock frequency tLOW Clock low time 1.3 µs tHIGH Clock high time 0.6 µs tHD;STA Hold time repeated START condition 0.6 µs tSU;STA Set-up time for a repeated START condition 0.6 µs tHD;DAT Data hold time 0 µs tSU;DAT Data set-up time 100 ns tSU;STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs tSP Pulse width of spikes that must be suppressed by the input filter (1) 50 ns (1) 400 After this period, the first clock pulse is generated. kHz This parameter is specified by design and/or characterization and is not tested in production. SDA tLOW tf tHD;STA tf tr tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT START tSU;STO tSU;DAT REPEATED START STOP START Figure 1. I2C Timing Diagram Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 7 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 6.8 Typical Characteristics Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C. One channel enabled with a button sampling window of 1 ms unless specified otherwise. 1600 800 10 SPS 20 SPS 40 SPS 80 SPS 1200 1000 800 600 400 600 500 400 300 200 200 100 0 0 0 1 2 3 4 5 6 Sensor RP (k:) 7 8 9 10 0 3 4 5 6 Sensor RP (k:) 7 8 9 10 D011 160 0.625 SPS 1.25 SPS 2.5 SPS 5 SPS 25 150 Average Supply Current (PA) Average Supply Current (PA) 2 Figure 3. Supply Current vs Sensor RP for Normal Power Mode. Sensor Frequency = 3.6 MHz. Two Channels Enabled. 30 20 15 10 5 VDD = 1.71 V VDD = 1.8 V VDD = 1.89 V 140 130 120 110 100 90 80 -40 0 0 1 2 3 4 5 6 Sensor RP (k:) 7 8 9 10 0 20 40 Temperature (qC) 60 80 100 D003 Figure 5. Supply Current vs Temperature. Sensor RP = 650 Ω, Scan Rate = 40 SPS. 160 9 150 8 Standby Current (PA) 140 130 120 110 100 VDD = 1.71 V VDD = 1.8 V VDD = 1.89 V 7 6 5 4 90 80 1.7 -20 D002 Figure 4. Supply Current vs Sensor RP for Low Power Mode. Sensor Frequency = 3.6 MHz. Average Supply Current (PA) 1 D001 Figure 2. Supply Current vs Sensor RP for Normal Power Mode. Sensor Frequency = 3.6 MHz. Four Channels Enabled. -40qC -25qC 1.75 1.8 VDD (V) 0qC 25qC 1.85 85qC 1.9 Submit Documentation Feedback 3 -40 -20 0 D004 Figure 6. Supply Current vs VDD. Sensor RP = 650 Ω, Scan Rate = 40 SPS. 8 10 SPS 20 SPS 40 SPS 80 SPS 700 Average Supply Current (PA) Average Supply Current (PA) 1400 20 40 Temperature (qC) 60 80 100 D005 Figure 7. Standby Current vs Temperature Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Typical Characteristics (continued) One channel enabled with a button sampling window of 1 ms unless specified otherwise. 450 9 400 8 7 Occurrences Standby Current (PA) 350 6 5 300 250 200 150 100 4 -40qC -25qC 3 1.7 0qC 25qC 85°C 50 0 1.75 1.8 VDD (V) 1.85 1.9 D006 Figure 8. Standby Current vs VDD -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Percentage Offset ( ) 1 2 3 4 D007 Figure 9. Scan Rate Distribution at 30 °C Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 9 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 7 Detailed Description 7.1 Overview The LDC2112/LDC2114 is a multi-channel, low-noise, high-resolution inductance to digital converter (LDC) optimized for inductive touch applications. Button presses form micro-deflections in the conductive targets which cause frequency shifts in the resonant sensors. The LDC2112/LDC2114 can measure such frequency shifts and determine when button presses have occurred. With adjustable sensitivity per input channel, the LDC2112/LDC2114 can reliably operate with a wide range of physical button structures and materials. The high resolution measurement enables the implementation of force level buttons. The LDC2112/LDC2114 incorporates customizable post-processing algorithms for enhanced robustness. The LDC2112/LDC2114 can operate in an ultra-low power mode for optimal battery life, or can be toggled into a higher scan rate for more responsive button press detection for game play or other low latency applications. The LDC2112/LDC2114 is operational from –40 °C to +85 °C with a 1.8 V ± 5% power supply voltage. The LDC2112/LDC2114 is configured through 400 kHz I2C. Button presses can be reported through the I2C interface or with configurable polarity dedicated push-pull outputs. Besides the LC resonant sensors, the only external components necessary for operation are supply bypassing capacitors and a COM pin capacitor to ground. 7.2 Functional Block Diagram VDD LDC2112 Digital Algorithm OUT0 OUT1 IN0 Resonant Circuit Driver Inductive Sensing Core INTB Logic LPWRB IN1 COM ADDR I2C SCL SDA GND Copyright © 2016, Texas Instruments Incorporated Figure 10. Block Diagram of LDC2112 10 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Functional Block Diagram (continued) VDD LDC2114 OUT0 OUT1 Digital Algorithm IN0 OUT2 OUT3 IN1 Resonant Circuit Driver IN2 Inductive Sensing Core INTB Logic LPWRB IN3 SCL I2C COM SDA GND Copyright © 2016, Texas Instruments Incorporated Figure 11. Block Diagram of LDC2114 7.3 Feature Description 7.3.1 Multi-Channel and Single-Channel Operation The LDC2112 provides two independent sensing channels; the LDC2114 provides four independent sensing channels. In the following sections, some parameters, such as DATAn and SENSORn_CONFIG, contain a channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. The LDC2112's two available channels are always enabled in Normal Power Mode. The LDC2112 sequentially samples both channels at the configured scan rate. Either channel can be independently enabled in Low Power Mode by setting the LPENn (n = 0 or 1) bit fields in Register EN (Address 0x0C). Any of the LDC2114’s four available channels can be independently enabled by setting the ENn and LPENn (n = 0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect if the corresponding ENn bit is also set. If only one channel is set active, the LDC2114 periodically samples the single active channel at the configured scan rate. When several channels are set active, the LDC2114 operates in multi-channel mode, and it sequentially samples the active channels at the configured scan rate. Each channel of the LDC2114 can be independently enabled in Low Power Mode and Normal Power Mode. 7.3.2 Button Output Interfaces Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2, or 3), which are push-pull outputs and can be used as interrupts to a micro-controller. The polarities of these pins are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also reported by the push-pull interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address 0x11). Any assertion of INTB is cleared upon reading Register STATUS (Address 0x00). Each push-pull output must be assigned to a dedicated general-purpose input pin on the micro-controller to avoid potential current fights. The second method is by use of the LDC2112/LDC2114’s I2C interface. The Register OUT (Address 0x01) contains the fields OUT0, OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For more advanced button press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), which are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a micro-controller. A valid button push is represented by a positive value. The polarity is configurable in Register OPOL_DPOL (Address 0x1C). The DATAn values can be used to implement multi-level buttons, where the data value is correlated to the amount of force applied to the button. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 11 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Feature Description (continued) 7.3.3 Programmable Button Sensitivity The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a 64-level gain factor for a normalized gain between 1 and 232. Each gain step increases the gain by an average of 9%. The gain required for an application is primarily determined by the mechanical rigidity of each individual button. The individual gain steps are listed in the Gain Table. 7.3.4 Baseline Tracking The LDC2112/LDC2114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the sensor output caused by environmental variations, such as temperature drift. The baseline tracking is configured independently for Normal Power Mode and Low Power Mode. For more information, refer to Tracking Baseline. 7.3.5 Integrated Button Algorithms The LDC2112/LDC2114 features several algorithms that can mitigate false button detections due to mechanical non-idealities. The algorithms look for correlated button responses, for example, similar or opposite responses between two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more information, refer to Mitigating False Button Detections. 7.3.6 I2C Interface The LDC2112/LDC2114 features an I2C Interface that can be used to program the internal registers and read channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x05) registers, the user should always read Register STATUS (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses. For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The sequence of register write is illustrated as follows: • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session • Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1 • I2C write to configure registers • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above process is shown in Figure 12. 25 ms scan cycle 25 ms scan cycle Sampling Sampling CONFIG_MODE < 1 ms (Register RESET) RDY_TO_WRITE (Register STATUS) Program registers only after confirming RDY_TO_WRITE = 1 Figure 12. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an I2C Write Handshake 7.3.6.1 Selectable I2C Address (LDC2112 Only) The LDC2112 provides an I2C address select pin, ADDR. Connecting this pin to ground will set the LDC2112 I2C address to 0x2A. Connecting ADDR to VDD will set the LDC2112 I2C address to 0x2B. The LDC2114 has a fixed I2C address of 0x2A. 12 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Feature Description (continued) 7.3.6.2 I2C Interface Specifications The maximum speed of the I2C interface is 400 kHz. This sequence uses the standard I2C 7-bit slave address followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will autoincrement as long as the master acknowledges. 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 Start by Master D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D0 Stop by Master Ack by Slave Frame 3 Data Byte Figure 13. I2C Sequence of Writing a Single Register 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address (ADDR) from Master 1 9 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 Ack by Slave D1 D0 Ack by Slave Frame 3 Data Byte to Register ADDR Frame 4 Data Byte to Register ADDR+1 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Stop by Master Frame N+3 Data Byte to Register ADDR+N Figure 14. I2C Sequence of Writing Consecutive Registers Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 13 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Feature Description (continued) 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Start by Master Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address from Master 1 1 9 9 SCL (continued) SDA (continued) A6 A5 A4 A3 A2 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 No Ack by Master Ack by Slave Repeat Start by Master Frame 3 Serial Bus Address Byte from Master Stop by Master Frame 4 Data Byte from Slave Figure 15. I2C Sequence of Reading a Single Register 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address (ADDR) from Master 1 9 1 9 SCL (continued) SDA (continued) A6 A5 A4 A3 A2 A1 A0 D7 R/W Repeat Start by Master D6 D5 D4 D3 D2 D1 D0 Ack by Master Ack by Slave Frame 3 Serial Bus Address Byte from Master Frame 4 Data Byte from Slave Register ADDR 1 9 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 D1 No Ack by Master Ack by Master Frame 5 Data Byte from Slave Register ADDR+1 D0 Stop by Master Frame N+4 Data Byte from Slave Register ADDR+N Figure 16. I2C Sequence of Reading Consecutive Registers 14 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Feature Description (continued) 7.3.6.3 I2C Bus Control The LDC2112/LDC2114 cannot drive the I2C clock (SCL), i.e. it does not support clock stretching. In the unlikely event where the SCL is stuck LOW, power cycle any device that is holding the SCL to activate its internal PowerOn Reset (POR) circuit. If the LDC is connected to the same power supply as that device, there will be about 66 ms set-up time before the LDC becomes active again. For more information, refer to Defining Power-On Timing. If the data line (SDA) is stuck LOW, the I2C master should send nine clock pulses. The device that is holding the bus LOW should release it sometime within those nine clocks. If not, then power cycle to clear the bus. The LDC2112/LDC2114 has built-in monitors to check that the device is currently working. In the unlikely event of a device fault, the device state will be reset internally, and all the registers will be reset with default settings. For system robustness, it is recommended to check the value of a modified register periodically to monitor the device status and reload the register settings if needed. 7.4 Device Functional Modes The LDC2112/LDC2114 supports two power modes of operation, a Normal Power Mode for active sampling at 10, 20, 40, or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS. Refer to Configuring Button Scan Rate for details. 7.4.1 Normal Power Mode When the LPWRB input pin is set to VDD, all enabled channels operate in Normal Power Mode. Each channel can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal Power Mode Scan Rate, refer to Electrical Characteristics. 7.4.2 Low Power Mode When the LPWRB input pin is set to Ground, only the low-power-enabled channels are active. Each channel can be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel to operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive power-saving state for the majority of the time. Lower scan rates correspond to lower current consumption. In addition, the individual button sampling window should be set to the lowest effective setting (this is system dependent, but typically 0.8 to 1 ms). For the electrical specification of the configurable Low Power Mode Scan Rate, refer to Electrical Characteristics. If a channel is operational in both Low Power Mode and Normal Power Mode, it is recommended to toggle the LPWRB pin only after the button associated with that channel is released. 7.4.3 Configuration Mode Before configuring any register settings, the device must be put into the configuration mode first. Setting CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device in configuration mode. Any device configuration changes can then be made. The current consumption in this mode is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation. Refer to I2C Interface for more information. 7.5 Register Maps Registers indicated with Reserved must be written only with indicated values. Improper device operation may occur otherwise. Table 1. Register List ADDRESS NAME DEFAULT VALUE 0x00 STATUS 0x00 DESCRIPTION Device status 0x01 OUT 0x00 Channel output logic states 0x02 DATA0_LSB 0x00 The lower 8 bits of the Button 0 data (Two’s complement) 0x03 DATA0_MSB 0x00 The upper 4 bits of the Button 0 data (Two’s complement) 0x04 DATA1_LSB 0x00 The lower 8 bits of the Button 1 data (Two’s complement) Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 15 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Register Maps (continued) Table 1. Register List (continued) 16 ADDRESS NAME DEFAULT VALUE DESCRIPTION 0x05 DATA1_MSB 0x00 The upper 4 bits of the Button 1 data (Two’s complement) 0x06 DATA2_LSB 0x00 The lower 8 bits of the Button 2 data (Two’s complement) 0x07 DATA2_MSB 0x00 The upper 4 bits of the Button 2 data (Two’s complement) 0x08 DATA3_LSB 0x00 The lower 8 bits of the Button 3 data (Two’s complement) 0x09 DATA3_MSB 0x00 The upper 4 bits of the Button 3 data (Two’s complement) 0x0A RESET 0x00 Reset device and register configurations 0x0B RESERVED 0x00 Reserved. Set to 0x00 0x0C EN 0x10 (LDC2112) 0x1F (LDC2114) Enable channels and low power modes 0x0D NP_SCAN_RATE 0x01 Normal Power Mode scan rate 0x0E GAIN0 0x28 Gain for Channel 0 sensitivity adjustment 0x0F LP_SCAN_RATE 0x02 Low Power Mode scan rate 0x10 GAIN1 0x28 Gain for Channel 1 sensitivity adjustment 0x11 INTPOL 0x01 Interrupt polarity 0x12 GAIN2 0x28 Gain for Channel 2 sensitivity adjustment 0x13 LP_BASE_INC 0x05 Low power base increment 0x14 GAIN3 0x28 Gain for Channel 3 sensitivity adjustment 0x15 NP_BASE_INC 0x03 Normal power base increment 0x16 BTPAUSE_MAXWIN 0x00 Baseline tracking pause and Max-win 0x17 LC_DIVIDER 0x03 LC oscillation frequency divider 0x18 HYST 0x08 Hysteresis for threshold 0x19 TWIST 0x00 Anti-twist 0x1A COMMON_DEFORM 0x00 Anti-common and anti-deformation 0x1B RESERVED 0x00 Reserved. Set to 0x00 0x1C OPOL_DPOL 0x0F Output polarity 0x1D RESERVED 0x00 Reserved. Set to 0x00 0x1E CNTSC 0x55 Counter scale 0x1F RESERVED 0x00 Reserved. Set to 0x00 0x20 SENSOR0_CONFIG 0x04 Sensor 0 cycle count, frequency, RP range 0x21 RESERVED 0x00 Reserved. Set to 0x00 0x22 SENSOR1_CONFIG 0x04 Sensor 1 cycle count, frequency, RP range 0x23 RESERVED 0x00 Reserved. Set to 0x00 0x24 SENSOR2_CONFIG 0x04 Sensor 2 cycle count, frequency, RP range 0x25 FTF0 0x02 Sensor 0 fast tracking factor 0x26 SENSOR3_CONFIG 0x04 Sensor 3 cycle count, frequency, RP range 0x27 RESERVED 0x00 Reserved. Set to 0x00 0x28 FTF1_2 0x50 Sensors 1 and 2 fast tracking factors 0x29 RESERVED 0x00 Reserved. Set to 0x00 0x2A RESERVED 0x00 Reserved. Set to 0x00 0x2B FTF3 0x01 Sensor 3 fast tracking factor 0xFC MANUFACTURER_ID_LSB 0x49 Manufacturer ID lower byte 0xFD MANUFACTURER_ID_MSB 0x54 Manufacturer ID upper byte 0xFE DEVICE_ID_LSB 0x01 (LDC2112) 0x00 (LDC2114) Device ID lower byte 0xFF DEVICE_ID_MSB 0x20 Device ID upper byte Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 7.5.1 Individual Register Listings Fields indicated with ‘Reserved’ must be written only with indicated values. Improper device operation may occur otherwise. The R/W column indicates the Read-Write status of the corresponding field. An ‘R/W’ entry indicates read and write capability, an ‘R’ indicates read-only, and a ‘W’ indicates write-only. Before reading the OUT (Address 0x01) or channel DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), the user should always read the STATUS register (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses. Table 2. Register STATUS – Address 0x00 BIT FIELD TYPE RESET DESCRIPTION 7 OUT_STATUS R 0 Output Status Logic OR of output bits from Register OUT (Address 0x01). This field is cleared by reading this register. 6 CHIP_READY R 1 Chip Ready Status b0: Chip not ready after internal reset. b1: Chip ready after internal reset. 5 RDY_TO_WRITE R 0 Ready to Write Indicates if registers are ready to be written. See I2C Interface for more information. b0: Registers not ready. b1: Registers ready. 4 MAXOUT R 0 Maximum Output Code Indicates if any channel output data reaches the maximum value (+0x7FF or –0x800). Cleared by a read of the status register. b0: No maximum output code. b1: Maximum output code. 3 FSM_WD R 0 Finite-State Machine Watchdog Error Reports an error has occurred and conversions have been halted. Cleared by a read of the status register. b0: No error in finite-state machine. b1: Error in finite-state machine. 2 LC_WD R 0 LC Sensor Watchdog Error Reports an error when any LC oscillator fails to start. Cleared by a read of the status register. b0: No error in LC oscillator initialization. b1: Error in LC oscillator initialization. 1 TIMEOUT R 0 Button Timeout Reports when any button is asserted for more than 50 seconds. Cleared by a read of the status register. b0: no timeout error. b1: timeout error. 0 REGISTER_FLAG R 0 Register Integrity Flag Reports if any register's value has an unexpected change. Cleared by a read of the status register. b0: No unexpected register change. b1: Unexpected register change. Table 3. Register OUT – Address 0x01 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3 OUT3 R 0 Output Logic State for Channel 3 (LDC2114 Only) b0: No button press detected on Channel 3. b1: Button press detected on Channel 3. 2 OUT2 R 0 Output Logic State for Channel 2 (LDC2114 Only) b0: No button press detected on Channel 2. b1: Button press detected on Channel 2. 1 OUT1 R 0 Output Logic State for Channel 1 b0: No button press detected on Channel 1. b1: Button press detected on Channel 1. 0 OUT0 R 0 Output Logic State for Channel 0 b0: No button press detected on Channel 0. b1: Button press detected on Channel 0. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 17 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table 4. Register DATA0_LSB – Address 0x02 BIT FIELD TYPE RESET 7:0 DATA0[7:0] R 0000 0000 The lower 8 bits of Channel 0 data (Two’s complement). DESCRIPTION Table 5. Register DATA0_MSB – Address 0x03 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. 3:0 DATA0[11:8] R 0000 The upper 4 bits of Channel 0 data (Two’s complement). BIT FIELD 7:0 DATA1[7:0] Table 6. Register DATA1_LSB – Address 0x04 TYPE RESET DESCRIPTION R 0000 0000 The lower 8 bits of Channel 1 data (Two’s complement). Table 7. Register DATA1_MSB – Address 0x05 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. 3:0 DATA1[11:8] R 0000 The upper 4 bits of Channel 1 data (Two’s complement). Table 8. Register DATA2_LSB – Address 0x06 BIT FIELD TYPE RESET 7:0 DATA2[7:0] R 0000 0000 The lower 8 bits of Channel 2 data (Two’s complement). (LDC2114 Only) DESCRIPTION Table 9. Register DATA2_MSB – Address 0x07 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. 3:0 DATA2[11:8] R 0000 The upper 4 bits of Channel 2 data (Two’s complement). (LDC2114 Only) Table 10. Register DATA3_LSB – Address 0x08 BIT FIELD TYPE RESET 7:0 DATA3[7:0] R 0000 0000 The lower 8 bits of Channel 3 data (Two’s complement). (LDC2114 Only) DESCRIPTION Table 11. Register DATA3_MSB – Address 0x09 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. 3:0 DATA3[11:8] R 0000 The upper 4 bits of Channel 3 data (Two’s complement). (LDC2114 Only) Table 12. Register RESET – Address 0x0A BIT FIELD TYPE RESET DESCRIPTION 7:5 RESERVED R/W 000 Reserved. Set to b000. FULL_RESET R/W 0 Device Reset b0: Normal operation. b1: Resets the device and register configurations. All registers will be returned to default values. Normal operation will not resume until STATUS:CHIP_READY = 1. RESERVED R/W 000 Reserved. Set to b000. CONFIG_MODE R/W 0 Configuration Mode b0: Normal operation. b1: Holds the device in configuration mode (no data conversion), but maintains current register configurations. Any device configuration changes should be made with this bit set to 1. After all configuration changes have been written, set this bit to 0 for normal operation. 4 3:1 0 18 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Table 13. Register EN – Address 0x0C BIT FIELD TYPE RESET DESCRIPTION 7 LPEN3 R/W 0 Channel 3 Low-Power-Enable (LDC2114 Only) b0: Disable Channel 3 in Low Power Mode. b1: Enable Channel 3 in Low Power Mode. EN3 must also be set to 1. 6 LPEN2 R/W 0 Channel 2 Low-Power-Enable (LDC2114 Only) b0: Disable Channel 2 in Low Power Mode. b1: Enable Channel 2 in Low Power Mode. EN2 must also be set to 1. 5 LPEN1 R/W 0 Channel 1 Low-Power-Enable b0: Disable Channel 1 in Low Power Mode. b1: Enable Channel 1 in Low Power Mode. EN1 must also be set to 1. 4 LPEN0 R/W 1 Channel 0 Low-Power-Enable b0: Disable Channel 0 in Low Power Mode. b1: Enable Channel 0 in Low Power Mode. EN0 must also be set to 1. 3 EN3 (LDC2114) R/W 1 Channel 3 Enable (LDC2114 Only) b0: Disable Channel 3. b1: Enable Channel 3. RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only) EN2 (LDC2114) R/W 1 Channel 2 Enable (LDC2114 Only) b0: Disable Channel 2. b1: Enable Channel 2. RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only) EN1 (LDC2114) R/W 1 Channel 1 Enable (LDC2114 Only) b0: Disable Channel 1. b1: Enable Channel 1. RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only) For LDC2112, Channel 1 is always enabled. EN0 (LDC2114) R/W 1 Channel 0 Enable (LDC2114 Only) b0: Disable Channel 0. b1: Enable Channel 0. RESERVED (LDC2112) R 0 Reserved. Set to b0. (LDC2112 Only) For LDC2112, Channel 0 is always enabled. 2 1 0 Table 14. Register NP_SCAN_RATE – Address 0x0D BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000. 1:0 NPSR R/W 01 Normal Power Mode Scan Rate Refer to Configuring Button Scan Rate for more information. b00: 80 SPS b01: 40 SPS (Default) b10: 20 SPS b11: 10 SPS BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R/W 00 Reserved. Set to b00. 5:0 GAIN0 R/W b10 1000 Gain for Channel 0 Refer to the Gain Table for detailed configuration. Table 15. Register GAIN0 – Address 0x0E Table 16. Register LP_SCAN_RATE – Address 0x0F BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000. 1:0 LPSR R/W 10 Low Power Mode Scan Rate Refer to Configuring Button Scan Rate for more information. b00: 5 SPS b01: 2.5 SPS b10: 1.25 SPS (Default) b11: 0.625 SPS Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 19 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table 17. Register GAIN1 – Address 0x10 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R/W 00 Reserved. Set to b00. 5:0 GAIN1 R/W b10 1000 Gain for Channel 1 Refer to the Gain Table for detailed configuration. Table 18. Register INTPOL – Address 0x11 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. INTPOL R/W 0 Interrupt Polarity b0: Set INTB pin polarity to active low. b1: Set INTB pin polarity to active high. RESERVED R/W 01 Reserved. Set to b01. 2 1:0 Table 19. Register GAIN2 – Address 0x12 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R/W 00 Reserved. Set to b00. 5:0 GAIN2 R/W b10 1000 Gain for Channel 2 (LDC2114 Only) Refer to the Gain Table for detailed configuration. Table 20. Register LP_BASE_INC – Address 0x13 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. 2:0 LPBI R/W b101 Baseline Tracking Increment in Low Power Mode Refer to Tracking Baseline for more information. Valid values: [b000:b111]. b101: LPBI = 5 (Default) Table 21. Register GAIN3 – Address 0x14 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R/W 00 Reserved. Set to b00. 5:0 GAIN3 R/W b10 1000 Gain for Channel 3 (LDC2114 Only) Refer to the Gain Table for detailed configuration. Table 22. Register NP_BASE_INC – Address 0x15 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. 2:0 NPBI R/W b011 Baseline Tracking Increment in Normal Power Mode Refer to Tracking Baseline for more information. Valid values: [b000:b111]. b011: NPBI = 3 (Default) Table 23. Register BTPAUSE_MAXWIN – Address 0x16 BIT 20 FIELD TYPE RESET DESCRIPTION 7 BTPAUSE3 R/W 0 Baseline Tracking Pause for Channel 3 (LDC2114 Only) Pauses baseline tracking for Channel 3 when OUT3 is asserted. Refer to Tracking Baseline for more information. b0: Normal baseline tracking for Channel 3 regardless of OUT3 status. (Default) b1: Pauses baseline tracking for Channel 3 when OUT3 is asserted. 6 BTPAUSE2 R/W 0 Baseline Tracking Pause for Channel 2 (LDC2114 Only) Pauses baseline tracking for Channel 2 when OUT2 is asserted. Refer to Tracking Baseline for more information. b0: Normal baseline tracking for Channel 2 regardless of OUT2 status. (Default) b1: Pauses baseline tracking for Channel 2 when OUT2 is asserted. Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Table 23. Register BTPAUSE_MAXWIN – Address 0x16 (continued) BIT FIELD TYPE RESET DESCRIPTION 5 BTPAUSE1 R/W 0 Baseline Tracking Pause for Channel 1 Pauses baseline tracking for Channel 1 when OUT1 is asserted. Refer to Tracking Baseline for more information. b0: Normal baseline tracking for Channel 1 regardless of OUT1 status. (Default) b1: Pauses baseline tracking for Channel 1 when OUT1 is asserted. 4 BTPAUSE0 R/W 0 Baseline Tracking Pause for Channel 0 Pauses baseline tracking for Channel 0 when OUT0 is asserted. Refer to Tracking Baseline for more information. b0: Normal baseline tracking for Channel 0 regardless of OUT0 status. (Default) b1: Pauses baseline tracking for Channel 0 when OUT0 is asserted. 3 MAXWIN3 R/W 0 Max-Win Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Exclude Channel 3 from the max-win group. (Default) b1: Include Channel 3 in the max-win group. 2 MAXWIN2 R/W 0 Max-Win Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Exclude Channel 2 from the max-win group. (Default) b1: Include Channel 2 in the max-win group. 1 MAXWIN1 R/W 0 Max-Win Algorithm Setting for Channel 1 Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Exclude Channel 1 from the max-win group. (Default) b1: Include Channel 1 in the max-win group. 0 MAXWIN0 R/W 0 Max-Win Algorithm Setting for Channel 0 Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Exclude Channel 0 from the max-win group. (Default) b1: Include Channel 0 in the max-win group. Table 24. Register LC_DIVIDER – Address 0x17 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. 2:0 LCDIV R/W b011 LC Oscillation Frequency Divider The frequency divider sets the button sampling window in conjunction with SENCYCn. Valid values: [b000:b111]. Refer to Programming Button Sampling Window for more information. b011: LCDIV = 3 (Default) BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R/W b0000 Reserved. Set to b0000. 3:0 HYST R/W b1000 Hysteresis Defines the hysteresis for button triggering threshold. Valid values: [b0000:b1111]. Hysteresis = HYST × 4 b1000: HYST = 8, Hysteresis = 32 (Default) Refer to Setting Button Triggering Threshold for more information. Table 25. Register HYST – Address 0x18 Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 21 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table 26. Register TWIST – Address 0x19 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. 2:0 ANTITWIST R/W b000 Anti-Twist When set to 0, the anti-twist algorithm is not enabled. When greater than 0, all buttons are enabled for the anti-twist algorithm. The validation of all buttons is void if any button’s DATA is negative by a threshold. Anti-twist Threshold = ANTITWIST × 4. Refer to Overcoming Case Twisting (Anti-Twist) for more information. Table 27. Register COMMON_DEFORM – Address 0x1A BIT FIELD TYPE RESET DESCRIPTION 7 ANTICOM3 R/W 0 Anti-Common Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 3 from the anti-common group. (Default) b1: Include Channel 3 in the anti-common group. 6 ANTICOM2 R/W 0 Anti-Common Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 2 from the anti-common group. (Default) b1: Include Channel 2 in the anti-common group. 5 ANTICOM1 R/W 0 Anti-Common Algorithm Setting for Channel 1 Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 1 from the anti-common group. (Default) b1: Include Channel 1 in the anti-common group. 4 ANTICOM0 R/W 0 Anti-Common Algorithm Setting for Channel 0 Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 0 from the anti-common group. (Default) b1: Include Channel 0 in the anti-common group. 3 ANTIDFORM3 R/W 0 Anti-Deform Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 3 from the anti-deform group. (Default) b1: Include Channel 3 in the anti-deform group. 2 ANTIDFORM2 R/W 0 Anti-Deform Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 2 from the anti-deform group. (Default) b1: Include Channel 2 in the anti-deform group. 1 ANTIDFORM1 R/W 0 Anti-Deform Algorithm Setting for Channel 1 Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 1 from the anti-deform group. (Default) b1: Include Channel 1 in the anti-deform group. 0 ANTIDFORM0 R/W 0 Anti-Deform Algorithm Setting for Channel 0 Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 0 from the anti-deform group. (Default) b1: Include Channel 0 in the anti-deform group. Table 28. Register OPOL_DPOL – Address 0x1C 22 BIT FIELD TYPE RESET DESCRIPTION 7 OPOL3 R/W 0 Output Polarity for OUT3 Pin (LDC2114 Only) b0: Active low (Default) b1: Active high 6 OPOL2 R/W 0 Output Polarity for OUT2 Pin (LDC2114 Only) b0: Active low (Default) b1: Active high Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Table 28. Register OPOL_DPOL – Address 0x1C (continued) BIT FIELD TYPE RESET DESCRIPTION 5 OPOL1 R/W 0 Output Polarity for OUT1 Pin b0: Active low (Default) b1: Active high 4 OPOL0 R/W 0 Output Polarity for OUT0 Pin b0: Active low (Default) b1: Active high 3 DPOL3 R/W 1 Data Polarity for Channel 3 (LDC2114 Only) b0: DATA3 decreases as fSENSOR3 increases. b1: DATA3 increases as fSENSOR3 increases. (Default) 2 DPOL2 R/W 1 Data Polarity for Channel 2 (LDC2114 Only) b0: DATA2 decreases as fSENSOR2 increases. b1: DATA2 increases as fSENSOR2 increases. (Default) 1 DPOL1 R/W 1 Data Polarity for Channel 1 b0: DATA1 decreases as fSENSOR1 increases. b1: DATA1 increases as fSENSOR1 increases. (Default) 0 DPOL0 R/W 1 Data Polarity for Channel 0 b0: DATA0 decreases as fSENSOR0 increases. b1: DATA0 increases as fSENSOR0 increases. (Default) Table 29. Register CNTSC – Address 0x1E (1) (1) BIT FIELD TYPE RESET DESCRIPTION 7:6 CNTSC3 R/W 01 Counter Scale for Channel 3 (LDC2114 Only) Refer to Scaling Frequency Counter Output for more information. b00: CNTSC3 = 0 b01: CNTSC3 = 1 (Default) b10: CNTSC3 = 2 b11: CNTSC3 = 3 5:4 CNTSC2 R/W 01 Counter Scale for Channel 2 (LDC2114 Only) Refer to Scaling Frequency Counter Output for more information. b00: CNTSC2 = 0 b01: CNTSC2 = 1 (Default) b10: CNTSC2 = 2 b11: CNTSC2 = 3 3:2 CNTSC1 R/W 01 Counter Scale for Channel 1 Refer to Scaling Frequency Counter Output for more information. b00: CNTSC1 = 0 b01: CNTSC1 = 1 (Default) b10: CNTSC1 = 2 b11: CNTSC1 = 3 1:0 CNTSC0 R/W 01 Counter Scale for Channel 0 Refer to Scaling Frequency Counter Output for more information. b00: CNTSC0 = 0 b01: CNTSC0 = 1 (Default) b10: CNTSC0 = 2 b11: CNTSC0 = 3 The Counter Scale sets a scaling factor for the internal frequency counter to avoid data overflow. The formula for calculating counter scale is CNTSCn = LCDIV + ceiling(log2 (0.0861×(SENCYCn+1)/fSENSORn)), n = 0, 1, 2, or 3, where LCDIV and SENCYCn are the exponential and linear scalers that set the number of sensor oscillation cycles, fSENSORn is the sensor frequency in MHz. Table 30. Register SENSOR0_CONFIG – Address 0x20 BIT 7 FIELD TYPE RESET DESCRIPTION RP0 R/W 0 Channel 0 Sensor RP Range Select Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350Ω ≤ RP ≤ 4kΩ (Default) b1: 800Ω ≤ RP ≤ 10kΩ Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 23 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table 30. Register SENSOR0_CONFIG – Address 0x20 (continued) BIT FIELD TYPE RESET DESCRIPTION 6:5 FREQ0 R/W 00 Channel 0 Sensor Frequency Range Select Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC0 R/W b0 0100 Channel 0 Sensor Cycle Count SENCYC0 sets the Channel 0 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. Table 31. Register SENSOR1_CONFIG – Address 0x22 BIT FIELD TYPE RESET DESCRIPTION RP1 R/W 0 Channel 1 Sensor RP Range Select Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ 6:5 FREQ1 R/W 00 Channel 1 Sensor Frequency Range Select Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC1 R/W b0 0100 Channel 1 Sensor Cycle Count SENCYC1 sets the Channel 1 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. 7 Table 32. Register SENSOR2_CONFIG – Address 0x24 BIT FIELD TYPE RESET DESCRIPTION RP2 R/W 0 Channel 2 Sensor RP Range Select (LDC2114 Only) Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ 6:5 FREQ2 R/W 00 Channel 2 Sensor Frequency Range Select (LDC2114 Only) Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC2 R/W b0 0100 Channel 2 Sensor Cycle Count (LDC2114 Only) SENCYC2 sets the Channel 2 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. 7 24 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Table 33. Register FTF0 – Address 0x25 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R/W b0 0000 Reserved. Set to b0 0000. 2:1 FTF0 R/W 01 Fast Tracking Factor for Channel 0 Defines baseline tracking speed for negative values of DATA0. Refer to Tracking Baseline for more information. b00: FTF0 = 0 b01: FTF0 = 1 (Default) b10: FTF0 = 2 b11: FTF0 = 3 RESERVED R/W 0 Reserved. Set to b0. 0 Table 34. Register SENSOR3_CONFIG – Address 0x26 BIT FIELD TYPE RESET DESCRIPTION RP3 R/W 0 Channel 3 Sensor RP Range Select (LDC2114 Only) Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ 6:5 FREQ3 R/W 00 Channel 3 Sensor Frequency Range Select (LDC2114 Only) Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC3 R/W b0 0100 Channel 3 Sensor Cycle Count (LDC2114 Only) SENCYC3 sets the Channel 3 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. 7 Table 35. Register FTF1_2 – Address 0x28 BIT FIELD TYPE RESET DESCRIPTION 7:6 FTF2 R/W 01 Fast Tracking Factor for Channel 2 (LDC2114 Only) Defines baseline tracking speed for negative values of DATA2. Refer to Tracking Baseline for more information. b00: FTF2 = 0 b01: FTF2 = 1 (Default) b10: FTF2 = 2 b11: FTF2 = 3 5:4 FTF1 R/W 01 Fast Tracking Factor for Channel 1 Defines baseline tracking speed for negative values of DATA1. Refer to Tracking Baseline for more information. b00: FTF1 = 0 b01: FTF1 = 1 (Default) b10: FTF1 = 2 b11: FTF1 = 3 3:0 RESERVED R/W b0000 Reserved. Set to b0000. Table 36. Register FTF3 – Address 0x2B BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R/W b00 0000 Reserved. Set to b00 0000. 1:0 FTF3 R/W 01 Fast Tracking Factor for Channel 3 (LDC2114 Only) Defines baseline tracking speed for negative values of DATA3. Refer to Tracking Baseline for more information. b00: FTF3 = 0 b01: FTF3 = 1 (Default) b10: FTF3 = 2 b11: FTF3 = 3 Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 25 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Table 37. Register MANUFACTURER_ID_LSB – Address 0xFC BIT FIELD TYPE RESET DESCRIPTION 7:0 MANUFACTURER_ID [7:0] R 0x49 Manufacturer ID [7:0] Table 38. Register MANUFACTURER_ID_MSB – Address 0xFD BIT FIELD 7:0 MANUFACTURER_ID [15:8] R TYPE RESET DESCRIPTION 0x54 Manufacturer ID [15:8] Table 39. Register DEVICE_ID_LSB – Address 0xFE BIT FIELD TYPE RESET DESCRIPTION 7:0 DEVICE_ID [7:0] R 0x01 (LDC2112) Device ID [7:0] 0x00 (LDC2114) Table 40. Register DEVICE_ID_MSB – Address 0xFF 26 BIT FIELD TYPE RESET DESCRIPTION 7:0 DEVICE_ID [15:8] R 0x20 Device ID [15:8] Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3 Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR 0 1.0 32 16 1 1.0625 33 17 2 1.1875 34 19 3 1.3125 35 21 4 1.4375 36 23 5 1.5625 37 25 6 1.6875 38 27 7 1.8125 39 29 8 2.0 40 32 9 2.125 41 34 10 2.375 42 38 11 2.625 43 42 12 2.875 44 46 13 3.125 45 50 14 3.375 46 54 15 3.625 47 58 16 4.0 48 64 17 4.25 49 68 18 4.75 50 76 19 5.25 51 84 20 5.75 52 92 21 6.25 53 100 22 6.75 54 108 23 7.25 55 116 24 8.0 56 128 25 8.5 57 136 26 9.5 58 152 27 10.5 59 168 28 11.5 60 184 29 12.5 61 200 30 13.5 62 216 31 14.5 63 232 Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 27 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LDC2112/LDC2114 supports multiple buttons. Each button can be configured in various ways for optimal operation. 8.1.1 Theory of Operation An AC current flowing through an inductor will generate an AC magnetic field. If a conductive material, such as a metal object, is in close proximity to the inductor, the magnetic field will induce circulating eddy currents on the surface of the conductor. The eddy currents are a function of the distance, size, and composition of the conductor. If the conductor is deflected toward the inductor as shown in Figure 17, more eddy currents will be generated. Figure 17. Metal Deflection The eddy currents create their own magnetic field, which opposes the original field generated by the inductor. This effect reduces the effective inductance of the system, resulting in an increase in sensor frequency. Figure 18 shows the inductance and frequency response of an example sensor with a diameter of 14 mm. As the sensitivity of an inductive sensor increases with closer targets, the conductive plate should be placed quite close to the sensor—typically 10% of the sensor diameter for circular coils. For rectangular or race-track-shaped coils, the target to sensor distance should typically be less than 10% of the shorter side of the coil. 28 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Application Information (continued) 7 5 4.75 6 4.5 5.5 4.25 Sensor Inductance (μH) 4 Sensor Frequency (MHz) 5 4.5 3.75 4 3.5 3.5 Sensor Frequency (MHz) Sensor Inductance (μH) 6.5 3.25 3 0 1 2 3 4 5 6 7 8 Distance between Sensor and Target (mm) 9 3 10 D010 Figure 18. Sensor Inductance and Frequency vs Target Distance. Sensor Diameter = 14 mm The output DATAn registers (Addresses 0x02 through 0x09) of the LDC2112/LDC2114 contain the processed values of the changes in sensor frequencies. 8.1.2 Designing Sensor Parameters Each inductive touch button uses an LC resonator sensor, as illustrated in Figure 19, where L is the inductor, C is the capacitor, and RS is the AC series resistance of the sensor at the frequency of operation. The key parameters of the LC sensor include frequency, effective parallel resistance RP, and quality factor Q. These parameters must be within the ranges as specified in the Sensor section of the Electrical Characteristics table. Note that the effective RP and Q changes when the conductive target is in place. L C RS Figure 19. LC Resonator The LC sensor frequency, as defined by the equation below, must be between 1 MHz and 30 MHz. 1 fSENSOR 2S LC (1) The sensor quality factor, as defined by the equation below, must be between 5 and 30. QSENSOR 1 RS L C (2) The series resistance can be represented as an equivalent parallel resistance, RP, which is given by L RP RS C Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback (3) 29 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com Application Information (continued) L RP C Figure 20. Equivalent Parallel Circuit RP can be viewed as the load on the sensor driver. This load corresponds to the current drive needed to maintain the oscillation amplitude. RP must be between 350 Ω and 10 kΩ. In summary, the LDC2112/LDC2114 requires that the sensor parameters are within the following ranges when the conductive target is present: • 1 MHz ≤ fSENSOR ≤ 30 MHz • 5 ≤ Q ≤ 30 • 350 Ω ≤ RP ≤ 10 kΩ 8.1.3 Setting COM Pin Capacitor The COM pin requires a bypass capacitor to ground. The capacitor should be a low ESL, low ESR type. CCOM must be sized so that the following relationship is valid for all channels. 100 × CSENSORn / QSENSORn < CCOM < 1250 × CSENSORn / QSENSORn (4) The value of QSENSORn when the sensor is at the minimum target distance should be used. The maximum acceptable value for CCOM is 20 nF. The CCOM range for a particular sensor configuration can be obtained with the Spiral_Inductor_Designer tab of the LDC Calculations Tool. 8.1.4 Defining Power-On Timing The low power architecture of the LDC2112/LDC2114 makes it possible for the device to be active all the time. When not being used, the LDC2112/LDC2114 can operate in Low Power Mode with a single standby power button, which typically consumes less than 10 µA. If additional power-saving is desired, or in the rare event where a power-on reset becomes necessary (see I2C Interface), the output data will become ready after 50 ms startup time, about 1 ms optional register loading time, and two sampling windows for all active channels. The power-on timing of the LDC2112/LDC2114 is illustrated in Figure 21 below. Only Channels 0 and 1 are enabled. Scan rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle 66 ms startup time Sampling Sampling VDD IN0 IN1 Events Power up DATA is ready after all active channels finish two conversions. 66 ms startup time is independent of scan rate. Figure 21. Power-On Timing 30 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Application Information (continued) 8.1.5 Configuring Button Scan Rate The LDC2112/LDC2114 periodically samples all active channels at the selected scan rate. The device can operate at eight different scan rates to meet various power consumption requirements, where a lower scan rate achieves lower power consumption. In Normal Power Mode, the scan rate can be programmed to 80, 40, 20, or 10 SPS through Register NP_SCAN_RATE (Address 0x0D). In Low Power Mode, the scan rate can be programmed to 5, 2.5, 1.25, or 0.625 SPS through Register LP_SCAN_RATE (Address 0x0F). The mode is selected by setting the LPWRB pin to VDD (Normal Power) or ground (Low Power). In either mode, each button can be independently enabled through a bit in Register EN (Address 0x0C). For typical distribution of the scan rates, refer to Figure 9. Table 42. Button Scan Rates SCAN RATE (SPS) LPSR (0x0F) SETTING NPSR (0x0D) SETTING LPWRB PIN SETTING 0.625 b11 Not Applicable Ground 1.25 b10 Not Applicable Ground 2.5 b01 Not Applicable Ground 5 b00 Not Applicable Ground 10 Not Applicable b11 VDD 20 Not Applicable b10 VDD 40 Not Applicable b01 VDD 80 Not Applicable b00 VDD 8.1.6 Programming Button Sampling Window The button sampling window is the actual duration per scan cycle for active data sampling of the sensor frequency. It is programmed with the exponential parameter, LCDIV, in Register LC_DIVIDER (Address 0x17), and the individual linear sensor cycle counter SENCYCn (n = 0, 1, 2, or 3) in Registers SENSORn_CONFIG (n = 0, 1, 2, or 3, Addresses 0x20, 0x22, 0x24, 0x26). For most touch button applications, the button sampling window should be set to between 1 ms and 8 ms. The recommended minimum sensor conversion time is 1 ms. Longer conversion time can be used to achieve better signal-to-noise ratio if needed. If multiple channels are enabled, the active channels will sample sequentially, as illustrated in Figure 22. Button Sampling Window: set by LCDIV, SENCYCn, and fSENSORn IN0 IN1 IN2 IN3 Scan Rate: set by NPSR, LPSR, and LPWRB pin Figure 22. Configurable Scan Rate and Button Sampling Window The LDC2112/LDC2114 is designed to work with LC resonator sensors with oscillation frequencies ranging from 1 MHz to 30 MHz. The exact definition of the button sampling window is given by the equation below. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 31 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Number of Sensor Oscillation Cycles Sensor Frequency Button Sampling Window 128 u SENCYCn 1 u 2LCDIV tSAMPLE www.ti.com fSENSORn ,n 0, 1, 2, or 3 where: • • • tSAMPLE is the button sampling window in µs, SENCYCn and LCDIV are the linear and exponential scalers that set the number of sensor oscillation cycles, and fSENSORn is the sensor frequency in MHz. (5) In the equation above, LCDIV (0 to 7, default 3) is the exponential LC divider that sets the approximate ranges for all channels, and SENCYCn (0 to 31, default 4) is the linear sensor cycle scaler that fine-tunes each individual channel. Together they set the number of sensor oscillation cycles used to determine the button sampling window. For example, if the LC sensor frequency is 9.2 MHz, and it is desirable to get 1 ms button sampling window, then this can be achieved by setting SENCYCn = 17 and LCDIV = 2. Alternatively, from the button sampling window and sensor frequency, the LCDIV can be read off from Figure 23. For example, 1 ms button sampling window and 9.2 MHz sensor frequency intersect at the region where LCDIV = 2. Then SENCYCn can be calculated accordingly. 30 Maximum Sensor Frequency (MHz) LCDIV=7 25 LCDIV=6 20 LCDIV=5 15 LCDIV=4 10 LCDIV=3 LCDIV=2 5 LCDIV=1 LCDIV=0 0 0 1 2 3 4 5 6 7 Button Sampling Window (ms) 8 9 D008 Figure 23. LCDIV as a Function of Sensor Frequency and Button Sampling Window 8.1.7 Scaling Frequency Counter Output The LDC2112/LDC2114 requires this internal frequency counter scaler to be set based on the button sampling window to avoid data overflow. The scaler in Register CNTSC (Address 0x1E) must be set by the following formula: CNTSCn § 0.0861u SENCYCn 1 · LCDIV ceiling ¨¨ log2 ¸¸ , n fSENSORn © ¹ 0, 1, 2, or 3 where: • • • 32 CNTSCn is the internal frequency counter scaler, SENCYCn and LCDIV are the linear and exponential scalers that set the number of sensor oscillation cycles, and fSENSORn is the sensor frequency in MHz. (6) Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 8.1.8 Setting Button Triggering Threshold Every material shows some hysteresis when it deforms then returns to the original state. The amount of hysteresis is a function of material properties and physical parameters, such as size and thickness. This feature modifies the hysteresis of the button signal threshold according to different materials and various button shapes and sizes. Hysteresis can be programmed in Register HYST (Address 0x18). By default, the button triggering hysteresis is set to 32. The nominal button triggering threshold is 128. With hysteresis, the effective on-threshold is 128 + 32 = 160. This means if the DATAn (n = 0, 1, 2, or 3) reaches 160, the LDC considers that as a button press. When the DATAn decreases to 128 – 32 = 96, the LDC considers the button to be released. ThresholdON 128 Hysteresis (7) ThresholdOFF 128 Hysteresis (8) OUTn High=Button Press Detected Low=No Button Press Detected DATAn ThresholdOFF 128 ThresholdON Figure 24. Button Triggering Threshold with Hysteresis. Output Polarity: Active High 8.1.9 Tracking Baseline The LDC2112/LDC2114 automatically tracks slow changes in the baseline signal and compensates for environmental drifts and variations. In Normal Power Mode, the effective baseline increment per scan cycle (BINCNP) can be determined by Equation 9: BINCNP 2NPBI 72 where: • NPBI is the Normal Power Baseline Increment index that can be configured in Register NP_BASE_INC (Address 0x15). (9) In Low Power Mode, the effective baseline increment per scan cycle (BINCLP) can be determined by Equation 10: BINCLP 2LPBI 9 where: • LPBI the Low Power Baseline Increment index that can be configured in Register LP_BASE_INC (Address 0x13). (10) As a result of baseline tracking, a button press with a constant force only lasts for a finite amount of time. The duration of a button press is defined by Equation 11 (DATAn > ThresholdON). DATAn ThresholdOFF Duration of Button Press BINC where: • • • Duration of Button Press is the number of scan cycles that the channel is asserted, DATAn is the button signal at the beginning of a press, and BINC is the baseline increment per scan cycle. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback (11) 33 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Button Pressed www.ti.com Button Released Baseline DATAn Baseline Increment Fast tracking if DATAn is negative Figure 25. Baseline Tracking in the Presence of a Button Press The baseline tracking for a particular channel can be paused when the channel output is asserted. This is achieved by setting the corresponding BTPAUSE bit in Register BTPAUSE_MAXWIN (Address 0x16) to b1. If DATAn is negative, the tracking speed will be scaled by the fast tracking factor as specified in Registers FTF0 (Address 0x25), FTF1_2 (Address 0x28), or FTF3 (Address 0x2B). The scaling factors for various FTFn settings are shown in Table 43. BINC (DATAn < 0) = Fast_Tracking_Factor_n × BINC (DATAn > 0) (12) Table 43. Fast Tracking Factor Settings FTFn Setting Fast Tracking Factor b00 1 b01 4 b10 8 b11 16 8.1.10 Mitigating False Button Detections The LDC2112/LDC2114 offers several algorithms that can mitigate false button detections due to mechanical non-idealities associated with groups of buttons. These are listed below. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common) This algorithm eliminates false detection when a user presses the middle of two or more buttons, which could lead to a common-mode response on multiple buttons. All the buttons can be individually enabled to have this feature by programming Register COMMON_DEFORM (Address 0x1A). 34 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Common-mode change to both Buttons 0 and 1. Button 0 Button 1 Intentional Press of Button 1 DATA Threshold = 128+Hysteresis Time Button 0 OUTPUT without Anti-common (High = Button Press Detected) Button 1 Time Button 0 OUTPUT with Anti-common (High = Button Press Detected) Button 1 Time Figure 26. Illustration of the Anti-Common Feature 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win) This algorithm enables the system to select the button pressed with maximum force when multiple buttons are pressed at the same time. This could happen when two buttons are physically very close to each other, and pressing one causes a residual reaction on the other. Buttons can be individually enabled to join the “max-win” group by configuring Register BTPAUSE_MAXWIN (Address 0x16). Intentional Press of Button 0 Intentional Press of with coupled response of Button 1 Button 1 Button 0 Button 1 DATA Threshold = 128+Hysteresis Time Button 0 OUTPUT without Max-Win (High = Button Press Detected) Button 1 Time Button 0 OUTPUT with Max-Win (High = Button Press Detected) Button 1 Time Figure 27. Illustration of the Max-Win Feature Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 35 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 8.1.10.3 Overcoming Case Twisting (Anti-Twist) The anti-twist algorithm reduces the likelihood of false detection when the case is twisted, which could cause unintended mechanical activation of the buttons, or an opposite reaction in two adjacent buttons. When this algorithm is enabled, detection of button presses is suppressed if any button’s output data is negative by a configurable threshold. The anti-twist algorithm can be enabled by configuring Register TWIST (Address 0x19). Twisting effect of Buttons 0 and 1. Button 0 Button 1 Intentional Press of Button 1. DATA Threshold = 128+Hysteresis Time Button 0 OUTPUT without Anti-twist (High = Button Press Detected) Button 1 Time Button 0 OUTPUT with Anti-twist (High = Button Press Detected) Button 1 Time Figure 28. Illustration of the Anti-Twist Feature 8.1.10.4 Mitigating Metal Deformation (Anti-Deform) This function filters changes due to metal deformation in the vicinity of one or more buttons. Such metal deformation can be accidentally caused by pressing a neighboring button that does not have sufficient mechanical isolation. The user can specify which buttons to join the anti-deform group by configuring Register COMMON_DEFORM (Address 0x1A). 8.1.11 Reporting Interrupts for Button Presses and Error Conditions INTB, the LDC2112/LDC2114 interrupt pin, is asserted when a button press or an error condition occurs. The default polarity is active low and can be configured through Register INTPOL (Address 0x11). Figure 29 shows the LDC2112/LDC2114 response to a single button press on Channel 0. At the end of the button sampling window following a press of Button 0, the OUT0 pin and INTB pin are asserted. The OUT_STATUS bit changes from 0 to 1, and remains so until a read of the STATUS register clears it. The OUTn (n = 0, 1, 2, or 3) and INTB pins are asserted until the end of the button sampling window following the release of the button. 36 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 OUTn DQG ,17% DUH SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle Sampling 25 ms scan cycle Sampling Sampling OUT0 Pin INTB Pin STATUS Register Events Button 0 pressed OUT0 and INTB asserted, OUT_STATUS bit asserted Reading the Status Register clears the OUT_STATUS bit. Button 0 released OUT0 de-asserted Figure 29. Timing Diagram of a Single Button Press Figure 30 shows the LDC2112/LDC2114 response to multiple button presses. In this example, after Button 0 is pressed, the OUT0 pin is asserted. After that, Button 1 is also pressed, following which Button 0 is released. The OUT0 pin is de-asserted and OUT1 pin asserted at the end of the next button sampling window. The INTB pin remains continuously asserted as long as at least one of the buttons is pressed. The OUT_STATUS bit only changes from 0 to 1 after the first button assertion. OUTn DQG ,17% DUH SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle Sampling Sampling 25 ms scan cycle Sampling OUT0 Pin OUT1 Pin INTB Pin STATUS Register Events Button 0 pressed OUT0 and INTB asserted Button 1 Button 0 pressed released OUT0 de-asserted OUT1 asserted Button 1 released OUT1 and INTB de-asserted Reading the Status Register clears the OUT_STATUS bit. Figure 30. Timing Diagram of Multiple Button Presses The INTB pin also reports any error event. If an error occurs, the INTB pin is asserted and the error is reported in the STATUS register (Address 0x00). Refer to Register STATUS (Address 0x00) for possible error events. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 37 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 8.1.12 Estimating Supply Current When the LDC2112/LDC2114 is active (in either Normal Power Mode or Low Power Mode), its current can be characterized by Equation 13: 12 IACTIVEn 1.6 0.011u fSENSORn 1 16 u RPn1.21 where • • • • IACTIVEn is the supply current in mA during active sampling, RPn is the sensor parallel resonant impedance in kΩ, fSENSORn is the sensor frequency in MHz, and n is the channel index, i.e. n = 0 or 1 for LDC2112; n = 0, 1, 2, or 3 for LDC2114. (13) The LDC2112/LDC2114 is only actively sampling the enabled channels during a fraction of the scan window. So the average supply current is: 1 IDD tSCAN § u¨ ¨ © · ¦IACTIVEn u tSAMPLEn ¸¸ n 0.005 ¹ where • • • • IDD is the average supply current in mA, tSCAN is the scan window (set by the scan rate) in ms, IACTIVEn is the supply current when the device is active as defined by Equation 13, and tSAMPLE is the button sampling window in ms. (14) 8.2 Typical Application 8.2.1 Touch Button Design The low power architecture of LDC2112/LDC2114 makes them suitable for driving button sensors in consumer electronics, such as mobile phones. Most mobile phones today have three buttons along the edges, namely the power button, volume up, and volume down. The LDC2112 can support two buttons, and LDC2114 can support four. On a typical smartphone, the two volume buttons are next to each other, so they may be susceptible to false detections such as simultaneous button presses. To prevent such mis-triggers, they can be grouped together to take advantage of the various features that mitigate false detections as explained in Mitigating False Button Detections. For example, if Max-win is applied to the two volume buttons, only the one with the greater force will be triggered. The inductive touch solution does not require any mechanical cutouts at the button locations. This can support reduced manufacturing cost for the phone case and enhance the case’s resistance to moisture, dust, and dirt. This is a great advantage compared to mechanical buttons in the market today. 8.2.1.1 Design Requirements The sensor parameters, including frequency, RP, and Q factor have to be within the design space of the LDC2112/LDC2114 as specified in Electrical Characteristics. 8.2.1.2 Detailed Design Procedure The LDC2112/LDC2114 is a multi-channel device. The italic n in the parameters below refers to the channel index, i.e., n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. 1. Select system-based options: • Select Normal or Low Power Mode of operation by setting the LPWRB pin to VDD or Ground, respectively. Configure the enable bits for all channels in Register EN (Address 0x0C). • Select the polarities of OUTn and INTB pins by configuring Register OPOL_DPOL (Address 0x1C) and Register INTPOL (Address 0x11). 38 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Typical Application (continued) • Configure the sensor frequency setting in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26). 2. Choose the sampling rate (80, 40, 20, 10, 5, 2.5, 1.25, or 0.625 SPS) based on system power consumption requirement, and configure Register NP_SCAN_RATE (Address 0x0D) or Register LP_SCAN_RATE (Address 0x0F). 3. Choose the button sampling window based on power consumption and noise requirements (recommended: 1 ms to 8 ms). While a longer button sampling window provides better noise performance, 1 ms is typically sufficient for most applications. Set SENCYCn and LCDIV in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26) and Register LC_DIVIDER (Address 0x17) in the following steps: • Calculate LCDIV = ceiling (log2 (fSENSORn × tSAMPLEn) – 12), where fSENSORn is the sensor frequency in MHz, tSAMPLEn is the button sampling window in µs • If LCDIV < 0, set it to 0 • Adjust SENCYCn to get desired tSAMPLEn according to tSAMPLEn = 128 × (SENCYCn + 1) × 2LCDIV / fSENSORn 4. Calibrate gain in the appropriate Registers GAINn (Addresses 0x0E, 0x10, 0x12, 0x14). The gain setting can be used to tune the sensitivity of the touch button. GAINn is a 6-bit field with 64 different gain levels corresponding to normalized gains between 1 and 232. A good mechanical and sensor design typically requires a gain level of around 32 to 50, corresponding to relative gains of 16 to 76 (normalized to gain level of 0). Use the following sequence to determine the appropriate gain for each button: • Apply minimum desired force to the button. • Read initial DATAn value after the button press. Note that the baseline tracking will affect this value. • Calculate gain factor needed to increase DATAn to the programmed threshold (default is 160). • Look up the Gain Table to find the required gain setting. 5. Enable special features to mitigate button interference if there is any. Registers BTPAUSE_MAXWIN, TWIST, COMMON_DEFORM (Addresses 0x16, 0x19, 0x1A). For more information on inductive touch system design, including mechanical design and sensor electrical design, refer to Inductive Touch System Design Guide. 8.2.1.3 Application Curves Figure 31 shows a sequence of button presses of 150 grams force, two presses to Channel 0, then two presses to Channel 1. Each button press response is greater than the threshold. 400 Channel 0 Channel 1 Threshold 350 Conversion DATA 300 250 200 150 100 50 0 -50 0 2 4 Time (s) 6 8 D009 Figure 31. Conversion DATA vs Time for Channels 0 and 1 Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 39 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 9 Power Supply Recommendations The LDC2112/LDC2114 power supply should be bypassed with a 1 µF and a 0.1 µF pair of capacitors in parallel to ground. The capacitors should be placed as close to the LDC as possible. The smaller value 0.1 µF capacitor should be placed closer to the VDD pin than the 1 µF capacitor. The capacitors should be a low ESL, low ESR type. To enable close positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is recommended for the DSBGA package. Refer to Recommended Operating Conditions for more details. 10 Layout 10.1 Layout Guidelines The COM pin must be bypassed to ground with an appropriate value capacitor. For details of how to choose the capacitor value, refer to Setting COM Pin Capacitor. CCOM should be placed as close as possible to the COM pin. The COM signal should be tied to a small copper fill placed underneath the INn signals. The INn signals should stay clear of other high frequency traces. Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor capacitor should be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in Figure 32) should be placed at the appropriate location next to (but not touching) the metal target. The INn traces should be at least 6 mil (0.15 mm) wide to minimize parasitic inductances. For the DSBGA package, the inner four device pads (INTB, OUT3, LPWRB, and SDA) should be routed out on an inner layer through vias, with the traces offset to reduce coupling with other signals. These four vias may need to use blind vias or microvias to bring the signals out. The PCB layer stack should use a thinner (4 mil or 0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used. 10.2 Layout Example Figure 32. Layout of LDC2114 (DSBGA-16) With Decoupling Capacitors and Sensor Capacitors 40 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 Layout Example (continued) Figure 33. Layout of LDC2114 (TSSOP-16) With Decoupling Capacitors and Sensor Capacitors 10.3 DSBGA Light Sensitivity Exposing the DSBGA device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 41 LDC2112, LDC2114 SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation see the following: • LDC Calculations Tool • Inductive Touch System Design Guide 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 44. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LDC2112 Click here Click here Click here Click here Click here LDC2114 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 42 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15B – DECEMBER 2016 – REVISED APRIL 2017 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 Submit Documentation Feedback 43 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LDC2112PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2112PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2112YFDR PREVIEW DSBGA YFD 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 17M LDC2112YFDT PREVIEW DSBGA YFD 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 17M LDC2114PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2114PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2114YFDR ACTIVE DSBGA YFD 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 14G LDC2114YFDT ACTIVE DSBGA YFD 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 14G PLDC2114PWT ACTIVE TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2017 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LDC2114YFDR DSBGA YFD 16 3000 180.0 8.4 LDC2114YFDT DSBGA YFD 16 250 180.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.69 1.69 0.46 4.0 8.0 Q1 1.69 1.69 0.46 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Mar-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LDC2114YFDR DSBGA YFD 16 3000 182.0 182.0 20.0 LDC2114YFDT DSBGA YFD 16 250 182.0 182.0 20.0 Pack Materials-Page 2 PACKAGE OUTLINE YFD0016 DSBGA - 0.4 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D 0.4 MAX C SEATING PLANE 0.175 0.125 BALL TYP 0.05 C 1.2 TYP SYMM D 1.2 TYP C SYMM D: Max = 1.625 mm, Min =1.565 mm B 0.4 TYP 16X 0.015 C A 0.285 0.185 B E: Max = 1.625 mm, Min =1.565 mm A 1 2 3 4 0.4 TYP 4222547/A 12/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com EXAMPLE BOARD LAYOUT YFD0016 DSBGA - 0.4 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP 16X ( 0.225) A (0.4) TYP B SYMM C D 2 1 4 3 SYMM LAND PATTERN EXAMPLE SCALE:40X 0.05 MAX ( 0.225) METAL METAL UNDER SOLDER MASK 0.05 MIN ( 0.225) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222547/A 12/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com EXAMPLE STENCIL DESIGN YFD0016 DSBGA - 0.4 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 16X ( 0.25) A (0.4) TYP B SYMM METAL TYP C D 1 2 3 4 SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4222547/A 12/2015 NOTES: (continued) 4. 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