plerowTM ALUC2535B3 Internally Matched Balanced LNA Module Including Coupler Features Description · S21 = 34.4 27.2 dB@2500 dB@1880 MHz = 33.6 26.8 dB@2570 dB@1920 MHz · NF of 0.75 0.65 dB over Frequency · Unconditionally Stable · Single 5 V Supply · High OIP3@Low Current · 3-stage 2-stage Balanced Type C C o o u upl p er l e C r o u pl er Specifications (in Production) Typ.@T = 25 C, Vs = 5 V, Freq. = 2535 MHz, Zo.sys = 50 ohms Parameter Specifications Unit Frequency Range Min 3-stage Balanced Type Typ Max MHz 2500 Gain dB 33 Gain Flatness dB 0.4 0.5 Noise Figure dB 0.75 0.80 (1) dBm Output P1dB dBm Switching Time (3) Output IP3 S11/S22 (2) 2570 34 39 40 23 24 dB Website: www.asb.co.kr E-mail: [email protected] Tel: (82) 42-528-7223 Fax: (82) 42-528-7222 -20/-20 sec - Supply Current mA 340 Supply Voltage V 5 380 50 Max. RF Input Power dBm C.W 29~31(before fail) Package Type & Size mm Surface Mount Type, 22Wx12Lx5H Impedance More Information Operating temperature is –40 C to +85 C. 1) OIP3 is measured with two tones at an output power of +7 dBm/tone separated by 1 MHz. 2) S11, S22(max) is the worst value within the frequency band. 3) Switching time means the time that takes for output power to get stabilized to its final level after switching DC voltage from 0 V to VS. Outline Drawing (Unit: mm) 8 1 2 ALUC2535B3 3 4 7 6 5 (Right side View) Port Number Function 1 RF In 5 RF Out 4, 8 Vs Others, Bottom GND Note: 1. The number and size of ground via holes in a circuit board is critical for thermal RF grounding considerations. 2. We recommend that the ground via holes be placed on the bottom of all ground pins for better RF and thermal performance, as shown in the drawing at the left side. (Top View) Solder Stencil Area C o u pl er (Bottom side View) Ø 0.4 plated thru holes to ground plane 1/3 (Recommended Footprint) www.asb.co.kr February 2010 plerowTM ALUC2535B3 Internally Matched Balanced LNA Module Including Coupler S-parameters Typical Performance (Measured) 2500~2570 MHz +5 V 2/3 S-parameters & K Factor Noise Figure OIP3 P1dB www.asb.co.kr February 2010 plerowTM ALUC2535B3 Internally Matched Balanced LNA Module Including Coupler Application Circuit VS Tantal or MLC (Multi Layer Ceramic) Capacitor + C1 IN C2 ALUC OUT Tantal or MLC (Multi Layer Ceramic) Capacitor + VS - 1) The tantal or MLC (Multi Layer Ceramic) capacitor is optional and for bypassing the AC noise introduced from the DC supply. The capacitance value may be determined by customer’s DC supply status. The capacitor should be placed as close as possible to Vs pin and be connected directly to the ground plane for the best electrical performance. 2) DC blocking capacitors are always necessarily placed at the input and output port for allowing only the RF signal to pass and blocking the DC component in the signal. The DC blocking capacitors are included inside the ALN module. Therefore, C1 & C2 capacitors may not be necessary, but can be added just in case that the customer wants. The value of C1 & C2 is determined by considering the application frequency. Recommended Soldering Reflow Process Evaluation Board Layout Vs 20~40 sec 260 C Ramp-up (3 ˚C/sec) 200 C Ramp-down (6 C/sec) IN OUT 150 C Vs 60~180 sec 3/3 Size 40x40 mm (for ALUC Series – 22x12 mm) www.asb.co.kr February 2010