STMicroelectronics M24C64-WDW3/P 128 kbit, 64 kbit and 32 kbit serial i2c bus eeprom Datasheet

M24128
M24C64 M24C32
128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM
Feature summary
■
Two-Wire I2C serial interface
Supports 400kHz Protocol
■
Single supply voltages (see Table 1 for root
part numbers):
– 2.5 to 5.5V
– 1.8 to 5.5V
– 1.7 to 5.5V
■
Write Control Input
■
Byte and Page Write
■
Random And Sequential Read modes
■
Self-Timed programming cycle
■
Automatic address incrementing
■
Enhanced ESD/Latch-Up Protection
■
More than 1 Million Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK® (RoHS compliant)
Table 1.
Reference
PDIP8 (BN)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
Product list
Root part number
Supply voltage
M24128-BW
2.5 to 5.5V
M24128-BR
1.8 to 5.5V
M24C64-W
2.5 to 5.5V
M24C64-R
1.8 to 5.5V
M24C64-F
1.7 to 5.5V
M24C32-W
2.5 to 5.5V
M24C32-R
1.8 to 5.5V
M24C32-F
1.7 to 5.5V
M24128
M24C64
M24C32
October 2006
UFDFPN8 (MB)
2x3mm² (MLP)
Rev 9
1/34
www.st.com
1
Contents
M24128, M24C64, M24C32
Contents
1
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.0.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1
2.3.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.3
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.9
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
4.10
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/34
M24128, M24C64, M24C32
Contents
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/34
List of tables
M24128, M24C64, M24C32
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
4/34
Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating conditions (M24128-BW, M24C64-W, M24C32-W) . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (M24128-BR, M24C64-R, M24C32-R) . . . . . . . . . . . . . . . . . . . . . . . 21
Operating conditions (M24C64-F, M24C32-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (VCC = 2.5V to 5.5V, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC characteristics (VCC = 2.5V to 5.5V, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics (VCC = 1.8V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics (VCC = 1.7V to 5.5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3) . . . . . . . . . . . . . . . . . . . . 25
AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V) . . . . . . . . . . . . . . . . . . . . . 25
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data . . . . . . . . . . . . 27
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data . . . . . . . . . . . . . . 29
UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
M24128, M24C64, M24C32
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 9
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package outline . . . . . . . . . . . . . . . . . . . . 27
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 28
TSSOP8 – 8 lead Thin Shrink Small Outline, package outline . . . . . . . . . . . . . . . . . . . . . . 29
UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5/34
Summary description
1
M24128, M24C64, M24C32
Summary description
The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable
programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits
and 16384 × 8 bits, respectively.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
VCC
3
E0-E2
SCL
WC
M24128-BW
M24128-BR
M24C64-W
M24C64-R
M24C64-F
M24C32-W
M24C32-R
M24C32-F
SDA
VSS
AI01844d
I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I2C bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
6/34
M24128, M24C64, M24C32
Table 2.
Summary description
Signal names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
Figure 2.
DIP, SO, TSSOP and UFDFPN connections
E0
E1
E2
VSS
M24128
M24C64
M24C32
1
8
2
7
3
6
4
5
VCC
WC
SCL
SDA
AI01845e
1. See Package mechanical section for package dimensions, and how to identify pin-1.
7/34
Signal description
M24128, M24C64, M24C32
2
Signal description
2.0.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.0.2
Serial Data (SDA)
This bi-directional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how
the value of the pull-up resistor can be calculated).
2.1
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to
VCC or VSS, to establish the Device Select Code as shown in Figure 3. When not connected
(left floating), these inputs are read as Low (0,0,0).
Figure 3.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.2
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device Select and Address bytes are
acknowledged, Data bytes are not acknowledged.
8/34
M24128, M24C64, M24C32
Signal description
2.3
Supply voltage (VCC)
2.3.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS
package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.3.2
Internal device reset
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR)
circuit is included. At Power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the Power On Reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 9 and Table 10).
When VCC has passed the POR threshold, the device is reset and is in Standby Power
mode.
Power-down
At Power-down (continuous decrease of VCC), as soon as VCC drops from the normal
operating voltage to below the Power On Reset threshold voltage, the device stops
responding to any instruction sent to it.
During Power-down, the device must be deselected and in the Standby Power mode (that is
there should be no internal Write cycle in progress).
Figure 4.
Maximum RP value versus bus parasitic capacitance (C) for an I2C bus
VCC
20
Maximum RP value (kΩ)
2.3.3
16
RP
12
RP
SDA
MASTER
8
fc = 100kHz
4
fc = 400kHz
C
SCL
C
0
10
100
1000
C (pF)
AI01665b
9/34
Signal description
Figure 5.
M24128, M24C64, M24C32
I2C bus protocol
SCL
SDA
SDA
Input
START
Condition
SCL
1
SDA
MSB
2
SDA
Change
STOP
Condition
3
7
8
9
ACK
START
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
STOP
Condition
AI00792B
Table 3.
Device select code
Device Type Identifier(1)
Device Select Code
Chip Enable Address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 4.
b15
Table 5.
b7
10/34
Address most significant byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Address least significant byte
b6
b5
b4
M24128, M24C64, M24C32
Memory organization
The memory is organized as shown in Figure 6.
Figure 6.
Block diagram
WC
E0
E1
High Voltage
Generator
Control Logic
E2
SCL
SDA
I/O Shift Register
Address Register
and Counter
Data
Register
Y Decoder
3
Memory organization
1 Page
X Decoder
AI06899
11/34
Device operation
4
M24128, M24C64, M24C32
Device operation
The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24C32, M24C64 and M24128
devices are always slaves in all communications.
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Stand-by mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
4.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
12/34
M24128, M24C64, M24C32
4.5
Device operation
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in Table 3 (on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Stand-by mode.
Table 6.
Operating modes
Mode
Current Address
Read
RW bit WC(1)
Bytes
1
Initial Sequence
1
X
START, Device Select, RW = 1
Random Address
Read
0
X
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
START, Device Select, RW = 0
Page Write
0
VIL
≤ 32 for M24C64
and M24C32
START, Device Select, RW = 0
START, Device Select, RW = 0, Address
1
reSTART, Device Select, RW = 1
Similar to Current or Random Address
Read
≤ 64 for M24128
1. X = VIH or VIL.
13/34
Device operation
Figure 7.
M24128, M24C64, M24C32
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
NO ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
NO ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
NO ACK
AI01120C
14/34
M24128, M24C64, M24C32
4.6
Device operation
Write operations
Following a Start condition the bus master sends a Device Select Code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write
instruction with Write Control (WC) driven High (during a period of time from the Start
condition until the end of the two address bytes) will not modify the memory contents, and
the accompanying data bytes are not acknowledged, as shown in Figure 7.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is
triggered. A Stop condition at any other time slot does not trigger the internal Write cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
4.7
Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 8.
4.8
Page Write
The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for
the M24128) to be written in a single Write cycle, provided that they are all located in the
same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for
M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent
than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be
avoided, as data starts to become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes
of data (for the M24128), each of which is acknowledged by the device if Write Control (WC)
is Low. If Write Control (WC) is High, the contents of the addressed memory location are not
modified, and each data byte is followed by a NoAck. After each byte is transferred, the
internal byte address counter (inside the page) is incremented. The transfer is terminated by
the bus master generating a Stop condition.
15/34
Device operation
Figure 8.
M24128, M24C64, M24C32
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN
STOP
DEV SEL
START
BYTE WRITE
ACK
R/W
WC
ACK
DEV SEL
START
PAGE WRITE
ACK
BYTE ADDR
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
WC (cont'd)
ACK
DATA IN N
STOP
PAGE WRITE
(cont'd)
ACK
AI01106C
16/34
M24128, M24C64, M24C32
Figure 9.
Device operation
Write cycle polling flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
STOP
NO
START
Condition
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
AI01847C
4.9
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 17 and Table 18, but the typical time is shorter. To make use of this, a polling
sequence can be used by the bus master.
The sequence, as shown in Figure 9, is:
–
Initial condition: a Write cycle is in progress.
–
Step 1: the bus master issues a Start condition followed by a Device Select Code
(the first byte of the new instruction).
–
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned
and the bus master goes back to Step 1. If the device has terminated the internal
Write cycle, it responds with an Ack, indicating that the device is ready to receive
the second part of the instruction (the first byte of this instruction having been sent
during Step 1).
17/34
Device operation
M24128, M24C64, M24C32
Figure 10. Read mode sequences
ACK
DATA OUT
STOP
START
DEV SEL
NO ACK
R/W
ACK
START
DEV SEL *
ACK
BYTE ADDR
ACK
DEV SEL *
ACK
DATA OUT 1
ACK
ACK
NO ACK
DATA OUT N
BYTE ADDR
ACK
BYTE ADDR
ACK
DEV SEL *
START
START
ACK
R/W
ACK
DATA OUT
R/W
R/W
DEV SEL *
NO ACK
STOP
START
DEV SEL
SEQUENTIAL
RANDOM
READ
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
ACK
START
RANDOM
ADDRESS
READ
STOP
CURRENT
ADDRESS
READ
ACK
DATA OUT 1
R/W
NO ACK
STOP
DATA OUT N
AI01105C
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)
must be identical.
18/34
M24128, M24C64, M24C32
4.10
Device operation
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.11
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the Device Select Code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.12
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the Read/Write bit (RW) set to 1. The device
acknowledges this, and outputs the byte addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition,
as shown in Figure 10, without acknowledging the Byte.
4.13
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
4.14
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Stand-by mode.
19/34
Initial delivery state
5
M24128, M24C64, M24C32
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TA
TSTG
Parameter
Min.
Max.
Unit
Ambient Operating Temperature
–40
130
°C
Storage Temperature
–65
150
°C
(1)
°C
Lead Temperature during Soldering
TLEAD
(2)
PDIP-Specific Lead Temperature during Soldering
VIO
Input or Output range
VCC
Supply Voltage
VESD
see note
Electrostatic Discharge Voltage (Human Body
model)(3)
260
–0.50
6.5
V
–0.50
6.5
V
–4000
4000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. TLEAD max must not be applied for more than 10s.
3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
20/34
°C
M24128, M24C64, M24C32
7
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M24128-BW, M24C64-W, M24C32-W)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply Voltage
2.5
5.5
V
Ambient Operating Temperature (Device Grade 6)
–40
85
°C
Ambient Operating Temperature (Device Grade 3)
–40
125
°C
Operating conditions (M24128-BR, M24C64-R, M24C32-R)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply Voltage
1.8
5.5
V
Ambient Operating Temperature
–40
85
°C
Min.
Max.
Unit
Supply Voltage
1.7
5.5
V
Ambient Operating Temperature
–20
85
°C
Min.
Max.
Unit
Operating conditions (M24C64-F, M24C32-F)
Symbol
VCC
TA
Table 11.
Parameter
AC test measurement conditions
Symbol
CL
Parameter
Load Capacitance
100
Input Rise and Fall Times
pF
50
ns
Input Levels
0.2VCC to 0.8VCC
V
Input and Output Timing Reference Levels
0.3VCC to 0.7VCC
V
Figure 11. AC test measurement I/O waveform
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
AI00825B
21/34
DC and AC parameters
Table 12.
Symbol
M24128, M24C64, M24C32
Input parameters
Parameter(1),(2)
Test Condition
Min.
Max.
Unit
CIN
Input Capacitance (SDA)
8
pF
CIN
Input Capacitance (other pins)
6
pF
200
kΩ
ZWCL
WC Input Impedance
VIN < 0.3VCC
50
ZWCH
WC Input Impedance
VIN > 0.7VCC
500
tNS
kΩ
Pulse width ignored
(Input Filter on SCL and SDA)
200
ns
1. TA = 25°C, f = 400kHz
2. Sampled only, not 100% tested.
Table 13.
Symbol
DC characteristics (VCC = 2.5V to 5.5V, device grade 6)
Parameter
Test Condition
(in addition to those in Table 8)
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Stand-by mode
±2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
ICC
Supply Current (Read)
2.5V < VCC < 5.5V, fc=400kHz
(rise/fall time < 30ns)
2
mA
ICC0
Supply Current (Write)
During tW, 2.5V < VCC < 5.5V
5(1)
mA
Stand-by Supply Current
VIN = VSS or VCC,
VCC = 5.5V
5
µA
Stand-by Supply Current
VIN = VSS or VCC,
VCC = 2.5V
2
µA
ICC1
VIL
Input Low Voltage (SDA,
SCL, WC)
–0.45
0.3VCC
V
VIH
Input High Voltage (SDA,
SCL, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
IOL = 2.1mA, VCC = 2.5V or
IOL = 3mA, VCC = 5.5V
1. Characterized value, not tested in production.
22/34
Min.
M24128, M24C64, M24C32
Table 14.
Symbol
DC and AC parameters
DC characteristics (VCC = 2.5V to 5.5V, device grade 3)
Parameter
Test Condition
(in addition to those in Table 8)
Min.
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Stand-by mode
±2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
ICC
Supply Current (Read)
2.5V < VCC < 5.5V, fc=400kHz
(rise/fall time < 30ns)
2
mA
ICC0
Supply Current (Write)
During tW, 2.5V < VCC < 5.5V
5(1)
mA
ICC1
Stand-by Supply Current
VIN = VSS or VCC,
2.5V < VCC < 5.5V
10
µA
VIL
Input Low Voltage (SDA,
SCL, WC)
–0.45
0.3VCC
V
VIH
Input High Voltage (SDA,
SCL, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.4
V
Max.
Unit
IOL = 2.1mA, VCC = 2.5V or
IOL = 3mA, VCC = 5.5V
1. Characterized value, not tested in production.
Table 15.
Symbol
DC characteristics (VCC = 1.8V to 5.5V)
Parameter
Test Condition
(in addition to those in Table 9)
Min.
ILI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Stand-by mode
±2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
ICC
Supply Current (Read)
VCC =1.8V, fc = 400kHz
(rise/fall time < 30ns)
0.8
mA
ICC0
Supply Current (Write)
During tW, 1.8V < VCC < 2.5V
3(1)
mA
ICC1
Stand-by Supply Current
VIN = VSS or VCC,
1.8V < VCC < 2.5V
1
µA
VIL
Input Low Voltage (SDA,
SCL, WC)
–0.45
0.3 VCC
V
VIH
Input High Voltage (SDA,
SCL, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.2
V
IOL = 0.7 mA, VCC = 1.8 V
1. Characterized value, not tested in production.
23/34
DC and AC parameters
Table 16.
M24128, M24C64, M24C32
DC characteristics (VCC = 1.7V to 5.5V)(1)
Symbol
Parameter
Test Condition
(in addition to those in
Table 10)
Max.
Unit
ILI
Input Leakage Current
(SCL, SDA, E2, E1, E0)
VIN = VSS or VCC
device in Stand-by mode
±2
µA
ILO
Output Leakage Current
VOUT = VSS or VCC, SDA in Hi-Z
±2
µA
ICC
Supply Current (Read)
VCC =1.7V, fc = 400kHz
(rise/fall time < 30ns)
0.8
mA
ICC0
Supply Current (Write)
During tW, 1.7V < VCC < 2.5V
3(2)
mA
ICC1
Stand-by Supply Current
VIN = VSS or VCC,
1.7V < VCC < 2.5V
1
µA
VIL
Input Low Voltage (SDA,
SCL, WC)
–0.45
0.3 VCC
V
VIH
Input High Voltage (SDA,
SCL, WC)
0.7VCC
VCC+1
V
VOL
Output Low Voltage
0.2
V
IOL = 0.7 mA, VCC = 1.7 V
1. Preliminary data.
2. Characterized value, not tested in production.
24/34
Min.
M24128, M24C64, M24C32
Table 17.
DC and AC parameters
AC characteristics (VCC = 2.5V to 5.5V, device grades 6 and 3)
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
fC
fSCL
Clock Frequency
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2(1)
tF
SDA Fall Time
tDXCX
tSU:DAT Data In Set Up Time
tCLDX
tHD:DAT Data In Hold Time
tCLQX
tCLQV
(2)
tCHDX(3)
Min.
20
Max.
Unit
400
kHz
300
ns
100
ns
0
ns
ns
tDH
Data Out Hold Time
200
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
1300
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
tW
tWR
Write Time
5
ms
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
Table 18.
AC characteristics (VCC = 1.8V to 5.5V or VCC = 1.7V to 5.5V)
Test conditions specified in Table 11 and Table 9 or Table 10
Symbol
Alt.
fC
fSCL
Clock Frequency
tCHCL
tHIGH
Clock Pulse Width High
600
ns
tCLCH
tLOW
Clock Pulse Width Low
1300
ns
tDL1DL2
(1)
tF
Parameter
SDA Fall Time
tDXCX
tSU:DAT Data In Set Up Time
tCLDX
tHD:DAT Data In Hold Time
Min.
20
Max.
Unit
400
kHz
300
ns
100
ns
0
ns
ns
tCLQX
tDH
Data Out Hold Time
200
tCLQV(2)
tCHDX(3)
tAA
Clock Low to Next Data Valid (Access Time)
200
900
ns
tSU:STA Start Condition Set Up Time
600
ns
tDLCL
tHD:STA Start Condition Hold Time
600
ns
tCHDH
tSU:STO Stop Condition Set Up Time
600
ns
1300
ns
tDHDL
tBUF
Time between Stop Condition and Next Start Condition
tW
tWR
Write Time
10
ms
1. Sampled only, not 100% tested.
2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the
falling or rising edge of SDA.
3. For a reSTART condition, or following a Write cycle.
25/34
DC and AC parameters
M24128, M24C64, M24C32
Figure 12. AC waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
START
Condition
SDA
Input
SDA tDXCX
Change
tCHDH tDHDL
START
STOP
Condition Condition
SCL
SDA In
tCHDH
tW
STOP
Condition
Write Cycle
tCHDX
START
Condition
SCL
tCLQV
SDA Out
tCLQX
Data Valid
AI00795C
26/34
M24128, M24C64, M24C32
8
Package mechanical
Package mechanical
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
1. Drawing is not to scale.
Table 19.
PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, package mechanical data
millimeters
inches
Symbol
Typ.
Min.
A
Max.
Typ.
Min.
5.33
A1
Max.
0.210
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
–
–
0.100
–
–
eA
7.62
–
–
0.300
–
–
eB
L
10.92
3.30
2.92
3.81
0.430
0.130
0.115
0.150
27/34
Package mechanical
M24128, M24C64, M24C32
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 20.
SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
–
–
0.050
–
–
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
1.27
0.016
0.050
L1
28/34
Max
1.04
0.041
M24128, M24C64, M24C32
Package mechanical
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 21.
TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data
millimeters
inches
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
29/34
Package mechanical
M24128, M24C64, M24C32
Figure 16. UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 × 3mm, package outline
e
D
b
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
1. Drawing is not to scale.
Table 22.
UFDFPN8 (MLP8) – 8-lead Ultra thin Fine pitch Dual Flat Package No lead
2 × 3mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.55
0.50
0.60
0.022
0.020
0.024
A1
0.02
0.00
0.05
0.001
0.000
0.002
b
0.25
0.20
0.30
0.010
0.008
0.012
D
2.00
1.90
2.10
0.079
0.075
0.083
D2
1.60
1.50
1.70
0.063
0.059
0.067
ddd
0.08
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
0.20
0.10
0.30
0.008
0.004
0.012
e
0.50
–
–
0.020
–
–
L
0.45
0.40
0.50
0.018
0.016
0.020
L1
L3
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0.003
0.15
0.30
0.006
0.012
M24128, M24C64, M24C32
9
Part numbering
Part numbering
Table 23.
Ordering information scheme
Example:
M24C32–
W MN 6
T
P /B
Device Type
M24 = I2C serial access EEPROM
Device Function
128–B = 128 Kbit (16384 x 8)
C64– = 64 Kbit (8192 x 8)
C32– = 32 Kbit (4096 x 8)
Operating Voltage
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V
F = VCC = 1.7 to 5.5V(1)
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
MB = UFDFPN8 (MLP8)(2)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with High Reliability Certified Flow(3) over –40 to 125°C.
5 = Consumer: device tested with standard test flow over –20 to 85°C(1)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPACK® (RoHS compliant)
Process
B = F6DP26% Rousset
P = F6DP26% Chartered
1. Device grade 5 is available only with the operating voltage option F.
2. The UFDFPN8 package is available in M24C32-x devices only. It is not available in M24C64-x devices.
3. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
The category of Second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
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Revision history
10
M24128, M24C64, M24C32
Revision history
Table 24.
32/34
Document revision history
Date
Revision
Changes
22-Dec-1999
2.3
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,
PackageMechData).
28-Jun-2000
2.4
TSSOP8 package data corrected
31-Oct-2000
2.5
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables
throughout.
20-Apr-2001
2.6
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
16-Jan-2002
2.7
Test condition for ILI made more precise, and value of ILI for E2-E0 and
WC added
-R voltage range added
02-Aug-2002
2.8
Document reformatted using new template.
TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003
2.9
SO8W package removed. -S voltage range removed
27-May-2003
2.10
TSSOP8 (3x3mm² body size) package (MSOP8) removed
22-Oct-2003
3.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to -0.45V.
01-Jun-2004
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
04-Nov-2004
5.0
Product List summary table added. Device Grade 3 added. 4.5-5.5V
range is Not for New Design. Some minor wording changes. AEC-Q100002 compliance. tNS(max) changed. VIL(min) is the same on all input
pins of the device. ZWCL changed.
05-Jan-2005
6.0
UFDFPN8 package added. Small text changes.
M24128, M24C64, M24C32
Table 24.
Revision history
Document revision history (continued)
Date
29-Jun-2006
03-Jul-2006
17-Oct-2006
Revision
Changes
7
Document converted to new ST template.
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.
Section 2.1: Chip Enable (E0, E1, E2) and Section 2.2: Write Control
(WC) modified, Section 2.3: Supply voltage (VCC) added and replaces
Power On Reset: VCC Lock-Out Write Protect section.
TA added, Note 1 updated and TLEAD specified for PDIP packages in
Table 7: Absolute maximum ratings.
ICC0 added, ICC voltage conditions changed and ICC1 specified over the
whole voltage range in Table 13: DC characteristics (VCC = 2.5V to
5.5V, device grade 6).
ICC0 added, ICC frequency conditions changed and ICC1 specified over
the whole voltage range in Table 15: DC characteristics (VCC = 1.8V to
5.5V).
tW modified in Table 17: AC characteristics (VCC = 2.5V to 5.5V, device
grades 6 and 3).
SO8N package specifications updated (see Figure 14 and Table 20).
Device grade 5 added, B and P Process letters added to Table 23:
Ordering information scheme. Small text changes.
8
ICC1 modified in Table 13: DC characteristics (VCC = 2.5V to 5.5V,
device grade 6).
Note 1 added to Table 16: DC characteristics (VCC = 1.7V to 5.5V) and
table title modified.
9
UFDFPN8 package specifications updated (see Table 22). M24128-BWand M24128-BR part numbers added.
Generic part number corrected in Feature summary on page 1.
ICC0 corrected in Table 14 and Table 13.
Packages are ECOPACK® compliant.
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M24128, M24C64, M24C32
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