STMicroelectronics OA1ZHA22C Fitness and healthcare Datasheet

OA1ZHA, OA2ZHA, OA4ZHA
High precision 5 µV zero drift, low-power op amps
Datasheet - production data
Benefits
High precision operational amplifiers
(op amps) with no need for calibration
Accuracy virtually unaffected by temperature
change
Applications
Wearable
Fitness and healthcare
Medical instrumentation
Description
The OA1ZHA, OA2ZHA, OA4ZHA series of lowpower, high-precision op amps offers very low
input offset voltages with virtually zero drift.
OA1ZHA, OA2ZHA, OA4ZHA are respectively
the single, dual and quad op amp versions, with
pinout compatible with industry standards.
Features
Very high accuracy and stability: offset
voltage 5 µV max at 25 °C, 8 µV over full
temperature range (-40 °C to 125 °C)
Rail-to-rail input and output
Low supply voltage: 1.8 - 5.5 V
Low power consumption: 40 µA max. at 5 V
Gain bandwidth product: 400 kHz
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 to 125 °C
Micro-packages: SC70-5, DFN8 2x2, and
QFN16 3x3
June 2016
The OA1ZHA, OA2ZHA, OA4ZHA series offers
rail-to-rail input and output, excellent
speed/power consumption ratio, and 400 kHz
gain bandwidth product, while consuming less
than 40 µA at 5 V. All devices also feature an
ultra-low input bias current.
The OA1ZHA, OA2ZHA, OA4ZHA family is the
ideal choice for wearable, fitness and healthcare
applications.
DocID025994 Rev 2
This is information on a product in full production.
1/35
www.st.com
Contents
OA1ZHA, OA2ZHA, OA4ZHA
Contents
1
Package pin connections................................................................ 3
2
Absolute maximum ratings and operating conditions ................. 4
3
4
Electrical characteristics ................................................................ 5
Electrical characteristic curves .................................................... 11
5
Application information ................................................................ 17
5.1
6
Operation theory ............................................................................. 17
5.1.1
Time domain ..................................................................................... 17
5.1.2
Frequency domain ............................................................................ 18
5.2
Operating voltages .......................................................................... 19
5.3
Input pin voltage ranges .................................................................. 19
5.4
Rail-to-rail input ............................................................................... 19
5.5
Input offset voltage drift over temperature ....................................... 20
5.6
Rail-to-rail output ............................................................................. 20
5.7
Capacitive load................................................................................ 21
5.8
PCB layout recommendations ......................................................... 21
5.9
Optimized application recommendation .......................................... 22
5.10
EMI rejection ration (EMIRR) .......................................................... 22
5.11
Application examples ...................................................................... 23
5.11.1
Oxygen sensor ................................................................................. 23
5.11.2
Precision instrumentation amplifier .................................................. 24
5.11.3
Low-side current sensing.................................................................. 24
Package information ..................................................................... 26
6.1
SC70-5 (or SOT323-5) package information ................................... 27
6.2
MiniSO8 package information ......................................................... 28
6.3
DFN8 2x2 package information ....................................................... 29
6.4
QFN16 3x3 package information..................................................... 31
7
Ordering information..................................................................... 33
8
Revision history ............................................................................ 34
2/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
1
Package pin connections
Package pin connections
Figure 1: Pin connections for each package (top view)
1.
The exposed pads of the DFN8 2x2 and the QFN16 3x3 can be connected to VCC- or left floating.
DocID025994 Rev 2
3/35
Absolute maximum ratings and operating
conditions
2
OA1ZHA, OA2ZHA, OA4ZHA
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol
Parameter
Value
Supply voltage (1)
VCC
6
Differential input voltage
Vid
Vin
Iin
Tstg
(2)
±VCC
Input voltage
(3)
(VCC-) - 0.2 to (VCC+) + 0.2
Input current
(4)
10
Storage temperature
Tj
-65 to 150
Maximum junction temperature
150
Thermal resistance junction-to-ambient (5) (6)
Rthja
HBM: human body model
SC70-5
205
MiniSO8
190
DFN8 2x2
57
QFN16 3x3
39
(7)
OA1ZHA only
MM: machine model (8)
ESD
Unit
QFN16 3x3
°C
°C/W
kV
300
V
TBD
Latch-up immunity
mA
4
1.5
CDM: charged device model
V
200
kV
mA
Notes:
(1)All
voltage values, except differential voltage, are with respect to network ground terminal.
(2)The
(3)V
differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
CC -
(4)Input
(5)R
th
Vin must not exceed 6 V, Vin must not exceed 6 V.
current must be limited by a resistor in series with the inputs.
are typical values.
(6)Short-circuits
can cause excessive heating and destructive dissipation.
(7)Human
body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin
combinations with other pins floating.
(8)Machine
model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with
no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.
Table 2: Operating conditions
Symbol
Parameter
Value
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
4/35
1.8 to 5.5
DocID025994 Rev 2
(VCC-) - 0.1 to (VCC+) + 0.1
-40 to 125
Unit
V
°C
OA1ZHA, OA2ZHA, OA4ZHA
3
Electrical characteristics
Electrical characteristics
Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
Input offset voltage
ΔVio/ΔT
Input offset voltage drift (1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
Avd
Large signal voltage gain,
Vout = 0.5 V to (VCC - 0.5 V)
VOH
High-level output voltage
VOL
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier),
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C
-40 °C < T < 125 °C
-40 °C < T < 125 °C
10
T = 25 °C
50
-40 °C < T < 125 °C
T = 25 °C
100
-40 °C < T < 125 °C
T = 25 °C
110
-40 °C < T < 125 °C
110
T = 25 °C
118
-40 °C < T < 125 °C
110
30
nV/°C
200
(2)
300
(2)
400
(2)
600
(2)
pA
122
dB
135
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
30
-40 °C < T < 125 °C
mV
70
T = 25 °C
7
-40 °C < T < 125 °C
6
T = 25 °C
5
-40 °C < T < 125 °C
4
T = 25 °C
μV
8
8
mA
7
28
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
Gain margin
SR
(3)
Slew rate
RL = 10 kΩ, CL = 100 pF
kHz
55
Degrees
17
dB
0.17
V/μs
To 0.1 %, Vin = 1 Vp-p,
RL = 10 kΩ, CL = 100 pF
50
μs
ts
Setting time
en
Equivalent input noise
voltage
f = 1 kHz
60
f = 10 kHz
60
Cs
Channel separation
f = 100 Hz
120
tinit
Initialization time
T = 25 °C
50
-40 °C < T < 125 °C
100
DocID025994 Rev 2
nV/√Hz
dB
μs
5/35
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Notes:
(1)See
Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)Guaranteed
(3)Slew
6/35
by design
rate value is calculated as the average between positive and negative slew rates.
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
Input offset voltage
ΔVio/ΔT
Input offset voltage drift (1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
Avd
Large signal voltage gain,
Vout = 0.5 V to (VCC - 0.5 V)
VOH
High-level output voltage
VOL
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier), Vout = VCC/2,
RL > 1 MΩ)
T = 25 °C
-40 °C < T < 125 °C
-40 °C < T < 125 °C
10
T = 25 °C
60
30
200
nV/°C
(2)
300 (2)
-40 °C < T < 125 °C
T = 25 °C
120
400 (2)
pA
600 (2)
-40 °C < T < 125 °C
T = 25 °C
115
-40 °C < T < 125 °C
115
T = 25 °C
118
-40 °C < T < 125 °C
110
128
dB
135
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
15
-40 °C < T < 125 °C
12
T = 25 °C
14
-40 °C < T < 125 °C
10
T = 25 °C
μV
8
mV
18
mA
16
29
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
Gain margin
SR
(3)
Slew rate
RL = 10 kΩ, CL = 100 pF
56
Degrees
19
dB
0.19
V/μs
To 0.1 %, Vin = 1 Vp-p,
RL = 10 kΩ, CL = 100 pF
50
μs
ts
Setting time
en
Equivalent input noise
voltage
f = 1 kHz
40
f = 10 kHz
40
Cs
Channel separation
f = 100 Hz
120
T = 25 °C
50
-40 °C < T < 125 °C
100
tinit
Initialization time
kHz
DocID025994 Rev 2
nV/√Hz
dB
μs
7/35
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Notes:
(1)See
Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)Guaranteed
(3)Slew
8/35
by design
rate value is calculated as the average between positive and negative slew rates.
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristics
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 ° C,
and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
1
5
Unit
DC performance
Vio
Input offset voltage
ΔVio/ΔT
Input offset voltage drift (1)
Iib
Input bias current
(Vout = VCC/2)
Iio
Input offset current
(Vout = VCC/2)
CMR
Common mode rejection
ratio, 20 log (ΔVicm/ΔVio),
Vic = 0 V to VCC,
Vout = VCC/2, RL > 1 MΩ
SVR
Supply voltage rejection
ratio, 20 log (ΔVCC/ΔVio),
VCC = 1.8 V to 5.5 V,
Vout = VCC/2, RL > 1 MΩ
Avd
Large signal voltage gain,
Vout = 0.5 V to
(VCC - 0.5 V)
EMIRR (3)
EMI rejection rate = -20
log (VRFpeak/ΔVio)
VOH
High-level output voltage
VOL
Low-level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per amplifier),
Vout = VCC/2, RL > 1 MΩ)
T = 25 °C
-40 °C < T < 125 °C
-40 °C < T < 125 °C
10
T = 25 °C
70
30
200
nV/°C
(2)
300 (2)
-40 °C < T < 125 °C
T = 25 °C
140
400 (2)
pA
600 (2)
-40 °C < T < 125 °C
T = 25 °C
115
-40 °C < T < 125 °C
115
T = 25 °C
120
-40 °C < T < 125 °C
120
T = 25 °C
120
-40 °C < T < 125 °C
110
136
140
dB
135
VRF = 100 mVp, f = 400 MHz
84
VRF = 100 mVp, f = 900 MHz
87
VRF = 100 mVp, f = 1800 MHz
90
VRF = 100 mVp, f = 2400 MHz
91
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
30
-40 °C < T < 125 °C
70
T = 25 °C
15
-40 °C < T < 125 °C
14
T = 25 °C
14
-40 °C < T < 125 °C
12
T = 25 °C
μV
8
mV
18
mA
17
31
-40 °C < T < 125 °C
40
40
μA
AC performance
GBP
Gain bandwidth product
400
Fu
Unity gain frequency
300
ɸm
Phase margin
Gm
SR
RL = 10 kΩ, CL = 100 pF
kHz
53
Degrees
Gain margin
19
dB
Slew rate (4)
0.19
V/μs
DocID025994 Rev 2
9/35
Electrical characteristics
OA1ZHA, OA2ZHA, OA4ZHA
Symbol
Parameter
Conditions
Min.
Typ.
ts
Setting time
To 0.1 %, Vin = 100 mVp-p,
RL = 10 kΩ, CL = 100 pF
10
en
Equivalent input noise
voltage
f = 1 kHz
37
f = 10 kHz
37
Cs
Channel separation
f = 100 Hz
120
tinit
Initialization time
T = 25 °C
50
-40 °C < T < 125 °C
100
Max.
Notes:
(1)See
Section 5.5: "Input offset voltage drift over temperature". Input offset measurements are performed on x100 gain
configuration. The amplifiers and the gain setting resistors are at the same temperature.
(2)Guaranteed
(3)Tested
(4)Slew
10/35
by design
on SC70-5 package
rate value is calculated as the average between positive and negative slew rates.
DocID025994 Rev 2
Unit
μs
nV/√Hz
dB
μs
OA1ZHA, OA2ZHA, OA4ZHA
4
Electrical characteristic curves
Electrical characteristic curves
Figure 2: Supply current vs. supply voltage
Figure 3: Input offset voltage distribution at VCC = 5 V
Figure 4: Input offset voltage distribution at VCC = 3.3 V
Figure 5: Input offset voltage distribution at VCC = 1.8 V
Figure 6: Vio temperature co-efficient distribution
(-40 °C to 25 °C)
Figure 7: Vio temperature co-efficient distribution
(25 °C to 125 °C)
DocID025994 Rev 2
11/35
Electrical characteristic curves
OA1ZHA, OA2ZHA, OA4ZHA
Figure 8: Input offset voltage vs. supply voltage
Figure 9: Input offset voltage vs. input common-mode
at VCC = 1.8 V
Figure 10: Input offset voltage vs. input common-mode
at VCC = 2.7 V
Figure 11: Input offset voltage vs. input common-mode
at VCC = 5.5 V
Figure 12: Input offset voltage vs. temperature
Figure 13: VOH vs. supply voltage
12/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristic curves
Figure 14: VOL vs. supply voltage
Figure 15: Output current vs. output voltage
at VCC = 1.8 V
Figure 16: Output current vs. output voltage
at VCC = 5.5 V
Figure 17: Input bias current vs. common mode
at VCC = 5 V
Figure 18: Input bias current vs. common-mode
at VCC = 1.8 V
Figure 19: Input bias current vs. temperature
at VCC = 5 V
DocID025994 Rev 2
13/35
Electrical characteristic curves
OA1ZHA, OA2ZHA, OA4ZHA
Figure 20: Bode diagram at VCC = 1.8 V
Figure 21: Bode diagram at VCC = 2.7 V
Figure 22: Bode diagram at VCC = 5.5 V
Figure 23: Open loop gain vs. frequency
Figure 24: Positive slew rate vs. supply voltage
Figure 25: Negative slew rate vs. supply voltage
14/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Electrical characteristic curves
Figure 26: 0.1 Hz to 10 Hz noise
Figure 27: Noise vs. frequency
Figure 28: Noise vs. frequency and temperature
Figure 29: Output overshoot vs. load capacitance
Figure 30: Small signal
Figure 31: Large signal
DocID025994 Rev 2
15/35
Electrical characteristic curves
OA1ZHA, OA2ZHA, OA4ZHA
Figure 32: Positive overvoltage recovery at VCC = 1.8 V
Figure 33: Positive overvoltage recovery at VCC = 5 V
Figure 34: Negative overvoltage recovery
at VCC = 1.8 V
Figure 35: Negative overvoltage recovery
at VCC = 5 V
Figure 36: PSRR vs. frequency
Figure 37: Output impedance vs. frequency
16/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Application information
5
Application information
5.1
Operation theory
The OA1ZHA, OA2ZHA and OA4ZHA are high precision CMOS op amp. They achieve a
low offset drift and no 1/f noise thanks to their chopper architecture. Chopper-stabilized
amps constantly correct low-frequency errors across the inputs of the amplifier.
Chopper-stabilized amplifiers can be explained with respect to:
Time domain
Frequency domain
5.1.1
Time domain
The basis of the chopper amplifier is realized in two steps. These steps are synchronized
thanks to a clock running at 400 kHz.
Figure 38: Block diagram in the time domain (step 1)
Figure 39: Block diagram in the time domain (step 2)
Figure 38: "Block diagram in the time domain (step 1)" shows step 1, the first clock cycle,
where Vio is amplified in the normal way.
Figure 39: "Block diagram in the time domain (step 2)" shows step 2, the second clock
cycle, where Chop1 and Chop2 swap paths. At this time, the Vio is amplified in a reverse
way as compared to step 1.
At the end of these two steps, the average Vio is close to zero.
The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input
offset and is consequently divided by A1(f).
DocID025994 Rev 2
17/35
Application information
OA1ZHA, OA2ZHA, OA4ZHA
In the time domain, the offset part of the output signal before filtering is shown in Figure 40:
"Vio cancellation principle".
Figure 40: Vio cancellation principle
The low pass filter averages the output value resulting in the cancellation of the V io offset.
The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio,
thanks to the chopper technique.
5.1.2
Frequency domain
The frequency domain gives a more accurate vision of chopper-stabilized amplifier
architecture.
Figure 41: Block diagram in the frequency domain
The modulation technique transposes the signal to a higher frequency where there is no 1/f
noise, and demodulate it back after amplification.
1.
2.
3.
4.
According to Figure 41: "Block diagram in the frequency domain", the input signal Vin
is modulated once (Chop1) so all the input signal is transposed to the high frequency
domain.
The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise))
to this modulated signal.
This signal is then demodulated (Chop2), but since the noise and the offset are
modulated only once, they are transposed to the high frequency, leaving the output
signal of the amplifier without any offset and low frequency noise. Consequently, the
input signal is amplified with a very low offset and 1/f noise.
To get rid of the high frequency part of the output signal (which is useless) a low pass
filter is implemented.
To further suppress the remaining ripple down to a desired level, another low pass filter
may be added externally on the output of the OA1ZHA, OA2ZHA and OA4ZHA device.
18/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
5.2
Application information
Operating voltages
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The
parameters are fully specified for 1.8 V, 3.3 V, and 5 V power supplies. However, the
parameters are very stable in the full ςΧΧ range and several characterization curves show
the OA1ZHA, OA2ZHA and OA4ZHA op amp characteristics at 1.8 V and 5.5 V.
Additionally, the main specifications are guaranteed in extended temperature ranges from
-40 to 125 ° C.
5.3
Input pin voltage ranges
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp can operate from 1.8 to 5.5 V. The
parameters are fully specified for 1.8 V, 3.3 V, and have internal ESD diode protection on
the inputs. These diodes are connected between the input and each supply rail to protect
the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become
conductive and excessive current can flow through them. Without limitation this over
current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input
pin, as described in Figure 42: "Input current limitation".
Figure 42: Input current limitation
5.4
Rail-to-rail input
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have a rail-to-rail input, and the input
common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V.
DocID025994 Rev 2
19/35
Application information
5.5
OA1ZHA, OA2ZHA, OA4ZHA
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio
V T – Vio 25 °C
= max io
∆T
T – 25 °C
where T = -40 °C and 125 °C.
The OA1ZHA, OA2ZHA and OA4ZHA CMOS datasheet maximum value is guaranteed by
measurements on a representative sample size ensuring a Cpk (process capability index)
greater than 1.3.
5.6
Rail-to-rail output
The operational amplifier output levels can go close to the rails: to a maximum of 30 mV
above and below the rail when connected to a 10 kΩ resistive load to VCC/2.
20/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
5.7
Application information
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load
capacitance produces gain peaking in the frequency response, with overshoot and ringing
in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an
op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive
large capacitive loads.
Figure 43: "Stability criteria with a serial resistor at VDD = 5 V" and Figure 44: "Stability
criteria with a serial resistor at VDD = 1.8 V" show the serial resistor that must be added to
the output, to make a system stable. Figure 45: "Test configuration for Riso" shows the test
configuration using an isolation resistor, Riso.
Figure 43: Stability criteria with a serial resistor at VDD
=5V
Figure 44: Stability criteria with a serial resistor at VDD
= 1.8 V
Figure 45: Test configuration for Riso
5.8
PCB layout recommendations
Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier,
load, and power supply. The power and ground traces are critical as they must provide
adequate energy and grounding for all circuits. Good practice is to use short and wide PCB
traces to minimize voltage drops and parasitic inductance.
In addition, to minimize parasitic impedance over the entire surface, a multi-via technique
that connects the bottom and top layer ground planes together in many locations is often
used.
The copper traces that connect the output pins to the load and supply pins should be as
wide as possible to minimize trace resistance.
DocID025994 Rev 2
21/35
Application information
5.9
OA1ZHA, OA2ZHA, OA4ZHA
Optimized application recommendation
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp are based on chopper architecture. As
they are switched devices, it is strongly recommended to place a 0.1 µF capacitor as close
as possible to the supply pins.
A good decoupling has several advantages for an application. First, it helps to reduce
electromagnetic interference. Due to the modulation of the chopper, the decoupling
capacitance also helps to reject the small ripple that may appear on the output.
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been optimized for use with 10 kΩ
in the feedback loop. With this, or a higher value of resistance, these devices offer the best
performance.
5.10
EMI rejection ration (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI
immunity of operational amplifiers. An adverse effect that is common to many op amp is a
change in the offset voltage as a result of RF signal rectification.
OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp have been specially designed to minimize
susceptibility to EMIRR and show an extremely good sensitivity. Figure 46: "EMIRR on IN+
pin" shows the EMIRR IN+ of the OA1ZHA, OA2ZHA and OA4ZHA measured from 10 MHz
up to 2.4 GHz.
Figure 46: EMIRR on IN+ pin
22/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Application information
5.11
Application examples
5.11.1
Oxygen sensor
The electrochemical sensor creates a current proportional to the concentration of the gas
being measured. This current is converted into voltage thanks to R resistance. This voltage
is then amplified by OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 47:
"Oxygen sensor principle schematic").
Figure 47: Oxygen sensor principle schematic
The output voltage is calculated using Equation 2:
Equation 2
Vou t = I × R – Vio ×
R2
+1
R1
As the current delivered by the O2 sensor is extremely low, the impact of the V io can
become significant with a traditional operational amplifier. The use of the chopper amplifier
of the OA1ZHA, OA2ZHA and OA4ZHA is perfect for this application.
In addition, using OA1ZHA, OA2ZHA and OA4ZHA op amp for the O2 sensor application
ensures that the measurement of O2 concentration is stable even at different temperature
thanks to a very good ∆Vio/∆T.
DocID025994 Rev 2
23/35
Application information
5.11.2
OA1ZHA, OA2ZHA, OA4ZHA
Precision instrumentation amplifier
The instrumentation amplifier uses three op amp. The circuit, shown in Figure 48:
"Precision instrumentation amplifier schematic", exhibits high input impedance, so that the
source impedance of the connected sensor has no impact on the amplification.
Figure 48: Precision instrumentation amplifier schematic
The gain is set by tuning the Rg resistor. With R1 = R2 and R3 = R4, the output is given by
Equation 3.
Equation 3
The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection
ratio (CMR).
5.11.3
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is
useful for protecting applications. The low-side current sensing method consists of placing
a sense resistor between the load and the circuit ground. The resulting voltage drop is
amplified using OA1ZHA, OA2ZHA and OA4ZHA CMOS op amp (see Figure 49: "Low-side
current sensing schematic").
Figure 49: Low-side current sensing schematic
24/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
Application information
Vout can be expressed as follows:
Equation 4
Vou t = Rshun t × I 1 –
Rg2
Rg2 + Rf2
1+
Rg2 × Rf2
Rf1
Rf1
Rf1
+ Ip
– l n × Rf1 – Vio 1 +
× 1+
Rg2 + Rf2
Rg1
Rg1
Rg1
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 4 can be simplified as follows:
Equation 5
Vout = Rshunt × I
Rf
Rf
– Vio 1 +
+ Rf × I io
Rg
Rg
The main advantage of using the chopper of the OA1ZHA, OA2ZHA and OA4ZHA, for a
low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be
neglected.
Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value,
resulting in lower power dissipation, lower drop in the ground path, and lower cost.
Particular attention must be paid on the matching and precision of Rg1, Rg2, Rf1, and Rf2, to
maximize the accuracy of the measurement.
DocID025994 Rev 2
25/35
Package information
6
OA1ZHA, OA2ZHA, OA4ZHA
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
26/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
6.1
Package information
SC70-5 (or SOT323-5) package information
Figure 50: SC70-5 (or SOT323-5) package outline
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
TOP VIEW
Table 6: SC70-5 (or SOT323-5) mechanical data
Dimensions
Ref.
Millimeters
Min.
A
Typ.
0.80
A1
Inches
Max.
Min.
1.10
0.032
Typ.
0.043
0.10
A2
0.80
b
0.90
Max.
0.004
1.00
0.032
0.035
0.15
0.30
0.006
0.012
c
0.10
0.22
0.004
0.009
D
1.80
2.00
2.20
0.071
0.079
0.087
E
1.80
2.10
2.40
0.071
0.083
0.094
E1
1.15
1.25
1.35
0.045
0.049
0.053
e
0.65
0.025
e1
1.30
0.051
L
0.26
<
0°
0.36
0.46
0.010
8°
0°
DocID025994 Rev 2
0.014
0.039
0.018
8°
27/35
Package information
6.2
OA1ZHA, OA2ZHA, OA4ZHA
MiniSO8 package information
Figure 51: MiniSO8 package outline
Table 7: MiniSO8 mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
0
Min.
Typ.
A2
0.75
b
0.22
c
0.08
D
2.80
E
E1
0.043
0
0.95
0.030
0.40
0.009
0.016
0.23
0.003
0.009
3.00
3.20
0.11
0.118
0.126
4.65
4.90
5.15
0.183
0.193
0.203
2.80
3.00
3.10
0.11
0.118
0.122
0.85
0.65
0.40
0.60
0.006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
Max.
0.15
e
28/35
Max.
1.1
A1
L
Inches
8°
0.10
DocID025994 Rev 2
0°
0.031
8°
0.004
OA1ZHA, OA2ZHA, OA4ZHA
6.3
Package information
DFN8 2x2 package information
Figure 52: DFN8 2x2 package outline
Table 8: DFN8 2x2 mechanical data
Dimensions
Ref.
A
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
0.51
0.55
0.60
0.020
0.022
0.024
A1
0.05
A3
0.002
0.15
0.006
b
0.18
0.25
0.30
0.007
0.010
0.012
D
1.85
2.00
2.15
0.073
0.079
0.085
D2
1.45
1.60
1.70
0.057
0.063
0.067
E
1.85
2.00
2.15
0.073
0.079
0.085
E2
0.75
0.90
1.00
0.030
0.035
0.039
e
0.50
0.020
L
0.425
0.017
ddd
0.08
0.003
DocID025994 Rev 2
29/35
Package information
OA1ZHA, OA2ZHA, OA4ZHA
Figure 53: DFN8 2x2 recommended footprint
30/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
6.4
Package information
QFN16 3x3 package information
Figure 54: QFN16 3x3 package outline
DocID025994 Rev 2
31/35
Package information
OA1ZHA, OA2ZHA, OA4ZHA
Table 9: QFN16 3x3 mechanical data
Dimensions
Ref.
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0
0.05
0
A3
0.20
b
0.18
D
2.90
D2
1.50
E
2.90
E2
1.50
e
L
3.00
3.00
0.008
0.30
0.007
3.10
0.114
1.80
0.059
3.10
0.114
1.80
0.059
0.50
0.30
0.012
0.118
0.122
0.071
0.118
0.122
0.071
0.020
0.50
0.012
Figure 55: QFN16 3x3 recommended footprint
32/35
0.002
DocID025994 Rev 2
0.020
OA1ZHA, OA2ZHA, OA4ZHA
7
Ordering information
Ordering information
Table 10: Order codes
Order code
Temperature range
Package
Packaging
Marking
OA1ZHA22C
SC70-5
K44
OA2ZHA34S
MiniSO8
K208
OA2ZHA22Q
OA4ZHA33Q
-40 to 125 °C
DFN8 2x2
QFN16 3x3
DocID025994 Rev 2
Tape and reel
K33
K193
33/35
Revision history
8
OA1ZHA, OA2ZHA, OA4ZHA
Revision history
Table 11: Document revision history
Date
Revision
04-Mar-2014
1
30-Jun-2016
2
Changes
Initial release.
Updated document layout
Removed “Device summary” table from cover page and added
information to Table 10: "Order codes".
Section 6.4: "QFN16 3x3 package information": added recommended
footprint.
Added Section 7: "Ordering information"
Table 10: "Order codes": updated marking of MiniSO8 package.
34/35
DocID025994 Rev 2
OA1ZHA, OA2ZHA, OA4ZHA
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
DocID025994 Rev 2
35/35