74ALVC162334A 16-bit registered driver with inverted register enable and 30 Ω termination resistors (3-state) Rev. 03 — 13 December 2006 Product data sheet 1. General description The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop. The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output stages. When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2. Features n n n n n n n n n n Wide supply voltage range of 1.2 V to 3.6 V Complies with JEDEC standard 8-1A CMOS low power consumption Direct interface with TTL levels Current drive: ±24 mA at 3.0 V MULTIBYTE flow-through standard pinout architecture Low inductance multiple VCC and GND pins for minimum noise and ground bounce Output drive capability 50 Ω transmission lines at 85 °C Integrated 30 Ω termination resistors Input diodes to accommodate strong drivers 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 3. Quick reference data Table 1. Quick reference data VCC = 3.3 V ± 0.3 V; GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF (see Figure 11). Symbol Parameter Conditions Min Typ[1] Max Unit tPHL HIGH-to-LOW propagation delay An to Yn; Figure 5 1.0 2.8 4.3 ns LOW-to-HIGH propagation delay tPLH fmax maximum input clock frequency Ci input capacitance Cio input/output capacitance power dissipation capacitance CPD LE to Yn; Figure 6 1.3 2.8 4.4 ns CP to Yn; Figure 8 1.4 3.2 4.9 ns An to Yn; Figure 5 1.0 2.8 4.3 ns LE to Yn; Figure 6 1.3 2.8 4.4 ns CP to Yn; Figure 8 1.4 3.2 4.9 ns Figure 8 150 240 - MHz - 4.0 - pF - 8.0 - pF transparent mode; output enabled - 10 - pF transparent mode; output disabled - 3 - pF clocked mode; output enabled - 21 - pF clocked mode; output disabled - 15 - pF per buffer; VI = GND to VCC [1] All typical values are at Tamb = 25 °C. [2] CPD is used to determine the dynamic power dissipation (PD) in µW. PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo), where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of outputs. [2] 4. Ordering information Table 2. Ordering information Type number 74ALVC162334ADGG Temperature range Package Name Description Version −40 °C to +85 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 2 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 5. Functional diagram 1 OE 48 CP 25 LE Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 EN1 2C3 C3 G2 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1 1 3D 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 002aac723 Fig 1. Logic symbol (IEEE/IEC) OE CP LE A1 D LE CP Y1 to the 15 other channels 002aac724 Fig 2. Logic diagram VCC A1 002aac725 Fig 3. Typical input (data or control) 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 3 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 6. Pinning information 6.1 Pinning OE 1 48 CP Y1 2 47 A1 Y2 3 46 A2 GND 4 45 GND Y3 5 44 A3 Y4 6 43 A4 VCC 7 Y5 8 42 VCC 41 A5 Y6 9 40 A6 GND 10 39 GND Y7 11 Y8 12 Y9 13 38 A7 74ALVC162334ADGG 37 A8 36 A9 Y10 14 35 A10 GND 15 34 GND Y11 16 33 A11 Y12 17 32 A12 VCC 18 Y13 19 31 VCC 30 A13 Y14 20 29 A14 GND 21 28 GND Y15 22 27 A15 Y16 23 26 A16 n.c. 24 25 LE 002aac722 Fig 4. Pin configuration for TSSOP48 6.2 Pin description Table 3. Pin description Symbol Pin Description OE 1 output enable input (active LOW) Y1 2 data output 1 Y2 3 data output 2 GND 4, 10, 15, 21, 28, 34, 39, 45 ground supply (0 V) Y3 5 data output 3 Y4 6 data output 4 VCC 7, 18, 31, 42 positive supply voltage Y5 8 data output 5 Y6 9 data output 6 Y7 11 data output 7 Y8 12 data output 8 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 4 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) Table 3. Pin description …continued Symbol Pin Description Y9 13 data output 9 Y10 14 data output 10 Y11 16 data output 11 Y12 17 data output 12 Y13 19 data output 13 Y14 20 data output 14 Y15 22 data output 15 Y16 23 data output 16 n.c. 24 not connected LE 25 latch enable input (active LOW) A16 26 data input 16 A15 27 data input 15 A14 29 data input 14 A13 30 data input 13 A12 32 data input 12 A11 33 data input 11 A10 35 data input 10 A9 36 data input 9 A8 37 data input 8 A7 38 data input 7 A6 40 data input 6 A5 41 data input 5 A4 43 data input 4 A3 44 data input 3 A2 46 data input 2 A1 47 data input 1 CP 48 clock input 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 5 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 7. Functional description Refer to Figure 1 “Logic symbol (IEEE/IEC)” and Figure 2 “Logic diagram”. 7.1 Function selection Table 4. Function selection H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state; ↑ = LOW to HIGH level transition. Inputs Outputs OE LE CP An Yn H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H H L H H X Y0[1] L H L X Y0[2] [1] Output level before the indicated steady-state input conditions were established, provided that CP is HIGH before LE goes LOW. [2] Output level before the indicated steady-state input conditions were established. 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 6 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions Min VI < 0 V [1] VO > VCC or VO < 0 V [1] output voltage VO IO(sink/source) output sink or source current VO = 0 V to VCC Max Unit −0.5 +4.6 V - −50 mA −0.5 +4.6 V - ±50 mA −0.5 VCC + 0.5 V - ±50 mA ICC supply current - ±100 mA IGND ground current - ±100 mA Tstg storage temperature Ptot/pack total power dissipation per package [1] for temperature range −40 °C to +125 °C; above +55 °C derate linearly with 8 mW/K −65 +150 °C - 600 mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage 2.5 V range for maximum speed performance at 30 pF output load 2.3 - 2.7 V 3.3 V range for maximum speed performance at 50 pF output load 3.0 - 3.6 V for low-voltage applications 1.2 - 3.6 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature operating in free-air −40 - +85 °C tr rise time VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V tf fall time VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 7 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 10. Static characteristics Table 7. Static characteristics Tamb = −40 °C to +85 °C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V VCC = 2.3 V to 3.6 V; IO = −100 µA VCC − 0.2 VCC - V VCC = 2.3 V; IO = −4 mA VCC − 0.4 VCC − 0.11 - V VCC = 2.3 V; IO = −6 mA VCC − 0.6 VCC − 0.17 - V VCC = 2.7 V; IO = −4 mA VCC − 0.5 VCC − 0.09 - V VCC = 2.7 V; IO = −8 mA VCC − 0.7 VCC − 0.19 - V VCC = 3.0 V; IO = −6 mA VCC − 0.6 VCC − 0.13 - V VCC = 3.0 V; IO = −12 mA VCC − 1.0 VCC − 0.27 - V VCC = 2.3 V to 3.6 V; IO = 100 µA - GND 0.20 V VCC = 2.3 V; IO = 4 mA - 0.07 0.40 V VCC = 2.3 V; IO = 6 mA - 0.11 0.55 V VCC = 2.7 V; IO = 4 mA - 0.06 0.40 V VCC = 2.7 V; IO = 8 mA - 0.13 0.60 V VCC = 3.0 V; IO = 6 mA - 0.09 0.55 V VCC = 3.0 V; IO = 12 mA - 0.19 0.80 V LOW-level input voltage VIL VOH HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VOL VI = VIH or VIL ILI input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 µA IOZ off-state output current 3-state; VCC = 2.3 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 µA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 mA - 0.2 40 µA ∆ICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 mA - 150 750 µA Ci input capacitance - 4.0 - pF Cio input/output capacitance - 8.0 - pF - 10 - pF power dissipation capacitance CPD per buffer; VI = GND to VCC transparent mode; output enabled transparent mode; output disabled - 3 - pF clocked mode; output enabled - 21 - pF clocked mode; output disabled - 15 - pF [1] All typical values are at Tamb = 25 °C. [2] CPD is used to determine the dynamic power dissipation (PD) in µW. PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo), where: fi = input frequency in MHz; 74ALVC162334A_3 Product data sheet [2] © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 8 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of outputs. 11. Dynamic characteristics Table 8. Dynamic characteristics for VCC = 2.3 V to 2.7 V range VCC = 2.3 V to 2.7 V; GND = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF (see Figure 11). Symbol Parameter Conditions Min Typ[1] Max Unit tPHL HIGH-to-LOW propagation delay An to Yn; Figure 5 1.0 3.5 5.0 ns LE to Yn; Figure 6 1.3 3.5 5.0 ns LOW-to-HIGH propagation delay tPLH CP to Yn; Figure 8 1.4 3.7 5.4 ns An to Yn; Figure 5 1.0 3.5 5.0 ns LE to Yn; Figure 6 1.3 3.5 5.0 ns CP to Yn; Figure 8 1.4 3.7 5.4 ns tPZH OFF-state to HIGH propagation delay OE to Yn; Figure 10 [2] 1.4 3.5 5.0 ns tPZL OFF-state to LOW propagation delay OE to Yn; Figure 10 [2] 1.4 3.5 5.0 ns HIGH to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.0 2.8 4.5 ns tPLZ LOW to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.0 2.8 4.5 ns tw pulse width CP HIGH or LOW; Figure 8 3.3 1.0 - ns LE HIGH; Figure 6 3.3 0.7 - ns An to CP; Figure 9 1.0 - - ns An to LE; Figure 7 1.5 - - ns An to CP; Figure 9 0.4 0.4 - ns An to LE; Figure 7 1.4 0.4 - ns Figure 8 150 190 - MHz Conditions Min Typ[1] Max Unit tPHZ set-up time tsu hold time th maximum input clock frequency fmax [1] All typical values are at VCC = 2.5 V and Tamb = 25 °C. [2] 3-state output enable time. [3] 3-state output disable time. Table 9. Dynamic characteristics for VCC = 2.7 V VCC = 2.7 V; GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF (see Figure 11). Symbol Parameter tPHL HIGH-to-LOW propagation delay tPLH LOW-to-HIGH propagation delay An to Yn; Figure 5 1.0 3.3 4.6 ns LE to Yn; Figure 6 1.3 3.4 4.8 ns CP to Yn; Figure 8 1.4 3.8 6.2 ns An to Yn; Figure 5 1.0 3.3 4.6 ns LE to Yn; Figure 6 1.3 3.4 4.8 ns CP to Yn; Figure 8 1.4 3.8 6.2 ns OFF-state to HIGH propagation delay OE to Yn; Figure 10 [2] 1.1 3.7 6.0 ns OFF-state to LOW propagation delay OE to Yn; Figure 10 [2] 1.1 3.7 6.0 ns tPHZ HIGH to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.3 3.5 4.9 ns tPLZ LOW to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.3 3.5 4.9 ns tPZH tPZL 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 9 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) Table 9. Dynamic characteristics for VCC = 2.7 V …continued VCC = 2.7 V; GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF (see Figure 11). Symbol Parameter Conditions Min Typ[1] Max Unit tw pulse width CP HIGH or LOW; Figure 8 3.3 1.2 - ns LE HIGH; Figure 6 3.3 0.6 - ns An to CP; Figure 9 1.0 - - ns An to LE; Figure 7 1.5 - - ns An to CP; Figure 9 0.6 0.3 - ns An to LE; Figure 7 1.7 0.4 - ns Figure 8 150 190 - MHz set-up time tsu hold time th maximum input clock frequency fmax [1] All typical values are measured at Tamb = 25 °C. [2] 3-state output enable time. [3] 3-state output disable time. Table 10. Dynamic characteristics for VCC = 3.0 V to 3.6 V range VCC = 3.3 V ± 0.3 V; GND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF (see Figure 11). Symbol Parameter Conditions Min Typ[1] Max Unit tPHL HIGH-to-LOW propagation delay An to Yn; Figure 5 1.0 2.8 4.3 ns LE to Yn; Figure 6 1.3 2.8 4.4 ns LOW-to-HIGH propagation delay tPLH CP to Yn; Figure 8 1.4 3.2 4.9 ns An to Yn; Figure 5 1.0 2.8 4.3 ns LE to Yn; Figure 6 1.3 2.8 4.4 ns CP to Yn; Figure 8 1.4 3.2 4.9 ns tPZH OFF-state to HIGH propagation delay OE to Yn; Figure 10 [2] 1.1 2.4 4.5 ns tPZL OFF-state to LOW propagation delay OE to Yn; Figure 10 [2] 1.1 2.4 4.5 ns HIGH to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.3 2.4 4.8 ns tPLZ LOW to OFF-state propagation delay OE to Yn; Figure 10 [3] 1.3 2.4 4.8 ns tw pulse width CP HIGH or LOW; Figure 8 3.3 0.7 - ns LE HIGH; Figure 6 3.3 0.6 - ns An to CP; Figure 9 1.0 - - ns An to LE; Figure 7 1.5 - - ns An to CP; Figure 9 0.9 0.3 - ns An to LE; Figure 7 1.4 0.4 - ns Figure 8 150 240 - MHz tPHZ set-up time tsu hold time th maximum input clock frequency fmax [1] All typical values are measured at VCC = 3.3 V, Tamb = 25 °C. [2] 3-state output enable time. [3] 3-state output disable time. 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 10 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 11.1 AC waveforms VCC = 3.0 V to 3.6 V and VCC = 2.7 V range: VM = 1.5 V; VX = VOL + 0.3 V; VY = VOH − 0.3 V; VI = 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 2.3 V to 2.7 V and VCC < 2.3 V range: VM = 0.5 V; VX = VOL + 0.15 V; VY = VOH − 0.15 V; VI = VCC. VOL and VOH are the typical output voltage drop that occur with the output load. VI VI An input LE input VM VM GND tPHL VM GND tw tPLH VOH VOH VM Yn output VM Yn output tPLH tPHL VOL 002aac727 VOL 002aac726 Fig 5. Input (An) to output (Yn) propagation delay Fig 6. LE input pulse width, LE input to Yn output propagation delays 1 / fmax VI An input VM CP input VM th tsu GND th tsu LE input GND tPLH tPHL VOH VM Yn output VM VM tw VI VM VI VM VOL 002aac729 GND 002aac728 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 7. Data set-up and hold times, An input to LE input Fig 8. CP to Yn propagation delays, clock pulse width, and maximum clock frequency VI OE input CP input th tsu GND th VI An input Yn output GND VI GND VOH tPZL tPLZ VM tsu VM VCC output LOW-to-OFF OFF-to-LOW VX tPHZ output HIGH-to-OFF OFF-to-HIGH VOL tPZH VOH VY VM GND outputs enabled VOL 002aac730 VM outputs disabled outputs enabled 002aac731 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Data set-up and hold times, An input to CP input Fig 10. 3-state enable and disable times 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 11 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 12. Test information S1 VCC PULSE GENERATOR VI RL 500 Ω VO 2 × VCC open GND DUT RT CL RL 500 Ω 002aac732 Test data are given in Table 11. RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to Zo of pulse generators. Fig 11. Test circuitry for switching times Table 11. Test data Supply voltage Input VCC VI Load Switch S1 tr, tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND (0 V) 2 × VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND (0 V) 2 × VCC 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND (0 V) 2 × VCC 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 12 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 13. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT362-1 (TSSOP48) 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 13 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 14 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 15 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 14. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor-Transistor Logic 16. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC162334A_3 20061213 Product data sheet - 74ALVC162334A_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. • Section 1 “General description”, 1st paragraph, 2nd sentence: changed “OE” to “OE” Table 2 “Ordering information”: changed (SOT364-1; TSSOP56) package to (SOT362-1; TSSOP48) package Table 3 “Pin description” corrected: – changed “Y1 to Y18” to (Y1 to Y16, noted separately) – GND pins: added pins 4 and 39 – VCC pins changed from “7, 22, 35, 50” to “7, 18, 31, 42” – changed “A1 to A18” to (A1 to A16, noted separately) • Figure 1 “Logic symbol (IEEE/IEC)”: corrected pin number for Y15 from “21” to “22” 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 16 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) Table 15. Revision history …continued Document ID Modifications: (continued) Release date • • Data sheet status Change notice Supersedes Figure 1 “Logic symbol (IEEE/IEC)”: corrected pin number for Y15 from “21” to “22” Figure 2 “Logic diagram”: – changed signal “A0” to “A1” – changed signal “Y0” to “Y1” – changed “to the 17 other channels” to “to the 15 other channels” • Table 5 “Limiting values” (title changed from “Absolute maximum ratings”): – parameter definition of IIK changed from “DC input diode current” to “input clamping current” – parameter definition of IOK changed from “DC output diode current” to “output clamping current” – symbol “IO” (DC output source or sink current) changed to “IO(sink/source)” (output sink or source current) – removed Ptot/pack information for SSOP package • Table 7 “Static characteristics” (title changed from “DC electrical characteristics”): – changed symbol “II” to “ILI” – parameter definition of IOZ changed from “3-State output OFF-state current” to “OFF-state output current” (moved “3-state” to Conditions column) – parameter definition of ICC changed from “quiescent supply current” to “supply current” – parameter definition of ∆ICC changed from “additional quiescent supply current” to “additional supply current” – added Ci, Cio, and CPD parameters • Section 11 “Dynamic characteristics”: table “AC characteristics for VCC = 3.0 V to 3.6 V range and VCC = 2.7 V” separated into 2 tables • Section 11.1 “AC waveforms”: – 1st paragraph, 2nd line: changed “VM = 1.5 VCC” to “VM = 1.5 V” – removed statement “VM = 0.5VCC at VCC = 2.3 V to 2.7 V.” from Figure 5, Figure 6, Figure 7, Figure 8, Figure 9 and Figure 10 as redundant (depends on voltage as stated above these figures) • Section 13 “Package outline”: replaced SOT364-1 (TSSOP56) package outline drawing with Figure 12 “Package outline SOT362-1 (TSSOP48)” 74ALVC162334A_2 (9397 750 07246) 20000620 Product specification 853-2197 23931 74ALVC162334A_1 74ALVC162334A_1 (9397 750 06963) 20000314 Product specification 853-2197 23314 - 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 17 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74ALVC162334A_3 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 03 — 13 December 2006 18 of 19 74ALVC162334A NXP Semiconductors 16-bit registered driver (3-state) 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Function selection. . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 December 2006 Document identifier: 74ALVC162334A_3