ETC 80386SX

Intel386™ SXSA
EMBEDDED MICROPROCESSOR
■ Static Intel386™ CPU Core
■ Integrated Memory Management Unit
— Low Power Consumption
— Operating Power Supply
4.5V to 5.5V - 25 and 33 MHz
4.75V to 5.25V - 40 MHz
— Operating Frequency
SA-40 = 40 MHz
SA-33 = 33 MHz
SA-25 = 25 MHz
■ Clock Freeze Mode Allows Clock
Stopping at Any Time
(MMU)
— Virtual Memory Support
— Optional On-chip Paging
— 4 Levels of Hardware-Enforced
Protection
— MMU Fully Compatible with 80286
and Intel386 DX Processors
■ Virtual 8086 Mode Allows Execution of
8086 Software in a Protected and Paged
System
■ Full 32-bit Internal Architecture
■ Large Uniform Address Space
— 8-, 16-, 32-bit Data Types
— 8 General Purpose 32-bit Registers
■ Runs Intel386 Architecture Software in
a Cost-effective, 16-bit Hardware
Environment
— Runs Same Applications and
Operating Systems as the Intel386
SX and Intel386 DX Processors
— Object Code Compatible with 8086,
80186, 80286, and Intel386
Processors
■ TTL-Compatible Inputs
— 16 Megabyte Physical
— 64 Terabyte Virtual
— 4 Gigabyte Maximum Segment Size
■ Numerics Support Intel387™ SX and
Intel387™ SL Math Coprocessors
■ On-chip Debugging Support Including
Breakpoint Registers
■ Complete System Development
Support
■ High Speed CHMOS Technology
■ 100-Pin Plastic Quad Flatpack Package
■ High-performance 16-bit Data Bus
— Two-clock Bus Cycles
— Address Pipelining Allows Use of
Slower, Inexpensive Memories
The Intel386™ SXSA embedded microprocessor is a 5-volt, 32-bit, fully static CPU with a 16-bit external data
bus and a 24-bit external address bus. The Intel386 SXSA CPU brings the vast software library of the Intel386
architecture to embedded systems. It provides the performance benefits of 32-bit programming with the cost
savings associated with 16-bit hardware systems.
The Intel386 SXSA microprocessor is manufactured on Intel’s 0.8-micron CHMOS V process. This process
provides high performance and low power consumption for power-sensitive applications. Figure 3 and Figure 4
illustrate the flexibility of low power devices with respect to temperature and frequency relationships.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability
whatsoever, including infringe-ment of any patent or copyright, for sale and use of Intel products except as
provided in Intel’s Terms and Conditions of Sale for such products. Information contained herein supersedes
previously published specifications on these devices from Intel.
Copyright© INTEL Corporation, 2002
June 2002
Order Number: 272419-004
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Segmentation Unit
Descriptor 32
Register
Page Cache
Limit and
Attribute
PLA
Control and
Attribute
PLA
Bus
Bus
Status
Multiply/ Flags
Divide
Register
File
ALU
ALU
Control
Control
ROM
Control
Linear Address
Displacement
Internal Control Bus
Decode
and
Sequencing
HOLD,
RESET
INTR, NMI
ERROR#
BUSY#,HLDA
27
Protection
Test Unit
Barrel
Shifter/
Adder
Request
Prioritizer
Control
32
Effective Address Bus
Adder
Physical Address Bus
Effective Address Bus
Bus Control
3-Input
Adder
Instruction
Decoder
Code
3-Decoded Stream
Instruction
Queue
32
Instruction
Predecode
Code Fetch/Page Table Fetch
32
Paging Unit
Address
Driver
32
Prefetcher/
Limit
Checker
Pipeline/
Bus Size
Control
MUX/
Transceivers
BLE#, BHE#
A23:1
M/IO#, D/C#
W/R#, LOCK#
ADS#, NA#
READY#
D15:0
16-Byte
Code
Queue
Instruction
Prefetch
32
Dedicated ALU Bus
A2298-01
Figure 1. Intel386™ SXSA Microprocessor Block Diagram
2
Intel386™ SXSA EMBEDDED MICROPROCESSOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TOP VIEW
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A20
A19
A18
A17
Vcc
A16
Vcc
Vss
Vss
A15
A14
A13
Vss
A12
A11
A10
A9
A8
Vcc
A7
A6
A5
A4
A3
A2
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
D0
Vss
HLDA
HOLD
Vss
NA#
READY#
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
CLK2
ADS#
BLE#
A1
BHE#
NC
Vcc
Vss
M/IO#
D/C#
W/R#
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D1
D2
Vss
Vcc
D3
D4
D5
D6
D7
Vcc
D8
D9
D10
D11
D12
Vss
Vcc
D13
D14
D15
A23
A22
Vss
Vss
A21
PIN ASSIGNMENT
LOCK#
NC
FLT#
NC
NC
NC
Vcc
RESET
BUSY#
Vss
ERROR#
PEREQ
NMI
Vcc
INTR
Vss
Vcc
NC
NC
NC
NC
NC
Vcc
Vss
Vss
1.0
NOTE:
NC = No Connection
A2297-0A
Figure 2. Intel386™ SXSA Microprocessor Pin Assignment (PQFP)
3
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Table 1. Pin Assignment
Pin
4
Symbol
1
D0
2
VSS
3
Pin
Symbol
26
LOCK#
27
NC
HLDA
28
4
HOLD
5
VSS
6
Pin
Symbol
Pin
Symbol
51
A2
76
A21
52
A3
77
VSS
FLT#
53
A4
78
VSS
29
NC
54
A5
79
A22
30
NC
55
A6
80
A23
NA#
31
NC
56
A7
81
D15
7
READY#
32
VCC
57
VCC
82
D14
8
VCC
33
RESET
58
A8
83
D13
9
VCC
34
BUSY#
59
A9
84
VCC
10
VCC
35
VSS
60
A10
85
VSS
11
VSS
36
ERROR#
61
A11
86
D12
12
VSS
37
PEREQ
62
A12
87
D11
13
VSS
38
NMI
63
VSS
88
D10
14
VSS
39
VCC
64
A13
89
D9
15
CLK2
40
INTR
65
A14
90
D8
16
ADS#
41
VSS
66
A15
91
VCC
17
BLE#
42
VCC
67
VSS
92
D7
18
A1
43
NC
68
VSS
93
D6
19
BHE#
44
NC
69
VCC
94
D5
20
NC
45
NC
70
A16
95
D4
21
VCC
46
NC
71
VCC
96
D3
22
VSS
47
NC
72
A17
97
VCC
23
M/IO#
48
VCC
73
A18
98
VSS
24
D/C#
49
VSS
74
A19
99
D2
25
W/R#
50
VSS
75
A20
100
D1
Intel386™ SXSA EMBEDDED MICROPROCESSOR
2.0
PIN DESCRIPTIONS
Table 2 lists the Intel386 SXSA microprocessor pin descriptions. The following definitions are used in the pin
descriptions:
#
I
O
I/O
P
G
The named signal is active low.
Input signal.
Output signal.
Input and output signal.
Power pin.
Ground pin.
Table 2. Pin Descriptions
Symbol
Type
Pin
Name and Function
A23:1
O
80–79, 76–72,
70, 66–64
62–58, 56–51,
18
Address Bus outputs physical memory or port I/O addresses.
ADS#
O
16
Address Status indicates that the processor is driving a valid
bus-cycle definition and address onto its pins (W/R#, D/C#,
M/IO#, BHE#, BLE#, and A23:1).
BHE#
O
19
Byte High Enable indicates that the processor is transferring
a high data byte.
BLE#
O
17
Byte Low Enable indicates that the processor is transferring
a low data byte.
BUSY#
I
34
Busy indicates that the math coprocessor is busy.
CLK2
I
15
CLK2 provides the fundamental timing for the device.
D/C#
O
24
Data/Control indicates whether the current bus cycle is a
data cycle (memory or I/O) or a control cycle (interrupt
acknowledge, halt, or code fetch). When D/C# is high, the bus
cycle is a data cycle; when D/C# is low, the bus cycle is a control cycle.
D15:0
I/O
81–83, 86–90,
92–96, 99–100,
1
Data Bus inputs data during memory read, I/O read, and
interrupt acknowledge cycles and outputs data during memory and I/O write cycles.
ERROR#
I
36
Error indicates that the math coprocessor has an error condition.
FLT#
I
28
Float forces all bidirectional and output signals, including
HLDA, to a high-impedance state.
HLDA
O
3
Bus Hold Acknowledge indicates that the CPU has surrendered control of its local bus to another bus master.
HOLD
I
4
Bus Hold Request allows another bus master to request control of the local bus.
INTR
I
40
Interrupt Request is a maskable input that causes the CPU
to suspend execution of the current program and then execute an interrupt acknowledge cycle.
5
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Table 2. Pin Descriptions (Continued)
Symbol
Type
Pin
Name and Function
LOCK#
O
26
Bus Lock prevents other system bus masters from gaining
control of the system bus while it is active (low).
M/IO#
O
23
Memory/IO indicates whether the current bus cycle is a memory cycle or an input/output cycle. When M/IO# is high, the
bus cycle is a memory cycle; when M/IO# is low, the bus cycle
is an I/O cycle.
NA#
I
NC
6
6
Next Address requests address pipelining.
20, 27, 29–31,
43–47
No Connection should always be left unconnected. Connecting a NC pin may cause the processor to malfunction or cause
your application to be incompatible with future steppings of
the device.
NMI
I
38
Nonmaskable Interrupt Request is a nonmaskable input
that causes the CPU to suspend execution of the current program and execute an interrupt acknowledge function.
PEREQ
I
37
Processor Extension Request indicates that the math
coprocessor has data to transfer to the processor.
READY#
I
7
Bus Ready indicates that the current bus cycle is finished and
the external device is ready to accept more data from the processor.
RESET
I
33
Reset suspends any operation in progress and places the
processor into a known reset state.
W/R#
O
25
Write/Read indicates whether the current bus cycle is a write
cycle or a read cycle. When W/R# is high, the bus cycle is a
write cycle; when W/R# is low, it is a read cycle.
VCC
P
8–10, 21, 32,
39, 42, 48, 57,
69, 71, 84, 91,
97
System Power provides the nominal DC supply input.
VSS
G
2, 5, 11–14, 22
35, 41, 49–50,
63, 67–68,
77–78, 85, 98
System Ground provides the 0V connection from which all
inputs and outputs are measured.
Intel386™ SXSA EMBEDDED MICROPROCESSOR
3.0
DESIGN CONSIDERATIONS
This section describes the Static Intel386 SXSA
microprocessor instruction set, component and
revision identifier, and package thermal specifications.
3.1.
Instruction Set
The Static Intel386 SXSA microprocessor uses the
same instruction set as the dynamic Intel386 SX
microprocessor. However, the Static Intel386 SXSA
microprocessor requires more clock cycles than the
dynamic Intel386 SX microprocessor to execute
some instructions. Table 4 lists these instructions
and the Static Intel386 SXSA microprocessor
execution times. For the equivalent dynamic
Intel386 SX microprocessor execution times, refer
to the “Instruction Set Clock Count Summary” table
in the Intel386™ SX Microprocessor data sheet
(order number 240187).
3.2.
Component and Revision
Identifier
To assist users, the microprocessor holds a
component identifier and revision identifier in its DX
register after reset. The upper 8 bits of DX hold the
component identifier, 23H. (The lower nibble, 3H,
identifies the Intel386 architecture, while the upper
nibble, 2H, identifies the second member of the
Intel386 microprocessor family.)
The lower 8 bits of DX hold the revision level
identifier. The revision identifier will, in general,
chronologically track those component steppings
that are intended to have certain improvements or
distinction from previous steppings. The revision
identifier will track that of the Intel386 CPU
whenever possible. However, the revision identifier
value is not guaranteed to change with every
stepping revision or to follow a completely uniform
numerical sequence, depending on the type or
intent of the revision or the manufacturing materials
required to be changed. Intel has sole discretion
over these characteristics of the component. The
initial revision identifier for the Static Intel386 SXSA
microprocessor is 09H.
3.3.
Package Thermal Specifications
Static Intel386 SXSA microprocessor is specified
for operation with case temperature (TCASE) as
specified in the “DC SPECIFICATIONS” on page 9.
The case temperature can be measured in any
environment to determine whether the microprocessor is within the specified operating range. The
case temperature should be measured at the center
of the top surface opposite the pins.
An increase in the ambient temperature (TA) causes
a proportional increase in the case temperature
(TCASE) and the junction temperature (TJ). See
Figures 3 and Figures 4 for case and ambient
temperature relationships to frequency. A packaged
device produces thermal resistance between
junction and case temperatures (θJC) and between
junction and ambient temperatures (θJA). The
relationships between the temperature and thermal
resistance parameters are expressed by these
equations (P = power dissipated as heat = VCC ×
ICC):
1.
TJ = TCASE + P × θJC
2.
TA = TJ – P × θJA
3.
TCASE = TA + P × [θJA – θJC]
A safe operating temperature can be calculated
from equation 1 by using the maximum safe TJ of
115° C, the maximum power drawn by the chip in
the specific design, and the θJC value from Table 3.
The θJA value depends on the airflow (measured at
the top of the chip) provided by the system ventilation. The θJA values are given for reference only
and are not guaranteed.
Table 3. Thermal Resistances (0°C/W) θJA, θJC
Pkg
θJC
100 PQFP
5.1
θJA versus Airflow (ft/min)
0
100
200
46.0
44.8
41.2
7
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Table 4. Intel386™ SXSA Microprocessor Instruction Execution Times (in Clock Counts)
Clock Count
Instruction
Virtual 8086 Mode
(Note 1)
POPA
Protected Virtual
Address Mode
(Note 3)
Real Address Mode
or Virtual 8086 Mode
28
35
27
28
14
15
7/29
8/29
OUT:
Fixed Port
Variable Port
27
28
14
15
7/29
9/29
INS
30
17
9/32
OUTS
31
18
10/33
REP INS
31+6n (Note 2)
17+6n (Note 2)
10+6n/32+6n (Note 2)
REP OUTS
30+8n (Note 2)
16+8n (Note 2)
10+8n/31+8n (Note 2)
HLT
7
7
MOV C0, reg
10
10
IN:
Fixed Port
Variable Port
NOTES:
1. The clock count values in this column apply if I/O permission allows I/O to the port in virtual 8086 mode. If the I/O bit map denies permission,
exception fault 13 occurs; see clock counts for the INT 3 instruction in the “Instruction Set Clock Count Summary” table in the Intel386™ SX
Microprocessor data sheet (order number 240187).
2. n = the number of times repeated.
3. When two clock counts are listed, the smaller value refers to a register operand and the larger value refers to a memory operand.
8
Intel386™ SXSA EMBEDDED MICROPROCESSOR
4.0
DC SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................ –65°C to +150°C
Case Temperature Under Bias ................. –65°C to +112°C
Supply Voltage with Respect to VSS ............... –0.5V to 6.5V
Voltage on Other Pins .......................... –0.5V to VCC + 0.5V
OPERATING CONDITIONS*
VCC (Digital Supply Voltage - 25 and 33 MHz) ...4.5V to 5.5V
VCC (Digital Supply Voltage - 40 MHz) ...........4.75V to 5.25V
TCASE minimum (Case Temperature Under Bias) ......... 0°C
TCASE maximum ......................................... see Figure 4
Operating Frequency ................................ 0 MHz to 40 MHz
NOTICE: This document contains information on
products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your local
Intel Sales office that you have the latest data sheet
before finalizing a design.
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage. These
are stress ratings only. Operation beyond the “Operating
Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device
reliability.
Table 5. DC Characteristics
Symbol
VIL
Parameter
Input Low Voltage
Min.
Max.
Unit
–0.3
+0.8
V
V
VIH
Input High Voltage
2.0
VCC + 0.3
VILC
CLK2 Input Low Voltage
–0.3
+0.8
V
VIHC
CLK2 Input High Voltage
VCC – 0.8
VCC + 0.3
V
VOL
Output Low Voltage
VOH
Output High Voltage
ILI
Input Leakage Current
(for all pins except PEREQ,
BUSY#, FLT#, ERROR#)
IIH
0.45
Test Condition
V
IOL = 5 mA
V
V
IOH = –1 mA
IOH = –0.2 mA
±15
µA
0 ≤ VIN ≤ VCC
Input Leakage Current
(PEREQ)
150
µA
VIH = 2.4V (Note 1)
IIL
Input Leakage Current
(BUSY#, FLT#, ERROR#)
–120
µA
VIL = 0.45V (Note2)
ILO
Output Leakage Current
±15
µA
0.45V ≤ VOUT ≤ VCC
ICC
Supply Current
CLK2 = 80 MHz, CLK = 40
MHz
CLK2 = 66 MHz, CLK = 33
MHz
CLK2 = 50 MHz, CLK = 25
MHz
mA
mA
mA
(Notes 3, 4)
typical = 200 mA
typical = 175 mA
typical = 140 mA
2.4
VCC – 0.5
275
225
175
ICCF
Standby Current (Freeze Mode)
150
µA
typical = 10 µA (Notes 3 4)
CIN
Input Capacitance
10
pF
FC = 1 MHz (Note 5)
COUT
Output or I/O Capacitance
12
pF
FC = 1 MHz (Note 5)
CCLK
CLK2 Capacitance
20
pF
FC = 1 MHz (Note 5)
NOTES:
1.
2.
3.
4.
5.
PEREQ input has an internal weak pull-down resistor.
BUSY#, FLT# and ERROR# inputs each have an internal weak pull-up resistor.
ICC max measurement at worst-case frequency, VCC, and temperature with reset active.
ICC typical and ICCF typical are measured at nominal VCC and are not fully tested.
Not fully tested.
9
Intel386™ SXSA EMBEDDED MICROPROCESSOR
100
90
85
80
70
75
58
Ta (˚C)
50
45
25
12
16
20
25
33
40
Operating Frequency (MHz)
A2586-01
Figure 3. Ambient Temperature vs. Frequency at Zero Air Flow and TJ = 115° C
10
Intel386™ SXSA EMBEDDED MICROPROCESSOR
115
112
111.5
111
Tc (˚C)
110
110
108.5
107
105
12
16
20
25
33
40
Operating Frequency (MHz)
A2587-01
Figure 4. Case Temperature vs. Frequency at TJ = 115° C
11
Intel386™ SXSA EMBEDDED MICROPROCESSOR
5.0
AC SPECIFICATIONS
Table 6 lists output delays, input setup requirements, and input hold requirements. All AC specifications are relative to the CLK2 rising edge
crossing the 2.0V level.
Figure 5 shows the measurement points for AC
specifications. Inputs must be driven to the
indicated voltage levels when AC specifications are
measured. Output delays are specified with
minimum and maximum limits measured as shown.
The minimum delay times are hold times provided
to external circuitry. Input setup and hold times are
specified as minimums, defining the smallest
12
acceptable sampling window. Within the sampling
window, a synchronous input signal must be stable
for correct operation.
Outputs ADS#, W/R#, D/C#, MI/O#, LOCK#, BHE#,
BLE#, A23:A1 and HLDA change only at the
beginning of phase one. D15:0 (write cycles)
change only at the beginning of phase two.
The READY#, HOLD, BUSY#, ERROR#, PEREQ,
FLT# and D15:0 (read cycles) inputs are sampled at
the beginning of phase one. The NA#, INTR and
NMI inputs are sampled at the beginning of phase
two.
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Tx
PH1
CLK2
PH2
b
A
OUTPUTS
(A23:1,BHE#
BLE#,ADS#,MI/O#
D/C#W/R#,LOCK#
HLDA)
B
Min
Valid
a
Output n
Max
a Valid
Output n+1
A
B
Min
Valid
a
Output n
OUTPUTS
(D15:0)
C
INPUTS
(N/A#,INTR
NMI)
3.0V
INPUTS
(READY#,HOLD
FLT#,ERROR#
BUSY#,PEREQ
D15:0)
0V
a
Max
a Valid
Output n+1
D
Valid
Input
a
C
3.0V
0V
a
D
Valid
Input
a
LEGEND
a - 1.5V
b - 2.0V
A - Maximum Output Delay Spec
B - Minimum Output Delay Spec
C - Minimum Input Setup Spec
D - Minimum Input Hold Spec
A2296-02
Figure 5. Drive Levels and Measurement Points for AC Specifications
13
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Table 6. AC Characteristics
40 MHz
Symbol
Parameter
33 MHz
25 MHz
Min.
(ns)
Max.
(ns)
Min.
(ns)
Max
.
(ns)
Min.
(ns)
Max.
(ns)
40
0
33
0
25
Test Condition
Operating Frequency
0
t1
CLK2 Period
12.5
15
20
t2a
CLK2 High Time
4.5
6.25
7
t2b
CLK2 High Time
3.5
4
4
(Note 2)
t3a
CLK2 Low Time
4.5
6.25
7
(Note 2)
t3b
CLK2 Low Time
3.5
t4
CLK2 Fall Time
4.5
4
4
(Note 2)
5
4
4
MHz (Note 1)
(Note 2)
7
(Note 2)
7
(Note 2)
t5
CLK2 Rise Time
t6
A23:1 Valid Delay
4
13
4
15
4
17
CL = 50 pF
t7
A23:1 Float Delay
4
20
4
20
4
30
(Note 3)
t8
BHE#, BLE#,
LOCK# Valid Delay
4
13
4
15
4
17
CL = 50 pF
t9
BHE#, BLE#,
LOCK# Float Delay
4
20
4
20
4
30
(Note 3)
t10
W/R#, M/IO#, D/C#,
ADS# Valid Delay
4
13
4
15
4
17
CL = 50 pF
t11
W/R#, M/IO#, D/C#,
ADS# Float Delay
4
20
4
20
4
30
(Note 3)
t12
D15:0 Write Data
Valid Delay
7
18
7
23
7
23
CL = 50 pF
(Note 5)
t12a
D15:0 Write Data
Hold Time
2
t13
D15:0 Write Data
Float delay
4
17
t14
HLDA Valid Delay
4
17
t15
NA# Setup Time
5
5
5
t16
NA# Hold Time
2
2
3
t19
READY#Setup Time
7
7
9
t20
READY#Hold Time
4
4
4
t21
D15:0 Read Setup
Time
4
5
7
2
2
4
17
4
20
CL = 50 pF
4
22
(Note 3)
4
22
CL = 50 pF
NOTES:
1.
2.
3.
4.
Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies.
These are not tested. They are guaranteed by characterization.
Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested.
These inputs may be asynchronous to CLK2. The setup and hold specifications are given for testing purposes to ensure recognition within
a specific CLK2 period.
5. Minimum time not 100% tested.
14
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Table 6. AC Characteristics (Continued)
40 MHz
Symbol
Parameter
Min.
(ns)
Max.
(ns)
33 MHz
Min.
(ns)
Max
.
(ns)
25 MHz
Min.
(ns)
Max.
(ns)
Test Condition
t22
D15:0 Read Hold
Time
3
3
5
t23
HOLD Setup Time
4
9
9
t24
HOLD Hold Time
2
2
3
t25
RESET Setup Time
4
5
8
t26
RESET Hold Time
2
2
3
t27
NMI, INTR Setup
Time
5
5
6
(Note 4)
t28
NMI, INTR Hold Time
5
5
6
(Note 4)
t29
PEREQ, ERROR#,
BUSY#, FLT# Setup
Time
5
5
6
(Note 4)
t30
PEREQ, ERROR#,
BUSY#, FLT# Hold
Time
4
4
5
(Note 4)
NOTES:
1.
2.
3.
4.
Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies.
These are not tested. They are guaranteed by characterization.
Float condition occurs when maximum output current becomes less than ILO in magnitude. Float delay is not fully tested.
These inputs may be asynchronous to CLK2. The setup and hold specifications are given for testing purposes to ensure recognition within
a specific CLK2 period.
5. Minimum time not 100% tested.
15
Intel386™ SXSA EMBEDDED MICROPROCESSOR
CPU Output
CL
A2200-0A
Figure 6. AC Test Loads
t1
t2a
t2b
CLK2
A
B
C
t5
t3b
t4
t3a
A = Vcc -.8
B = 2.0V
C = .8V
A2291-0A
Figure 7. CLK2 Waveform
16
Intel386™ SXSA EMBEDDED MICROPROCESSOR
TX
PH2
PH1
TX
PH2
PH1
TX
CLK2
t19
t20
t23
t24
t21
t22
t29
t30
READY#
HOLD
D15:0
(Input)
BUSY#
ERROR#
PEREQ
FLT#
t15
t16
t27
t28
NA#
INTR
NMI
A2292-01
Figure 8. AC Timing Waveforms — Input Setup and Hold Timing
17
Intel386™ SXSA EMBEDDED MICROPROCESSOR
TX
PH2
PH1
TX
PH2
PH1
TX
CLK2
t8
BHE#, BLE#
LOCK#
Valid n+1
Min
Max
Valid n
t6
A23:1
Max
Valid n
t10
W/R#, M/IO#
D/C#, ADS#
Min
Valid n+1
Min
Max
Valid n
Valid n+1
t12,t12a
D15:0
(Output)
Min
Max
Valid n
Valid n+1
HLDA
A2293-01
Figure 9. AC Timing Waveforms — Output Valid Delay Timing
18
Intel386™ SXSA EMBEDDED MICROPROCESSOR
TI or T1
Th
PH1
PH2
PH2
PH1
PH2
CLK2
t8
t9
BHE#, BLE#
LOCK#
Min
Max
Min
Max
Min
Max
Min
Max
(High Z)
t11
Min
t10
Max
W/R#, M/IO#
D/C#, ADS#
(High Z)
t7
Min
t6
Max
A23:1
(High Z)
t13
Min
t12
Max
D15:0
Min
Max
(High Z)
t13 Also applies to data float when write
cycle is followed by read or idle.
t14
Min
Max
t14
Min
Max
HLDA
A2294-01
Figure 10. AC Timing Waveforms — Output Float Delay and HLDA Valid Delay Timing
19
Intel386™ SXSA EMBEDDED MICROPROCESSOR
Initialization Sequence
Reset
PH2 or PH1
PH2 or PH1
PH2
PH1
CLK2
t26
RESET
t25
A2205-0A
Figure 11. AC Timing Waveforms — RESET Setup and Hold Timing and Internal Phase
6.0
REVISION HISTORY
This -003 data sheet contains the following changes from the -002 version.
• Changed VCC at 40 MHz to 4.75V to 5.25V (Pages 1 and 9)
• Renamed “Powerdown Mode” to “Clock Freeze Mode” on page one.
• Added clarifications to Figure 1.
• Corrected pin numbering for A23:1 in Table 2
• Changed the first sentence in Section 3.3 from “...on page 12” to “...on page 9.”
• Changed the first sentence on page 12 from “Table 7 lists...” to “Table 6...” Also changed the first sentence
of the fourth paragraph on page 12 from “...A25:1” to “...A23:1.”
20