IDT 9DB423BGLF

DATASHEET
9DB423B
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Recommended Application:
Features/Benefits
DB400Q compatible part with PCIe Gen1, Gen 2 and QPI
support
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
General Description:
•
Supports undriven differential outputs in Power Down and
DIF_STOP# modes for power management.
The ICS9DB423 is compatible with the Intel DB400Q Differential
Buffer Specification. This buffer provides 4 PCI-Express SRC or
4 QPI clocks. The ICS9DB423 is driven by a differential output
pair from a CK410B+ or CK509B main clock generator.
Output Features
•
•
•
•
•
Key Specifications
•
•
•
•
•
•
Output cycle-cycle jitter < 50ps.
Output to Output skew <50ps
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
Phase jitter: QPI < 0.5ps rms
RoHS compliant packaging
4 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-133 MHz operation in PLL mode
33-400 MHz operation in Bypass mode
Funtional Block Diagram
2
OE(6,1)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
PD
BYPASS#_133_100
HIGH_BW#
DIF_STOP#
SDATA
SCLK
4
STOP
LOGIC
DIF(6,5,2,1)
CONTROL
LOGIC
IREF
Note: Polarities shown for OE_INV = 0.
IDT® Four Output Differential Buffer for PCIe and Gen 1, Gen 2 and QPI
1437B - 02/04/10
1
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
9DB423
(same as 9DB104)
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#_133_100
SCLK
SDATA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYPASS#_133_100
SCLK
SDATA
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
DIF_STOP#
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
9DB423
(same as 9DB403)
Pin Configuration
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
OE_INV
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
HIGH_BW#
DIF_STOP
PD#
OE_INV = 1
Note: Pin 15 is always active low. This is different
than 9DB403.
OE_INV = 0
28-pin SSOP & TSSOP
Polarity Inversion Pin List Table
Frequency Selection
BYPASS#_133_100
Low
Mid
High
OE_INV
Pins
0
1
8
OE_1
OE1#
15
PD#
PD#
16
DIF_STOP#
DIF_STOP
Various
OE_x
OEx#
Power Groups
Pin Number
VDD
GND
1
4
5,11,18, 24
4
N/A
27
28
27
Voltage
MODE
<0.8V
Bypass
1.2<Vin<1.8V QPI 133MHz
Vin > 2.0V PCIe 100MHz
Bypass Readback Table
BYPASS#_133_100
Low
Mid
High
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Byte0, bit 3
0
1
0
Byte 0 bit 1
0
0
1
1437B - 02/04/10
2
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Pin Description for OE_INV = 0
PIN #
1
2
3
4
5
6
7
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
8
OE_1
IN
9
10
11
DIF_2
DIF_2#
VDD
12
BYPASS#_133_100
IN
13
14
SCLK
SDATA
IN
I/O
15
PD#
IN
16
DIF_STOP#
IN
17
HIGH_BW#
IN
18
19
20
VDD
DIF_5#
DIF_5
21
OE_6
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode
0 = Bypass mode, M= QPI, 1= PCIe PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
3
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Pin Description for OE_INV = 1
PIN #
1
2
3
4
5
6
7
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
8
OE1#
IN
9
10
11
DIF_2
DIF_2#
VDD
12
BYPASS#_133_100
IN
13
14
SCLK
SDATA
IN
I/O
15
PD#
IN
16
DIF_STOP
IN
17
HIGH_BW#
IN
18
19
20
VDD
DIF_5#
DIF_5
21
OE6#
22
23
24
DIF_6#
DIF_6
VDD
OUT
OUT
PWR
25
OE_INV
IN
26
IREF
OUT
27
28
GNDA
VDDA
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode
0 = Bypass mode, M= QPI, 1= PCIe PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
Active High input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
4
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Absolute Max
Symbol
VDD_A
VDD_In
V IL
V IH
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
Min
Max
4.6
4.6
Units
V
V
V
V
GND-0.5
VDD+0.5V
-65
0
°
C
°C
°C
150
70
115
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V IH
V IL
I IH
I IL1
I IL2
Operating Supply Current
IDD3.3OP
Powerdown Current
IDD3.3PD
Input Frequency
FiPLL
FiPLL
Pin Inductance
Capacitance
FiBYPASS
Lpin
CIN
CINSRC_IN
COUT
PLL Bandwidth
BW
PLL Jitter Peaking
t JPEAK
Clk Stabilization
TSTAB
Input SS Modulation
Frequency
f MODIN
OE# Latency
tLATOE#
Tdrive_DIF_Stop#
tDRVSTP
Tdrive_PD#
t DRVPD
Tfall
Trise
SMBus Voltage
Low-level Output Voltage
Current sinking at VOL
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
SMBus Operating Frequency
tF
tR
VMAX
V OL
CONDITIONS
MIN
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
Full Active, CL = Full load;
all diff pairs driven
all differential pairs tri-stated
PCIe Mode (Bypass/133/100= 1)
QPI Mode (Bypass/133/100= M)
Bypass Mode (Bypass/133/100= 0)
2
GND - 0.3
-5
-5
-200
Logic Inputs, except SRC_IN
SRC_IN differential clock inputs
Output pin capacitance
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
DIF_Stop# de-assertion
DIF output enable after
PD# de-assertion
Fall time of PD# and DIF_Stop#
Rise time of PD# and DIF_Stop#
Maximum input voltage
@ I PULLUP
1.5
1.5
IPULLUP
t RSMB
t FSMB
fMAXSMB
TYP
MAX
200
60
6
110
140
400
7
5
2.7
6
4
1.4
2
V
V
uA
uA
uA
mA
mA
mA
MHz
MHz
MHz
nH
pF
pF
pF
MHz
MHz
dB
1
1
1
1
1
1
1
1
1
1
1
1
1
1,4
1
1
1
1
1
ms
1,2
30
33
kHz
1
1
3
cycles
1,3
10
ns
1,3
300
us
1,3
5
5
5.5
0.4
ns
ns
V
V
mA
1
2
1
1
1
1000
ns
1
300
ns
1
100
kHz
1,5
50
67
33
2
0.7
VDD + 0.3
0.8
5
100.00
133.33
3
1
1.5
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
Maximum SMBus operating frequency
UNITS NOTES
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
4
SRC_IN input
5
The differential input clock must be running for the SMBus to be active
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
5
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Electrical Characteristics - Clock Input Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage - DIF_IN
VIHDIF
Input Low Voltage - DIF_IN
V ILDIF
Input Common Mode Voltage DIF_IN
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
SYMBOL
CONDITIONS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
MIN
TYP
MAX
UNITS NOTES
600
800
1150
mV
1
V SS - 300
0
300
mV
1
VCOM
Common Mode Input Voltage
300
1000
mV
1
VSWING
dv/dt
IIN
dtin
J DIFIn
Peak to Peak value
Measured differentially
VIN = V DD , VIN = GND
Measurement from differential wavefrom
Differential Measurement
300
0.4
-5
45
0
1450
8
5
55
125
mV
V/ns
uA
%
ps
1
1,2
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through Vswing min centered around differential zero
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
6
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33Ω, RP=49.9Ω, RREF=475Ω
PARAMETER
Current Source Output
Impedance
SYMBOL
Voltage High
VHigh
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Skew, Input to Output
Skew, Output to Output
Jitter, Cycle to cycle
Jitter, Phase
Zo
CONDITIONS
1
VLow
MIN
TYP
MAX
Ω
3000
Statistical measurement on single ended
signal using oscilloscope math function.
Measurement on single ended signal using
Vovs
absolute value.
Vuds
Vcross(abs)
d-Vcross
Variation of crossing over all edges
VOL = 0.175V, VOH = 0.525V
tr
VOH = 0.525V VOL = 0.175V
tf
d-tr
d-tf
dt3
Measurement from differential wavefrom
Bypass Mode, VT = 50%
tpdBYP
PLL Mode VT = 50%
tpdPLL
VT = 50%
tsk3
PLL mode
tjcyc-cyc
Additive Jitter in Bypass Mode
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
tjphaseBYP
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
QPI phase jitter
(Additive in Bypass Mode)
660
850
1
1,2
mV
-150
150
1150
-300
250
550
140
700
700
125
125
55
4500
250
50
50
50
175
175
45
2500
-250
7
10
0
0.1
0.7
0.9
0.16
PCIe Gen 1 phase jitter
37
86
PCIe Gen 2 Low Band phase jitter
1.5
3
PCIe Gen 2 High Band phase jitter
2.7/
2.2
3.1
QPI phase jitter
0.28
0.5
tjphasePLL
UNITS NOTES
1,2
mV
1
1
1
1
1
1
1
1
1
1
1
1
1,3
1,3
mV
mV
ps
ps
ps
ps
%
ps
ps
ps
ps
ps
ps
1,4,5
(pk2pk)
ps
1,4,5
(rms)
ps
1,4,5
(rms)
ps
1,5,6
(rms)
ps
1,4,5
(pk2pk)
ps
1,4,5
(rms)
ps
1,4,5,7
(rms)
ps
1,5,6
(rms)
1
Guaranteed by design and characterization, not 100% tested in production.
IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
3 Measured from differential waveform
4
See http://www.pcisig.com for complete specs
5
Device driven by 932S421C or equivalent.
6
6.4Gb 12UI
7
First number is High Bandwidth Mode, second number is Low Bandwidth Mode
2
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
7
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Clock Periods Differential Outputs with Spread Spectrum Enabled
Measurement
Window
Symbol
Signal Name
Definition
DIF
DIF
DIF
DIF
DIF
DIF
DIF
100
133
166
200
266
333
400
1 Clock
Lg-
0.1s
-ppm error
0.1s
0ppm
Absolute Short-term Long-Term
Period
Average
Average
Period
Minimum
Absolute
Period
9.949
7.449
5.949
4.950
3.700
2.950
2.450
1us
-SSC
Minimum
Absolute
Period
9.999
7.499
5.999
5.000
3.750
3.000
2.500
Minimum
Absolute
Period
10.024
7.518
6.014
5.012
3.759
3.007
2.506
0.1s
+ ppm error
1us
+SSC
Long-Term Short-term
Average
Average
1 Clock
Lg+
Period
Nominal
Maximum
Maximum
Maximum
10.025
7.519
6.015
5.013
3.759
3.008
2.506
10.026
7.520
6.016
5.013
3.760
3.008
2.507
10.051
7.538
6.031
5.026
3.769
3.015
2.513
10.101
7.588
6.081
5.076
3.819
3.065
2.563
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
Units
ns
ns
ns
ns
ns
ns
ns
Notes
1,2,3
1,2,4
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
Clock Periods Differential Outputs with Spread Spectrum Disabled
Measurement
Window
Symbol
Signal Name
Definition
1
DIF
DIF
DIF
DIF
DIF
DIF
DIF
100
133
166
200
266
333
400
1 Clock
Lg-
0.1s
-ppm error
0.1s
0ppm
Absolute Short-term Long-Term
Period
Average
Average
Period
Minimum
Absolute
Period
9.949
7.449
5.949
4.950
3.700
2.950
2.450
1us
-SSC
Minimum
Absolute
Period
Minimum
Absolute
Period
9.999
7.499
5.999
5.000
3.750
3.000
2.500
0.1s
+ ppm error
1us
+SSC
Long-Term Short-term
Average
Average
Nominal
Maximum
10.000
7.500
6.000
5.000
3.750
3.000
2.500
10.001
7.501
6.001
5.001
3.750
3.000
2.500
Maximum
1 Clock
Lg+
Period
Maximum
10.051
7.551
6.051
5.051
3.800
3.050
2.550
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy
requirements. The 9DB423/823 itself does not contribute to ppm error.
3
Driven by SRC output of main clock, PCIe PLL Mode or Bypass mode
4
Driven by CPU output of main clock, QPI PLL Mode or Bypass mode
5
Driven by CPU output of CK410B+/CK420BQ/CK505 main clock, Bypass mode only
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
8
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Output Termination & Layout Information
Common Recommendations for Differential Routing
Dimension or Value
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
Rs
33
Rt
49.9
Unit
inch
inch
inch
ohm
ohm
Figure
1
1
1
1
1
Down Device Differential Routing
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Figure
1
1
Differential Routing to PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value
0.25 to 14 max
0.225 min to 12.6 max
Unit
inch
inch
Figure
2
2
Figure 1. Down Device Differential Routing
L1
L2
L4
Rs
L1’
L4’
L2
Rs
Rt
HSCL Output
Buffer
L3’
Rt
PCI Ex Board
Down Device
REF_CLK Input
L3
Figure 2. Differential Routing to PCI Express Controller
L1
Rs
L1’
L2
L4
L4’
L2’
Rs
HSCL Output
Buffer
Rt
L3’
Rt
L3
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
PCI Ex
Add In Board
REF_CLK Input
1437B - 02/04/10
9
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Figure 3. Terminations for LVDS and other common differential signals.
L1
R1a
L1’
L2
R3
L4’
L2’
R1b
R2a
HSCL Output
Buffer
R4
L4
R2b
Down Device
REF_CLK Input
L3
L3’
R2a = R2b = R2
Vdiff
Vp-p
0.45 v
0.22v
0.58
0.28
0.80
0.40
0.60
0.3
R1a = R1b = R1
Vcm
1.08
0.6
0.6
1.2
R1
33
33
33
33
R2
150
78.7
78.7
174
R3
100
137
none
140
R4
100
100
100
100
Note
ICS874003i-02 input compatible
Standard LVDS
Figure 4. Terminations for cable AC coupled applications
3.3 Volts
R5a
R5b
L4
Cc
L4’
Cc
R6a
R6b
PCIe Device
REF_CLK Input
Component
R5a,R5b
R6a,R6b
Cc
Vcm
Value
8.2K 5%
1K 5%
0.1 uF
0.350 volts
Note
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
10
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
General SMBus serial interface information for the 9DB423B
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address DC(h)
WRite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (h)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (h)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controller (Host)
T
starT bit
Slave Address DC(h)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(h)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Not acknowledge
stoP bit
1437B - 02/04/10
11
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
PD_Mode
PD# drive mode
Bit 7
STOP_Mode
DIF_Stop# drive mode
Bit 6
Select PD polarity
PD_Polarity
Bit 5
Reserved
Bit 4
Type
RW
RW
RW
Bit 3
-
BYPASS#1
BYPASS#/PLL1
RW
Bit 2
-
PLL_BW#
Select PLL BW
RW
Bit 1
-
BYPASS#0
BYPASS#/PLL0
RW
Bit 0
-
SRC_DIV#
SRC Divide by 2 Select
RW
0
driven
driven
Low
1
Hi-Z
Hi-Z
High
See Bypass Readback
Table
High BW
Low BW
See Bypass Readback
Table
x/2
x/1
Default
0
0
0
X
Input
1
Input
1
SMBus Table: Output Control Register
0
1
Default
Pin #
Name
Control Function
Type
Byte 1
Reserved
1
Bit 7
22,23
DIF_6
Output Enable
RW
Disable
Enable
1
Bit 6
19,20
DIF_5
Output Enable
RW
Disable
Enable
1
Bit 5
Reserved
1
Bit 4
Reserved
1
Bit 3
9,10
DIF_2
Output Enable
RW
Disable
Enable
1
Bit 2
6,7
DIF_1
Output Enable
RW
Disable
Enable
1
Bit 1
Reserved
1
Bit 0
NOTE: The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Byte 2
Pin #
Name
Bit 7
22,23
DIF_6
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
6,7
DIF_1
Bit 1
Bit 0
SMBus Table: Reserved Register
Byte 3
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
DIF_6 Stoppable with OE6
Reserved
Reserved
Reserved
Reserved
DIF_1 Stoppable with OE1
Reserved
Type
0
RW
Free-run
RW
Free-run
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1
Default
0
Stoppable
0
0
0
0
0
Stoppable
0
0
1
Default
X
X
X
X
X
X
X
X
1437B - 02/04/10
12
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
SMBus Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Byte 4
RID3
Bit 7
RID2
Bit 6
REVISION ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
0
-
1
-
SMBus Table: DEVICE ID
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Type
R
R
R
R
R
R
R
R
0
1
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
SMBus Table: Byte Count Register
Byte 6
Pin #
Name
BC7
Bit 7
BC6
Bit 6
BC5
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Writing to this register configures how
many bytes will be read back.
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Default
0
0
0
1
0
0
0
1
Default
0
1
0
Device ID is 42 Hex for
0
9DB423
0
0
1
0
Default
0
0
0
0
0
1
1
1
1437B - 02/04/10
13
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1.
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting
off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the
device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD#
drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending
on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode
bit is set to ‘0’, all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is
set to ‘1’, both DIF and DIF# are tri-stated.
PWRDWN#
DIF
DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from
valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set
to ‘1’, all the DIF outputs must driven to a voltage of >200 mV within 300 us of PD# de-assertion.
Tstable
<1mS
PWRDWN#
DIF
DIF#
Tdrive_PwrDwn#
<300uS, >200mV
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
14
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
DIF_STOP#
The DIF_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The DIF_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
DIF_STOP# - Assertion
Asserting DIF_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the DIF_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
DIF_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
DIF_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the DIF_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
DIF_STOP_1 (Stop_Mode = Driven, PD_Mode = Driven)
1mS
DIF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF_STOP_2 (Stop_Mode = Tristate, PD_Mode = Driven)
1mS
DIF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
15
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
DIF_STOP_3 (Stop_Mode = Driven, PD_Mode = Tristate)
1mS
DIF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
DIF_STOP_4 (Stop_Mode = Tristate, PD_Mode = Tristate)
1mS
DIF_Stop#
PWRDWN#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
16
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
209 mil SSOP
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-2.00
0.05
-1.65
1.85
0.22
0.38
0.09
0.25
SEE VARIATIONS
7.40
8.20
5.00
5.60
0.65 BASIC
0.55
0.95
In Inches
COMMON DIMENSIONS
MIN
MAX
-.079
.002
-.065
.073
.009
.015
.0035
.010
SEE VARIATIONS
.291
.323
.197
.220
0.0256 BASIC
.022
.037
0°
8°
0°
MIN
9.90
MAX
10.50
MIN
.390
8°
VARIATIONS
D (inch)
28
MAX
.413
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
209 mil SSOP
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
17
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
4.40 mm. Body, 0.65 mm. Pitch TSSOP
c
N
(173 mil)
SYMBOL
L
E1
INDEX
AREA
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
1 2
a
D
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
A
A2
(25.6 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
SEE VARIATIONS
6.40 BASIC
4.30
4.50
0.65 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
N
A1
28
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
-CReference Doc.: JEDEC Publication 95, MO-153
e
SEATING
PLANE
b
10-0035
aaa C
Ordering Information
Part / Order Number
9DB423BFLF
9DB423BFLFT
9DB423BGLF
9DB423BGLFT
Shipping Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
28-pin SSOP
28-pin SSOP
28-pin TSSOP
28-pin TSSOP
Temperature
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
“LF” suffix to the part numbers are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate to the datasheet revision).
IDT® Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
1437B - 02/04/10
18
9DB423B
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Revision History
Rev.
Issue Date Description
A
9/30/2008
B
2/3/2010
Page #
1. Updated Electrical Characteristics to add propagation delay and phase noise information.
2. Corrected SMBus to reference pin numbers for 423 instead of 823 device.
3. Removed references to OE controls that are not present on 423.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus interface to work
Various
6. Added foot note to Byte 1 about functionality of OE bits and OE pins.
7. Corrected Block Diagram with proper OE pins indicated and PD and DIF_STOP# pins
added
8. Updated clock periods to reflect +/-100ppm input clock tolerance
(CK410B+/CK420BQ/CK505).
9. Changed SRC_Stop references to DIF_Stop references for consistency.
1. Corrected Polarity of PD pin when OE_INV = 1. PD is always active low (or PD#). This is
Various
a difference from the 9DB803D.
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
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are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
19