DATASHEET ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Description Features/Benefits ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the ICS932S421, drives the ICS9FG1200D-1. The ICS9FG1200D-1 can provide outputs up to 400MHz. • • • • • • • • Key Specifications • • DIF output cycle-to-cycle jitter < 50ps DIF output-to-output skew < 100ps across all outputs in 1:1 mode • • 56-pin SSOP/TSSOP package RoHS compliant packaging Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs) Power up default is all outputs in 1:1 mode DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock Spread spectrum compatible Supports output clock frequencies up to 400 MHz 8 Selectable SMBus addresses SMBus address determines PLL or Bypass mode Functional Block Diagram OE# SPREAD COMPATIBLE 1:1 PLL STOP LOGIC 2 SPREAD COMPATIBLE GEARING PLL STOP LOGIC 10 DIF(11:10) 10 OE(9:0)# CLK_IN CLK_IN# HIGH_BW# FS_A_410 VTT_PWRGD#/PD SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK DIF(9:0) CONTROL LOGIC IREF IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 1 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD HIGH_BW# CLK_IN CLK_IN# SMB_A0 OE0# DIF_0 DIF_0# OE1# DIF_1 DIF_1# VDD GND DIF_2 DIF_2# OE2# DIF_3 DIF_3# OE3# DIF_4 DIF_4# OE4# VDD GND DIF_5 DIF_5# OE5# SMB_A1 SMBDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 9FG1200-1 Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDA GNDA IREF OE10_11# DIF_11 DIF_11# VDD GND DIF_10 DIF_10# FS_A_410 VTT_PWRGD#/PD OE9# DIF_9 DIF_9# OE8# DIF_8 DIF_8# VDD GND DIF_7 DIF_7# OE7# DIF_6 DIF_6# OE6# SMB_A2_PLLBYP# SMBCLK 56-pin SSOP & TSSOP Power Groups VDD 56 11,22,38,50 Pin Number GND 55 12,23,37,49 Description Main PLL, Analog DIF clocks Functionality at Power Up (PLL Mode) CLK_IN (CPU FSB) DIF_(11:0) MHz MHz 1 100 <= CLK_IN < 200 CLK_IN 0 200<= CLK_IN <= 400 CLK_IN 1. FS_A_410 is a low-threshold input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. 1 FS_A_410 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 2 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Pin Description PIN # PIN NAME PIN TYPE 1 HIGH_BW# IN 2 3 4 CLK_IN CLK_IN# SMB_A0 IN IN IN 5 OE0# IN 6 7 DIF_0 DIF_0# 8 OE1# OUT OUT IN 9 10 11 12 13 14 DIF_1 DIF_1# VDD GND DIF_2 DIF_2# OUT OUT PWR PWR OUT OUT 15 OE2# 16 17 DIF_3 DIF_3# 18 OE3# 19 20 DIF_4 DIF_4# 21 OE4# 22 23 24 25 VDD GND DIF_5 DIF_5# 26 OE5# IN 27 28 SMB_A1 SMBDAT IN I/O IN OUT OUT IN OUT OUT IN PWR PWR OUT OUT DESCRIPTION 3.3V input for selecting PLL Band Width 0 = High, 1= Low Input for reference clock. "Complementary" reference clock input. SMBus address bit 0 (LSB) Active low input for enabling DIF pair 0. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 1. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 2. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 3. 1 = tri-state outputs, 0 = enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 4 1 = tri-state outputs, 0 = enable outputs Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output Active low input for enabling DIF pair 5. 1 = tri-state outputs, 0 = enable outputs SMBus address bit 1 Data pin of SMBUS circuitry, 5V tolerant IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 3 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Pin Description (continued) PIN # PIN NAME 29 SMBCLK Type IN 30 SMB_A2_PLLBYP# IN 31 OE6# IN 32 33 DIF_6# DIF_6 34 OE7# 35 36 37 38 39 40 DIF_7# DIF_7 GND VDD DIF_8# DIF_8 41 OE8# 42 43 DIF_9# DIF_9 44 OE9# IN 45 VTT_PWRGD#/PD IN 46 FS_A_410 IN 47 48 49 50 51 52 DIF_10# DIF_10 GND VDD DIF_11# DIF_11 53 OE10_11# 54 IREF OUT 55 56 GNDA VDDA PWR PWR OUT OUT IN OUT OUT PWR PWR OUT OUT IN OUT OUT OUT OUT PWR PWR OUT OUT IN Pin Description Clock pin of SMBUS circuitry, 5V tolerant SMBus address bit 2. When Low, the part operates as a fanout buffer with the PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with the PLL operating. 0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used) Active low input for enabling DIF pair 6. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 7. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 8. 1 = tri-state outputs, 0 = enable outputs 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling DIF pair 9. 1 = tri-state outputs, 0 = enable outputs Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. 3.3V tolerant low threshold input for CPU frequency selection. This pin requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and Vih_FS threshold values. 0.7V differential complement clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential complement clock output 0.7V differential true clock output Active low input for enabling output pairs 10 and 11. 1 = tri-state outputs, 0 = enable outputs This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 4 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 9FG1200-1 Programmable Gear Ratios CLK_IN (CPU FSB) MHz Geared DIF Outputs MHz 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 160.00 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.67 320.00 266.67 333.33 320.00 333.33 333.33 400.00 400.00 400.00 400.00 400.00 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 400.00 133.33 200.00 266.67 320.00 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67 200.00 200.00 133.33 160.00 166.67 200.00 133.33 160.00 166.67 320.00 333.33 (FS_A#) Byte 0, Byte 0, Byte 0, Byte 0, Byte 0, Gear bit 4 bit 3 bit 2 bit 1 bit 0 Ratio n/M FS4 FS3 FS2 FS1 FS0 1.333 0 0 0 0 0 1.667 0 0 0 0 1 2.000 0 0 0 1 0 2.667 0 0 0 1 1 3.333 0 0 1 0 0 4.000 0 0 1 0 1 1.250 0 0 1 1 0 1.500 0 0 1 1 1 1.250 0 1 0 0 0 1.500 0 1 0 0 1 3.000 0 1 0 1 0 0.800 0 1 0 1 1 1.200 0 1 1 0 0 1.600 0 1 1 0 1 M 3 3 1 3 3 1 4 2 1 2 1 5 5 5 n 4 5 2 8 10 4 5 3 2 5 3 4 6 8 1 2 2.000 0 1 1 1 0 1,2 5 3 6 3 3 1 2 12 2 5 4 5 2 1 2.400 0.667 0.833 1.333 1.667 2.000 0.500 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 8 5 0.625 1 0 1 1 0 1, 6 4 5 3 2 0.750 0.400 1 1 0 1 1 0 1 0 1 0 1 1 2 1 0.500 1 1 0 0 1 1,5 5 3 5 12 5 6 3 1 2 5 4 5 0.600 0.333 0.400 0.417 0.800 0.833 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1,4 1 1 1 1 Notes 1 1 1,3 1 Notes: 1. Targetted input/output frequency pairs 2. This Gear is also used for 160MHz/320 MHz. 3. Gear Ratio 5/4 is power up default for FS_A_410 = 1 4. Gear Ratio 3/1 is power up default for FS_A_410 = 0 5. This Gear is also used for 400MHz/200MHz 6. This Gear is also used for 320MHz/200MHz IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 5 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 9FG1200-1 1:1 PLL Programming Byte 8, bit 2 FSC Byte 8, bit 1 FSB Byte 8, bit 0 FS_A_410 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 0 0 1 1 1 1 0 1 CLK_IN 1:1 DIF (CPU FSB) Outputs MHz MHz 100.00 100.00 133.33 133.33 166.67 166.67 200.00 200.00 266.67 266.67 333.33 333.33 400.00 400.00 Reserved Notes 3 3 1 3 3 3 2 Notes:FS_A_410 = 1 1. Powerup Default for FS_A_410 = 1 2. Powerup Default for FS_A_410 = 0 3. Setting the exact FSB frequency after Power up is required for best phase noise performance. IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 6 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS 3.3V Core Supply Voltage 3.3V Logic Supply Voltage VDD_A VDD_In GND - 0.5 GND - 0.5 VDD + 0.5V VDD + 0.5V Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection Ts Tambient Tcase ESD prot -65 0 150 70 115 Human Body Model MIN TYP MAX 2000 UNITS Notes V V ° C °C °C V 1 1 1 1 1 1 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN Input High Voltage VIH 3.3 V +/-5%, except CLK_IN 2 VDD + 0.3 V 1 Input Low Voltage Input High Current VIL I IH VSS - 0.3 -5 0.8 5 V uA 1 Input Low Current I IL1 3.3 V +/-5%, except CLK_IN VIN = VDD VIN = 0 V; Inputs with no pullup resistors Low Threshold InputHigh Voltage VIH_FS Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance Clk Stabilization VIL_FS I DD3.3OP I DD3.3PD Fi Lpin CIN COUT TSTAB Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking at VOL = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time VMAX VOL 3.3 V +/-5%, Applies to FS_A_410 pin 3.3 V +/-5%, Applies to FS_A_410 pin all outputs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation DIF output enable after PD# de-assertion PD# fall time of PD# rise time of Maximum input voltage @ I PULLUP TFI2C MAX -5 (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD UNITS Notes uA 0.7 VDD + 0.3 V 1 VSS - 0.3 0.35 V 1 375 24 400 7 6 5 mA mA MHz nH pF pF 1 1 3 1 1 1 1.8 ms 1 33 kHz 1 300 us 1 5 5 5.5 0.4 ns ns V V 1 2 1 1 mA 1 1000 ns 1 300 ns 1 100 30 4 I PULLUP TRI2C TYP 1138C 7 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - DIF 0.7V Current Mode Differential Pair TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, ΙREF = 475Ω PARAMETER Current Source Output Impedance SYMBOL CONDITIONS MIN Zo VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. 660 1 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Duty Cycle dt3 tJCYC-CYC Jitter, Cycle to cycle tJBYP Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V Measurement from differential wavefrom PLL mode, from differential wavefrom Bypass mode as additive jitter TYP MAX UNITS NOTES Ω 850 1 1,3 mV -150 150 1150 1,3 550 mV 1 1 1 140 mV 1 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 700 700 125 125 ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 45 55 % 1 50 ps 1,4,5 50 ps 1,4 -300 250 mV Notes: 1.Guaranteed by design and characterization, not 100% tested in production. 2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B+ accuracy requirements 3.IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω. 4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 5. Measured from differential cross-point to differential cross-point 6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 8 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - Skew and Differential Jitter Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% Group Parameter CLK_IN, DIF[x:0] tSPO_PLL CLK_IN, DIF[x:0] tPD_BYP CLK_IN, DIF [x:0] ∆tSPO_PLL CLK_IN, DIF [x:0] ∆tPD_BYP DIF[11:10] tSKEW_G2 DIF[9:0] tSKEW_G10 DIF[11:0] tSKEW_A12 DIF[11:0] DIF[11:0] tJPH tSSTERROR Description Input-to-Output Skew in PLL mode (1:1 only), nominal value @ 25°C, 3.3V Input-to-Output Skew in Bypass mode (1:1 only), nominal value @ 25°C, 3.3V Input-to-Output Skew Variation in PLL mode (over specified voltage / temperature operating ranges) Input-to-Output Skew Variation in Bypass mode (over specified voltage / temperature operating ranges) Output-to-Output Skew Group of 2 (Common to Bypass and PLL mode) Output-to-Output Skew Group of 10 (Common to Bypass and PLL mode) Output-to-Output Skew across all 12 outputs (Common to Bypass and PLL mode - all outputs at same gear) Differential Phase Jitter (RMS Value) Differential Spread Spectrum Tracking Error (peak to peak) Min Typ Max Units PLL Jitter Peaking jpeak-hibw (HIGH_BW# = 0) PLL Jitter Peaking jpeak-lobw pllHIBW PLL Bandwidth pllLOBW PLL Bandwidth NOTES on Skew and Differential Jitter Parameters: Notes 1,2,4,5,8, 12 1,2,3,5, 12 1,2,4,5,6, 10,12 1,2,3,4,5, 6,10,12 -500 140 500 ps 2.5 3.1 4.5 ns 270 |350| ps 470 |500| ps 10 25 ps 1,2,12 40 50 ps 1,2,12 80 100 ps 1,2,3,12 5 40 10 80 ps ps 1,4,7,12 1,4,9,12 0 2.15 2.5 dB 11,12 (HIGH_BW# = 1) 0 1.2 2 dB 11,12 (HIGH_BW# = 0) (HIGH_BW# = 1) 2 0.7 3.6 1.2 4 1.4 MHz MHz 12,13 12,13 1. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input. 2. Measured from differential cross-point to differential cross-point 3. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it. 4. This parameter is deterministic for a given device 5. Measured with scope averaging on to find mean value. 6. Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device. 7. This parameter is measured at the outputs of two separate 9FG1200D-1 devices driven by a single CK410B+. The 9FG1200D-1 must be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22MHz and 11-33MHz. 8. t is the period of the input clock 9. Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9FG1200D-1 devices This parameter is measured at the outputs of two separate 9FG1200D-1 devices driven by a single CK410B+ in Spread Spectrum mode. The 9FG1200D-1 must set to high bandwidth. The spread spectrum characterisitics are : maximum of 0.5%, 30 to 33KHz modulation frequency, linear profile. 10. This parameter is an absolute value. It is not a double-sided figure. 11. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking. 12. Guaranteed by design and characterization, not 100% tested in production. 13. Measured at 3 db down or half power point. IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 9 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Electrical Characteristics - Phase Jitter PARAMETER SYMBOL tjphPCIe1 tjphPCIe2Lo Jitter, Phase tjphPCIe2Hi tjphFBD1_3.2G tjphFBD1_4.8G CONDITIONS PCIe Gen 1 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz ) PCIe Gen 2 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=12 ns) Lo-band content (10kHz to 1.5MHz) PCIe Gen 2 REFCLK phase jitter (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=12 ns) Hi-band content (1.5MHz to Nyquist) FBD REFCLK phase jitter (including PLL BW 11 - 33 MHz, ζ = 0.54, Td=12 ns Ftrl=0.2MHz) FBD REFCLK phase jitter (including PLL BW 11 - 33 MHz, ζ = 0.54, Td=12 ns Ftrl=0.2MHz) MIN TYP. MAX UNITS NOTES 43/37 86 ps 1,2,3 1.2/1.3 3 ps rms 1,2 3.0/2.4 3.1 ps rms 1,2 2.5/2.1 3 ps (RMS) 1,2 2.0/1.6 2.5 ps (RMS) 1,2 Notes on Phase Jitter: See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. 2 Device driven by 932S421BGLF or equivalent 3 -12 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1 4 Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers. 1 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 10 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 9FG1200 SMBus Address Mapping when using CK410B+ and DB400/800 PLL BYPASS MODE SMB_A2_PLLBYP# = 0 SMB_A(2:0) = 000 SMB Adr: D0 9FG1200 (DB1200G) SMB_A(2:0) = 001 SMB Adr: D2 9FG1200 (DB1200G) OR SMB Adr: D2 932S421 (CK410B+) OR SMB Adr: DC 9DB401/801 (DB400/800) SMB_A(2:0) = 010 SMB Adr: D4 9FG1200 (DB1200G) SMB_A(2:0) = 011 SMB Adr: D6 9FG1200 (DB1200G) SMB_A(2:0) = 100 SMB Adr: D8 9FG1200 (DB1200G) PLL ZDB MODE SMB_A2_PLLBYP# = 1 SMB_A(2:0) = 101 SMB Adr: DA 9FG1200 (DB1200G) SMB_A(2:0) = 110 SMB Adr: DC 9FG1200 (DB1200G) SMB_A(2:0) = 111 SMB Adr: DE 9FG1200 (DB1200G) IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 11 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD General SMBus serial interface information for the 9FG1200D-1 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D0 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D0(h)* WR WRite Controller (host) will send start bit. Controller (host) sends the write address D0 (h) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D1 (h) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(h) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Controller (Host) T starT bit Slave Address D0(h)* WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D1(h)* RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P Not acknowledge stoP bit * Note: See SMBus Address Mapping (page 10), for programming SMBus Read/Write Address IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 12 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Gear Ratio Select Register Pin # Name Control Function Byte 0 DIF(9:0) Group of 10 gear ratio enable Bit 7 DIF(11:10) Group of 2 gear ratio enable Bit 6 Reserved Bit 5 Gear Ratio FS4 (FS_A_410#) Bit 4 Gear Ratio FS3 Bit 3 Gear Ratio FS2 Bit 2 Gear Ratio FS1 Bit 1 Gear Ratio FS0 Bit 0 Type 0 1 RW Gear Ratio 1:1 RW Gear Ratio 1:1 RW RW See 9FG1200-1 RW Programmable Gear RW Ratios Table RW RW PWD 1 1 1 Latch 1 0 1 1 SMBusTable: Output Control Register Byte 1 Pin # Name 35, 36 DIF_7 Bit 7 32, 33 DIF_6 Bit 6 24, 25 DIF_5 Bit 5 19,20 DIF_4 Bit 4 16,17 DIF_3 Bit 3 13,14 DIF_2 Bit 2 9,10 DIF_1 Bit 1 6,7 DIF_0 Bit 0 Type RW RW RW RW RW RW RW RW 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1 1 PWD 1 1 1 1 1 1 1 1 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SMBusTable: Output and PLL BW Control Register 0 Pin # Name Control Function Type Byte 2 Reserved Bit 7 see note PLL_BW# adjust RW High BW Bit 6 BYPASS# test mode / PLL see note RW Bypass Bit 5 Reserved Bit 4 51,52 DIF_11 Output Control RW Hi-Z Bit 3 47,48 DIF_10 Output Control RW Hi-Z Bit 2 42,43 DIF_9 Output Control RW Hi-Z Bit 1 39,40 DIF_8 Output Control RW Hi-Z Bit 0 Note: Bit 6 is wired OR to the pin 1 input, any 0 selects High BW Note: Bit 5 is wired OR to the pin 30 input, any 0 selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte 3 Pin # Name Control Function 34 Readback OE7# Input Bit 7 31 Readback - OE6# Input Bit 6 Readback - OE5# Input 26 Bit 5 Readback - OE4# Input 21 Bit 4 Readback - OE3# Input 18 Bit 3 Readback - OE2# Input 15 Bit 2 8 Readback - OE1# Input Bit 1 5 Readback - OE0# Input Bit 0 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Type R R R R R R R R Low BW PLL Enable Enable Enable Enable 0 1 Readback Readback Readback Readback Readback Readback Readback Readback PWD X X X X X X X X 1138C 13 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Output Enable Readback Register Byte 4 Pin # Name Control Function Readback - FS_A_410 46 Bit 7 1 Readback - HIGH_BW# In Bit 6 30 Readback - SMB_A2_PLLBYP# In Bit 5 Reserved Bit 4 Reserved Bit 3 53 Readback - OE10_11# Input Bit 2 44 Readback - OE9# Input Bit 1 41 Readback - OE8# Input Bit 0 Type R R R R R R R R 0 SMBusTable: Vendor & Revision ID Register Byte 5 Pin # Name Control Function RID3 Bit 7 RID2 Bit 6 REVISION ID RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VENDOR ID VID1 Bit 1 VID0 Bit 0 Type R R R R R R R R 0 - SMBusTable: DEVICE ID Byte 6 Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type RW RW RW RW RW RW RW RW 0 Type RW RW RW Writing to this register RW configures how many RW bytes will be read back. RW RW RW 0 - Name Control Function Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0 SMBusTable: Byte Count Register Byte 7 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0 Control Function IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1 PWD X X X X X X X X 1 - PWD X X X X 0 0 0 1 1 PWD 1 1 0 0 0 0 0 0 1 - PWD 0 0 0 0 1 0 0 1 Readback Readback Readback Readback Readback Readback Readback Readback Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1138C 14 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: 1:1 PLL Frequency Selection Pin # Name Control Function Byte 8 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RESERVED Bit 3 Frequency Select C Bit 2 Frequency Select B Bit 1 FS_A_410 Bit 0 SMBusTable: Reserved Register Pin # Name Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SMBus Table: M/N Programming Enable Byte 10 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - M/N_EN Type RW RW RW 0 1 See 9FG1200-1 1:1 PLL Programming Table PWD 0 0 0 0 0 x 1 Latch Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 1 PWD 0 0 0 0 0 0 0 0 Control Function Type Gear PLL and 1:1 PLL M/N Programming RW Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 1 PWD Disable Enable 0 SMBus Table: Gear PLL Frequency Control Register Byte 11 Pin # Name Control Function RESERVED Bit 7 RESERVED Bit 6 Gear PLL M Div5 Bit 5 Gear PLL M Div4 Bit 4 M Divider Programming Gear PLL M Div3 Bit 3 bits Gear PLL M Div2 Bit 2 Gear PLL M Div1 Bit 1 Gear PLL M Div0 Bit 0 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Type RW RW RW RW RW RW X X X X X X X 0 1 PWD X X X X Contact IDT for 9FG1200X 1 M/N programming Table X X X 1138C 15 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBus Table: Gear PLL Frequency Control Register Byte 12 Pin # Name Control Function Gear PLL N Div7 Bit 7 Gear PLL N Div6 Bit 6 Gear PLL N Div5 Bit 5 N Divider Programming Gear PLL N Div4 Bit 4 bits Gear PLL N Div3 Bit 3 Gear PLL N Div2 Bit 2 Gear PLL N Div1 Bit 1 Gear PLL N Div0 Bit 0 SMBusTable: Gear PLL Output Divider Register Pin # Name Control Function Byte 13 RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 GoutDiv 3 Bit 3 GoutDiv 2 Bit 2 Gear Output Divider GoutDiv 1 Bit 1 GoutDiv 1 Bit 0 0 1 PWD Type RW X RW X RW X RW Contact IDT for 9FG1200X 1 M/N programming Table RW X RW X RW X RW X Type RW RW RW RW 0 1 Contact IDT for Output Divider Table PWD 0 0 0 0 X X X X SMBusTable: Reserved Register Pin # Name Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 1 PWD 0 0 0 0 0 0 0 0 SMBusTable: Reserved Register Byte 15 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 0 1 PWD 0 0 0 0 0 0 0 0 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 16 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Reserved Register Pin # Name Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SMBus Table: 1:1 PLL Frequency Control Register Pin # Name Control Function Byte 17 RESERVED Bit 7 RESERVED Bit 6 1:1 PLL M Div5 Bit 5 1:1 PLL M Div4 Bit 4 M Divider Programming 1:1 PLL M Div3 Bit 3 bits 1:1 PLL M Div2 Bit 2 1:1 PLL M Div1 Bit 1 1:1 PLL M Div0 Bit 0 SMBus Table: 1:1 PLL Frequency Control Register Byte 18 Pin # Name Control Function 1:1 PLL N Div7 Bit 7 1:1 PLL N Div6 Bit 6 1:1 PLL N Div5 Bit 5 N Divider Programming 1:1 PLL N Div4 Bit 4 bits 1:1 PLL N Div3 Bit 3 1:1 PLL N Div2 Bit 2 1:1 PLL N Div1 Bit 1 1:1 PLL N Div0 Bit 0 Type RW RW RW RW RW RW 1 0 1 PWD 0 0 0 0 0 0 0 0 PWD 0 0 X X Contact IDT for 9FG1200X 1 M/N programming Table X X X Type 0 1 PWD RW X RW X RW X RW Contact IDT for 9FG1200X RW 1 M/N programming Table X RW X RW X RW X SMBusTable: 1:1 PLL Output Divider Register Byte 19 Pin # Name Control Function Type RESERVED Bit 7 RESERVED Bit 6 RESERVED Bit 5 RESERVED Bit 4 RW 1outDiv 3 Bit 3 RW 1outDiv 2 Bit 2 1:1 Output Divider RW 1outDiv 1 Bit 1 RW 1outDiv 1 Bit 0 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 0 0 1 Contact IDT for Output Divider Table PWD 0 0 0 0 X X X X 1138C 17 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SMBusTable: Reserved Register Byte 20 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SMBusTable: Test Byte Register Test Type Test Function Byte 21 RW ` ICS ONLY TEST Bit 7 RW ICS ONLY TEST Bit 6 RW ICS ONLY TEST Bit 5 RW ICS ONLY TEST Bit 4 RW ICS ONLY TEST Bit 3 RW ICS ONLY TEST Bit 2 RW ICS ONLY TEST Bit 1 RW ICS ONLY TEST Bit 0 Note: Do NOT write to Bit 21. Erratic device operation will result! IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 0 1 Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 0 0 PWD 0 0 0 0 0 0 0 0 1138C 18 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch Figure 1 1 Differential Routing to PCIe Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch Figure 2 2 Figure 1 Down device routing. L1 L2 L4 Rs L1’ L4’ L2 Rs Rt HSCL Output Buffer L3’ Rt PCI Ex Board Down Device REF_CLK Input L3 Figure 1 Figure 2 PCIe Connector Routing. L1 Rs L1’ L2 L4 L4’ L2’ Rs HSCL Output Buffer Rt L3’ Rt L3 PCI Ex Add In Board REF_CLK Input Figure 2 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 19 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Alternative termination for LVDS and other common differential signals. Figure 3. Vdiff Vp-p 0.45 v 0.22v 0.58 0.28 0.80 0.40 0.60 0.3 R1a = R1b = R1 Vcm 1.08 0.6 0.6 1.2 R1 33 33 33 33 R2 150 78.7 78.7 174 R3 100 137 none 140 R4 100 100 100 100 Note ICS874003i-02 input compatible Standard LVDS Figure_3. L1 R1a L1’ L2 R3 L4 L4’ L2’ R1b R2a HSCL Output Buffer R4 R2b Down Device REF_CLK Input L3 L3’ R2a = R2b = R2 Cable connected AC coupled application, figure 4 Component R5a,R5b R6a,R6b Cc Vcm Value 8.2K 5% 1K 5% 0.1 uF 0.350 volts Note 3.3 Volts R5a R5b L4 L4’ Cc Cc R6a R6b PCIe Device REF_CLK Input Figure_4. IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 20 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 56-Lead, 300 mil Body, 25 mil, SSOP c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D A -Cb In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS A1 e A A1 b c D E E1 e h L N a In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° SEATING PLANE .10 (.004) C N 56 D mm. MIN 18.31 D (inch) MAX 18.55 MIN .720 MAX .730 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 21 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD c N L E1 INDEX AREA E 1 2 a D A A2 A1 -Ce SEATING PLANE b 56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS aaa C N 56 D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 MAX .555 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 Ordering Information Part / Order Number 9FG1200DF-1LF 9FG1200DF-1LFT 9FG1200DG-1LF 9FG1200DG-1LFT Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 56-pin SSOP 56-pin SSOP 56-pin TSSOP 56-pin TSSOP Temperature 0 to +70°C 0 to +70°C 0 to +70°C 0 to +70°C “LF” suffix to the part numbers denotes Pb-Free configuration, RoHS compliant. “D” is the device revision designator (will not correlate with the datasheet revision). IDT® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD 1138C 22 02/08/10 ICS9FG1200D-1 Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD Revision History A B C 12/11/2007 Final Release. 1/21/2009 Update Skew and Phase Jitter tables. 2/8/2010 Updated part ordering information 10,11 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 408-284-6578 [email protected] Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) IDT Singapore Pte. Ltd. 1 Kallang Sector #07-01/06 KolamAyer Industrial Park Singapore 349276 Phone: 65-6-744-3356 Fax: 65-6-744-1764 IDT Europe Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England Phone: 44-1372-363339 Fax: 44-1372-378851 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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