Revision 3 Accelerator Series FPGAs – ACT 3 Family Features • Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates) • Highly Predictable Performance with 100% Automatic Placeand-Route • As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade) • Up to 186 MHz On-Chip Performance (–1 Speed Grade) • Up to 228 User-Programmable I/O Pins • Four Fast, Low-Skew Clock Networks • • • • • • • • • • More than 500 Macro Functions Replaces up to Twenty 32 Macro-Cell CPLDs Replaces up to One Hundred 20-Pin PAL® Packages Up to 1,153 Dedicated Flip-Flops VQFP, TQFP, BGA, and PQFP Packages Nonvolatile, User Programmable Fully Tested Prior to Shipment 5.0 V and 3.3 V Versions Optimized for Logic Synthesis Methodologies Low Power CMOS Technology Table 1 • ACT 3 Family Product Information Device A1415 A1425 A1440 A1460 A14100 Gate Array Equivalent Gates 1,500 2,500 4,000 6,000 10,000 PLD Equivalent Gates 3,750 6,250 10,000 15,000 25,000 Capacity TTL Equivalent Package (40 gates) 40 60 100 150 250 20-Pin PAL Equivalent Packages (100 gates) 15 25 40 60 100 Logic Modules S-Module C-Module 200 310 564 848 1,377 104 160 288 432 697 96 150 276 416 680 Dedicated Flip-Flops1 264 360 568 768 1,153 User I/Os (maximum) 80 100 140 168 228 Maximum Performance2 (worst-case commercial, –1 speed grade) Chip-to-Chip3 (MHz) 80 80 80 78 76 Accumulators (16-bit, MHz) 47 47 47 47 47 Loadable Counter (16-bit, MHz) 82 82 82 82 78 Prescaled Loadable Counters (16-bit, MHz) 186 186 186 150 150 Datapath, Shift Registers (MHz) 186 186 186 150 150 Clock-to-Output (pad-to-pad, ns) 9.0 9.0 9.5 10.0 10.5 PG1005 PL84 PQ100 – VQ100 PG1335 PL84 PQ100, PQ160 – VQ100 – – CQ132 PG1755 PL84 PQ160 – VQ100 TQ176 – – PG207 – PQ160, PQ208 – – TQ176 BG2255 CQ196 PG257 – – RQ208 – – BG313 CQ256 Packages4 (by pin count) CPGA PLCC PQFP RQFP VQFP TQFP BGA CQFP – – – Notes: 1. One flip-flop per S0Module, two flip-flops per I/O Module. 2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1. 3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and Table 1-1 on page 1-2. 4. See the "Product Plan" table on page III for package availability. 5. Discontinued device and package combination. 6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website: PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004 January 2012 © 2012 Microsemi Corporation I Accelerator Series FPGAs – ACT 3 Family Ordering Information A14100 A _ 1 RQ G 208 C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array Speed Grade Std = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Die Revision A = 1.0 mm CMOS Process Part Number A1415A = 1,500 Gates A14V15A = 1,500 Gates (3.3 V) A1425A = 2,500 Gates A14V25A = 2,500 Gates (3.3 V) A1440A = 4,000 Gates A14V40A = 4,000 Gates (3.3 V) A1460A = 6,000 Gates A14V60A = 6,000 Gates (3.3 V) A14100A = 10,000 Gates A14V100A = 10,000 Gates (3.3 V) Notes: 1. The –2 and –3 speed grades have been discontinued. 2. The Ceramic Pin Grid Array packages PG100, PG133, and PG175 have been discontinued in all device densities, speed grades, and temperature grades. 3. The Plastic Ball Grid Array package BG225 has been discontinued in all device densities (specifically for A1460A), all speed grades, and all temperature grades. 4. Military Grade devices are no longer available for the A1440A device. 5. For more information about discontinued devices, refer to the Product Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website: PDN March 2001 PDN 0104 PDN 0203 PDN 0604 PDN 1004 II R ev i si o n 3 Accelerator Series FPGAs – ACT 3 Family Product Plan Speed Grade1 Device/Package Application1 Std. –1 –2 –3 C I M B 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ ✓ D D ✓ ✓ ✓ – 100-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ ✓ – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ ✓ D D ✓ ✓ ✓ – 100-Pin Ceramic Pin Grid Array (CPGA) D D D D D – – – 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ – – – ✓ – – – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ – – – ✓ – – – 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ ✓ D D ✓ ✓ 100-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ – – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ ✓ D D ✓ ✓ – – 132-Pin Ceramic Quad Flatpack (CQFP) ✓ ✓ – – ✓ – ✓ ✓ 133-Pin Ceramic Pin Grid Array (CPGA) D D D D D – D D 160-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ – – 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ – – – ✓ – – – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ – – – ✓ – – – 160-Pin Plastic Quad Flatpack (PQFP) ✓ – – – ✓ – – – 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ ✓ D D ✓ ✓ – – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ ✓ D D ✓ ✓ – – 160-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ – – 175-Pin Ceramic Pin Grid Array (CPGA) D D D D D – – – 176-Pin Thin Quad Flatpack (TQFP) ✓ ✓ D D ✓ ✓ – – Notes: 1. Applications: C = Commercial I = Industrial M = Military 2. Commercial only Availability: ✓ = Available P = Planned – = Not planned D = Discontinued A1415A Device A14V15A Device A1425A Device A14V25A Device A1440A Device R e visi on 3 Speed Grade: –1 = Approx. 15% faster than Std. –2 = Approx. 25% faster than Std. –3 = Approx. 35% faster than Std. (–2 and –3 speed grades have been discontinued.) III Accelerator Series FPGAs – ACT 3 Family Speed Grade1 Device/Package Application1 Std. –1 –2 –3 C I M B 84-Pin Plastic Leaded Chip Carrier (PLCC) ✓ – – – ✓ – – – 100-Pin Very Thin Quad Flatpack (VQFP) ✓ – – – ✓ – – – 160-Pin Plastic Quad Flatpack (PQFP) ✓ – – – ✓ – – – 176-Pin Thin Quad Flatpack (TQFP) ✓ – – – ✓ – – – 160-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ – – 176-Pin Thin Quad Flatpack (TQFP) ✓ ✓ D D ✓ ✓ – – 196-Pin Ceramic Quad Flatpack (CQFP) ✓ ✓ – – ✓ – ✓ ✓ 207-Pin Ceramic Pin Grid Array (CPGA) ✓ ✓ D D ✓ – ✓ ✓ 208-Pin Plastic Quad Flatpack (PQFP) ✓ ✓ D D ✓ ✓ – – 225-Pin Plastic Ball Grid Array (BGA) D D D D D – – – 160-Pin Plastic Quad Flatpack (PQFP) ✓ – – – ✓ – – – 176-Pin Thin Quad Flatpack (TQFP) ✓ – – – ✓ – – – 208-Pin Plastic Quad Flatpack (PQFP) ✓ – – – ✓ – – – 208-Pin Power Quad Flatpack (RQFP) ✓ ✓ D D ✓ ✓ – – 257-Pin Ceramic Pin Grid Array (CPGA) ✓ ✓ D D ✓ – ✓ ✓ 313-Pin Plastic Ball Grid Array (BGA) ✓ ✓ D D ✓ – – – 256-Pin Ceramic Quad Flatpack (CQFP) ✓ ✓ – – ✓ – ✓ ✓ 208-Pin Power Quad Flatpack (RQFP) ✓ – – – ✓ – – – 313-Pin Plastic Ball Grid Array (BGA) ✓ – – – ✓ – – – Notes: 1. Applications: C = Commercial I = Industrial M = Military 2. Commercial only Availability: ✓ = Available P = Planned – = Not planned D = Discontinued A14V40A Device A1460A Device A14V60A Device A14100A Device A14V100A Device IV R ev i si o n 3 Speed Grade: –1 = Approx. 15% faster than Std. –2 = Approx. 25% faster than Std. –3 = Approx. 35% faster than Std. (–2 and –3 speed grades have been discontinued.) Accelerator Series FPGAs – ACT 3 Family Plastic Device Resources User I/Os Device Series Logic Modules Gates PL84 PQ100 PQ160 PQ/RQ208 VQ100 TQ176 BG225* BG313 A1415 200 1500 70 80 – – 80 – – – A1425 310 2500 70 80 100 – 83 – – – A1440 564 4000 70 – 131 – 83 140 – – A1460 848 6000 – – 131 167 – 151 168 – A14100 1377 10000 – – – 175 – – – 228 Note: *Discontinued Hermetic Device Resources User I/Os Device Series Logic Modules Gates PG100* PG133* PG175* PG207 PG257 CQ132 CQ196 CQ256 A1415 200 1500 80 – – – – – – – A1425 310 2500 – 100 – – – 100 – – A1440 564 4000 – – 140 – – – – – A1460 848 6000 – – – 168 – – 168 – A14100 1377 10000 – – – – 228 – – 228 Note: *Discontinued Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. R e visi on 3 V Table of Contents ACT 3 Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Detailed Specifications Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 ACT 3 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 Package Pin Assignments PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 PQ208, RQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 CQ132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 CQ196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 BG313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 PG133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 PG175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 PG207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 PG257 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 VI Revision 3 1 – ACT 3 Family Overview General Description Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade), with capacities spanning from 1,500 to 10,000 gate array equivalent gates. The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high fanout signals such as flip-flop resets and output. The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user programming, and debug and diagnostic probe capabilities. Accumulators (16-Bit) 47 MHz Loadable Counters (16-Bit) Figure 1-1 • 82 MHz Prescaled Loadable Counters (16-Bit) 186 MHz Shift Registers 186 MHz Predictable Performance (worst-case commercial, –1 speed grade) System Performance Model Chip #1 I/O Module Chip #2 I/O Module 35 pF I/O CLK I/O CLK tCKHS tTRACE Revision 3 tINSU 1 -1 ACT 3 Family Overview Table 1-1 • Chip-to-Chip Performance (worst-case commercial) Device and Speed Grade tCKHS (ns) tTRACE (ns) tINSU (ns) Total (ns) MHz A1425A -3 7.5 1.0 1.8 10.3 97 A1460A -3 9.0 1.0 1.3 11.3 88 A1425A -2 7.5 1.0 2.0 10.5 95 A1460A -2 9.0 1.0 1.5 11.5 87 A1425A -1 9.0 1.0 2.3 12.3 81 A1460A -1 10.0 1.0 1.8 12.8 78 A1425A STD 10.0 1.0 2.7 13.7 73 A1460A STD 11.5 1.0 2.0 14.5 69 Note: The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 1-2 R e vi s i o n 3 2 – Detailed Specifications This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. Topology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 2-1. An Array with n rows and m columns 0 Rows 1 2 3 4 5 c–1 c c+1 m m+1 m+2 m+3 Columns Channels n+2 IO n+1 IO IO CLKM IO IO IO IO IO IO Top I/Os n+1 n IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO IO IO IO IO IO IO IO IO Right I/Os Bottom I/Os n n–1 • • • 2 n–1 • • • 2 1 1 Left I/Os 0 BIO IO 0 Figure 2-1 • Generalized Floor Plan of ACT 3 Device Revision 3 2 -1 Detailed Specifications Logic Modules ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL family, there are two types of modules: C-modules and S-modules (Figure 2-2 and Figure 2-3). The Cmodule is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The S-module is designed to implement high-speed sequential functions within a single module. D00 D01 OUT Y D10 D11 Figure 2-2 • S1 S0 A1 B1 A0 B0 C-Module Diagram D00 D01 D10 Y D Q OUT D11 S1 S0 A1 B1 A0 B0 CLK Figure 2-3 • CLR S-Module Diagram S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are arranged in alternating patterns and make up the bulk of the array. This arrangement allows the placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module implements the following function: Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 EQ 1 where: S0 = A0 * B0 and S1 = A1 + B1 2-2 R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to be implemented with no delay penalty. The Designer Series Development System will automatically combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic module and eliminating a module delay. The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a multiplexer select at the clock input to the S-module. I/Os I/O Modules I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in the array and access the routing channels in a similar fashion to logic modules. The I/O module schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver. D 0 MUX 1 Q DATAOUT CLR/PRE ODE Y D 0 MUX 1 0 S0 S1 1 MUX 2 3 Q D 1 MUX 0 DATAIN CLR/PRE IOPCL IOCLK Figure 2-4 • Functional Diagram for I/O Module Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock (IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be selected individually on an I/O module by I/O module basis. Revision 3 2 -3 Detailed Specifications The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into the array. This allows the output register to be used in high-speed state machine applications. Side I/O modules have a dedicated output segment for Y extending into the routing channels above and below (similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained in detail in the routing section). I/O Pad Drivers All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN (global input enable), and SLEW (individual slew selection). See Figure 2-5. OE SLEW DATAOUT PAD DATAIN IEN INEN OUTEN Figure 2-5 • Function Diagram for I/O Pad Driver Special I/Os The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change once the device has been programmed. The permanent special I/Os consist of the array clock input buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is determined by the I/O macros selected. Clock Networks The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks and two general purpose routed networks. The high-performance networks function up to 200 MHz, while the general purpose routed networks function up to 150 MHz. 2-4 R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family Dedicated Clocks Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by special I/Os. CLKB CLKINB CLKA CLKINA FROM PADS CLKMOD S0 S1 INTERNAL SIGNAL CLKO(17) CLOCK DRIVERS CLKO(16) CLKO(15) CLKO(2) CLKO(1) CLOCK TRACKS Figure 2-6 • Clock Networks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6): • Externally from the CLKA pad • Externally from the CLKB pad • Internally from the CLKINA input • Internally from the CLKINB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The function of the clock module is determined by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like resets, output enables, or data enables. This saves logic modules and results in performance increases in some cases. Routing Structure The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. Revision 3 2 -5 Detailed Specifications Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 2-7. Undedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Module Row HCLK CLK0 NVCC SIGNAL Track Segment SIGNAL (LHT) | | | | | | | HF SIGNAL NVSS CLK1 Module Row Figure 2-7 • Horizontal Routing Tracks and Segments Vertical Routing Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 2-8. LVTs Module Row C-Module S-Module VF Channel XF Vertical Input Segment FF S-Module Figure 2-8 • 2-6 Vertical Routing Tracks and Segments R e vi s i o n 3 C-Module Accelerator Series FPGAs – ACT 3 Family Antifuse Connections An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as an efficient programming architecture. The structure is highly testable because there are no preexisting connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical structure of the antifuse is identical in each case; only the usage differs.) Table 2-1 shows four types of antifuses. Table 2-1 • Antifuse Types Type Description XF Horizontal-to-vertical connection HF Horizontal-to-horizontal connection VF Vertical-to-vertical connection FF "Fast" vertical connection Examples of all four types of connections are shown in Figure 2-7 on page 2-6 and Figure 2-8 on page 2-6. Module Interface Connections to Logic and I/O modules are made through vertical segments that connect to the module inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array. Module Input Connections The tracks dedicated to module inputs are segmented by pass transistors in each module row. During normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the inputs of the module directly above or below it. During certain test modes, the pass transistors are active to verify the continuity of the metal tracks. Vertical input segments span only the channel above or the channel below. The logic modules are arranged such that half of the inputs are connected to the channel above and half of the inputs to segments in the channel below, as shown in Figure 2-9. Y+2 Y+2 Y+1 B1 B0 D01 D00 A1 D10 D11 A0 Y+1 Y-1 D10 B1 D01 A0 D11 A1 Y-1 Y-2 Y-2 LVTs S-Modules Figure 2-9 • B0 Y Y C-Modules Logic Module Routing Interface Revision 3 2 -7 Detailed Specifications Module Output Connections Module outputs have dedicated output segments. Output segments extend vertically two channels above and two channels below, except at the top or bottom of the array. Output segments twist, as shown in Figure 10, so that only four vertical tracks are required. LVT Connections Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module pair in the array shares four LVTs that span the length of the column. Any module in the column pair can connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses connected directly to the driver stage of the module output, bypassing the isolation transistor. FF antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower resistance value. Antifuse Connections In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed antifuse (XF-type). One exception is in the case of the clock networks. Clock Connections To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a few of the C-module and S-module inputs can be connected to the clock networks. To further reduce loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock inputs of the S-module. Programming and Test Circuits The array of logic and I/O modules is surrounded by test and programming circuits controlled by the temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family devices. The ACT 3 family also includes support for two Actionprobe® circuits, allowing complete observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB. 2-8 R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family 5 V Operating Conditions Table 2-2 • Absolute Maximum Ratings1, Free Air Temperature Range Symbol Parameter VCC DC supply voltage VI Input voltage VO Output voltage Limits Units –0.5 to +7.0 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V ±20 mA –65 to +150 °C current2 IIO I/O source sink TSTG Storage temperature Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the recommended operating conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive current. Table 2-3 • Recommended Operating Conditions Parameter Temperature range* 5 V power supply tolerance Commercial Industrial Military Units 0 to +70 –40 to +85 –55 to +125 °C ±5 ±10 ±10 %VCC Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Table 2-4 • Electrical Specifications Commercial Symbol 1,2 VOH Parameter High level output VOL1,2 Low level output Test Condition Industrial Military Min. Max. Min. Max. Min. Max. Units IOH = –4 mA (CMOS) – – 3.7 – 3.7 – V IOH = –6 mA (CMOS) 3.84 V IOH = –10 mA (TTL)3 2.40 V IOL = +6 mA (CMOS) 0.33 3 0.50 IOL = +12 mA (TTL) 0.4 0.4 V VIH High level input TTL inputs 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Low level input TTL inputs –0.3 0.8 –0.3 0.8 –0.3 0.8 V IIN Input leakage VI = VCC or GND –10 +10 –10 +10 –10 +10 µA IOZ 3-state output leakage VO = VCC or GND –10 +10 –10 +10 –10 +10 µA CIO 3,4 I/O capacitance ICC(S) Standby VCC supply current (typical = 0.7 mA) 10 10 10 pF 2 10 20 mA ICC(D) Dynamic VCC supply current. See the Power Dissipation section. Notes: 1. Microsemi devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time, VCC = minimum. 3. Not tested; for information only. 4. VOUT = 0 V, f = 1 MHz 5. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = VCC or GND. Revision 3 2 -9 Detailed Specifications 3.3 V Operating Conditions Table 2-5 • Absolute Maximum Ratings1, Free Air Temperature Range Symbol Parameter VCC DC supply voltage VI Input voltage VO Output voltage Limits Units –0.5 to +7.0 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V ±20 mA –65 to +150 °C current2 IIO I/O source sink TSTG Storage temperature Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the recommended operating conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive current. Table 2-6 • Recommended Operating Conditions Parameter Commercial Units Temperature range* 0 to +70 °C Power supply tolerance 3.0 to 3.6 V Note: *Ambient temperature (TA) is used for commercial. Table 2-7 • Electrical Specifications Commercial Parameter 1 VOH VOL1 Min. Max. Units IOH = –4 mA 2.15 – V IOH = –3.2 mA 2.4 0.4 V –0.3 0.8 V 2.0 VCC + 0.3 V –10 +10 µA 10 pF 0.75 mA 10 µA IOL = 6 mA VIL VIH Input transition time tR, tF2 VI = VCC or GND CIO I/O Capacitance2,3 4 Standby current, ICC (typical = 0.3 mA) 5 –10 Leakage current 1. 2. 3. 4. 5. Only one output tested at a time. VCC = minimum. Not tested; for information only. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f - 1 MHz. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. VO, VIN = VCC or GND 2- 10 R e visio n 3 V Accelerator Series FPGAs – ACT 3 Family Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at commercial temperature and still air is as follows: 150°C – 70°C Max. junction temp. (°C) – Max. ambient temp. (°C)-------------------------------------------------------------------------------------------------------------------------------------= ------------------------------------ = 3.2 W 25°C/W θ ja °C/W EQ 2 Table 2-8 • Package Thermal Characteristics Pin Count θjc θja Still Air θja 300 ft./min. Units 100 20 35 17 °C/W 133 20 30 15 °C/W 175 20 25 14 °C/W 207 20 22 13 °C/W 257 20 15 8 °C/W 132 13 55 30 °C/W 196 13 36 24 °C/W 256 13 30 18 °C/W 100 13 51 40 °C/W 160 10 33 26 °C/W 208 10 33 26 °C/W Very Thin Quad Flatpack 100 12 43 35 °C/W Thin Quad Flatpack 176 11 32 25 °C/W Power Quad Flatpack 208 0.4 17 13 °C/W Plastic Leaded Chip Carrier 84 12 37 28 °C/W Plastic Ball Grid Array 225 10 25 19 °C/W 313 10 23 17 °C/W Package Type* Ceramic Pin Grid Array Ceramic Quad Flatpack Plastic Quad Flatpack Note: Maximum power dissipation in still air: PQ160 = 2.4 W PQ208 = 2.4 W PQ100 = 1.6 W VQ100 = 1.9 W TQ176 = 2.5 W PL84 = 2.2 W RQ208 = 4.7 W BG225 = 3.2 W BG313 = 3.5 W Revision 3 2- 11 Detailed Specifications Power Dissipation P = [ICC standby + Iactive] * VCC * IOL * VOL * N + IOH* (VCC – VOH) * M EQ 3 where: ICC standby is the current flowing when no inputs or outputs are changing Iactive is the current flowing due to CMOS switching. IOL and IOH are TTL sink/source current. VOL and VOH are TTL level output voltages. N is the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the design and on the system I/O. The power can be divided into two components: static and active. Static Power Component Microsemi FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated in Table 2-9 for commercial, worst case conditions. Table 2-9 • Standby Power Calculation ICC 2 mA VCC Power 5.25 V 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by EQ 4. Power (µW) = CEQ * VCC2 * F EQ 4 Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. 2- 12 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown in Figure 2-10. Table 2-10 • CEQ Values for Microsemi FPGAs Item CEQ Value Modules (CEQM) 6.7 Input Buffers (CEQI) 7.2 Output Buffers (CEQO) 10.4 Routed Array Clock Buffer Loads (CEQCR) 1.6 Dedicated Clock Buffer Loads (CEQCD) 0.7 I/O Clock Buffer Loads (CEQCI) 0.9 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. EQ 5 shows a piece-wise linear summation over all components. Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk] EQ 5 Where: m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock r1 = Fixed capacitance due to first routed array clock r2 = Fixed capacitance due to second routed array clock s1 = Fixed number of clock loads on the dedicated array clock s2 = Fixed number of clock loads on the dedicated I/O clock CEQM = Equivalent capacitance of logic modules in pF CEQI = Equivalent capacitance of input buffers in pF CEQO = Equivalent capacitance of output buffers in pF CEQCR = Equivalent capacitance of routed array clock in pF CEQCD = Equivalent capacitance of dedicated array clock in pF CEQCI = Equivalent capacitance of dedicated I/O clock in pF CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz fs1 = Average dedicated array clock rate in MHz fs2 = Average dedicated I/O clock rate in MHz Revision 3 2- 13 Detailed Specifications Table 2-11 • Fixed Capacitance Values for Microsemi FPGAs Device Type r1, routed_Clk1 r2, routed_Clk2 A1415A 60 60 A14V15A 57 57 A1425A 75 75 A14V25A 72 72 A1440A 105 105 A14V40A 100 100 A1440B 105 105 A1460A 165 165 A14V60A 157 157 A1460B 165 165 A14100A 195 195 A14V100A 185 185 A14100B 195 195 s1, Clock Loads on Dedicated Array Clock s2, Clock Loads on Dedicated I/O Clock A1415A 104 80 A14V15A 104 80 A1425A 160 100 A14V25A 160 100 A1440A 288 140 A14V40A 288 140 A1440B 288 140 A1460A 432 168 A14V60A 432 168 A1460B 432 168 A14100A 697 228 A14V100A 697 228 A14100B 697 228 Table 2-12 • Fixed Clock Loads (s1/s2) Device Type 2- 14 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Table 2-13 • Guidelines for Predicting Power Dissipation Data Value Logic Modules (m) 80% of modules Inputs switching (n) # inputs/4 Outputs switching (p) # output/4 First routed array clock loads (q1) 40% of sequential modules Second routed array clock loads (q2) 40% of sequential modules Load capacitance (CL) 35 pF Average logic module switching rate (fm) F/10 Average input switching rate (fn) F/5 Average output switching rate (fp) F/10 Average first routed array clock rate (fq1) F/2 Average second routed array clock rate (fq2) F/2 Average dedicated array clock rate (fs1) F Average dedicated I/O clock rate (fs2) F Revision 3 2- 15 Detailed Specifications ACT 3 Timing Model Input Delays I/O Module tINY = 3.6 ns Internal Delays Combinatorial Logic Module Predicted Routing Delays Output Delays I/O Module tIRD2 = 1.6 ns tDHS = 6.4 ns D Q tINH = 0.0 ns tINSU = 2.3 ns tICKY = 6.0 ns tRD1 = 1.1 ns tRD4 = 2.2 ns tRD8 = 3.6 ns tPD = 2.6 ns I/O Module tDHS = 6.4 ns Sequential Logic Module Comb. Logic Included D D Q tRD1 = 1.1 ns in tSUD ARRAY CLOCK tHCKH = 3.9 ns tSUD = 0.7 ns tHD = 0.0 ns tCO = 2.6 ns FHMAX = 150 MHz I/O CLOCK tCKHS = 9.0 ns (pad-pad) FIOMAX = 150 MHz Note: Values shown for A1425A –1 speed grade device. Figure 2-10 • Timing Model 2- 16 R e visio n 3 Q tENZHS = 5.1 ns tOUTH = 0.9 ns tOUTSU = 0.9 ns Accelerator Series FPGAs – ACT 3 Family E D VCC In 50% Out VOL 50% VOH PAD To AC test loads (shown below) TRIBUFF VCC GND En 1.5 V 1.5 V 50% VCC VCC GND 50% 1.5 V Out 10% VOL tDHS, tENZHS, tDHS En 50% Out GND 50% VOH 90% 1.5 V tENZHS, tENHSZ GND tENHSZ Figure 2-11 • Output Buffers Load 2 (Used to measure rising/falling edges) Load 1 (Used to measure propagation delay) VCC GND To the output under test 35 pF To the output under test R to VCCfor tPLZ / tPZL R to GND for tPHZ / tPZH R = 1 kΩ 35 pF Figure 2-12 • AC Test Loads PAD Y INBUF 3V In 0V 1.5 V 1.5 V VCC Out GND 50% 50% tINY tINY Figure 2-13 • Input Buffer Delays Revision 3 2- 17 Detailed Specifications S A B Y VCC S, A or B 50% 50% VCC Out GND 50% GND 50% tPD tPD VCC Out GND 50% tPD 50% tPD Figure 2-14 • Module Delays Flip-Flops D CLK Q CLR (Positive edge triggered) tHD D tSUD tA tWCLKA CLK tWCLKA tCO Q tCLR CLR tWASYN Figure 2-15 • Sequential Module Timing Characteristics 2- 18 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family D E Y PRE IOCLK CLR (Positive edge triggered) tINH D tIOP tIOPWH tINSU IOCLK tIDESU tIOPWL tIDEH E tICKY Y tICLRY PRE, CLR tIOASPW Figure 2-16 • I/O Module: Sequential Input Timing Characteristics D E Q PRE IOCLK CLR Y (Positive edge triggered) tOUTH D tOUTSU tIOP tIOPWH IOCLK tODESU tIOPWL tODEH E tOCKY Y tCKHS, tCKLS Q tOCLRY PRE, CLR tIOASPW Figure 2-17 • I/O Module: Sequential Output Timing Characteristics Revision 3 2- 19 Detailed Specifications Tightest Delay Distributions Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Microsemi’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3 family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200Ω resistance and 6 femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects using only two antifuses. The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can be traded for the increased performance of reduced logic level designs. This also simplifies performance estimates when designing with ACT 3 devices. Table 2-14 • Logic Module and Routing Delay by Fanout (ns); Worst-Case Commercial Conditions Speed Grade FO = 1 FO = 2 FO = 3 FO = 4 FO = 8 ACT 3 –3 2.9 3.2 3.4 3.7 4.8 ACT 3 –2 3.3 3.7 3.9 4.2 5.5 ACT 3 –1 3.7 4.2 4.4 4.8 6.2 ACT 3 STD 4.3 4.8 5.1 5.5 7.2 Notes: 1. Obtained by added tRD(x=FO) to tPD from the Logic Module Timing Characteristics Tables found in this datasheet. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. Timing Characteristics Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ACT 3 family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design is complete. Delay values may then be determined by using the ALS Timer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, result ng in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout (FO = 8) routing delays in the datasheet specifications section. 2- 20 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family Timing Derating ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. Table 2-15 • Timing Derating Factor (Temperature and Voltage) (Commercial Minimum/Maximum Specification) x Industrial Military Min. Max. Min. 0.66 1.07 0.63 Max. 1.17 Table 2-16 • Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C) and Voltage (5.0 V) (Commercial Maximum Specification) x 0.85 Table 2-17 • Temperature and Voltage Derating Factors (normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C) –55 –40 0 25 70 85 125 4.50 0.72 0.76 0.85 0.90 1.04 1.07 1.117 4.75 0.70 0.73 0.82 0.87 1.00 1.03 1.12 5.00 0.68 0.71 0.79 0.84 0.97 1.00 1.09 5.25 0.66 0.69 0.77 0.82 0.94 0.97 1.06 5.50 0.63 0.66 0.74 0.79 0.90 0.93 1.01 1.20 Derating Factor 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50 Voltage (V) Note: This derating factor applies to all routing and propagation delays. Figure 2-18 • Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C) Revision 3 2- 21 Detailed Specifications A1415A, A14V15A Timing Characteristics Table 2-18 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1 Logic Module Propagation Delays2 –3 Speed3 –2 Speed3 Parameter/Description Min. Max. Min. Max. Min. Max. –1 Speed Std. Speed 3.3 V Speed1 Units Min. Max. Min. Max. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns 4 Predicted Routing Delays tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3 V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 3. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed below: PDN March 2001 PDN 0104 PDN 0203 PDN 0604 PDN 1004 4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2- 22 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1415A, A14V15A Timing Characteristics (continued) Table 2-19 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed2 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Output Asynchronous Clear to Y Predicted Input Routing Delays2 tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing (wrt IOCLK pad) tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns tINSU Input F-F Data Setup 2.0 2.3 2.5 3.0 3.0 ns tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns tOUTH 0.7 0.8 0.9 1.0 1.0 ns 0.7 0.8 0.9 1.0 1.0 ns 0.3 0.4 0.4 0.5 0.5 ns 1.3 1.5 1.7 2.0 2.0 ns Output F-F Data hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold fODESU Output Data Enable Setup Notes: 1. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed below: PDN March 2001 PDN 0104 PDN 0203 PDN 0604 PDN 1004 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Revision 3 2- 23 Detailed Specifications A1415A, A14V15A Timing Characteristics (continued) Table 2-20 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module – TTL Output Timing1 –3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 6.5 7.5 8.5 10.0 13.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 6.5 7.5 8.5 10.0 13.0 ns tCKHS IOCLK Pad to Pad H/L, High Slew 7.5 7.5 9.0 10.0 13.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, High Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 6.7 7.5 8.5 10.0 13.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 6.7 7.5 9.0 10.0 13.0 ns tCKHS IOCLK Pad to Pad H/L, High Slew 8.9 8.9 10.7 11.8 15.3 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, High Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.04 0.05 0.07 ns/pF Notes: 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed below: PDN March 2001 PDN 0104 PDN 0203 PDN 0604 PDN 1004 2- 24 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1415A, A14V15A Timing Characteristics (continued) Table 2-21 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C Dedicated (hardwired) I/O Clock Network –3 Speed –2 Speed –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tIOCKH Input Low to High (pad to I/O module input) tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIPOWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 2.0 2.3 0.4 4.0 2.6 0.4 5.0 3.0 0.4 6.8 3.5 0.4 8.0 0.4 10.0 ns ns ns 250 200 150 125 100 MHz Dedicated (hardwired) Array Clock tHCKH Input Low to High (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHCKL Input High to Low (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Delta High to Low, Low Slew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO = 64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO = 64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL Min. Pulse Width Low (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRCKSW Maximum Skew (FO = 128) tRP Minimum Period (FO = 64) fRMAX Maximum Frequency (FO = 64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 3.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 50% maximum) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 0.0 3.0 3.0 ns Notes: 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. Revision 3 2- 25 Detailed Specifications A1425A, A14V25A Timing Characteristics Table 2-22 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1 Logic Module Propagation Delays2 –3 Speed3 –2 Speed3 Parameter/Description Min. Max. Min. Max. Min. Max. –1 Speed Std. Speed 3.3 V Speed1 Units Min. Max. Min. Max. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns 4 Predicted Routing Delays tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3 V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2- 26 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1425A, A14V25A Timing Characteristics (continued) Table 2-23 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Output Asynchronous Clear to Y Predicted Input Routing Delays2 tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing (wrt IOCLK pad) tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns tINSU Input F-F Data Setup 1.8 2.0 2.3 2.7 3.0 ns tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns tOUTH 0.7 0.8 0.9 1.0 1.0 ns 0.7 0.8 0.9 1.0 1.0 ns 0.3 0.4 0.4 0.5 0.5 ns 1.3 1.5 1.7 2.0 2.0 ns Output F-F Data hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold fODESU Output Data Enable Setup Notes: * 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Revision 3 2- 27 Detailed Specifications A1425A, A14V25A Timing Characteristics (continued) Table 2-24 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module – TTL Output Timing1 –3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 6.5 7.5 8.5 10.0 13.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 6.5 7.5 8.5 10.0 13.0 ns tCKHS IOCLK Pad to Pad H/L, High Slew 7.5 7.5 9.0 10.0 13.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, High Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 6.7 7.5 8.5 10.0 13.0 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 6.7 7.5 9.0 10.0 13.0 ns tCKHS IOCLK Pad to Pad H/L, High Slew 8.9 8.9 10.7 11.8 15.3 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, High Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.04 0.05 0.07 ns/pF Notes: * 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2- 28 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1425A, A14V25A Timing Characteristics (continued) Table 2-25 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C Dedicated (hardwired) I/O Clock Network –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tIOCKH Input Low to High (pad to I/O module input) tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIPOWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 2.0 2.3 0.4 4.0 2.6 0.4 5.0 3.0 0.4 6.8 3.5 0.4 8.0 0.4 10.0 ns ns ns 250 200 150 125 100 MHz Dedicated (hardwired) Array Clock tHCKH Input Low to High (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHCKL Input High to Low (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Delta High to Low, Low Slew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO = 64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO = 64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL Min. Pulse Width Low (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRCKSW Maximum Skew (FO = 128) tRP Minimum Period (FO = 64) fRMAX Maximum Frequency (FO = 64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns Notes: 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Delays based on 35 pF loading. Revision 3 2- 29 Detailed Specifications A1440A, A14V40A Timing Characteristics Table 2-26 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1 Logic Module Propagation Delays2 –3 Speed 3 –2 Speed3 Parameter/Description Min. Max. Min. Max. Min. Max. –1 Speed Std. Speed 3.3 V Speed1 Units Min. Max. Min. Max. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns 4 Predicted Routing Delays tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3 V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2- 30 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1440A, A14V40A Timing Characteristics (continued) Table 2-27 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Output Asynchronous Clear to Y Predicted Input Routing Delays2 tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing (wrt IOCLK pad) tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns tINSU Input F-F Data Setup 1.8 1.7 2.0 2.3 2.3 ns tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns tOUTH 0.7 0.8 0.9 1.0 1.0 ns 0.7 0.8 0.9 1.0 1.0 ns 0.3 0.4 0.4 0.5 0.5 ns 1.3 1.5 1.7 2.0 2.0 ns Output F-F Data hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold fODESU Output Data Enable Setup Notes: 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Revision 3 2- 31 Detailed Specifications A1440A, A14V40A Timing Characteristics (continued) Table 2-28 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module – TTL Output Timing1 –3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 7.4 8.3 9.4 11.0 14.3 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 8.5 8.5 9.5 11.0 14.3 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, High Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 7.4 8.3 9.4 11.0 14.3 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 9.0 9.0 10.1 11.8 14.3 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, High Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.04 0.05 0.07 ns/pF Notes: 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2- 32 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1440A, A14V40A Timing Characteristics (continued) Table 2-29 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C Dedicated (hardwired) I/O Clock Network –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tIOCKH Input Low to High (pad to I/O module input) tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIPOWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 2.0 2.3 0.4 4.0 2.6 0.4 5.0 3.0 0.4 6.8 3.5 0.4 8.0 0.4 10.0 ns ns ns 250 200 150 125 100 MHz Dedicated (hardwired) Array Clock tHCKH Input Low to High (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHCKL Input High to Low (pad to S-module input) 3.0 3.4 3.9 4.5 5.5 ns tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Delta High to Low, Low Slew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO = 64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO = 64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL Min. Pulse Width Low (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns tRCKSW Maximum Skew (FO = 128) tRP Minimum Period (FO = 64) fRMAX Maximum Frequency (FO = 64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns Notes: 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Delays based on 35 pF loading. Revision 3 2- 33 Detailed Specifications A1460A, A14V60A Timing Characteristics Table 2-30 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1 Logic Module Propagation Delays2 –3 Speed3 –2 Speed 3 Parameter/Description Min. Max. Min. Max. Min. Max. –1 Speed Std. Speed 3.3 V Speed1 Units Min. Max. Min. Max. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns 4 Predicted Routing Delays tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tWCLKA Flip-Flop Clock Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tA Flip-Flop Clock Input Period 5.0 6.8 8.0 10.0 13.4 ns fMAX Flip-Flop Clock Frequency 200 150 125 100 75 MHz Notes: 1. VCC = 3.0 V for 3.3 V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2- 34 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1460A, A14V60A Timing Characteristics (continued) Table 2-31 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Output Asynchronous Clear to Y Predicted Input Routing Delays2 tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing (wrt IOCLK pad) tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns tINSU Input F-F Data Setup 1.3 1.5 1.8 2.0 2.0 ns tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns tOUTH 0.7 0.8 0.9 1.0 1.0 ns 0.7 0.8 0.9 1.0 1.0 ns 0.3 0.4 0.4 0.5 0.5 ns 1.3 1.5 1.7 2.0 2.0 ns Output F-F Data hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold fODESU Output Data Enable Setup Notes: 5. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 6. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Revision 3 2- 35 Detailed Specifications A1460A, A14V60A Timing Characteristics (continued) Table 2-32 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module – TTL Output Timing1 –3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 7.8 8.7 9.9 11.6 15.1 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 9.0 9.0 10.0 11.5 15.0 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 12.8 12.8 15.3 17.0 22.1 ns dTLHHS Delta Low to High, High Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 7.4 8.3 9.4 11.0 14.3 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 10.4 10.4 12.1 13.8 17.9 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 14.5 14.5 17.4 19.3 25.1 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, High Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.04 0.05 0.07 ns/pF Notes: 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2- 36 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A1460A, A14V60A Timing Characteristics (continued) Table 2-33 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C Dedicated (hardwired) I/O Clock Network –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tIOCKH Input Low to High (pad to I/O module input) tIOPWH Minimum Pulse Width High 2.4 3.2 3.8 4.8 6.5 ns tIPOWL Minimum Pulse Width Low 2.4 3.2 3.8 4.8 6.5 ns tIOSAPW Minimum Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 2.3 2.6 0.6 5.0 3.0 0.6 6.8 3.5 0.6 8.0 4.5 0.6 10.0 0.6 13.4 ns ns ns 200 150 125 100 75 MHz Dedicated (hardwired) Array Clock tHCKH Input Low to High (pad to S-module input) 3.7 4.1 4.7 5.5 7.0 ns tHCKL Input High to Low (pad to S-module input) 3.7 4.1 4.7 5.5 7.0 ns tHPWH Minimum Pulse Width High 2.4 3.2 3.8 4.8 6.5 ns tHPWL Minimum Pulse Width Low 2.4 3.2 3.8 4.8 6.5 ns tHCKSW Delta High to Low, Low Slew tHP Minimum Period fHMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.6 8.0 0.6 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Routed Array Clock Networks tRCKH Input Low to High (FO = 64) 6.0 6.8 7.7 9.0 11.8 ns tRCKL Input High to Low (FO = 64) 6.0 6.8 7.7 9.0 11.8 ns tRPWH Min. Pulse Width High (FO = 64) 4.1 4.5 5.4 6.1 8.2 ns tRPWL Min. Pulse Width Low (FO = 64) 4.1 4.5 5.4 6.1 8.2 ns tRCKSW Maximum Skew (FO = 128) tRP Minimum Period (FO = 64) fRMAX Maximum Frequency (FO = 64) 1.2 8.3 1.4 9.3 120 1.6 11.1 105 1.8 12.5 90 1.8 16.7 80 ns ns 60 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 216) 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 216) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns Notes: 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Delays based on 35 pF loading. Revision 3 2- 37 Detailed Specifications A14100A, A14V100A Timing Characteristics Table 2-34 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1 Logic Module Propagation Delays2 –3 Speed3 –2 Speed 3 Parameter/Description Min. Max. Min. Max. Min. Max. –1 Speed Std. Speed 3.3 V Speed1 Units Min. Max. Min. Max. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns 4 Predicted Routing Delays tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.8 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.5 0.5 0.5 ns tSUD Latch Data Input Setup 0.5 0.6 0.8 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.5 0.5 0.5 ns tWASYN Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tWCLKA Flip-Flop Clock Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tA Flip-Flop Clock Input Period 5.0 6.8 8.0 10.0 13.4 ns fMAX Flip-Flop Clock Frequency 200 150 125 100 75 MHz Notes: 1. VCC = 3.0 V for 3.3 V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2- 38 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A14100A, A14V100A Timing Characteristics (continued) Table 2-35 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Output Asynchronous Clear to Y Predicted Input Routing Delays2 tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing (wrt IOCLK pad) tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns tINSU Input F-F Data Setup 1.2 1.4 1.5 1.8 1.8 ns tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns tOUTH 0.7 0.8 1.0 1.0 1.0 ns 0.7 0.8 1.0 1.0 1.0 ns 0.3 0.4 0.5 0.5 0.5 ns 1.3 1.5 2.0 2.0 2.0 ns Output F-F Data hold tOUTSU Output F-F Data Setup tODEH Output Data Enable Hold fODESU Output Data Enable Setup Notes: * 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. Revision 3 2- 39 Detailed Specifications A14100A, A14V100A Timing Characteristics (continued) Table 2-36 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C I/O Module – TTL Output Timing1 –3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 8.0 9.0 10.2 12.0 15.6 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 9.5 9.5 10.5 12.0 15.6 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 12.8 12.8 15.3 17.0 22.1 ns dTLHHS Delta Low to High, High Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, High Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns tENHSZ Enable to Pad, H/L to Z, High Slew 8.0 9.0 10.0 12.0 15.6 ns tENLSZ Enable to Pad, H/L to Z, Low Slew 7.4 8.3 9.4 11.0 14.3 ns tCKHS IOCLK Pad to Pad H/L, High Slew 10.4 10.4 12.4 13.8 17.9 ns tCKLS IOCLK Pad to Pad H/L, Low Slew 14.5 14.5 17.4 19.3 25.1 ns dTLHHS Delta Low to High, High Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, High Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.04 0.05 0.07 ns/pF Notes: * 1. Delays based on 35 pF loading. 2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2- 40 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family A14100A, A14V100A Timing Characteristics (continued) Table 2-37 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C Dedicated (hardwired) I/O Clock Network –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. tIOCKH Input Low to High (pad to I/O module input) tIOPWH Minimum Pulse Width High 2.4 3.3 3.8 4.8 6.5 ns tIPOWL Minimum Pulse Width Low 2.4 3.3 3.8 4.8 6.5 ns tIOSAPW Minimum Asynchronous Pulse Width 2.4 3.3 3.8 4.8 6.5 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 2.3 2.6 0.6 5.0 3.0 0.6 6.8 3.5 0.7 8.0 4.5 0.8 10.0 0.6 13.4 ns ns ns 200 150 125 100 75 MHz Dedicated (hardwired) Array Clock tHCKH Input Low to High (pad to S-module input) 3.7 4.1 4.7 5.5 7.0 ns tHCKL Input High to Low (pad to S-module input) 3.7 4.1 4.7 5.5 7.0 ns tHPWH Minimum Pulse Width High 2.4 3.3 3.8 4.8 6.5 ns tHPWL Minimum Pulse Width Low 2.4 3.3 3.8 4.8 6.5 ns tHCKSW Delta High to Low, Low Slew tHP Minimum Period fHMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.7 8.0 0.8 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Routed Array Clock Networks tRCKH Input Low to High (FO = 64) 6.0 6.8 7.7 9.0 11.8 ns tRCKL Input High to Low (FO = 64) 6.0 6.8 7.7 9.0 11.8 ns tRPWH Min. Pulse Width High (FO = 64) 4.1 4.5 5.4 6.1 8.2 ns tRPWL Min. Pulse Width Low (FO = 64) 4.1 4.5 5.4 6.1 8.2 ns tRCKSW Maximum Skew (FO = 128) tRP Minimum Period (FO = 64) fRMAX Maximum Frequency (FO = 64) 1.2 8.3 1.4 9.3 120 1.6 11.1 105 1.8 12.5 90 1.8 16.7 80 ns ns 60 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 350) 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 350) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns Notes: * 1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn. 2. Delays based on 35 pF loading. Revision 3 2- 41 Detailed Specifications Pin Descriptions CLKA Clock A (Input) Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds independent of the number of S-Modules being driven. This pin can also be used as an I/O. I/O Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tristated by the Designer Series software. IOCLK Dedicated (Hard-wired) I/O Clock (Input) Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) Input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. MODE Mode (Input) The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC No Connection This pin is not connected to circuitry within the device. PRA Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. 2- 42 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family SDO Serial Data Output (Output) Serial data output for diagnostic probe. SDO is active when the MODE pin is High. This pin functions as an I/O when the MODE pin is Low. DCLK Diagnostic Clock (Input) Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. VCC 5 V Supply Voltage HIGH supply voltage. Revision 3 2- 43 3 – Package Pin Assignments PL84 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 21 65 84-Pin PLCC 22 64 23 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Revision 3 3 -1 Package Pin Assignments PL84 Pin Number A1415, A14V15 Function A1425, A14V25 Function A1440, A14V40 Function 1 VCC VCC VCC 2 GND GND GND 3 VCC VCC VCC 4 PRA, I/O PRA, I/O PRA, I/O 11 DCLK, I/O DCLK, I/O DCLK, I/O 12 SDI, I/O SDI, I/O SDI, I/O 16 MODE MODE MODE 27 GND GND GND 28 VCC VCC VCC 40 PRB, I/O PRB, I/O PRB, I/O 41 VCC VCC VCC 42 GND GND GND 43 VCC VCC VCC 45 HCLK, I/O HCLK, I/O HCLK, I/O 52 SDO SDO SDO 53 IOPCL, I/O IOPCL, I/O IOPCL, I/O 59 VCC VCC VCC 60 VCC VCC VCC 61 GND GND GND 68 VCC VCC VCC 69 GND GND GND 74 IOCLK, I/O IOCLK, I/O IOCLK, I/O 83 CLKA, I/O CLKA, I/O CLKA, I/O 84 CLKB, I/O CLKB, I/O CLKB, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 3-2 R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family PQ100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 100-Pin 90 41 PQFP 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx Revision 3 3 -3 Package Pin Assignments PQ100 Pin Number A1415 Function A1425 Function 2 IOCLK, I/O IOCLK, I/O 14 CLKA, I/O CLKA, I/O 15 CLKB, I/O CLKB, I/O 16 VCC VCC 17 GND GND 18 VCC VCC 19 GND GND 20 PRA, I/O PRA, I/O 27 DCLK, I/O DCLK, I/O 28 GND GND 29 SDI, I/O SDI, I/O 34 MODE MODE 35 VCC VCC 36 GND GND 47 GND GND 48 VCC VCC 61 PRB, I/O PRB, I/O 62 GND GND 63 VCC VCC 64 GND GND 65 VCC VCC 67 HCLK, I/O HCLK, I/O 77 SDO SDO 78 IOPCL, I/O IOPCL, I/O 79 GND GND 85 VCC VCC 86 VCC VCC 87 GND GND 96 VCC VCC 97 GND GND Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 3-4 R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 PQ160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160-Pin PQFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 Note: This is the top view of the package Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx Revision 3 3 -5 Package Pin Assignments PQ160 3-6 Pin Number A1425, A14V25 Function A1440, A14V40 Function A1460, A14V60 Function 1 GND GND GND 2 SDI, I/O SDI, I/O SDI, I/O 5 NC I/O I/O 9 MODE MODE MODE 10 VCC VCC VCC 14 NC I/O I/O 15 GND GND GND 18 VCC VCC VCC 19 GND GND GND 20 NC I/O I/O 24 NC I/O I/O 27 NC I/O I/O 28 VCC VCC VCC 29 VCC VCC VCC 40 GND GND GND 41 NC I/O I/O 43 NC I/O I/O 45 NC I/O I/O 46 VCC VCC VCC 47 NC I/O I/O 49 NC I/O I/O 51 NC I/O I/O 53 NC I/O I/O 58 PRB, I/O PRB, I/O PRB, I/O 59 GND GND GND 60 VCC VCC VCC 62 HCLK, I/O HCLK, I/O HCLK, I/O 63 GND GND GND 74 NC I/O I/O 75 VCC VCC VCC 76 NC I/O I/O 77 NC I/O I/O 78 NC I/O I/O 79 SDO SDO SDO 80 IOPCL, I/O IOPCL, I/O IOPCL, I/O 81 GND GND GND 90 VCC VCC VCC 91 VCC VCC VCC R e vi s i o n 3 Accelerator Series FPGAs – ACT 3 Family PQ160 Pin Number A1425, A14V25 Function A1440, A14V40 Function A1460, A14V60 Function 92 NC I/O I/O 93 NC I/O I/O 98 GND GND GND 99 VCC VCC VCC 100 NC I/O I/O 103 GND GND GND 107 NC I/O I/O 109 NC I/O I/O 110 VCC VCC VCC 111 GND GND GND 112 VCC VCC VCC 113 NC I/O I/O 119 NC I/O I/O 120 IOCLK, I/O IOCLK, I/O IOCLK, I/O 121 GND GND GND 124 NC I/O I/O 127 NC I/O I/O 136 CLKA, I/O CLKA, I/O CLKA, I/O 137 CLKB, I/O CLKB, I/O CLKB, I/O 138 VCC VCC VCC 139 GND GND GND 140 VCC VCC VCC 141 GND GND GND 142 PRA, I/O PRA, I/O PRA, I/O 143 NC I/O I/O 145 NC I/O I/O 147 NC I/O I/O 149 NC I/O I/O 151 NC I/O I/O 153 NC I/O I/O 154 VCC VCC VCC 160 DCLK, I/O DCLK, I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3 -7 Package Pin Assignments 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 PQ208, RQ208 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208-Pin PQFP, RQFP Note: This is the top view of the package Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3-8 R e vi s i o n 3 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 Accelerator Series FPGAs – ACT 3 Family PQ208, RQ208 PQ208, RQ208 Pin Number A1460, A14V60 Function A14100, A14V100 Function Pin Number A1460, A14V60 Function A14100, A14V100 Function 1 GND GND 115 VCC VCC 2 SDI, I/O SDI, I/O 116 NC I/O 11 MODE MODE 129 GND GND 12 VCC VCC 130 VCC VCC 25 VCC VCC 131 GND GND 26 GND GND 132 VCC VCC 27 VCC VCC 145 VCC VCC 28 GND GND 146 GND GND 40 VCC VCC 147 NC I/O 41 VCC VCC 148 VCC VCC 52 GND GND 156 IOCLK, I/O IOCLK, I/O 53 NC I/O 157 GND GND 60 VCC VCC 158 NC I/O 65 NC I/O 164 VCC VCC 76 PRB, I/O PRB, I/O 180 CLKA, I/O CLKA, I/O 77 GND GND 181 CLKB, I/O CLKB, I/O 78 VCC VCC 182 VCC VCC 79 GND GND 183 GND GND 80 VCC VCC 184 VCC VCC 82 HCLK, I/O HCLK, I/O 185 GND GND 98 VCC VCC 186 PRA, I/O PRA, I/O 102 NC I/O 195 NC I/O 103 SDO SDO 201 VCC VCC 104 IOPCL, I/O IOPCL, I/O 205 NC I/O 105 GND GND 208 DCLK, I/O DCLK, I/O 114 VCC VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3 -9 Package Pin Assignments 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 TQ176 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 176-Pin TQFP Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 10 R e visio n 3 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 Accelerator Series FPGAs – ACT 3 Family TQ176 TQ176 Pin Number A1440, A14V40 Function A1460, A14V60 Function Pin Number A1440, A14V40 Function A1460, A14V60 Function 1 GND GND 89 GND GND 2 SDI, I/O SDI, I/O 98 VCC VCC 10 MODE MODE 99 VCC VCC 11 VCC VCC 108 GND GND 20 NC I/O 109 VCC VCC 21 GND GND 110 GND GND 22 VCC VCC 119 NC I/O 23 GND GND 121 NC I/O 32 VCC VCC 122 VCC VCC 33 VCC VCC 123 GND GND 44 GND GND 124 VCC VCC 49 NC I/O 132 IOCLK, I/O IOCLK, I/O 51 NC I/O 133 GND GND 63 NC I/O 138 NC I/O 64 PRB, I/O PRB, I/O 152 CLKA, I/O CLKA, I/O 65 GND GND 153 CLKB, I/O CLKB, I/O 66 VCC VCC 154 VCC VCC 67 VCC VCC 155 GND GND 69 HCLK, I/O HCLK, I/O 156 VCC VCC 82 NC I/O 157 PRA, I/O PRA, I/O 83 NC I/O 158 NC I/O 87 SDO SDO 170 NC I/O 88 IOPCL, I/O IOPCL, I/O 176 DCLK, I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 11 Package Pin Assignments 76 77 78 80 79 81 82 84 83 86 85 87 88 89 91 90 93 92 94 95 96 97 98 99 100 VQ100 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 100-Pin VQFP 12 13 64 63 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 12 R e visio n 3 50 49 48 47 46 45 44 43 42 41 40 39 38 51 37 52 25 36 53 24 35 54 23 34 55 22 33 56 21 32 57 20 31 58 19 30 59 18 29 60 17 28 61 16 27 62 15 26 14 Accelerator Series FPGAs – ACT 3 Family VQ100 Pin Number A1415, A14V15 Function A1425, A14V25 Function A1440, A14V40 Function 1 GND GND GND 2 SDI, I/O SDI, I/O SDI, I/O 7 MODE MODE MODE 8 VCC VCC VCC 9 GND GND GND 20 VCC VCC VCC 21 NC I/O I/O 34 PRB, I/O PRB, I/O PRB, I/O 35 VCC VCC VCC 36 GND GND GND 37 VCC VCC VCC 39 HCLK, I/O HCLK, I/O HCLK, I/O 49 SDO SDO SDO 50 IOPCL, I/O IOPCL, I/O IOPCL, I/O 51 GND GND GND 57 VCC VCC VCC 58 VCC VCC VCC 67 VCC VCC VCC 68 GND GND GND 69 GND GND GND 74 NC I/O I/O 75 IOCLK, I/O IOCLK, I/O IOCLK, I/O 87 CLKA, I/O CLKA, I/O CLKA, I/O 88 CLKB, I/O CLKB, I/O CLKB, I/O 89 VCC VCC VCC 90 VCC VCC VCC 91 GND GND GND 92 PRA, I/O PRA, I/O PRA, I/O 93 NC I/O I/O 100 DCLK, I/O DCLK, I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 13 Package Pin Assignments CQ132 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 Pin #1 Index 1 99 2 98 3 97 4 96 5 95 6 94 7 93 8 92 132-Pin CQFP 25 75 26 74 27 73 28 72 29 71 30 70 31 69 32 68 33 67 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 Note: This is the top view Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 14 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family CQ132 CQ132 Pin Number A1425 Function Pin Number A1425 Function 1 NC 67 NC 2 GND 74 GND 3 SDI, I/O 75 VCC 9 MODE 78 VCC 10 GND 89 VCC 11 VCC 90 GND 22 VCC 91 VCC 26 GND 92 GND 27 VCC 98 IOCLK, I/O 34 NC 99 NC 36 GND 100 NC 42 GND 101 GND 43 VCC 106 GND 48 PRB, I/O 107 VCC 50 HCLK, I/O 116 CLKA, I/O 58 GND 117 CLKB, I/O 59 VCC 118 PRA, I/O 63 SDO 122 GND 64 IOPCL, I/O 123 VCC 65 GND 131 DCLK, I/O 66 NC 132 NC Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 15 Package Pin Assignments CQ196 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 Pin #1 Index 1 147 2 146 3 145 4 144 5 143 6 142 7 141 8 140 196-Pin CQFP 41 107 42 106 43 105 44 104 45 103 46 102 47 101 48 100 49 99 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 16 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family CQ196 CQ196 Pin Number A1460 Function Pin Number A1460 Function 1 GND 101 GND 2 SDI, I/O 110 VCC 11 MODE 111 VCC 12 VCC 112 GND 13 GND 137 VCC 37 GND 138 GND 38 VCC 139 GND 39 VCC 140 VCC 51 GND 148 IOCLK, I/O 52 GND 149 GND 59 VCC 155 VCC 64 GND 162 GND 77 HCLK, I/O 172 CLKA, I/O 79 PRB, I/O 173 CLKB, I/O 86 GND 174 PRA, I/O 94 VCC 183 GND 98 GND 189 VCC 99 SDO 193 GND 100 IOPCL, I/O 196 DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 17 Package Pin Assignments CQ256 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 1 192 2 191 3 190 4 189 5 188 6 187 7 186 8 185 256-Pin CQFP 56 137 57 136 58 135 59 134 60 133 61 132 62 131 63 130 64 129 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 18 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family CQ256 CQ256 Pin Number A14100 Function Pin Number A14100 Function 1 GND 141 VCC 2 SDI, I/O 158 GND 11 MODE 159 VCC 28 VCC 160 GND 29 GND 161 VCC 30 VCC 174 VCC 31 GND 175 GND 46 VCC 176 GND 59 GND 188 IOCLK, I/O 90 PRB, I/O 189 GND 91 GND 219 CLKA, I/O 92 VCC 220 CLKB, I/O 93 GND 221 VCC 94 VCC 222 GND 96 HCLK, I/O 223 VCC 110 GND 224 GND 126 SDO 225 PRA, I/O 127 IOPCL, I/O 240 GND 128 GND 256 DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 19 Package Pin Assignments BG225 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 20 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family BG225 A1460 Function Location CLKA or I/O C8 CLKB or I/O B8 DCLK or I/O B2 GND A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15 HCLK or I/O P9 IOCLK or I/O B14 IOPCL or I/O P14 MODE D1 NC A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14 PRA or I/O A7 PRB or I/O L7 SDI or I/O D4 SDO N13 VCC A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 4. The BG225 package has been discontinued. Revision 3 3- 21 Package Pin Assignments BG313 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A A B B C C D D E E F F G G H J H K K L L M M N N P P R R T U T V V W W Y AA Y AA J U AB AB AC AC AD AD AE AE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 22 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family BG313 A14100, A14V100 Function Location CLKA or I/O J13 CLKB or I/O G13 DCLK or I/O B2 GND A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13 HCLK or I/O T14 IOCLK or I/O B24 IOPCL or I/O AD24 MODE NC G3 A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25, D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7, N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24 PRA or I/O H12 PRB or I/O AD12 SDI or I/O C1 SDO AE23 VCC AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 23 Package Pin Assignments PG100 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E 100-Pin CPGA F F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 Orientation Pin Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 24 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family PG100 A1415 Function Location CLKA or I/O C7 CLKB or I/O D6 DCLK or I/O C4 GND C3, C6, C9, E9, F3, F9, J3, J6, J8, J9 HCLK or I/O H6 IOCLK or I/O C10 IOPCL or I/O K9 MODE C2 PRA or I/O A6 PRB or I/O L3 SDI or I/O B3 SDO L9 VCC B6, B10, E11, F2, F10, G2, K2, K6, K10 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 4. The PG100 package has been discontinued. Revision 3 3- 25 Package Pin Assignments PG133 1 2 3 4 5 6 7 8 9 10 11 12 13 A A B B C C D D E E F F 133-Pin CPGA G G H H J J K K L L M M N N 1 2 3 4 5 6 7 8 9 10 11 12 13 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 26 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family PG133 A1425 Function Location CLKA or I/O D7 CLKB or I/O B6 DCLK or I/O D4 GND A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12 HCLK or I/O K7 IOCLK or I/O C10 IOPCL or I/O L10 MODE E3 NC A1, A7, A13, G1, G13, N1, N7, N13 PRA or I/O A6 PRB or I/O L6 SDI or I/O C2 SDO M11 VCC B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 4. The PG133 package has been discontinued. Revision 3 3- 27 Package Pin Assignments PG175 A B C D E F G H J K L M N P R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 175-Pin CPGA 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 A B C D E F G H J K L M N P R Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 28 R e visio n 3 Accelerator Series FPGAs – ACT 3 Family PG175 A1440 Function Location CLKA or I/O C9 CLKB or I/O A9 DCLK or I/O D5 GND D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8, M12 HCLK or I/O R8 IOCLK or I/O E12 IOPCL or I/O P13 MODE NC F3 A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15 PRA or I/O B8 PRB or I/O R7 SDI or I/O D3 SDO N12 VCC C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 4. The PG175 package has been discontinued. Revision 3 3- 29 Package Pin Assignments PG207 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A A B B C C D D E E F F G G H H 207-Pin CPGA J K L L M M N N P P R R S S T T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 30 J K R e visio n 3 Accelerator Series FPGAs – ACT 3 Family PG207 A1460 Function Location CLKA or I/O K1 CLKB or I/O J3 DCLK or I/O E4 GND C14, D4, D5, D9, D14, J4, J14, P3, P4, P7, P9, P14, R15 HCLK or I/O J15 IOCLK or I/O P5 IOPCL or I/O N14 MODE D7 NC A1, A2, A16, A17, B1, B17, C1, C2, S1, S3, S17, T1, T2, T16, T17 PRA or I/O H1 PRB or I/O K16 SDI or I/O C3 SDO P15 VCC B2, B9, B16, D11, J2, J16, P12, S2, S9, S16, T5 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 31 Package Pin Assignments PG257 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A A B B C C D D E E F F G G H H J J 257-Pin CPGA K L L M M N N P P R R T T V V X X Y Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Note: This is the top view. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx 3- 32 K R e visio n 3 Accelerator Series FPGAs – ACT 3 Family PG257 A14100 Function Location CLKA or I/O L4 CLKB or I/O L5 DCLK or I/O E4 GND B16, C4, D4, D10, D16, E11, J5, K4, K16, L15, R4, T4, T10, T16, T17, X7 HCLK or I/O J16 IOCLK or I/O T5 IOPCL or I/O R16 MODE A5 NC E5 PRA or I/O J1 PRB or I/O J17 SDI or I/O B4 SDO R17 VCC C3, C10, C13, C17, K3, K17, V3, V7, V10, V17, X14 Notes: 1. All unlisted pin numbers are user I/Os. 2. NC denotes no connection. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. Revision 3 3- 33 4 – Datasheet Information List of Changes The following table lists critical changes that were made in each version of the datasheet. Revision Revision 3 (January 2012) Revision 2 (September 2011) Changes Page The description for SDO pins had earlier been removed from the datasheet and has now been included again, in the "Pin Descriptions" section (SAR 35820). 2-21 SDO pin numbers had earlier been removed from package pin assignment tables in the datasheet, and have now been restored to the pin tables (SAR 35820). 3-1 The ACT 3 datasheet was formatted newly in the style used for current datasheets. The same information is present (other than noted in the list of changes for this revision) but divided into chapters. N/A The datasheet was revised to note in multiple places that speed grades –2 and –3 have been discontinued. The following device/package combinations have been discontinued for all speed grades and temperatures (SAR 33872): I and others A1415 PG100 A1425 PG133 A1440 PG175 A1460 BG225 Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004. The "Features" section was revised to state the clock-to-ouput time and on-chip performance for –1 speed grade as 9.0 ns and 186 MHz. The "General Description" section was revised in accordance (SAR 33872). I The maximum performance values were updated in Table 1 • ACT 3 Family Product Information, and now reflect worst-case commercial for the –1 speed grade (SAR 33872). I The "Product Plan" table was updated as follows to conform to current offerings (SAR 33872): III The A1415A device is offered in PL84, PG100, and VQ100 packages for Military application. The A1440A device is offered in TQ176 and VQ100 packages for Industrial application. Table 1-1 • Chip-to-Chip Performance (worst-case commercial) was updated to include data for all speed grades instead of only –3 (SAR 33872). 1-2 Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade) was revised to reflect values for the –1 speed grade (SAR 33872). 1-1 Figure 2-10 • Timing Model was updated to show data for the –1 speed grade instead of –3 (SAR 33872). 2-16 Table 2-14 • Logic Module and Routing Delay by Fanout (ns); Worst-Case Commercial Conditions was updated to include data for all speed grades instead of only –3 (SAR 33872). 2-20 Package names used in the "Package Pin Assignments" section and throughout the document were revised to match standards given in Package Mechanical Drawings (SAR 27395). 3-1 Revision 3 4 -1 Datasheet Information Revision Revision 2 (continued) Changes In the "Package Pin Assignments" section, notes were added to the pin tables for the following packages, stating that they are discontinued: 3-20 3-24 3-26 3-28 "BG225" "PG100" "PG133" "PG175" Revision 1 (June 2006) 4-2 Page RoHS compliant information was added to the "Ordering Information" section. R e vi s i o n 3 II Accelerator Series FPGAs – ACT 3 Family Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. Revision 3 4 -3 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 5172106-3/1.12