Accelerator Series FPGAs – ACT™ 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates) • Replaces up to one hundred 20-pin PAL® Packages • Up to 1153 Dedicated Flip-Flops • Highly Predictable Performance with 100% Automatic Placement and Routing • VQFP, TQFP, BGA, and PQFP Packages • Nonvolatile, User Programmable • 7.5 ns Clock-to-Output Times • Fully Tested Prior to Shipment • Up to 250 MHz On-Chip Performance • 5.0V and 3.3V Versions • Up to 228 User-Programmable I/O Pins • Optimized for Logic Synthesis Methodologies • Four Fast, Low-Skew Clock Networks • Low-power CMOS Technology • More than 500 Macro Functions Device A1415 A1425 A1440 A1460 A14100 1,500 3,750 40 15 2,500 6,250 60 25 4,000 10,000 100 40 6,000 15,000 150 60 10,000 25,000 250 100 Logic Modules S-Module C-Module 200 104 96 310 160 150 564 288 276 848 432 416 1,377 697 680 Dedicated Flip-Flops1 264 360 568 768 1,153 User I/Os (maximum) 80 100 140 168 228 100 84 100 — 100 — — — 133 84 100, 160 — 100 — — 132 175 84 160 — 100 176 — — 207 — 160, 208 — — 176 225 196 257 — — 208 — — 313 256 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns 100 MHz 63 MHz 110 MHz 250 MHz 250 MHz 8.5 ns 97 MHz 63 MHz 110 MHz 200 MHz 200 MHz 9.0 ns 93 MHz 63 MHz 105 MHz 200 MHz 200 MHz 9.5 ns Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages (40 gates) 20-Pin PAL Equivalent Packages (100 gates) Packages2 (by pin count) CPGA PLCC PQFP RQFP VQFP TQFP BGA CQFP Performance3 (maximum, worst-case commercial) Chip-to-Chip4 Accumulators (16-bit) Loadable Counter (16-bit) Prescaled Loadable Counters (16-bit) Datapath, Shift Registers Clock-to-Output (pad-to-pad) Notes: 1. One flip-flop per S-Module, two flip-flops per I/O-Module. 2. See product plan on page 1-178 for package availability. 3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3. 4. Clock-to-Output + Setup S e p t e m b e r 1997 © 1997 Actel Corporation 1-175 Description Actel’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity programmable logic device. ACT 3 FPGAs offer a high perfomance, PCI compliant programmable solution capable of 250 MHz on-chip performance and 7.5 nanosecond clock-to-output, with capacities spanning from 1,500 to 10,000 gate array equivalent gates. For further information regarding PCI compliance of ACT 3 devices, see “Accelerator Series FPGAs—ACT 3 PCI Compliant Family.” The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and sequential logic modules used in Actel’s 3200DX and 1200XL families. In addition, the ACT 3 I/O modules contain registers which deliver 7.5 nanosecond clock-to-out times. The devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high fanout signals such as flip-flop resets and output enables. The ACT 3 family is supported by Actel’s Designer Series Development System which offers automatic placement and routing (with automatic or fixed pin assignments), static timing anlaysis, user programming, and debug and diagnostic probe capabilities. The Designer Series is supported on the following platforms: 486/Pentium class PC’s, Sun®‚ and HP®‚ workstations. The software provides CAE interfaces to Cadence, Mentor Graphics®, OrCAD™ and Viewlogic®‚ design environments. Additional platforms are supported through Actel’s Industry Alliance Program, including DATA I/O (ABEL FPGA) and MINC. Predictable Performance* (Worst-Case Commercial) Accumulators (16-bit) 63 MHz Loadable Counters (16-bit) 110 MHz Prescaled Loadable Counters (16-bit) 250 MHz Shift Registers 250 MHz System Performance Model Chip #1 Chip #2 I/O Module I/O Module 35 pF I/O CLK I/O CLK tCKHS tTRACE tINSU Chip-to-Chip Performance (Worst-Case Commercial) tCKHS tTRACE tINSU Total MHz A1425A-3 7.5 1.0 1.8 10.3 ns 97 A1460A-3 9.0 1.0 1.3 11.3 ns 88 1-176 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Ordering Information A14100 A – RQ 208 C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array Speed Grade Std = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Die Revision Part Number A1415A = A14V15A = A1425A = A14V25A = A1440A = A14V40A = A1460A = A14V60A = A14100A = A14V100A = 1500 Gates 1500 Gates (3.3V) 2500 Gates 2500 Gates (3.3V) 4000 Gates 4000 Gates (3.3V) 6000 Gates 6000 Gates (3.3V) 10000 Gates 10000 Gates (3.3V) 1-177 Product Plan Speed Grade* Application Std –1 –2 –3 C I M B ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — — — — — — — — ✔ ✔ — — — — — — ✔ ✔ — — — — — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — ✔† ✔ ✔ ✔ ✔ — ✔† ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — ✔ — — — ✔ ✔ — — — ✔ ✔ — — ✔ ✔ ✔ — — — — — — — — — ✔ ✔ ✔ — — — — — — — — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — ✔ — — — — — — — — — — — — ✔ ✔ ✔ ✔ — — — — — — — — — — — — ✔ ✔ ✔ ✔ — — — — — — — — — — — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — ✔† ✔ ✔ ✔ ✔ P P — P† P P ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — ✔ — — — ✔ ✔ — — — — ✔ ✔ — — A1415A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 100-pin Ceramic Pin Grid Array (CPGA) A14V15A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) A1425A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 132-pin Ceramic Quad Flatpack (CQFP) 133-pin Ceramic Pin Grid Array (CPGA) 160-pin Plastic Quad Flatpack (PQFP) A14V25A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) A1440A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 175-pin Ceramic Pin Grid Array (CPGA) 176-pin Thin Quad Flatpack (TQFP) A14V40A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) A1460A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 196-pin Ceramic Quad Flatpack (CQFP) 207-pin Ceramic Pin Grid Array (CPGA) 208-pin Plastic Quad Flatpack (PQFP) 225-pin Platic Ball Grid Array (BGA) Applications: 1-178 C I M B † = Commercial = Industrial = Military = MIL-STD-883 Commercial Only Availability: ✔ = Available P = Planned — = Not Planned * Speed Grade: –1 = Approx. 15% faster than Standard –2 = Approx. 25% faster than Standard –3 = Approx. 35 % faster than Standard. A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Product Plan (continued) Speed Grade* Application Std –1 –2 –3 C I M B ✔ ✔ ✔ — — — — — — — — — ✔ ✔ ✔ — — — — — — — — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔† ✔ — ✔ ✔† ✔ — ✔ ✔ ✔ ✔ ✔ — — — — ✔ — ✔ — ✔ — ✔ ✔ ✔ — — — — — — ✔ ✔ — — — — — — A14V60A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 208-pin Plastic Quad Flatpack (PQFP) A14100A Device 208-pin Power Quad Flatpack (RQFP) 257-pin Ceramic Pin Grid Array (CPGA) 313-pin Plastic Ball Grid Array (BGA) 256-pin Ceramic Quad Flatpack (CQFP) A14V100A Device 208-pin Power Quad Flatpack (RQFP) 313-pin Plastic Ball Grid Array (BGA) Applications: C I M B † = Commercial = Industrial = Military = MIL-STD-883 Commercial Only Availability: ✔ = Available P = Planned — = Not Planned * Speed Grade: –1 = Approx. 15% faster than Standard –2 = Approx. 25% faster than Standard –3 = Approx. 35 % faster than Standard. Plastic Device Resources User I/Os PLCC PQFP, RQFP VQFP TQFP 208-pin 100-pin 176-pin 225-pin 313-pin — — 80 — — — 80 100 — 83 — — — 70 — 131 — 83 140 — — 6000 — — 131 167 — 151 168 — 10000 — — — 175 — — — 228 Device Series Logic Modules Gates 84-pin 100-pin 160-pin A1415 200 1500 70 80 A1425 310 2500 70 A1440 564 4000 A1460 848 A14100 1377 BGA 1-179 Hermetic Device Resources User I/Os CPGA CQFP Device Series Logic Modules Gates 100-pin 133-pin 175-pin 207-pin 257-pin 132-pin 196-pin 256-pin A1415 200 1500 80 — — — — — — — A1425 310 2500 — 100 — — — 100 — — A1440 564 4000 — — 140 — — — — — A1460 848 6000 — — — 168 — — 168 — A14100 1377 10000 — — — — 228 — — 228 Pin Description CLKA Clock A (Input) function as I/Os. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. NC CLKB This pin is not connected to circuitry within the device. Clock B (Input) Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds independent of the number of S-Modules being driven. This pin can also be used as an I/O. I/O Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tristated by the Designer Series software. IOCLK Dedicated (Hard-wired) I/O Clock (Input) Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) Input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. MODE Mode (Input) The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins 1-180 PRA No Connection Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. DCLK Diagnostic Clock (Input) Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. V CC 5 V Supply Voltage HIGH supply voltage. A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Architecture Logic Modules This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL family, there are two types of modules: C-modules and S-modules. The C-module is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The S-module is designed to implement high-speed sequential functions within a single module. S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are arranged in alternating patterns and make up the bulk of the array. This arrangement allows the placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module implements the following function: Topology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 1. Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 where: S0 = A0 * B0 and S1 = A1 + B1 An Array with n rows and m columns 0 Rows 1 2 3 4 5 c–1 c c+1 m m+1 m+2 m+3 Columns Channels n+2 IO n+1 IO IO CLKM IO IO IO IO IO IO Top I/Os n+1 n IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO IO IO IO IO IO IO IO IO Right I/Os Bottom I/Os n n–1 • • • 2 n–1 • • • 2 1 1 Left I/Os 0 BIO IO 0 Figure 1 • Generalized Floor Plan of ACT 3 Device 1-181 The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to be implemented with no delay penalty. The Designer Series Development System will automatically combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic module and eliminating a module delay. D00 D01 Y D10 OUT D11 The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional descriptions are shown in Figures 2 and 3. The clock selection is determined by a multiplexor select at the clock input to the S-module. S1 S0 A1 B1 A0 B0 I/Os I/O Modules Figure 2 • C-Module Diagram I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in the array and access the routing channels in a similar fashion to logic modules. The I/O module schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver. Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock (IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be selected individually on an I/O module by I/O module basis. The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into the array. This allows the output register to be used in high-speed state machine applications. Side I/O modules have a dedicated output segment for Y extending into the routing channels above and below (similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained in detail in the routing section). D00 D01 D10 Y D Q D11 S1 S0 CLK A1 B1 Figure 3 • S-Module Diagram 1-182 A0 B0 CLR OUT A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y D 0 MUX 1 Q DATAOUT CLR/PRE ODE S0 Y D 0 MUX 1 0 S1 1 MUX 2 3 Q D 1 MUX 0 DATAIN CLR/PRE IOPCL IOCLK Figure 4 • Functional Diagram for I/O Module I/O Pad Drivers All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN (global input enable), and SLEW (individual slew selection). See Figure 5. Special I/Os The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change once the device has been programmed. The permanent special I/Os consist of the array clock input buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is determined by the I/O macros selected. Clock Networks The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks and two general purpose routed networks. The high-performance networks function up to 200 MHz, while the general purpose routed networks function up to 150 MHz. Dedicated Clocks Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by special I/Os. 1-183 CLKB CLKINB CLKA CLKINA OE FROM PADS SLEW CLKMOD DATAOUT S0 S1 INTERNAL SIGNAL CLKO(17) CLOCK DRIVERS CLKO(16) PAD CLKO(15) DATAIN CLKO(2) CLKO(1) IEN CLOCK TRACKS INEN OUTEN Figure 6 • Clock Networks Routing Structure Figure 5 • Function Diagram for I/O Pad Driver Routed Clocks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows (see Figure 6): • externally from the CLKA pad • externally from the CLKB pad • internally from the CLKINA input • internally from the CLKINB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The function of the clock module is determined by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like resets, output enables, or data enables. This saves logic modules and results in performance increases in some cases. 1-184 The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 7. Undedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 8. MODULE ROW HCLK CLK0 NVCC SIGNAL TRACK SIGNAL (LHT) | | | | | | | SEGMENT HF SIGNAL NVSS CLK1 MODULE ROW Figure 7 • Horizontal Routing Tracks and Segments LVTS S-MODULE MODULE ROW C-MODULE VF CHANNEL XF VERTICLE INPUT SEGMENT FF S-MODULE C-MODULE Figure 8 • Vertical Routing Tracks and Segments 1-185 Antifuse Connections An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as an efficient programming architecture. The structure is highly testable because there are no preexisting connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. or the channel below. The logic modules are arranged such that half of the inputs are connected to the channel above and half of the inputs to segments in the channel below as shown in Figure 9. Module Output Connections Module outputs have dedicated output segments. Output segments extend vertically two channels above and two channels below, except at the top or bottom of the array. Output segments twist, as shown in Figure 10, so that only four vertical tracks are required. LVT Connections XF Horizontal-to-Vertical Connection Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module pair in the array shares four LVTs that span the length of the column. Any module in the column pair can connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses connected directly to the driver stage of the module output, bypassing the isolation transistor. FF antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower resistance value. HF Horizontal-to-Horizontal Connection Antifuse Connections VF Vertical-to-Vertical Connection FF “Fast” Vertical Connection In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed antifuse (XF-type). One exception is in the case of the clock networks. Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical structure of the antifuse is identical in each case; only the usage differs.) Table 1 shows four types of antifuses. Table 1 • Antifuse Types Examples of all four types of connections are shown in Figures 7 and 8. Clock Connections Connections to Logic and I/O modules are made through vertical segments that connect to the module inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array. To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a few of the C-module and S-module inputs can be connected to the clock networks. To further reduce loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock inputs of the S-module. Module Input Connections Programming and Test Circuits The tracks dedicated to module inputs are segmented by pass transistors in each module row. During normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the inputs of the module directly above or below it. During certain test modes, the pass transistors are active to verify the continuity of the metal tracks. Vertical input segments span only the channel above The array of logic and I/O modules is surrounded by test and programming circuits controlled by the temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family devices. The ACT 3 family also includes support for two Actionprobe® circuits allowing complete observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB. Module Interface 1-186 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Y+2 Y+2 Y+1 B1 B0 D01 D00 A1 D10 D11 A0 Y+1 B0 Y Y Y-1 D10 B1 D01 A0 D11 A1 Y-1 Y-2 Y-2 LVTs S-MODULES C-MODULES Figure 9 • Logic Module Routing Interface 1-187 5V Operating Conditions Recommended Operating Conditions Parameter Absolute Maximum Ratings 1 Temperature Range1 Free air temperature range Symbol Parameter Limits Units –0.5 to +7.0 V VCC DC Supply Voltage VI Input Voltage –0.5 to VCC +0.5 V VO Output Voltage –0.5 to VCC +0.5 V IIO I/O Source Sink ±20 mA –65 to +150 °C Commercial Industrial Military Units 0 to +70 –40 to +85 –55 to +125 °C ±5 ±10 ±10 %VCC 5V Power Supply Tolerance Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Current2 TSTG Storage Temperature Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Symbol Parameter Test Condition VOH1,2 IOH = –4 mA (CMOS) HIGH Level Output Min. Max. Industrial Min. Max. 3.7 Military Min. Max. 3.7 V IOH = –6 mA (CMOS) 3.84 IOH = –10 mA VOL1,2 LOW Level Output (TTL)3 V 2.40 V IOL = +6 mA (CMOS) 0.33 (TTL)3 0.50 IOL = +12 mA Units 0.4 0.4 V V VIH HIGH Level Input TTL Inputs 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL LOW Level Input TTL Inputs –0.3 0.8 –0.3 0.8 –0.3 0.8 V IIN Input Leakage VI = VCC or GND –10 +10 –10 +10 –10 +10 µA IOZ 3-state Output Leakage VO = VCC or GND –10 +10 –10 +10 –10 +10 µA CIO I/O Capacitance3,4 ICC(S) Standby VCC Supply Current (typical = 0.7 mA) ICC(D) Dynamic VCC Supply Current See “Power Dissipation” Section 10 10 10 pF 2 10 20 mA Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time, VCC = min. 3. Not tested, for information only. 4. VOUT = 0V, f = 1 MHz. 5. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = VCC or GND. 1-188 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 3.3V Operating Conditions Recommended Operating Conditions Absolute Maximum Ratings 1 Parameter Free air temperature range Symbol Parameter Limits Units –0.5 to +7.0 V VCC DC Supply Voltage VI Input Voltage –0.5 to VCC +0.5 V VO Output Voltage –0.5 to VCC +0.5 V I/O Source Sink ±20 mA –65 to +150 °C IIO TSTG Current2 Storage Temperature Commercial Units Temperature Range1 0 to +70 °C Power Supply Tolerance 3.0 to 3.6 V Note: 1. Ambient temperature (TA) is used for commercial. Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Parameter Units Min. VOH1 VOL1 Max. (IOH = –4 mA) 2.15 V (IOH = –3.2 mA) 2.4 V (IOL = 6 mA) 0.4 V VIL –0.3 0.8 V VIH 2.0 VCC + 0.3 V 500 ns 10 pF 0.75 mA 10 µA Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical 5 Leakage Current = 0.3 mA) –10 Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO, VIN = VCC or GND. 1-189 Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at commercial temperature and still air is as follows: 150°C – 70°C Max. junction temp. (°C) – Max. ambient temp. (°C) Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 3.2 W θ ja (°C/W) 25 °C/W Pin Count θjc θja Still Air θja 300 ft/min Units Ceramic Pin Grid Array 100 133 175 207 257 20 20 20 20 20 35 30 25 22 15 17 15 14 13 8 °C/W °C/W °C/W °C/W °C/W Ceramic Quad Flatpack 132 196 256 13 13 13 55 36 30 30 24 18 °C/W °C/W Plastic Quad Flatpack 100 160 208 13 10 10 51 33 33 40 26 26 °C/W °C/W °C/W Very Thin Quad Flatpack 100 12 43 35 °C/W Thin Quad Flatpack 176 11 32 25 °C/W Power Quad Flatpack 208 0.4 17 13 °C/W Plastic Leaded Chip Carrier 84 12 37 28 °C/W Plastic Ball Grid Array 225 313 10 10 25 23 19 17 °C/W Package Type1 °C/W °C/W Note: 1. Maximum Power Dissipation in Still Air for 160-pin PQFP package is 2.4 Watts, 208-pin PQFP package is 2.4 Watts, 100-pin PQFP package is 1.6 Watts, 100-pin VQFP package is 1.9 Watts, 176-pin TQFP package is 2.5 Watts, 84-pin PLCC package is 2.2 Watts, 208-pin RQFP package is 4.7 Watts, 225-pin BGA package is 3.2 Watts, 313-pin BGA package is 3.5 Watts. Power Dissipation P = [ICC standby+ Iactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Static Power Component (1) Where: ICC standby is the current flowing when no inputs or outputs are changing. Iactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the design and on the system I/O. The power can be divided into two components: static and active. 1-190 Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC 2mA VCC 5.25 V Power 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Active Power Component Where: Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. m n p q1 = = = = q2 = r1 = r2 = Equivalent Capacitance s1 = The power dissipated by a CMOS circuit can be expressed by the Equation 2. s2 = CEQM CEQI CEQO = = = CEQCR = CEQCD = CEQCI = CL fm fn fp fq1 fq2 = = = = = = fs1 fs2 = = Power (uW) = CEQ * VCC2 * F (2) Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C EQ Values for Actel FPGAs Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) I/O Clock Buffer Loads (CEQCI) 6.7 7.2 10.4 1.6 0.7 0.9 Number of logic modules switching at fm Number of input buffers switching at fn Number of output buffers switching at fp Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock Fixed number of clock loads on the dedicated array clock Fixed number of clock loads on the dedicated I/O clock Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffers in pF Equivalent capacitance of routed array clock in pF Equivalent capacitance of dedicated array clock in pF Equivalent capacitance of dedicated I/O clock in pF Output lead capacitance in pF Average logic module switching rate in MHz Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Average dedicated array clock rate in MHz Average dedicated I/O clock rate in MHz To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 3 shows a piece-wise linear summation over all components. Power =VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk] (3) 1-191 Fixed Capacitance Values for Actel FPGAs (pF) Device Type A1415A A14V15A A1425A A14V25A A1440A A14V40A A1440B A1460A A14V60A A1460B A14100A A14V100A A14100B r1 routed_Clk1 60 57 75 72 105 100 105 165 157 165 195 185 195 r2 routed_Clk2 60 57 75 72 105 100 105 165 157 165 195 185 195 Fixed Clock Loads (s 1 /s 2 ) Device Type A1415A A14V15A A1425A A14V25A A1440A A14V40A A1440B A1460A A14V60A A1460B A14100A A14V100A A14100B 1-192 s1 Clock Loads on dedicated array clock 104 104 160 160 288 288 288 432 432 432 697 697 697 s2 Clock Loads on dedicated I/O clock 80 80 100 100 140 140 140 168 168 168 228 228 228 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs switching (n) Outputs switching (p) First routed array clock loads (q1) = = = = 80% of modules # inputs/4 # output/4 40% of sequential modules Second routed array clock loads (q2) = 40% of sequential modules Load capacitance (CL) = 35 pF Average logic module switching rate = F/10 (fm) Average input switching rate (fn) = F/5 Average output switching rate (fp) = F/10 Average first routed array clock rate = F/2 (fq1) Average second routed array clock rate = F/2 (fq2) Average dedicated array clock rate = F (fs1) Average dedicated I/O clock rate (fs2) = F A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y ACT 3 Timing Model* Input Delays I/O Module tINY = 2.8 ns Internal Delays Combinatorial Logic Module Predicted Routing Delays Output Delays I/O Module tIRD2 = 1.2 ns tDHS = 5.0 ns D Q tINH = 0.0 ns tINSU = 1.8 ns tICKY = 4.7 ns tHCKH = 3.0 ns I/O Module tDHS = 5.0 ns Sequential Logic Module Combinatorial Logic included in tSUD ARRAY CLOCK tRD1 = 0.9 ns tRD4 = 1.7 ns tRD8 = 2.8 ns tPD = 2.0 ns tSUD = 0.5 ns tHD = 0.0 ns D D Q tRD1 = 0.9 ns tCO = 2.0 ns Q tENZHS = 4.0 ns tOUTH = 0.7 ns tOUTSU = 0.7 ns FHMAX = 250 MHz I/O CLOCK tCKHS = 7.5 ns (pad-pad) FIOMAX = 250 MHz *Values shown for A1425A-3. 1-193 Output Buffer Delays E D VCC In VCC GND 50% VOH 50% Out VOL PAD To AC test loads (shown below) TRIBUFF En 1.5 V 1.5 V Out 50% VCC VCC 50% 1.5 V GND En Out GND 10% VOL tENZHS, tDHS, tDHS, 90% 1.5 V tENZHS, tENHSZ, GND 50% VOH 50% tENHSZ, AC Test Loads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 35 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 kΩ To the output under test 35 pF Input Buffer Delays PAD Module Delays S A B Y INBUF Y VCC 3V In Out GND 50% 50% VCC Out GND 50% 50% 50% tINY 1-194 0V 1.5 V 1.5 V VCC S, A or B tPD GND 50% tPD VCC Out tINY 50% tPD GND tPD 50% A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Sequential Module Timing Characteristics Flip-Flops D Q CLK CLR (Positive edge triggered) tHD D tA tWCLKA tSUD CLK tWCLKA tCO Q tCLR CLR tWASYN I/O Module: Sequential Input Timing Characteristics D E IOCLK Y PRE CLR (Positive edge triggered) tINH D tINSU tIOP tIOPWH IOCLK tIDESU tIOPWL tIDEH E tICKY Y tICLRY PRE, CLR tIOASPW 1-195 I/O Module: Sequential Output Timing Characteristics D E Q PRE IOCLK CLR Y (Positive edge triggered) tOUTH D tOUTSU tIOP tIOPWH IOCLK tODESU tIOPWL tODEH E tOCKY Y tCKHS, tCKLS Q tOCLRY PRE, CLR tIOASPW 1-196 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Predictable Performance: Tightest Delay Distributions Timing Characteristics Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3 family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200Ω resistance and 6 femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects using only two antifuses. The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can be traded for the increased performance of reduced logic level designs. This also simplifies performance estimates when designing with ACT 3 devices. Table 2 • Logic Module and Routing Delay by Fanout (ns) (Worst-Case Commercial Conditions) Speed ACT 3 –3 FO=1 FO=2 FO=3 FO=4 FO=8 2.9 3.2 3.4 3.7 4.8 Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ACT 3 family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design is complete. Delay values may then be determined by using the ALS Timer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximatley 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 1-197 Timing Derating Factor (Temperature and Voltage) Industrial (Commercial Minimum/Maximum Specification) x Military Min. Max. Min. Max. 0.66 1.07 0.63 1.17 Timing Derating Factor for Designs at Typical Temperature (T J = 25°C) and Voltage (5.0 V) (Commercial Maximum Specification) x 0.85 Temperature and Voltage Deratin g Factors (normalized to Worst-Case Commercial, T J = 4.75 V, 70°C) –55 –40 0 25 70 85 125 4.50 0.72 0.76 0.85 0.90 1.04 1.07 1.17 4.75 0.70 0.73 0.82 0.87 1.00 1.03 1.12 5.00 0.68 0.71 0.79 0.84 0.97 1.00 1.09 5.25 0.66 0.69 0.77 0.82 0.94 0.97 1.06 5.50 0.63 0.66 0.74 0.79 0.90 0.93 1.01 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T J = 4.75 V, 70°C) 1.20 Derating Factor 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 Voltage (V) Note: 1-198 This derating factor applies to all routing and propagation dealys. 5.25 5.50 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1415A, A14V15A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70°C) 1 Logic Module Propagation Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed1 Parameter Description Min. Min. Min. Min. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns Max. Max. Max. Max. Min. Max. Units 3 Predicted Routing Delays tRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-199 A1415A, A14V15A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Predicted Input Routing Max. Max. Max. Max. Max. Units Delays1 tIRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tIRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tIRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tIRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tIRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input F-F Data Setup (w.r.t. IOCLK Pad) 2.0 2.3 2.5 3.0 3.0 ns Input Data Enable Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input Data Enable Setup (w.r.t. IOCLK Pad) 5.8 6.5 7.5 8.6 8.6 ns Output F-F Data Hold (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output F-F Data Setup (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output Data Enable Hold (w.r.t. IOCLK Pad) 0.3 0.4 0.4 0.5 0.5 ns Output Data Enable Setup (w.r.t. IOCLK Pad) 1.3 1.5 1.7 2.0 2.0 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-200 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1415A, A14V15A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 4.0 4.5 5.1 6.0 7.8 ns Enable to Pad, Z to H/L, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Hi Slew 6.5 7.5 8.5 10.0 13.0 ns Enable to Pad, H/L to Z, Lo Slew 6.5 7.5 8.5 10.0 13.0 ns IOCLK Pad to Pad H/L, Hi Slew 7.5 7.5 9.0 10.0 13.0 ns IOCLK Pad to Pad H/L, Lo Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Max. Max. Max. Max. Max. Units 1 I/O Module – CMOS Output Timing tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 5.2 5.9 6.6 7.8 10.1 ns Enable to Pad, Z to H/L, Lo Slew 8.9 10.0 11.3 13.3 17.3 ns Enable to Pad, H/L to Z, Hi Slew 6.7 7.5 8.5 10.0 13.0 ns Enable to Pad, H/L to Z, Lo Slew 6.7 7.5 9.0 10.0 13.0 ns IOCLK Pad to Pad H/L, Hi Slew 8.9 8.9 10.7 11.8 15.3 ns IOCLK Pad to Pad H/L, Lo Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Note: 1. Delays based on 35pF loading. 1-201 A1415A, A14V15A Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tIOCKH Input Low to High (Pad to I/O Module Input) Max. 2.0 Max. 2.3 Max. 2.6 Max. 3.0 Max. Units 3.5 ns tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIOPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 0.4 4.0 0.4 5.0 0.4 6.8 0.4 8.0 0.4 10.0 ns ns 250 200 150 125 100 MHz Input Low to High (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Input High to Low (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO=64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO=64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO=64) 3.3 3.8 4.2 4.9 6.5 ns Min. Pulse Width Low (FO=64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL tRCKSW Maximum Skew (FO=128) tRP Minimum Period (FO=64) fRMAX Maximum Frequency (FO=64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 3.0 ns 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 0.0 1.0 3.0 ns tHRCKSW H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) Note: 1. Delays based on 35pF loading. 1-202 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1425A, A14V25A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70°C) 1 Logic Module Propagation Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed1 Parameter Description Min. Min. Min. Min. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns Predicted Routing Max. Max. Max. Max. Min. Max. Units Delays3 tRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-203 A1425A, A14V25A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Predicted Input Routing Max. Max. Max. Max. Max. Units Delays1 tIRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tIRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tIRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tIRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tIRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input F-F Data Setup (w.r.t. IOCLK Pad) 1.8 2.0 2.3 2.7 3.0 ns Input Data Enable Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input Data Enable Setup (w.r.t. IOCLK Pad) 5.8 6.5 7.5 8.6 8.6 ns Output F-F Data Hold (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output F-F Data Setup (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output Data Enable Hold (w.r.t. IOCLK Pad) 0.3 0.4 0.4 0.5 0.5 ns Output Data Enable Setup (w.r.t. IOCLK Pad) 1.3 1.5 1.7 2.0 2.0 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-204 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1425A, A14V25A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 4.0 4.5 5.1 6.0 7.8 ns Enable to Pad, Z to H/L, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Hi Slew 6.5 7.5 8.5 10.0 13.0 ns Enable to Pad, H/L to Z, Lo Slew 6.5 7.5 8.5 10.0 13.0 ns IOCLK Pad to Pad H/L, Hi Slew 7.5 7.5 9.0 10.0 13.0 ns IOCLK Pad to Pad H/L, Lo Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS I/O Module – CMOS Max. Max. Max. Max. Max. Units Output Timing1 tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 5.2 5.9 6.6 7.8 10.1 ns Enable to Pad, Z to H/L, Lo Slew 8.9 10.0 11.3 13.3 17.3 ns Enable to Pad, H/L to Z, Hi Slew 6.7 7.5 8.5 10.0 13.0 ns Enable to Pad, H/L to Z, Lo Slew 6.7 7.5 9.0 10.0 13.0 ns IOCLK Pad to Pad H/L, Hi Slew 8.9 8.9 10.7 11.8 15.3 ns IOCLK Pad to Pad H/L, Lo Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Note: 1. Delays based on 35pF loading. 1-205 A1425A, A14V25A Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tIOCKH Input Low to High (Pad to I/O Module Input) Max. 2.0 Max. 2.3 Max. 2.6 Max. 3.0 Max. Units 3.5 ns tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIOPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 0.4 4.0 0.4 5.0 0.4 6.8 0.4 8.0 0.4 10.0 ns ns 250 200 150 125 100 MHz Input Low to High (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Input High to Low (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO=64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO=64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO=64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL Min. Pulse Width Low (FO=64) 3.3 3.8 4.2 4.9 6.5 ns tRCKSW Maximum Skew (FO=128) tRP Minimum Period (FO=64) fRMAX Maximum Frequency (FO=64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns ns H-Clock to R-Clock Skew (FO = 64) (FO = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-206 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1440A, A14V40A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70°C) 1 Logic Module Propagation Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed1 Parameter Description Min. Min. Min. Min. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns Predicted Routing Max. Max. Max. Max. Min. Max. Units Delays3 tRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns tA Flip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-207 A1440A, A14V40A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Predicted Input Routing Max. Max. Max. Max. Max. Units Delays1 tIRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tIRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tIRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tIRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tIRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input F-F Data Setup (w.r.t. IOCLK Pad) 1.5 1.7 2.0 2.3 2.3 ns Input Data Enable Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input Data Enable Setup (w.r.t. IOCLK Pad) 5.8 6.5 7.5 8.6 8.6 ns Output F-F Data Hold (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output F-F Data Setup (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output Data Enable Hold (w.r.t. IOCLK Pad) 0.3 0.4 0.4 0.5 0.5 ns Output Data Enable Setup (w.r.t. IOCLK Pad) 1.3 1.5 1.7 2.0 2.0 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-208 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1440A, A14V40A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 4.0 4.5 5.1 6.0 7.8 ns Enable to Pad, Z to H/L, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Hi Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 8.5 8.5 9.5 11.0 14.3 ns IOCLK Pad to Pad H/L, Lo Slew 11.3 11.3 13.5 15.0 19.5 ns dTLHHS Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS I/O Module – CMOS Max. Max. Max. Max. Max. Units Output Timing1 tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 5.2 5.9 6.6 7.8 10.1 ns Enable to Pad, Z to H/L, Lo Slew 8.9 10.0 11.3 13.3 17.3 ns Enable to Pad, H/L to Z, Hi Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 9.0 9.0 10.1 11.8 14.3 ns IOCLK Pad to Pad H/L, Lo Slew 13.0 13.0 15.6 17.3 22.5 ns dTLHHS Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Note: 1. Delays based on 35pF loading. 1-209 A1440A, A14V40A Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tIOCKH Input Low to High (Pad to I/O Module Input) Max. 2.0 Max. 2.3 Max. 2.6 Max. 3.0 Max. Units 3.5 ns tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tIOPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 0.4 4.0 0.4 5.0 0.4 6.8 0.4 8.0 0.4 10.0 ns ns 250 200 150 125 100 MHz Input Low to High (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Input High to Low (Pad to S-Module Input) 3.0 3.4 3.9 4.5 5.5 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 4.0 0.3 5.0 0.3 6.8 0.3 8.0 0.3 10.0 ns ns 250 200 150 125 100 MHz Routed Array Clock Networks tRCKH Input Low to High (FO=64) 3.7 4.1 4.7 5.5 9.0 ns tRCKL Input High to Low (FO=64) 4.0 4.5 5.1 6.0 9.0 ns tRPWH Min. Pulse Width High (FO=64) 3.3 3.8 4.2 4.9 6.5 ns Min. Pulse Width Low (FO=64) 3.3 3.8 4.2 4.9 6.5 ns tRPWL tRCKSW Maximum Skew (FO=128) tRP Minimum Period (FO=64) fRMAX Maximum Frequency (FO=64) 0.7 6.8 0.8 8.0 150 0.9 8.7 125 1.0 10.0 115 1.0 13.4 100 ns ns 75 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns ns H-Clock to R-Clock Skew (FO = 64) (FO = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-210 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1460A, A14V60A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70°C) 1 Logic Module Propagation Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed1 Parameter Description Min. Min. Min. Min. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns Predicted Routing Max. Max. Max. Max. Min. Max. Units Delays3 tRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tWCLKA Flip-Flop Clock Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tA Flip-Flop Clock Input Period 5.0 6.8 8.0 10.0 13.4 ns fMAX Flip-Flop Clock Frequency 200 150 125 100 75 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-211 A1460A, A14V60A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Predicted Input Routing Max. Max. Max. Max. Max. Units Delays1 tIRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tIRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tIRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tIRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tIRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input F-F Data Setup (w.r.t. IOCLK Pad) 1.3 1.5 1.8 2.0 2.0 ns Input Data Enable Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input Data Enable Setup (w.r.t. IOCLK Pad) 5.8 6.5 7.5 8.6 8.6 ns Output F-F Data Hold (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output F-F Data Setup (w.r.t. IOCLK Pad) 0.7 0.8 0.9 1.0 1.0 ns Output Data Enable Hold (w.r.t. IOCLK Pad) 0.3 0.4 0.4 0.5 0.5 ns Output Data Enable Setup (w.r.t. IOCLK Pad) 1.3 1.5 1.7 2.0 2.0 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-212 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A1460A, A14V60A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 4.0 4.5 5.1 6.0 7.8 ns Enable to Pad, Z to H/L, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Hi Slew 7.8 8.7 9.9 11.6 15.1 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 9.0 9.0 10.0 11.5 15.0 ns IOCLK Pad to Pad H/L, Lo Slew 12.8 12.8 15.3 17.0 22.1 ns dTLHHS Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS I/O Module – CMOS Max. Max. Max. Max. Max. Units Output Timing1 tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 5.2 5.9 6.6 7.8 10.1 ns Enable to Pad, Z to H/L, Lo Slew 8.9 10.0 11.3 13.3 17.3 ns Enable to Pad, H/L to Z, Hi Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 10.4 10.4 12.1 13.8 17.9 ns IOCLK Pad to Pad H/L, Lo Slew 14.5 14.5 17.4 19.3 25.1 ns dTLHHS Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Note: 1. Delays based on 35pF loading. 1-213 A1460A, A14V60A Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tIOCKH Input Low to High (Pad to I/O Module Input) Max. 2.3 Max. 2.6 Max. 3.0 Max. 3.5 Max. Units 4.5 ns tIOPWH Minimum Pulse Width High 2.4 3.2 3.8 4.8 6.5 ns tIOPWL Minimum Pulse Width Low 2.4 3.2 3.8 4.8 6.5 ns tIOSAPW Minimum Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.6 8.0 0.6 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Input Low to High (Pad to S-Module Input) 3.7 4.1 4.7 5.5 7.0 ns Input High to Low (Pad to S-Module Input) 3.7 4.1 4.7 5.5 7.0 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width High 2.4 3.2 3.8 4.8 6.5 ns tHPWL Minimum Pulse Width Low 2.4 3.2 3.8 4.8 6.5 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.6 8.0 0.6 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Routed Array Clock Networks tRCKH Input Low to High (FO=256) 6.0 6.8 7.7 9.0 11.8 ns tRCKL Input High to Low (FO=256) 6.0 6.8 7.7 9.0 11.8 ns tRPWH Min. Pulse Width High (FO=256) 4.1 4.5 5.4 6.1 8.2 ns Min. Pulse Width Low (FO=256) 4.1 4.5 5.4 6.1 8.2 ns tRPWL tRCKSW Maximum Skew (FO=128) tRP Minimum Period (FO=256) fRMAX Maximum Frequency (FO=256) 1.2 8.3 1.4 9.3 120 1.6 11.1 105 1.8 12.5 90 1.8 16.7 80 ns ns 60 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 216) 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns ns H-Clock to R-Clock Skew (FO = 64) (FO = 216) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-214 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A14100A, A14V100A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4.75 V, T J = 70°C) 1 Logic Module Propagation Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed1 Parameter Description Min. Min. Min. Min. tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns Predicted Routing Max. Max. Max. Max. Min. Max. Units Delays3 tRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns Logic Module Sequential Timing tSUD Flip-Flop Data Input Setup 0.5 0.6 0.8 0.8 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.5 0.5 0.5 ns tSUD Latch Data Input Setup 0.5 0.6 0.8 0.8 0.8 ns tHD Latch Data Input Hold 0.0 0.0 0.5 0.5 0.5 ns tWASYN Asynchronous Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tWCLKA Flip-Flop Clock Pulse Width 2.4 3.2 3.8 4.8 6.5 ns tA Flip-Flop Clock Input Period 5.0 6.8 8.0 10.0 13.4 ns fMAX Flip-Flop Clock Frequency 200 150 125 100 75 MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-215 A14100A, A14V100A Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns tOCLRY Predicted Input Routing Max. Max. Max. Max. Max. Units Delays1 tIRD1 FO=1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns tIRD2 FO=2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns tIRD3 FO=3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns tIRD4 FO=4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns tIRD8 FO=8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input F-F Data Setup (w.r.t. IOCLK Pad) 1.2 1.4 1.5 1.8 1.8 ns Input Data Enable Hold (w.r.t. IOCLK Pad) 0.0 0.0 0.0 0.0 0.0 ns Input Data Enable Setup (w.r.t. IOCLK Pad) 5.8 6.5 7.5 8.6 8.6 ns Output F-F Data Hold (w.r.t. IOCLK Pad) 0.7 0.8 1.0 1.0 1.0 ns Output F-F Data Setup (w.r.t. IOCLK Pad) 0.7 0.8 1.0 1.0 1.0 ns Output Data Enable Hold (w.r.t. IOCLK Pad) 0.3 0.4 0.5 0.5 0.5 ns Output Data Enable Setup (w.r.t. IOCLK Pad) 1.3 1.5 2.0 2.0 2.0 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-216 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y A14100A, A14V100A Timing Characteristics (continued) (Worst-Case Commercial Conditions ) I/O Module – TTL Output Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 4.0 4.5 5.1 6.0 7.8 ns Enable to Pad, Z to H/L, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns Enable to Pad, H/L to Z, Hi Slew 8.0 9.0 10.2 12.0 15.6 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 9.5 9.5 10.5 12.0 15.6 ns IOCLK Pad to Pad H/L, Lo Slew 12.8 12.8 15.3 17.0 22.1 ns dTLHHS Delta Low to High, Hi Slew 0.02 0.02 0.03 0.03 0.04 ns/pF dTLHLS Delta Low to High, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF dTHLHS Delta High to Low, Hi Slew 0.04 0.04 0.04 0.05 0.07 ns/pF dTHLLS Delta High to Low, Lo Slew 0.05 0.05 0.06 0.07 0.09 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS I/O Module – CMOS Max. Max. Max. Max. Max. Units Output Timing1 tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns tENZHS Enable to Pad, Z to H/L, Hi Slew 5.2 5.9 6.6 7.8 10.1 ns Enable to Pad, Z to H/L, Lo Slew 8.9 10.0 11.3 13.3 17.3 ns Enable to Pad, H/L to Z, Hi Slew 8.0 9.0 10.0 12.0 15.6 ns Enable to Pad, H/L to Z, Lo Slew 7.4 8.3 9.4 11.0 14.3 ns IOCLK Pad to Pad H/L, Hi Slew 10.4 10.4 12.4 13.8 17.9 ns IOCLK Pad to Pad H/L, Lo Slew 14.5 14.5 17.4 19.3 25.1 ns dTLHHS Delta Low to High, Hi Slew 0.04 0.04 0.05 0.06 0.08 ns/pF dTLHLS Delta Low to High, Lo Slew 0.07 0.08 0.09 0.11 0.14 ns/pF dTHLHS Delta High to Low, Hi Slew 0.03 0.03 0.03 0.04 0.05 ns/pF dTHLLS Delta High to Low, Lo Slew 0.04 0.04 0.04 0.05 0.07 ns/pF tENZLS tENHSZ tENLSZ tCKHS tCKLS Note: 1. Delays based on 35pF loading. 1-217 A14100A, A14V100A Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3V Speed Parameter Description Min. Min. Min. Min. Min. tIOCKH Input Low to High (Pad to I/O Module Input) Max. 2.3 Max. 2.6 Max. 3.0 Max. 3.5 Max. Units 4.5 ns tIOPWH Minimum Pulse Width High 2.4 3.3 3.8 4.8 6.5 ns tIOPWL Minimum Pulse Width Low 2.4 3.3 3.8 4.8 6.5 ns tIOSAPW Minimum Asynchronous Pulse Width 2.4 3.3 3.8 4.8 6.5 ns tIOCKSW Maximum Skew tIOP Minimum Period fIOMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.7 8.0 0.8 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Input Low to High (Pad to S-Module Input) 3.7 4.1 4.7 5.5 7.0 ns Input High to Low (Pad to S-Module Input) 3.7 4.1 4.7 5.5 7.0 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width High 2.4 3.3 3.8 4.8 6.5 ns tHPWL Minimum Pulse Width Low 2.4 3.3 3.8 4.8 6.5 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.6 5.0 0.6 6.8 0.7 8.0 0.8 10.0 0.6 13.4 ns ns 200 150 125 100 75 MHz Routed Array Clock Networks tRCKH Input Low to High (FO=256) 6.0 6.8 7.7 9.0 11.8 ns tRCKL Input High to Low (FO=256) 6.0 6.8 7.7 9.0 11.8 ns tRPWH Min. Pulse Width High (FO=256) 4.1 4.5 5.4 6.1 8.2 ns Min. Pulse Width Low (FO=256) 4.1 4.5 5.4 6.1 8.2 ns tRPWL tRCKSW Maximum Skew (FO=128) tRP Minimum Period (FO=256) fRMAX Maximum Frequency (FO=256) 1..2 8.3 1.4 9.3 120 1.6 11.1 105 1.8 12.5 90 1.8 16.7 80 ns ns 60 MHz Clock-to-Clock Skews tIOHCKSW I/O Clock to H-Clock Skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns tIORCKSW I/O Clock to R-Clock Skew (FO = 64) (FO = 350) 0.0 0.0 1.7 5.0 0.0 0.0 17 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns H-Clock to R-Clock Skew (FO = 64) (FO = 350) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-218 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Package Pin Assignments 100-Pin PQFP (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 100-Pin 90 41 PQFP 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Number A1415 Function A1425 Function 2 IOCLK, I/O IOCLK, I/O 14 CLKA, I/O 15 Pin Number A1415 Function A1425 Function 48 VCC VCC CLKA, I/O 61 PRB, I/O PRB, I/O CLKB, I/O CLKB, I/O 62 GND GND 16 VCC VCC 63 VCC VCC 17 GND GND 64 GND GND 18 VCC VCC 65 VCC VCC 19 GND GND 67 HCLK, I/O HCLK, I/O 20 PRA, I/O PRA, I/O 78 IOPCL, I/O IOPCL, I/O 27 DCLK, I/O DCLK, I/O 79 GND GND 28 GND GND 85 VCC VCC 29 SDI, I/O SDI, I/O 86 VCC VCC 34 MODE MODE 87 GND GND 35 VCC VCC 96 VCC VCC 36 GND GND 97 GND GND 47 GND GND Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-219 Package Pin Assignments (continued) 84-Pin PLCC (Top View) 11 10 9 8 7 6 5 4 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 21 65 84-Pin PLCC 22 64 23 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 1-220 3 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 84-Pin PLCC A1415 A14V15 Function A1425 A14V25 Function A1440 A14V40 Function 1 VCC VCC VCC 2 GND GND GND 3 VCC VCC VCC 4 PRA, I/O PRA, I/O PRA, I/O 11 DCLK, I/O DCLK, I/O DCLK, I/O 12 SDI, I/O SDI, I/O SDI, I/O 16 MODE MODE MODE 27 GND GND GND 28 VCC VCC VCC 40 PRB, I/O PRB, I/O PRB, I/O 41 VCC VCC VCC 42 GND GND GND 43 VCC VCC VCC 45 HCLK, I/O HCLK, I/O HCLK, I/O 53 IOPCL, I/O IOPCL, I/O IOPCL, I/O 59 VCC VCC VCC 60 VCC VCC VCC 61 GND GND GND 68 VCC VCC VCC 69 GND GND GND 74 IOCLK, I/O IOCLK, I/O IOCLK, I/O 83 CLKA, I/O CLKA, I/O CLKA, I/O 84 CLKB, I/O CLKB, I/O CLKB, I/O Pin Number Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-221 Package Pin Assignments (continued) 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 160-Pin PQFP (Top View) 160-Pin PQFP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1-222 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 160-Pin PQFP A1425 A14V25 Function A1440 A14V40 Function A1460 A14V60 Function A1425 A14V25 Function A1440 A14V40 Function A1460 A14V60 Function 1 GND GND GND 90 VCC VCC VCC 2 SDI, I/O SDI, I/O SDI, I/O 91 VCC VCC VCC 5 NC I/O I/O 92 NC I/O I/O 9 MODE MODE MODE 93 NC I/O I/O 10 VCC VCC VCC 98 GND GND GND 14 NC I/O I/O 99 VCC VCC VCC 15 GND GND GND 100 NC I/O I/O 18 VCC VCC VCC 103 GND GND GND 19 GND GND GND 107 NC I/O I/O 20 NC I/O I/O 109 NC I/O I/O 24 NC I/O I/O 110 VCC VCC VCC 27 NC I/O I/O 111 GND GND GND 28 VCC VCC VCC 112 VCC VCC VCC 29 VCC VCC VCC 113 NC I/O I/O 40 GND GND GND 119 NC I/O I/O 41 NC I/O I/O 120 IOCLK, I/O IOCLK, I/O IOCLK, I/O 43 NC I/O I/O 121 GND GND GND 45 NC I/O I/O 124 NC I/O I/O 46 VCC VCC VCC 127 NC I/O I/O 47 NC I/O I/O 136 CLKA, I/O CLKA, I/O CLKA, I/O 49 NC I/O I/O 137 CLKB, I/O CLKB, I/O CLKB, I/O 51 NC I/O I/O 138 VCC VCC VCC 53 NC I/O I/O 139 GND GND GND 58 PRB, I/O PRB, I/O PRB, I/O 140 VCC VCC VCC 59 GND GND GND 141 GND GND GND 60 VCC VCC VCC 142 PRA, I/O PRA, I/O PRA, I/O 62 HCLK, I/O HCLK, I/O HCLK, I/O 143 NC I/O I/O 63 GND GND GND 145 NC I/O I/O 74 NC I/O I/O 147 NC I/O I/O 75 VCC VCC VCC 149 NC I/O I/O 76 NC I/O I/O 151 NC I/O I/O 77 NC I/O I/O 153 NC I/O I/O 78 NC I/O I/O 154 VCC VCC VCC 80 IOPCL, I/O IOPCL, I/O IOPCL, I/O 160 DCLK, I/O DCLK, I/O DCLK, I/O 81 GND GND GND Pin Number Pin Number Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-223 Package Pin Assignments (continued) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 208-Pin PQFP, RQFP (Top View) 208-Pin PQFP, RQFP 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 1-224 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 208-Pin PQFP, RQFP A1460 A14V60 Function A14100 A14V100 Function A1460 A14V60 Function A14100 A14V100 Function 1 GND GND 115 VCC VCC 2 SDI, I/O SDI, I/O 116 NC I/O 11 MODE MODE 129 GND GND 12 VCC VCC 130 VCC VCC 25 VCC VCC 131 GND GND 26 GND GND 132 VCC VCC 27 VCC VCC 145 VCC VCC 28 GND GND 146 GND GND 40 VCC VCC 147 NC I/O 41 VCC VCC 148 VCC VCC 52 GND GND 156 IOCLK, I/O IOCLK, I/O 53 NC I/O 157 GND GND 60 VCC VCC 158 NC I/O 65 NC I/O 164 VCC VCC 76 PRB, I/O PRB, I/O 180 CLKA, I/O CLKA, I/O 77 GND GND 181 CLKB, I/O CLKB, I/O 78 VCC VCC 182 VCC VCC 79 GND GND 183 GND GND 80 VCC VCC 184 VCC VCC 82 HCLK, I/O HCLK, I/O 185 GND GND 98 VCC VCC 186 PRA, I/O PRA, I/O 102 NC I/O 195 NC I/O 104 IOPCL, I/O IOPCL, I/O 201 VCC VCC 105 GND GND 205 NC I/O 114 VCC VCC 208 DCLK, I/O DCLK, I/O Pin Number Pin Number Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-225 Package Pin Assignments (continued) 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 176-Pin TQFP (Top View) 176-Pin TQFP 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1-226 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 176-Pin TQFP A1440 A14V40 Function A1460 A14V60 Function A1440 A14V40 Function A1460 A14V60 Function 1 GND GND 98 VCC VCC 2 SDI, I/O SDI, I/O 99 VCC VCC 10 MODE MODE 108 GND GND 11 VCC VCC 109 VCC VCC 20 NC I/O 110 GND GND 21 GND GND 119 NC I/O 22 VCC VCC 121 NC I/O 23 GND GND 122 VCC VCC 32 VCC VCC 123 GND GND 33 VCC VCC 124 VCC VCC 44 GND GND 132 IOCLK, I/O IOCLK, I/O 49 NC I/O 133 GND GND 51 NC I/O 138 NC I/O 63 NC I/O 152 CLKA, I/O CLKA, I/O 64 PRB, I/O PRB, I/O 153 CLKB, I/O CLKB, I/O 65 GND GND 154 VCC VCC 66 VCC VCC 155 GND GND 67 VCC VCC 156 VCC VCC 69 HCLK, I/O HCLK, I/O 157 PRA, I/O PRA, I/O 82 NC I/O 158 NC I/O 83 NC I/O 170 NC I/O 88 IOPCL, I/O IOPCL, I/O 176 DCLK, I/O DCLK, I/O 89 GND GND Pin Number Pin Number Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-227 Package Pin Assignments (continued) 76 77 78 80 79 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 100-Pin VQFP (Top View) 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 100-Pin VQFP 12 13 63 50 49 48 47 46 45 44 43 42 41 40 39 51 38 52 25 37 53 24 36 54 23 35 55 22 34 56 21 33 57 20 32 58 19 31 59 18 30 60 17 29 61 16 28 62 15 27 14 26 1-228 64 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 100-Pin VQFP A1415 A14V15 Function A1425 A14V25 Function A1440 A14V40 Function 1 GND GND GND 2 SDI, I/O SDI, I/O SDI, I/O 7 MODE MODE MODE 8 VCC VCC VCC 9 GND GND GND 20 VCC VCC VCC 21 NC I/O I/O 34 PRB, I/O PRB, I/O PRB, I/O 35 VCC VCC VCC 36 GND GND GND 37 VCC VCC VCC 39 HCLK, I/O HCLK, I/O HCLK, I/O 50 IOPCL, I/O IOPCL, I/O IOPCL, I/O 51 GND GND GND 57 VCC VCC VCC 58 VCC VCC VCC 67 VCC VCC VCC 68 GND GND GND 69 GND GND GND 74 NC I/O I/O 75 IOCLK, I/O IOCLK, I/O IOCLK, I/O 87 CLKA, I/O CLKA, I/O CLKA, I/O 88 CLKB, I/O CLKB, I/O CLKB, I/O 89 VCC VCC VCC 90 VCC VCC VCC 91 GND GND GND 92 PRA, I/O PRA, I/O PRA, I/O 93 NC I/O I/O 100 DCLK, I/O DCLK, I/O DCLK, I/O Pin Number Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-229 Package Pin Assigments (continued) 132-Pin CQFP (Top View) 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 Pin #1 Index 1 99 2 98 3 97 4 96 5 95 6 94 7 93 8 92 132-Pin CQFP 25 75 26 74 27 73 28 72 29 71 30 70 31 69 32 68 33 67 34 35 36 37 38 39 40 41 42 1-230 59 60 61 62 63 64 65 66 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 132-Pin CQFP Pin Number A1425 Function Pin Number A1425 Function 1 NC 74 GND 2 GND 75 VCC 3 SDI, I/O 78 VCC 9 MODE 89 VCC 10 GND 90 GND 11 VCC 91 VCC 22 VCC 92 GND 26 GND 98 IOCLK, I/O 27 VCC 99 NC 34 NC 100 NC 36 GND 101 GND 42 GND 106 GND 43 VCC 107 VCC 48 PRB, I/O 116 CLKA, I/O 50 HCLK, I/O 117 CLKB, I/O 58 GND 118 PRA, I/O 59 VCC 122 GND 64 IOPCL, I/O 123 VCC 65 GND 131 DCLK, I/O 66 NC 132 NC 67 NC Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-231 Package Pin Assigments (continued) 196-Pin CQFP (Top View) 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 Pin #1 Index 1 147 2 146 3 145 4 144 5 143 6 142 7 141 8 140 196-Pin CQFP 41 107 42 106 43 105 44 104 45 103 46 102 47 101 48 100 49 99 50 51 52 53 54 55 56 57 58 1-232 91 92 93 94 95 96 97 98 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 196-Pin CQFP Pin Number A1460 Function Pin Number A1460 Function 1 GND 110 VCC 2 SDI, I/O 111 VCC 11 MODE 112 GND 12 VCC 137 VCC 13 GND 138 GND 37 GND 139 GND 38 VCC 140 VCC 39 VCC 148 IOCLK, I/O 51 GND 149 GND 52 GND 155 VCC 59 VCC 162 GND 64 GND 172 CLKA, I/O 77 HCLK, I/O 173 CLKB, I/O 79 PRB, I/O 174 PRA, I/O 86 GND 183 GND 94 VCC 189 VCC 98 GND 193 GND 100 IOPCL, I/O 196 DCLK, I/O 101 GND Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-233 Package Pin Assigments (continued) 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 1 192 2 191 3 190 4 189 5 188 6 187 7 186 8 185 256-Pin CQFP 56 137 57 136 58 135 59 134 60 133 61 132 62 131 63 130 64 129 65 66 67 68 69 70 71 72 73 1-234 121 122 123 124 125 126 127 128 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y 256-Pin CQFP Pin Number A14100 Function Pin Number A14100 Function 1 GND 158 GND 2 SDI, I/O 159 VCC 11 MODE 160 GND 28 VCC 161 VCC 29 GND 174 VCC 30 VCC 175 GND 31 GND 176 GND 46 VCC 188 IOCLK, I/O 59 GND 189 GND 90 PRB, I/O 219 CLKA, I/O 91 GND 220 CLKB, I/O 92 VCC 221 VCC 93 GND 222 GND 94 VCC 223 VCC 96 HCLK, I/O 224 GND 110 GND 225 PRA, I/O 127 IOPCL, I/O 240 GND 128 GND 256 DCLK, I/O 141 VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. NC: Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-235 Package Pin Assignments (continued) 225-Pin BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A1460 Function Location CLKA or I/O C8 CLKB or I/O B8 DCLK or I/O B2 GND A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15 HCLK or I/O P9 IOCLK or I/O B14 IOPCL or I/O P14 MODE D1 NC A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14 PRA OR I/O A7 PRB or I/O L7 SDI or I/O D4 VCC A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13 Notes: 1. Unused I/O pins are designated as outputs by ALS and are driven low. 2. All unassigned pins are available for use as I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-236 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Package Pin Assignments (continued) 313-Pin BGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A A B B C C D D E E F F G G H H J J K K L L M M N N P P R R T U T U V V W W Y AA Y AA AB AB AC AC AD AD AE AE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A14100 A14V100 Function Location CLKA or I/O J13 CLKB or I/O G13 DCLK or I/O B2 GND A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13 HCLK or I/O T14 IOCLK or I/O B24 IOPCL or I/O AD24 MODE G3 NC A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25, D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7, N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24 PRA OR I/O H12 PRB or I/O AD12 SDI or I/O C1 VCC AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-237 Package Pin Assignments (continued) 100-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E 100-Pin CPGA F F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 Orientation Pin A1415 Function Location CLKA or I/O C7 CLKB or I/O D6 DCLK or I/O C4 GND C3, C6, C9, E9, F3, F9, J3, J6, J8, J9 HCLK or I/O H6 IOCLK or I/O C10 IOPCL or I/O K9 MODE C2 PRA OR I/O A6 PRB or I/O L3 SDI or I/O B3 VCC B6, B10, E11, F2, F10, G2, K2, K6, K10 Notes: 1. 2. 3. 1-238 Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Package Pin Assignments (continued) 133-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 A A B B C C D D E E F F 133-Pin CPGA G G H H J J K K L L M M N N 1 2 3 4 5 6 7 8 9 10 11 12 13 A1425 Function Location CLKA or I/O D7 CLKB or I/O B6 DCLK or I/O D4 GND A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12 HCLK or I/O K7 IOCLK or I/O C10 IOPCL or I/O L10 MODE E3 NC A1, A7, A13, G1, G13, N1, N7, N13 PRA OR I/O A6 PRB or I/O L6 SDI or I/O C2 VCC B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-239 Package Pin Assignments (continued) 175-Pin CPGA (Top View) A B C D E F G H J K L M N P R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 175-Pin CPGA 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 A B C D E A1440 Function Location CLKA or I/O C9 CLKB or I/O A9 F G H J K L M N P R DCLK or I/O D5 GND D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8, M12 HCLK or I/O R8 IOCLK or I/O E12 IOPCL or I/O P13 MODE F3 NC A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15 PRA OR I/O B8 PRB or I/O R7 SDI or I/O D3 VCC C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13 Notes: 1. 2. 3. 1-240 Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 Fami l y Package Pin Assignments (continued) 207-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A A B B C C D D E E F F G G H H 207-Pin CPGA J J K K L L M M N N P P R R S S T T 1 2 3 4 5 A1460 Function Location CLKA or I/O K1 CLKB or I/O J3 6 7 8 9 10 11 12 13 14 15 16 17 DCLK or I/O E4 GND C15, D4, D5, D9, D14, J4, J14, P3, P4, P7, P9, P14, R15 HCKL or I/O J15 IOCLK or I/O P5 IOPCL or I/O N14 MODE D7 NC A1, A2, A16, A17, B1, B17, C1, C2, S1, S3, S17, T1, T2, T16, T17 PRA OR I/O H1 PRB or I/O K16 SDI or I/O C3 VCC B2, B9, B16, D11, J2, J16, P12, S2, S9, S16, T5 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-241 Package Pin Assignments (continued) 257-Pin CPGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A A B B C C D D E E F F G G H H J J 257-Pin CPGA K L K L M M N N P P R R T T V V X X Y Y 1 2 3 4 A14100 Function Location CLKA or I/O L4 CLKB or I/O L5 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DCLK or I/O E4 GND B16, C4, D4, D10, D16, E11, J5, K4, K16, L15, R4, T4, T10, T16, T17, X7 HCLK or I/O J16 IOCLK or I/O T5 IOPCL or I/O R16 MODE A5 NC E5 PRA OR I/O J1 PRB or I/O J17 SDI or I/O B4 VCC C3, C10, C13, C17, K3, K17, V3, V7, V10, V17, X14 Notes: 1. 2. 3. 1-242 Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND.