AMIC A29L004AW 512k x 8 bit cmos 3.0 volt-only, boot sector flash memory Datasheet

A29L004A Series
512K X 8 Bit CMOS 3.0 Volt-only,
Preliminary
Boot Sector Flash Memory
Document Title
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev.
0.0
History
Issue Date
Initial issue
March 9, 2005
PRELIMINARY
(March, 2005, Version 0.0)
Remark
Preliminary
AMIC Technology, Corp.
A29L004A Series
512K X 8 Bit CMOS 3.0 Volt-only,
Preliminary
Boot Sector Flash Memory
Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
- Regulated voltage range: 3.0 to 3.6 volt read and write
operations for compatibility with high performance 3.3
volt microprocessors
Access times:
- 70/90 (max.)
Current:
- 4 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that
sector. Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
- Superior inadvertent write protection
Data Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Ready / BUSY pin (RY / BY )
- Provides a hardware method of detecting completion of
program or erase operations (not available on 32-pin
PLCC & (s)TSOP packages)
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin ( RESET )
- Hardware method to reset the device to reading array
data (not available on 32 pin PLCC & (s)TSOP
packages)
Package options
- 40-pin TSOP (forward type), 32-pin PLCC or (s)TSOP
(forward type)
General Description
The A29L004A is a 4Mbit, 3.0 volt-only Flash memory
organized as 524,288 bytes of 8 bits. The 8 bits of data
appear on I/O0 - I/O7. The A29L004A is offered in 40-pin
TSOP, 32-pin PLCC or (s)TSOP packages. This device is
designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L004A can also be programmed in standard EPROM
programmers.
The A29L004A has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29L004A has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29L004A also offers the ability to program in the Erase
Suspend mode. The standard A29L004A offers access times
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable ( CE ), write enable ( WE )
and output enable ( OE ) controls.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
PRELIMINARY
(March, 2005, Version 0.0)
The A29L004A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY / BY pin (not
1
AMIC Technology, Corp.
A29L004A Series
available on 32-pin PLCC & (s)TSOP), or by reading the I/O7
( Data Polling) and I/O6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready to
read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L004A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data (not available on 32-pin PLCC & (s)TSOP). The
RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the device, enabling the
system microprocessor to read the boot-up firmware from the
Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
40-pin TSOP
A16
1
40
A17
A15
2
39
VSS
A14
3
38
NC
A13
4
37
NC
A12
5
36
A10
A11
6
35
I/O7
A9
7
34
I/O6
A8
8
33
I/O5
WE
9
32
I/O4
31
VCC
A29L004AW
RESET
10
NC
11
30
VCC
RY/BY
12
29
NC
A18
13
28
I/O3
A7
14
27
I/O2
A6
15
26
I/O1
A5
16
25
I/O0
A4
17
24
OE
A3
18
23
VSS
A2
19
22
CE
A1
20
21
A0
WE
VCC
A17
30
31
32
A16
A18
1
A15
32-pin TSOP (8mm X 20mm)
32-pin sTSOP (8mm X 13.4mm)
32-pin sTSOP (8mm X 14mm)
2
3
4
A12
PLCC
A7
5
29
A14
A6
6
28
A13
A5
7
27
A8
A4
8
26
A9
A3
9
25
A11
A2
10
24
OE
A1
11
23
A10
A0
12
22
CE
I/O0
13
21
I/O7
PRELIMINARY
15
16
17
18
19
20
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O1
14
A29L004AL
(March, 2005, Version 0.0)
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A29L004AV (8mm X 20mm)
A29L004AX (8mm X 13.4mm)
A29L004AY (8mm X 14mm)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
AMIC Technology, Corp.
A29L004A Series
Block Diagram
RY/BY (N/A 32-pin PLCC, (s)TSOP)
VCC
VSS
I/O 0 - I/O 7
Sector Switches
Input/Output
Buffers
Erase Voltage
Generator
RESET
(N/A 32-pin PLCC,
(s)TSOP)
State
Control
WE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
CE
OE
VCC Detector
Address Latch
STB
Timer
A0-A18
STB
Data Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A18
Address Inputs
I/O0 - I/O7
Data Inputs/Outputs
CE
Chip Enable
WE
Write Enable
OE
Output Enable
RESET
Hardware Reset (N/A 32-pin PLCC, (s)TSOP)
RY/ BY
Ready/ BUSY - Output (N/A 32-pin PLCC, (s)TSOP)
VSS
Ground
VCC
Power Supply
NC
PRELIMINARY
Description
(March, 2005, Version 0.0)
Pin not connected internally
3
AMIC Technology, Corp.
A29L004A Series
Absolute Maximum Ratings*
*Comments
Storage Temperature Plastic Packages . …… .0°C to + 70°C
Ambient Temperature with Power Applied…… 0°C to + 70°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . …... . . . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . ….. . -0.5 to +12.5V
All other pins (Note 1) . . . . . . . . . . . ….. -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . ….. … 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Notes:
Operating Ranges
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
2. Minimum DC input voltage on A9, OE and RESET is -
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . ….. . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . ….. . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
0.5V. During voltage transitions, A9, OE and RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns. ( RESET is
N/A on 32-pin PLCC & (s)TSOP)
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29L004A Device Bus Operations
Operation
A0 – A18
I/O0 - I/O7
H
AIN
DOUT
L
H
AIN
DIN
X
X
VCC ± 0.3 V
X
High-Z
L
H
H
H
X
High-Z
X
X
X
L
X
High-Z
L
H
L
VID
Sector Address,
A6=L, A1=H, A0=L
DIN
Sector Unprotect
(See Note 2)
L
H
L
VID
Sector Address,
A6=H, A1=H, A0=L
DIN
Temporary Sector
Unprotect
X
X
X
VID
AIN
DIN
CE
OE
WE
Read
L
L
H
Write
L
H
VCC ± 0.3 V
Output Disable
Hardware Reset
Sector Protect
(See Note 2)
RESET
(N/A 32-pin PLCC, (s)TSOP)
CMOS Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:
1. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.
2. This function is not available on 32-pin PLCC & (s)TSOP packages.
PRELIMINARY
(March, 2005, Version 0.0)
4
AMIC Technology, Corp.
A29L004A Series
Requirements for Reading Array Data
The device enters the CMOS standby mode when the CE &
RESET pins ( CE only on 32-pin PLCC & (s)TSOP
packages) are both held at VCC ± 0.3V. (Note that this is a
more restricted voltage range than VIH.) If CE and RESET
(N/A on 32-pin PLCC & (s)TSOP packages) are held at VIH,
but not within VCC ± 0.3V, the device will be in the standby
mode, but the standby current will be greater. The device
requires the standard access time (tCE) before it is ready to
read data.
If the device is deselected during erasure or programming, the
device draws active current until the operation is completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
To read array data from the outputs, the system must drive the
CE and OE pins to VIL. CE is the power control and selects
the device. OE is the output control and gates array data to
the output pins. WE should remain at VIH all the time during
read operation. The internal state machine is set for reading
array data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content
occurs during the power transition. No command is necessary
in this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address
inputs produce valid data on the device data outputs. The
device remains enabled for read access until the command
register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
sleep mode is independent of the CE , WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep mode
current specification.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
OE to VIH. The device features an Unlock Bypass mode to
Output Disable Mode
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a byte, instead of four.
The “Byte Program Command Sequence” section has details
on programming data to the device using both standard and
Unlock Bypass command sequence. An erase operation can
erase one sector, multiple sectors, or the entire device. The
Sector Address Tables indicate the address range that each
sector occupies. A "sector address" consists of the address
inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
RESET : Hardware Reset Pin (N/A on 32-pin PLCC &
(s)TSOP packages)
The RESET pin provides a hardware method of resetting the
device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates all
data output pins, and ignores all read/write attempts for the
duration of the RESET pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws CMOS
standby current (ICC4 ). If RESET is held at VIL but not within
VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
the RY/ BY pin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor RY/ BY
to determine whether the reset operation is complete. If
RESET is asserted when a program or erase operation is not
Standby Mode
executing (RY/ BY pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The
system can read data tRH after the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET parameters
and diagram.
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE input.
PRELIMINARY
(March, 2005, Version 0.0)
5
AMIC Technology, Corp.
A29L004A Series
Table 2. A29L004A Top Boot Block Sector Address Table
Sector
A18
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
0
X
X
X
64
00000h - 0FFFFh
SA1
0
0
1
X
X
X
64
10000h - 1FFFFh
SA2
0
1
0
X
X
X
64
20000h - 2FFFFh
SA3
0
1
1
X
X
X
64
30000h - 3FFFFh
SA4
1
0
0
X
X
X
64
40000h - 4FFFFh
SA5
1
0
1
X
X
X
64
50000h - 5FFFFh
SA6
1
1
0
X
X
X
64
60000h - 6FFFFh
SA7
1
1
1
0
X
X
32
70000h - 77FFFh
SA8
1
1
1
1
0
0
8
78000h - 79FFFh
SA9
1
1
1
1
0
1
8
7A000h - 7BFFFh
SA10
1
1
1
1
1
X
16
7C000h - 7FFFFh
A13
Sector Size
(Kbytes)
Address Range
Table 3. A29L004A Bottom Boot Block Sector Address Table
Sector
A18
A17
SA0
0
0
SA1
0
0
SA2
0
0
SA3
0
SA4
A16
A14
(in hexadecimal)
0
0
X
16
00000h - 03FFFh
0
1
0
8
04000h - 05FFFh
0
0
1
1
8
06000h - 07FFFh
0
0
1
X
X
32
08000h - 0FFFFh
0
0
1
X
X
X
64
10000h - 1FFFFh
SA5
0
1
0
X
X
X
64
20000h - 2FFFFh
SA6
0
1
1
X
X
X
64
30000h - 3FFFFh
SA7
1
0
0
X
X
X
64
40000h - 4FFFFh
SA8
1
0
1
X
X
X
64
50000h - 5FFFFh
SA9
1
1
0
X
X
X
64
60000h - 6FFFFh
SA10
1
1
1
X
X
X
64
70000h - 7FFFFh
PRELIMINARY
0
A15
0
(March, 2005, Version 0.0)
6
AMIC Technology, Corp.
A29L004A Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when
verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown in
the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on using
the autoselect mode.
Table 4. A29L004A Autoselect Codes (High Voltage Method)
Description
Manufacturer ID: AMIC
Device ID: A29L004A
CE
OE
WE
A18
to
A13
A12
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
I/O7
to
I/O0
L
L
H
X
X
VID
X
L
X
L
L
37h
L
L
H
X
X
VID
X
L
X
L
H
34h
L
L
H
X
X
VID
X
L
X
L
H
B5h
L
L
H
X
X
VID
X
L
X
H
H
7Fh
(Top Boot Block)
Device ID: A29L004A
(Bottom Boot Block)
Continuation ID
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
01h
(protected)
00h
(unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences.
PRELIMINARY
(March, 2005, Version 0.0)
7
AMIC Technology, Corp.
A29L004A Series
Sector Protection/Unprotection
Temporary Sector Unprotect (N/A on 32-pin PLCC
& (s)TSOP packages)
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the
RESET pin only (N/A on 32-pin PLCC & (s)TSOP packages),
and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithm and
the Sector Protect / Unprotect Timing Diagram illustrates the
timing waveforms for this feature. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the first
sector unprotect write cycle. The alternate method must be
implemented using programming equipment. The procedure
requires a high voltage (VID) on address pin A9 and the
control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID.
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET pin, all the previously
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
START
RESET = VID
(Note 1)
Hardware Data Protection
Perform Erase or
Program Operations
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device
is powered up to read array data to avoid accidentally writing
data to the array.
RESET = VIH
Write Pulse "Glitch" Protection
Temporary Sector
Unprotect
Completed (Note 2)
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL,
CE = VIH or WE = VIH. To initiate a write cycle, CE and
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
WE must be a logical zero while OE is a logical one.
Figure 1. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of
WE . The internal state machine is automatically reset to
reading array data on the initial power-up.
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AMIC Technology, Corp.
A29L004A Series
START
START
Protect all sectors:
The indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors prior
to issuing the first sector
unprotect address
PLSCNT=1
RESET=V ID
Wait 1 us
No
Temporary Sector
Unprotect Mode
PLSCNT=1
RESET=V ID
Wait 1 us
No
First Write
Cycle=60h?
First Write
Cycle=60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
All sectors
protected?
Sector Protect
Write 60h to sector
address with A6=0,
A1=1, A0=0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Increment
PLSCNT
No
Reset
PLSCNT=1
Wait 15 ms
Read from
sector address
with A6=0,
A1=1, A0=0
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Increment
PLSCNT
No
PLSCNT
=25?
No
Read from sector
address with A6=1,
A1=1, A0=0
Data=01h?
No
Set up
next sector
address
Yes
Yes
Protect another
sector?
Device failed
PLSCNT=
1000?
Yes
No
Remove V ID
from RESET
Device failed
Write reset
command
Sector Protect
complete
Yes
Yes
No
Sector Protect
Algorithm
Data=00h?
Last sector
verified?
No
Yes
Remove V ID
from RESET
Sector Unprotect
Algorithm
Write reset
Command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
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A29L004A Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising
edge of WE or CE , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
section.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. Table 5 shows the
address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O7, I/O6, or RY/ BY (N/A on 32pin PLCC & (s)TSOP packages). See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
“1”, or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
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AMIC Technology, Corp.
A29L004A Series
00h. Addresses are don’t care for both cycle. The device
returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See the Erase/Program Operations in “AC Characteristics” for
parameters, and to Program Operation Timings for timing
diagrams.
START
Write Program
Command
Sequence
Embedded
Program
algorithm in
progress
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 4 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Data Poll
from System
Verify Data ?
No
Yes
Increment Address
Last Address ?
Yes
Programming
Completed
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase timeout of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50µs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50µs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 3. Program Operation
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unlock cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is required to program in this mode. The
first cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 5
shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the twocycle unlock bypass reset command sequence. The first
cycle must contain the data 90h; the second cycle the data
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AMIC Technology, Corp.
A29L004A Series
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
4 illustrates the algorithm for the erase operation. Refer to
the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
Erase Suspend/Erase Resume Commands
START
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erasesuspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within nonsuspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
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Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 4. Erase Operation
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AMIC Technology, Corp.
A29L004A Series
Command Sequence
(Note 1)
Cycles
Table 5. A29L004A Command Definitions
Bus Cycles (Notes 2 - 5)
First
Second
Addr Data
Addr Data
Third
Fourth
1
RA
RD
Reset (Note 7)
1
XXX
F0
4
555
AA
2AA
55
555
90
X00
37
4
555
AA
2AA
55
555
90
X01
34
Bottom Boot Block
4
555
AA
2AA
55
555
90
X01
B5
Continuation ID
4
555
AA
2AA
55
555
90
4
555
AA
2AA
55
555
90
X02 XX01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Unlock Bypass
3
555
AA
2AA
55
555
20
Autoselect (Note 8)
Sixth
Addr Data Addr Data Addr Data Addr Data
Read (Note 6)
Manufacturer ID
Fifth
Device ID,
Top Boot Block
Device ID,
7F
(SA) XX00
Sector Protect Verify
(Note 9)
X03
Unlock Bypass Program (Note 10)
2
XXX A0
PA
PD
Unlock Bypass Reset (Note 11)
2
XXX 90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A13 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.
9. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
10. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
11. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
12. The Erase Resume command is valid only during the Erase Suspend mode.
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A29L004A Series
Write Operation Status
START
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/ BY are provided in
the A29L004A to determine the status of a write operation
(RY/ BY pin is not available on 32-pin PLCC & (s)TSOP
packages). Table 6 and the following subsections describe
the functions of these status bits. I/O7, I/O6 and RY/ BY each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
Read I/O7-I/O0
Address = VA
I/O7: Data Polling
Yes
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data Polling is
I/O7 = Data ?
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data Polling produces a "1" on I/O7.This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
( OE ) is asserted low. The Data Polling Timings (During
Embedded Algorithms) in the "AC Characteristics" section
illustrates this. Table 6 shows the outputs for Data Polling
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
Yes
I/O7 = Data ?
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 5. Data Polling Algorithm
on I/O7. Figure 5 shows the Data Polling algorithm.
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A29L004A Series
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But I/O2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. I/O6, by comparison,
indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs for
I/O2 and I/O6.
Figure 6 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
RY/ BY : Read/ Busy (N/A on 32-pin PLCC & (s)TSOP
packages)
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequence. Since
RY/ BY is an open-drain output, several RY/ BY pins can be
tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 6 shows the outputs for RY/ BY . Refer to “ RESET
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
Reading Toggle Bits I/O6, I/O2
I/O6: Toggle Bit I
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O7 - I/O0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the
system must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6).
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
of the final WE pulse in the command sequence (prior to the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use either OE or CE to control the read
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 6 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit II".
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
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(March, 2005, Version 0.0)
15
AMIC Technology, Corp.
A29L004A Series
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out
is complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit I) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 6 shows the outputs for I/O3.
START
Read I/O7-I/O0
Read I/O7-I/O0
Toggle Bit
= Toggle ?
(Note 1)
No
Yes
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Twice
Toggle Bit
= Toggle ?
(Notes 1,2)
No
Yes
Program/Erase
Operation Not
Commplete, Write
Reset Command
Program/Erase
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O5
changes to "1". See text.
Figure 6. Toggle Bit Algorithm
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(March, 2005, Version 0.0)
16
AMIC Technology, Corp.
A29L004A Series
Table 6. Write Operation Status
I/O7
Operation
I/O6
(Note 1)
Standard
Mode
Embedded Program Algorithm
Erase
Suspend
Mode
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend-Program
I/O5
I/O3
(Note 2)
I/O2
(Note 1)
I/O7
Toggle
0
N/A
0
0
1
Toggle
No
toggle
Data
I/O7
RY/ BY
(N/A on 32-pin PLCC
& (s)TSOP packages)
1
No
toggle
Toggle
0
0
0
N/A
Toggle
1
Data
Data
Data
Data
1
Toggle
0
N/A
N/A
0
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
PRELIMINARY
(March, 2005, Version 0.0)
20ns
17
AMIC Technology, Corp.
A29L004A Series
DC Characteristics
CMOS Compatible
Parameter
Parameter Description
Symbol
ILI
Input Load Current
Test Description
Min.
VIN = VSS to VCC. VCC = VCC Max
ILIT
A9 Input Load Current
VCC = VCC Max, A9 =12.5V
ILO
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
ICC1
VCC Active Read Current
(Notes 1, 2)
ICC2
ICC3
ICC4
ICC5
VIL
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
VCC Standby Current (Note 2)
VCC Standby Current During Reset
(Note 2) (N/A on 32-pin PLCC &
(s)TSOP packages)
Automatic Sleep Mode
(Note 2, 4, 5)
Input Low Level
VIH
Input High Level
VID
Voltage for Autoselect and
VOL
VOH2
Unit
±1.0
µA
35
µA
±1.0
µA
4
10
1 MHz
2
4
CE = VIL, OE =VIH
20
30
mA
CE = VIH, RESET = VCC ± 0.3V
1
5
µA
RESET = VSS ± 0.3V
1
5
µA
VIH = VCC ± 0.3V; VIL = VSS ± 0.3V
1
5
µA
-0.5
0.8
V
0.7 x VCC
VCC + 0.3
V
11.5
12.5
V
0.45
V
VCC = 3.3 V
Output Low Voltage
IOL = 4.0mA, VCC = VCC Min
Output High Voltage
Max.
5 MHz
CE = VIL, OE = VIH
Temporary Unprotect Sector
VOH1
Typ.
mA
IOH = -2.0 mA, VCC = VCC Min
0.85 x VCC
V
IOH = -100 µA, VCC = VCC Min
VCC - 0.4
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE at VIH. Typical VCC is 3.0V.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns. Typical sleep mode current
is 1µA.
5. Not 100% tested.
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(March, 2005, Version 0.0)
18
AMIC Technology, Corp.
A29L004A Series
DC Characteristics (continued)
Zero Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1MHz
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
3.6V
8
Supply Current in mA
2.7V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note : T = 25 ° C
Typical ICC1 vs. Frequency
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AMIC Technology, Corp.
A29L004A Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
Speed
Test Setup
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
tOEH
Output Enable Hold
Time (Note 1)
Unit
-70
-90
Min.
70
90
ns
CE = VIL
OE = VIL
Max.
70
90
ns
OE = VIL
Max.
70
90
ns
Max.
30
35
ns
Min.
0
0
ns
Min.
10
10
Max.
25
30
ns
25
30
ns
0
0
ns
Read
Toggle and
Data Polling
tEHQZ
tDF
Chip Enable to Output High Z
(Notes 1)
tGHQZ
tDF
Output Enable to Output High Z
(Notes 1)
tAXQX
tOH
Output Hold Time from Addresses,
CE or OE , Whichever Occurs First
(Note 1)
Min.
ns
Notes:
1. Not 100% tested.
2. See Test Conditions and Test Setup for test specifications.
Timing Waveforms for Read Only Operation
tRC
Addresses
Addresses Stable
tACC
CE
tDF
tOE
OE
tOEH
WE
tCE
tOH
High-Z
Output
Output Valid
High-Z
RESET
0V
RY/BY
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20
AMIC Technology, Corp.
A29L004A Series
AC Characteristics
Hardware Reset ( RESET , N/A on 32-pin PLCC & (s)TSOP packages)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
RESET Pulse Width
RESET High Time Before Read (See Note)
RY/ BY Recovery Time
RESET Low to Standby Mode
Min
500
ns
Min
50
ns
tRP
tRH
tRB
tRPD
Min
0
ns
Min
20
µs
Note: Not 100% tested.
RESET Timings
RY/BY
CE, OE
tRH
RESET
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
~
~ ~
~
tReady
RY/BY
tRB
CE, OE
~
~
RESET
tRP
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(March, 2005, Version 0.0)
21
AMIC Technology, Corp.
A29L004A Series
Temporary Sector Unprotect (N/A on 32-pin PLCC & (s)TSOP packages)
Parameter
JEDEC
Std
tVIDR
tRSP
Description
All Speed Options
Unit
VID Rise and Fall Time (See Note)
Min
500
ns
RESET Setup Time for Temporary Sector
Unprotect
Min
4
µs
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
~
~
12V
0 or 3V
0 or 3V
RESET
tVIDR
Program or Erase Command Sequence
tVIDR
CE
~
~
WE
~ ~
~
~
tRSP
RY/BY
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(March, 2005, Version 0.0)
22
AMIC Technology, Corp.
A29L004A Series
AC Characteristics
Erase and Program Operations
Parameter
Speed
Description
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVWL
tAS
Address Setup Time
Min.
tWLAX
tAH
Address Hold Time
Min.
45
45
ns
tDVWH
tDS
Data Setup Time
Min.
35
45
ns
tWHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
Read Recover Time Before Write
Min.
0
ns
tGHWL
tGHWL
-70
-90
70
90
0
ns
ns
( OE high to WE low)
tELWL
tCS
CE Setup Time
Min.
0
ns
tWHEH
tCH
CE Hold Time
Min.
0
ns
tWLWH
tWP
Write Pulse Width
Min.
tWHWL
tWPH
Write Pulse Width High
Min.
30
ns
tWHWH1
tWHWH1
Byte Programming Operation
(Note 2)
Typ.
17
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ.
1
sec
tvcs
VCC Set Up Time (Note 1)
Min.
50
µs
tRB
Recovery Time from RY/ BY
(N/A on 32-pin PLCC & (s)TSOP packages)
Min
0
ns
Program/Erase Valid to RY/ BY Delay
(N/A on 32-pin PLCC & (s)TSOP packages)
Min
90
ns
tBUSY
35
35
ns
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
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(March, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L004A Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
PA
555h
PA
tAH
PA
~
~ ~
~
Addresses
tAS
~
~
tWC
Read Status Data (last two cycles)
CE
~
~
tCH
OE
tWP
~
~
tWHWH1
WE
tCS
tWPH
A0h
Data
tDH
PD
~
~
tDS
tBUSY
Status
DOUT
tRB
~
~ ~
~
RY/BY
tVCS
VCC
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
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(March, 2005, Version 0.0)
24
AMIC Technology, Corp.
A29L004A Series
Timing Waveforms for Chip/Sector Erase Operation
Read Status Data
Erase Command Sequence (last two cycles)
tAS
SA
2AAh
VA
555h for chip erase
tAH
VA
~
~ ~
~
Addresses
~
~
tWC
~
~
CE
OE
tCH
~
~
tWP
WE
tWPH
tWHWH2
tCS
Data
tDH
55h
30h
~
~
tDS
10h for chip erase
tBUSY
In
Progress
Complete
tRB
~
~
RY/BY
~
~
tVCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
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25
AMIC Technology, Corp.
A29L004A Series
Timing Waveforms for Data Polling (During Embedded Algorithms)
Addresses
~
~
tRC
VA
tAC
C
CE
VA
~
~ ~
~
VA
tCE
tCH
~
~
tOE
OE
tDF
~
~
tOEH
WE
tOH
High-Z
Status Data
High-Z
~
~
I/O0 - I/O6
Complement
Complement
True
Valid Data
~
~
I/O7
Status Data
True
Valid Data
High-Z
tBUSY
~
~
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
Addresses
~
~
tRC
VA
tAC
C
CE
VA
VA
~
~ ~
~
VA
tCE
tCH
tOE
~
~ ~
~
OE
tDF
tOEH
WE
I/O6 , I/O2
High-Z
tBUSY
Valid Status
Valid Status
(first read)
(second read)
~
~
tOH
Valid Status
Valid Data
(stop togging)
~
~
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
PRELIMINARY
(March, 2005, Version 0.0)
26
AMIC Technology, Corp.
A29L004A Series
Timing Waveforms for Sector Protect/Unprotect
VID
VIH
~
~
RESET
SA, A6,
A1, A0
Valid*
~
~ ~
~
Valid*
Sector Protect/Unprotect
60h
60h
Verify
40h
Status
~
~
Data
Valid*
Sector Protect:150us
Sector Unprotect:15ms
1us
CE
WE
OE
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
Timing Waveforms for I/O2 vs. I/O6
~
~
~
~
Erase
Complete
~
~
~
~
~
~
~
~
~
~
Erase
~
~
Erase Suspend
Read
~
~
~
~
~
~
I/O2
~
~
I/O6
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
~
~
Erase
Enter Erase
Suspend Program
~
~
WE
Erase
Suspend
~
~
Enter
Embedded
Erasing
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle with OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
PRELIMINARY
(March, 2005, Version 0.0)
27
AMIC Technology, Corp.
A29L004A Series
AC Characteristics
Erase and Program Operations
Alternate CE Controlled Writes
Parameter
Speed
Description
Unit
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
Min.
tAVEL
tAS
Address Setup Time
Min.
tELAX
tAH
Address Hold Time
Min.
45
45
ns
tDVEH
tDS
Data Setup Time
Min.
35
45
ns
tEHDX
tDH
Data Hold Time
Min.
0
ns
tOES
Output Enable Setup Time
Min.
0
ns
tGHEL
Read Recover Time Before Write
Min.
0
ns
tGHEL
-70
-90
70
90
0
ns
ns
( OE High to WE Low)
tWLEL
tWS
WE Setup Time
Min.
0
ns
tEHWH
tWH
WE Hold Time
Min.
0
ns
tELEH
tCP
CE Pulse Width
Min.
tEHEL
tCPH
CE Pulse Width High
Min.
30
ns
tWHWH1
tWHWH1
Byte Programming Operation (Note 2)
Typ.
17
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ.
1
sec
35
35
ns
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
PRELIMINARY
(March, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L004A Series
Timing Waveforms for Alternate CE Controlled Write Operation
PA for program
SA for sector erase
555 for chip erase
Data Polling
~
~
555 for program
2AA for erase
PA
tAS
tAH
tWH
~
~
tWC
~
~
Addresses
~
~
WE
OE
tWHWH1 or 2
~
~
tCP
tBUSY
tCPH
CE
tWS
tDS
~
~
tDH
tRH
A0 for program
55 for erase
PD for program
30 for sector erase 10
for chip erase
I/O7
DOUT
~
~
Data
RESET
~
~
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O 7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Typ. (Note 1)
1
11
17
Max. (Note 2)
8
64
200
Unit
sec
sec
6
13.5
sec
µs
Comments
Excludes 00h programming
prior to erasure
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
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(March, 2005, Version 0.0)
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AMIC Technology, Corp.
A29L004A Series
Latch-up Characteristics
Description
Input Voltage with respect to VSS on all I/O pins
VCC Current
Input voltage with respect to VSS on all pins except I/O pins
Min.
Max.
-1.0V
VCC+1.0V
-100 mA
+100 mA
-1.0V
12.5V
(including A9, OE and RESET )
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at time.
TSOP Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
Typ.
Max.
Unit
VIN=0
6
7.5
pF
VOUT=0
8.5
12
pF
VIN=0
7.5
9
pF
Test Setup
Typ.
Max.
Unit
VIN=0
4
6
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
PLCC Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
VOUT=0
8
12
pF
CIN2
Control Pin Capacitance
VPP=0
8
12
pF
Notes:
1. Sampled, not 100% tested.
2.
Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
PRELIMINARY
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AMIC Technology, Corp.
A29L004A Series
Test Conditions
Test Specifications
Test Condition
-70
-90
Output Load
Unit
1 TTL gate
Output Load Capacitance, CL(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
5
ns
Input Pulse Levels
0.0 - 3.0
0.0 - 3.0
V
Input timing measurement reference levels
1.5
1.5
V
Output timing measurement reference levels
1.5
1.5
V
Test Setup
3.3 V
2.7 KΩ
Device
Under
Test
CL
PRELIMINARY
(March, 2005, Version 0.0)
Diodes = IN3064 or Equivalent
6.2 KΩ
31
AMIC Technology, Corp.
A29L004A Series
Ordering Information
Top Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA)
A29L004ATL-70
Package
32-pin PLCC
A29L004ATL-70F
32-Pin Pb-Free PLCC
A29L004ATX-70
32-pin sTSOP
(8mm X 13.4mm)
32-Pin Pb-Free sTSOP
(8mm X 13.4mm)
A29L004ATX-70F
32-pin TSOP
(8mm X 20mm)
A29L004ATV-70
70
4
20
0.2
A29L004ATV-70F
32-pin Pb-Free TSOP
(8mm X 20mm)
A29L004ATW-70
40-pin TSOP
A29L004ATW-70F
40-pin Pb-Free TSOP
32-pin sTSOP
(8mm X 14mm)
A29L004ATY-70
32-Pin Pb-Free sTSOP
(8mm X 14mm)
A29L004ATY-70F
A29L004ATL-90
32-pin PLCC
A29L004ATL-90F
32-pin Pb-Free PLCC
A29L004ATX-90
32-pin sTSOP
(8mm X 13.4mm)
32-pin Pb-Free sTSOP
(8mm X 13.4mm)
A29L004ATX-90F
32-pin TSOP
(8mm X 20mm)
A29L004ATV-90
90
4
20
0.2
A29L004ATV-90F
32-pin Pb-Free TSOP
(8mm X 20mm)
A29L004ATW-90
40-pin TSOP
A29L004ATW-90F
40-pin Pb-Free TSOP
32-pin sTSOP
(8mm X 14mm)
A29L004ATY-90
32-Pin Pb-Free sTSOP
(8mm X 14mm)
A29L004ATY-90F
PRELIMINARY
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32
AMIC Technology, Corp.
A29L004A Series
Bottom Boot Sector Flash
Part No.
Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA)
Package
32-pin PLCC
A29L004AUL-70
A29L004AUL-70F
32-pin Pb-Free PLCC
A29L004AUX-70
32-pin sTSOP
(8mm X 13.4mm)
32-pin Pb-Free sTSOP
(8mm X 13.4mm)
A29L004AUX-70F
32-pin TSOP
(8mm X 20mm)
A29L004AUV-70
70
4
20
0.2
A29L004AUV-70F
32-pin Pb-Free TSOP
(8mm X 20mm)
A29L004AUW-70
40-pin TSOP
40-pin Pb-Free TSOP
A29L004AUW-70F
32-pin sTSOP
(8mm X 14mm)
A29L004AUY-70
32-Pin Pb-Free sTSOP
(8mm X 14mm)
A29L004AUY-70F
32-pin PLCC
A29L004AUL-90
A29L004AUL-90F
32-pin Pb-Free PLCC
A29L004AUX-90
32-pin sTSOP
(8mm X 13.4mm)
32-pin Pb-Free sTSOP
(8mm X 13.4mm)
A29L004AUX-90F
32-pin TSOP
(8mm X 13.4mm)
A29L004AUV-90
90
4
20
0.2
A29L004AUV-90F
32-pin Pb-Free TSOP
(8mm X 13.4mm)
A29L004AUW-90
40-pin TSOP
40-pin Pb-Free TSOP
A29L004AUW-90F
32-pin sTSOP
(8mm X 14mm)
A29L004AUY-90
32-Pin Pb-Free sTSOP
(8mm X 14mm)
A29L004AUY-90F
PRELIMINARY
(March, 2005, Version 0.0)
33
AMIC Technology, Corp.
A29L004A Series
Package Information
TSOP 40L TYPE I (10 X 20mm) Outline Dimensions
unit: inches/mm
A
A1
D
A2
0.076
C
e
E
b
Pin1
D1
D
0.25
Detail "A"
Gage Plane
θ
c
Dimensions in inches
Symbol
Min
Nom
Max
Seating Plane
L
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.0067
0.0087
0.0106
0.17
0.22
0.27
c
0.004
-
0.0083
0.10
-
0.21
E
0.394 BSC
10.00 BSC
e
0.020 BSC
0.50 BSC
D
0.787 BSC
20.00 BSC
D1
0.724 BSC
18.40 BSC
L
0.020
0.024
0.028
0.50
0.60
0.70
θ
0°
3°
5°
0°
3°
5°
Notes:
1. Dimension D1 and E do not include mold flash.
2. The lead width dimension does not include dambar protrusion.
Total in excess of the lead width dimension at maximum material condition.
Dambar cannot be located on the lower radius of the foot.
PRELIMINARY
(March, 2005, Version 0.0)
34
AMIC Technology, Corp.
A29L004A Series
Package Information
PLCC 32L Outline Dimension
unit: inches/mm
HD
D
13
5
E
1
HE
4
14
32
20
30
29
c
A1
b
e
L
A
A2
21
b1
D
GE
GD
y
Symbol
θ
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.134
-
-
3.40
A1
0.0185
-
-
0.47
-
-
A2
0.105
0.110
0.115
2.67
2.80
2.93
b1
0.026
0.028
0.032
0.66
0.71
0.81
b
0.016
0.018
0.021
0.41
0.46
0.54
C
0.008
0.010
0.014
0.20
0.254
0.35
D
0.547
0.550
0.553
13.89
13.97
14.05
E
0.447
0.450
0.453
11.35
11.43
11.51
e
0.044
0.050
0.056
1.12
1.27
1.42
GD
0.490
0.510
0.530
12.45
12.95
13.46
GE
0.390
0.410
0.430
9.91
10.41
10.92
HD
0.585
0.590
0.595
14.86
14.99
15.11
12.57
HE
0.485
0.490
0.495
12.32
12.45
L
0.075
0.090
0.095
1.91
2.29
2.41
y
-
-
0.003
-
-
0.075
θ
0°
-
10°
0°
-
10°
Notes:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
PRELIMINARY
(March, 2005, Version 0.0)
35
AMIC Technology, Corp.
A29L004A Series
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
A
A1
c
E
A2
e
D
θ
L
LE
HD
Detail "A"
D
Detail "A"
y
S
Dimensions in inches
Symbol
Min
Nom
Max
b
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.007
0.009
0.011
0.18
0.22
0.27
c
0.004
-
0.008
0.11
-
0.20
D
0.720
0.724
0.728
18.30
18.40
18.50
E
-
0.315
0.319
-
8.00
8.10
e
0.020 BSC
0.50 BSC
HD
0.779
0.787
0.795
19.80
20.00
20.20
L
0.016
0.020
0.024
0.40
0.50
0.60
LE
-
0.032
-
-
0.80
-
S
-
-
0.020
-
-
0.50
y
-
-
0.003
-
-
0.08
θ
0°
-
5°
0°
-
5°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(March, 2005, Version 0.0)
36
AMIC Technology, Corp.
A29L004A Series
Package Information
unit: inches/mm
A
A1
c
E
A2
e
sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
θ
L
LE
D1
D
Detail "A"
D
Detail "A"
0.076MM
S
b
SEATING PLANE
Dimensions in inches
Symbol
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.049
-
-
1.25
A1
0.002
-
-
0.05
-
-
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.007
0.008
0.009
0.17
0.20
0.23
c
0.0056
0.0059
0.0062
0.142
0.150
0.158
E
0.311
0.315
0.319
7.90
8.00
8.10
e
0.020 TYP
0.50 TYP
D
0.520
0.528
0.535
13.20
13.40
13.60
D1
0.461
0.465
0.469
11.70
11.80
11.90
L
0.012
0.020
0.028
0.30
0.50
0.70
LE
0.0275
0.0315
0.0355
0.700
0.800
0.900
S
θ
0.0109 TYP
0°
3°
0.278 TYP
5°
0°
3°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(March, 2005, Version 0.0)
37
AMIC Technology, Corp.
A29L004A Series
Package Information
sTSOP 32L TYPE I (8 X 14mm) Outline Dimensions
unit: inches/mm
c
E
A
A2
0.254
Pin1
Gage Plane
A1
θ
L
D1
Detail "A"
D
Detail "A"
b
D
e
Dimensions in inches
Symbol
Min
Nom
Max
y
Dimensions in mm
Min
Nom
Max
A
-
-
0.047
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.041
0.95
1.00
1.05
b
0.0067
0.0087
0.0106
0.17
0.22
0.27
c
0.004
-
0.0083
0.10
-
0.21
E
0.311
0.315
0.319
7.90
8.00
8.10
e
-
0.0197
-
-
0.50
-
D
0.543
0.551
0.559
13.80
14.00
14.20
D1
0.484
0.488
0.492
12.30
12.40
12.50
L
0.020
0.024
0.028
0.50
0.60
0.70
y
0.000
-
0.003
0.00
-
0.076
θ
0°
3°
5°
0°
3°
5°
Notes:
1. Dimension E does not include mold flash.
3. Dimension D1 does not include interlead flash.
4. Dimension b does not include dambar protrusion.
PRELIMINARY
(March, 2005, Version 0.0)
38
AMIC Technology, Corp.