Revision 11 ProASIC3 nano Flash FPGAs Features and Benefits Advanced I/Os • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • I/O Registers on Input, Output, and Enable Paths • Selectable Schmitt Trigger Inputs • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate† and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the ProASIC3 Family Wide Range of Features • 10 k to 250 k System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Instant On Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off High Performance • 350 MHz System Performance Clock Conditioning Circuit (CCC) and PLL† In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)† • FlashLock® Designed to Secure FPGA Contents Low Power • • • • Low Power ProASIC®3 nano Products 1.5 V Core Voltage for Low Power Support for 1.5 V-Only Systems Low-Impedance Flash Switches • Up to Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities and External Feedback • Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18 organization)† High-Performance Routing Hierarchy Enhanced Commercial Temperature Range • Segmented, Hierarchical Routing and Clock Structure • –20°C to +70°C Table 1 • ProASIC3 nano Devices ProASIC3 nano Devices ProASIC3 nano-Z A3PN010 A3PN0151 A3PN020 Devices1 System Gates A3PN060 A3PN125 A3PN250 A3PN030Z1,2 A3PN060Z1 A3PN125Z1 A3N250Z1 10,000 15,000 20,000 30,000 60,000 125,000 250,000 Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048 VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144 RAM Kbits (1,024 bits)2 – – – – 18 36 36 4,608-Bit Blocks – – – – 4 8 8 FlashROM Kbits 1 1 1 1 1 1 1 – – – – Yes Yes Yes 2 Secure (AES) ISP 2 Integrated PLL in CCCs 2 – – – – 1 1 1 VersaNet Globals 4 4 4 6 18 18 18 I/O Banks 2 3 3 2 2 2 4 Maximum User I/Os (packaged device) 34 49 49 77 71 71 68 Maximum User I/Os (Known Good Die) 34 – 52 83 71 71 68 QN48 QN68 QN68 QN48, QN68 VQ100 VQ100 VQ100 VQ100 Package Pins QFN VQFP Notes: 1. Not recommended for new designs. 2. A3PN030Z and smaller devices do not support this feature. 3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets. † A3PN030 and smaller devices do not support this feature. January 2013 © 2013 Microsemi Corporation I I/Os Per Package ProASIC3 nano Devices A3PN010 A3PN0151 A3PN020 ProASIC3 nano-Z Devices1 A3PN060 A3PN125 A3PN250 A3PN030Z1 A3PN060Z1 A3PN125Z1 A3PN250Z1 Known Good Die 34 – 52 83 71 71 68 QN48 34 – – 34 – – – QN68 – 49 49 49 – – – VQ100 – – – 77 71 71 68 Notes: 1. Not recommended for new designs. 2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions Packages QN48 QN68 VQ100 Length × Width (mm\mm) 6x6 8x8 14 x 14 Nominal Area (mm2) 36 64 196 Pitch (mm) 0.4 0.4 0.5 Height (mm) 0.90 0.90 1.20 ProASIC3 nano Device Status ProASIC3 nano Devices Status A3PN010 Production A3PN015 Not recommended for new designs. A3PN020 Production ProASIC3 nano-Z Devices Status A3PN030Z Not recommended for new designs. A3PN060 Production A3PN060Z Not recommended for new designs. A3PN125 Production A3PN125Z Not recommended for new designs. A3PN250 Production A3PN250Z Not recommended for new designs. II R evis i o n 11 ProASIC3 nano Flash FPGAs ProASIC3 nano Ordering Information A3PN250 _ Z 1 VQ G 100 Y I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) DIELOT = Known Good Die Speed Grade Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number Feature Grade Z = nano devices without enhanced features* (Not recommended for new designs) Blank = Standard ProASIC3 nano Devices A3PN010 = 10,000 System Gates A3PN015 = 15,000 System Gates (A3PN015 is not recommended for new designs) A3PN020 = 20,000 System Gates A3PN030 = 30,000 System Gates A3PN060 = 60,000 System Gates A3PN125 = 125,000 System Gates A3PN250 = 250,000 System Gates Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device. Devices Not Recommended For New Designs A3PN015, A3PN030Z, A3PN060Z, A3PN125Z, and A3PN250Z are not recommended for new designs. Device Marking Microsemi normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples. Figure 1 on page 1-IV shows an example of device marking based on the AGL030V5-UCG81. R ev i si o n 1 1 III The actual mark will vary by the device/package combination ordered. Package Wafer Lot # Figure 1 • Country of Origin ACTELXXX AGL030YWW UCG81XXXX XXXXXXXX Device Name (six characters) Date Code Customer Mark (if applicable) Example of Device Marking for Small Form Factor Packages ProASIC3 nano Products Available in the Z Feature Grade Devices A3PN030* A3PN060* A3PN125* A3PN250* QN48 – – – QN68 – – – VQ100 VQ100 VQ100 VQ100 Packages Note: *Not recommended for new designs. Temperature Grade Offerings ProASIC3 nano Devices A3PN010 A3PN015* A3PN020 ProASIC3 nano-Z Devices* A3PN060 A3PN125 A3PN250 A3PN030Z* A3PN060Z* A3PN125Z* A3PN250Z* QN48 C, I – – C, I – – – QN68 – C, I C, I C, I – – – VQ100 – – – C, I C, I C, I C, I Note: *Not recommended for new designs. C = Commercial temperature range: 0°C to 70°C ambient temperature I = Industrial temperature range: –40°C to 85°C ambient temperature Speed Grade and Temperature Grade Matrix Temperature Grade C I Std. 1 2 Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature. 2. I = Industrial temperature range: –40°C to 85°C ambient temperature. Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. IV Revision 11 ProASIC3 nano Flash FPGAs Table of Contents ProASIC3 nano Device Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ProASIC3 nano DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71 Pin Descriptions and Packaging Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-3 3-4 3-4 3-4 Package Pin Assignments 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 R ev i si o n 1 1 V 1 – ProASIC3 nano Device Overview General Description ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Added features include smaller footprint packages designed with two-layer PCBs in mind, low power, hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of programmable logic and quick time to market. Security Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. R ev i si o n 1 1 1 -1 ProASIC3 nano Device Overview Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3 nano device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Microsemi flash-based ProASIC3 nano devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based ProASIC3 nano devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flashbased FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings. Advanced Flash Technology ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. 1- 2 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Advanced Architecture The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3 to Figure 1-4 on page 1-4): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs • Advanced I/O structure Bank 1* I/Os Bank 1 Bank 0 VersaTile User Nonvolatile FlashROM Charge Pumps CCC-GL Bank 1 Note: *Bank 0 for the A3PN030 device Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM (A3PN010 and A3PN030) Bank 1 I/Os Bank 2 Bank 0 VersaTile User Nonvolatile FlashROM Charge Pumps CCC-GL Bank 1 Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and A3PN020) R ev i si o n 1 1 1 -3 ProASIC3 nano Device Overview Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os ISP AES Decryption User Nonvolatile FlashROM Charge Pumps Bank 0 Bank 1 VersaTile Bank 1 Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125) Bank 0 CCC Bank 1 Bank 3 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block ISP AES Decryption User Nonvolatile FlashROM Charge Pumps Bank 1 Bank 3 I/Os VersaTile Bank 2 Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. 1- 4 R ev isio n 1 1 ProASIC3 nano Flash FPGAs VersaTiles The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The ProASIC3 nano VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-5 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 D-Flip-Flop with Clear or Set Y Data CLK CLR Enable D-Flip-Flop with Clear or Set Y D-FF Data CLK Y D-FF Enable CLR Figure 1-5 • VersaTile Configurations User Nonvolatile FlashROM ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The ProASIC3 nano development software solutions, Libero® System-on-Chip (SoC) software and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature enables the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. R ev i si o n 1 1 1 -5 ProASIC3 nano Device Overview SRAM and FIFO ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3PN030 and smaller devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any PLLs or programmable delays. For devices using the six CCC block architecture, these six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to the CCC block, which are located near the CCC. The CCC block has these key features: • Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz • Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz • Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns • 2 programmable delay types for clock skew minimization • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty cycle = 50% ± 1.5% or better (for PLL only) • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) • Maximum acquisition time = 300 µs (for PLL only) • Low power consumption of 5 mW • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / fOUT_CCC) (for PLL only) Global Clocking ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. 1- 6 R ev isio n 1 1 ProASIC3 nano Flash FPGAs I/Os with Advanced I/O Standards ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of various single-data-rate applications for all versions of nano devices and double-datarate applications for the A3PN060, A3PN125, and A3PN250 devices. ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support cold-sparing and Schmitt trigger. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support ProASIC3 nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-6 on page 1-8). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming R ev i si o n 1 1 1 -7 ProASIC3 nano Device Overview Z -Tri-State: I/O is tristated Figure 1-6 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. 1- 8 R ev isio n 1 1 2 – ProASIC3 nano DC and Switching Characteristics General Specifications The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing, and hot-swap I/O capability. Refer to the "ProASIC3 nano Ordering Information" section on page III for more information. DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range. Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V V TSTG 1 Storage temperature –65 to +150 °C 1 Junction temperature +125 °C TJ Notes: 1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. 2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 3. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. R ev i si o n 1 1 2 -1 ProASIC3 nano DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions 1, 2 Symbol TA –20 to +85 –40 to +100 °C 1.425 to 1.575 1.425 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V 1.425 to 1.575 1.425 to 1.575 V 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 1.5 V DC core supply voltage VJTAG JTAG DC voltage VPUMP 4 Programming voltage Programming Mode Operation VCCPLL 6 Analog power supply (PLL) 4 5 1.5 V DC core supply voltage VCCI and 1.5 V DC supply voltage VMV 7 3 2 Units °C –20 to +70 Junction temperature 3 Industrial 2 Ambient temperature TJ VCC Extended Commercial Parameter –40 to +85 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V 3.3 V Wide Range supply voltage 8 2.7 to 3.6 2.7 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank. 4. The programming temperature range supported is Tambient = 0°C to 85°C. 5. VPUMP can be left floating during operation (not programming mode). 6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information. 7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for further information. 8. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1 Product Grade Commercial Industrial Maximum Operating Programming Program Retention Maximum Storage Cycles (biased/unbiased) Temperature TSTG (°C) 2 Junction Temperature TJ (°C) 2 500 20 years 110 100 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2- 2 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Table 2-4 • Overshoot and Undershoot Limits 1 VCCI and VMV Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle 2 Maximum Overshoot/ Undershoot 2 10% 1.4 V 5% 1.49 V 2.7 V or less 3V 3.3 V 3.6 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric User’s Guide for information on clock and lock recovery. R ev i si o n 1 1 2 -3 ProASIC3 nano DC and Switching Characteristics Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional but slower because VCCI is below specification. For the same reason, input buffers do Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. not meet VIH / VIL levels, and output buffers do not meet VOH/VOL levels. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Figure 2-1 • 2- 4 Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V I/O State as a Function of VCCI and VCC Voltage Levels R ev isio n 1 1 VCCI ProASIC3 nano Flash FPGAs Thermal Characteristics Introduction The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. · junction temp. (C) – Max. ambient temp. (C)- = 100C – 70C = 1.463 W ----------------------------------------------------------------------------------------------------------------------------------------Maximum Power Allowed = Max. ------------------------------------20.5C/W ja (C/W) EQ 2 Table 2-5 • Package Thermal Resistivities ja Package Type Quad Flat No Lead (QFN) Very Thin Quad Flat Pack (VQFP) Device Pin Count jc All devices 48 TBD TBD TBD TBD C/W 68 TBD TBD TBD TBD C/W 100 TBD TBD TBD TBD C/W 100 10.0 35.3 29.4 27.1 C/W All devices Still Air 200 ft./min. 500 ft./min. Units Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Junction Temperature (°C) Array Voltage VCC (V) –40°C –20°C 0°C 25°C 70°C 85°C 100°C 1.425 0.968 0.973 0.979 0.991 1.000 1.006 1.013 1.500 0.888 0.894 0.899 0.910 0.919 0.924 0.930 1.575 0.836 0.841 0.845 0.856 0.864 0.870 0.875 R ev i si o n 1 1 2 -5 ProASIC3 nano DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-7 • Quiescent Supply Current Characteristics A3PN010 A3PN015 A3PN020 A3PN060 A3PN125 A3PN250 600 µA 1 mA 1 mA 2 mA 2 mA 3 mA Max. (Commercial) 5 mA 5 mA 5 mA 10 mA 10 mA 20 mA Max. (Industrial) 8 mA 8 mA 8 mA 15 mA 15 mA 30 mA Typical (25°C) Note: IDD includes VCC, VPUMP, and VCCI, currents. Power per I/O Pin Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings VCCI (V) Dynamic Power, PAC9 (µW/MHz)1 3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.45 3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.93 3.3 V LVCMOS wide range2 3.3 16.45 3.3 V LVCMOS wide range – Schmitt Trigger 3.3 18.93 2.5 V LVCMOS 2.5 4.73 2.5 V LVCMOS – Schmitt Trigger 2.5 6.14 1.8 V LVCMOS 1.8 1.68 1.8 V LVCMOS – Schmitt Trigger 1.8 1.80 1.5 V LVCMOS (JESD8-11) 1.5 0.99 1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.96 Single-Ended Notes: 1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 2- 6 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 CLOAD (pF) 2 VCCI (V) Dynamic Power, PAC10 (µW/MHz)3 10 3.3 162.01 10 3.3 162.01 2.5 V LVCMOS 10 2.5 91.96 1.8 V LVCMOS 10 1.8 46.95 1.5 V LVCMOS (JESD8-11) 10 1.5 32.22 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS wide range 4 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. Values for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 correspond to a default loading of 35 pF. 3. PAC10 is the total dynamic power measured on VCCI. 4. All LVCMOS3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. R ev i si o n 1 1 2 -7 ProASIC3 nano DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices A3PN250 A3PN125 A3PN060 A3PN020 A3PN015 A3PN010 Device Specific Dynamic Contributions (µW/MHz) PAC1 Clock contribution of a Global Rib 11.03 11.03 9.3 9.3 9.3 9.3 PAC2 Clock contribution of a Global Spine 1.58 0.81 0.81 0.4 0.4 0.4 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-8 on page 2-6. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-9 on page 2-7. PAC11 Average contribution of a RAM block during a read operation 25.00 N/A PAC12 Average contribution of a RAM block during a write operation 30.00 N/A PAC13 Dynamic contribution for PLL 2.60 N/A Parameter Definition Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC. Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices PDC1 Array static power in Active mode PDC4 Static PLL contribution 1 PDC5 Bank quiescent power (VCCI-dependent) A3PN010 A3PN015 A3PN020 A3PN060 Definition A3PN125 Parameter A3PN250 Device Specific Static Power (mW) See Table 2-7 on page 2-6. 2.55 N/A See Table 2-7 on page 2-6. Notes: 1. Minimum contribution of the PLL when running at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC. 2- 8 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on page 2-11. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-13 on page 2-11. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-13 on page 2-11. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's Guide. NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. R ev i si o n 1 1 2 -9 ProASIC3 nano DC and Switching Characteristics Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-11. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on page 2-11. PLL Contribution—PPLL PPLL = PDC4 + PAC13 * FCLKOUT FCLKOUT is the output clock frequency.1 1. 2- 10 The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – … – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% R ev i si o n 1 1 2- 11 ProASIC3 nano DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVCMOS 2.5V Output Drive Strength = 8 mA High Slew Rate Y tPD = 0.56 ns tPD = 0.49 ns tDP = 2.25 ns I/O Module (Non-Registered) Combinational Cell Y tDP = 2.87 ns tPD = 0.87 ns I/O Module (Non-Registered) Combinational Cell I/O Module (Registered) Y tPY = 1.04 ns Input LVCMOS 2.5 V D LVTTL Output drive strength = 4 mA High slew rate tPD = 0.51 ns Q I/O Module (Non-Registered) Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns LVCMOS 1.5 V Output drive strength = 2 mA High slew rate tDP = 3.02 ns tPD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.84 ns D Combinational Cell Y Q I/O Module (Non-Registered) tPY = 1.14 ns Figure 2-2 • 2- 12 I/O Module (Registered) Register Cell D Q D tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns LVCMOS 1.5 V LVTTL Output drive strength = 8 mA High slew rate tDP = 2.21 ns Q tDP = 2.21 ns tCLKQ = 0.55 ns tSUD = 0.43 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.84 ns tPY = 0.84 ns LVTTL 3.3 V Output drive strength = 8 mA High slew rate tOCLKQ = 0.59 ns tOSUD = 0.31 ns Timing Model Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V, with Default Loading at 10 pF R ev i sio n 1 1 ProASIC3 nano Flash FPGAs tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND 50% tDIN tDIN (R) Figure 2-3 • (F) Input Buffer Timing Model and Delays (example) R ev i si o n 1 1 2- 13 ProASIC3 nano DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-4 • 2- 14 Output Buffer Model and Delays (example) R ev i sio n 1 1 tDP (F) ProASIC3 nano Flash FPGAs tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% tEOUT (F) 50% E tEOUT (R) VCC 50% EOUT tZL PAD 50% 50% tHZ Vtrip tZH 50% tLZ VCCI 90% VCCI Vtrip VOL 10% VCCI VCC D VCC E 50% tEOUT (R) 50% tEOUT (F) VCC EOUT PAD 50% tZLS VOH Vtrip Figure 2-5 • 50% 50% tZHS Vtrip VOL Tristate Output Buffer Timing Model and Delays (example) R ev i si o n 1 1 2- 15 ProASIC3 nano DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Equivalent Software Default Drive Drive Strength Slew Min. I/O Standard Strength Option2 Rate V VIL VIH VOL VOH IOL1 IOH1 mA mA Max V Min. V Max. V Max. V Min. V 2.4 3.3 V LVTTL/ 3.3 V LVCMOS 8 mA 8 mA High –0.3 0.8 2 3.6 0.4 8 8 3.3 V LVCMOS Wide Range 100 µA 8 mA High –0.3 0.8 2 3.6 0.2 2.5 V LVCMOS 8 mA 8 mA High –0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 1.5 V LVCMOS 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 VCCI – 0.2 100 100 µA µA Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models . 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. Table 2-15 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial 1 DC I/O Standards Industrial 2 IIL 3 IIH 4 IIL 3 IIH 4 µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 Notes: 1. 2. 3. 4. 2- 16 Commercial range (–20°C < TA < 70°C) Industrial range (–40°C < TA < 85°C) IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-16 • Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 3.3 V LVCMOS Wide Range 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V Table 2-17 • I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—HIGH to Z tZH Enable to Pad delay through the Output Buffer—Z to HIGH tLZ Enable to Pad delay through the Output Buffer—LOW to Z tZL Enable to Pad delay through the Output Buffer—Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW R ev i si o n 1 1 2- 17 ProASIC3 nano DC and Switching Characteristics tDP (ns) tDIN (ns) tPYS (ns) tE O U T (ns) tZL (ns) 35 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 3.3 V LVCMOS Wide Range 100 µA 8 mA High 35 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 tHZ (ns) tDOUT (ns) High tLZ (ns) Capacitive Load (pF) 8 mA tZH (ns) Slew Rate 8 3.3 V LVTTL / 3.3 V LVCMOS tPY (ns) Equivalent Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF) STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V For A3PN060, A3PN125, and A3PN250 2.5 V LVCMOS 8 8 mA High 35 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 1.8 V LVCMOS 4 4 mA High 35 0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89 1.5 V LVCMOS 2 2 mA High 35 0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Capacitive Load (pF) tDOUT (ns) tDP (ns) tDIN (ns) tPY (ns) tPYS (ns) tEO UT (ns) tZL (ns) tZH (ns) tLZ (ns) tHZ (ns) 3.3 V LVCMOS Wide Range Slew Rate 3.3 V LVTTL / 3.3 V LVCMOS Equivalent Software Default Drive Strength Option1 I/O Standard Drive Strength (mA) Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF) STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V For A3PN020, A3PN015, and A3PN010 8 8 mA High 10 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 100 µA 8 mA High 10 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 2.5 V LVCMOS 8 8 mA High 10 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 1.8 V LVCMOS 4 4 mA High 10 0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89 1.5 V LVCMOS 2 2 mA High 10 0.60 3.76 0.04 1.56 2.14 0.43 3.74 3.76 2.66 2.83 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 18 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Detailed I/O DC Characteristics Table 2-20 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-21 • I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength RPULL-DOWN ()2 RPULL-UP ()3 2 mA 100 300 4 mA 100 300 6 mA 50 150 50 150 8 mA 3.3 V LVCMOS Wide Range 100 µA 2.5 V LVCMOS Same as equivalent software default drive 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 1.8 V LVCMOS 2 mA 200 225 4 mA 100 112 1.5 V LVCMOS 2 mA 200 224 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models, located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () R(WEAK PULL-DOWN)2 () VCCI Min. Max. Min. Max. 3.3 V 10 K 45 K 10 K 45 K 3.3 V (wide range I/Os) 10 K 45 K 10 K 45 K 2.5 V 11 K 55 K 12 K 74 K 1.8 V 18 K 70 K 17 K 110 K 1.5 V 19 K 90 K 19 K 140 K Notes: 1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN) R ev i si o n 1 1 2- 19 ProASIC3 nano DC and Switching Characteristics Table 2-23 • I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 100 µA Same as equivalent software default drive 2 mA 16 18 4 mA 16 18 6 mA 32 37 8 mA 32 37 2 mA 9 11 4 mA 17 22 2 mA 13 16 Note: *TJ = 100°C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-24 • Duration of Short Circuit Event before Failure Temperature 2- 20 Time before Failure –40°C > 20 years –20°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-25 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (100°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis 20 years (100°C) Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. R ev i si o n 1 1 2- 21 ProASIC3 nano DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-27 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-6 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 10 Notes: 1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF. 2- 22 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-29 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 9.70 0.04 1.13 1.52 0.43 9.88 8.82 2.31 2.50 ns –1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns –2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns Std. 0.60 9.70 0.04 1.13 1.52 0.43 9.88 8.82 2.31 2.50 ns –1 0.51 8.26 0.04 0.96 1.29 0.36 8.40 7.50 1.96 2.13 ns –2 0.45 7.25 0.03 0.84 1.13 0.32 7.37 6.59 1.72 1.87 ns Std. 0.60 6.90 0.04 1.13 1.52 0.43 7.01 6.22 2.61 3.01 ns –1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns –2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns Std. 0.60 6.90 0.04 1.13 1.52 0.43 7.01 6.22 2.61 3.01 ns –1 0.51 5.87 0.04 0.96 1.29 0.36 5.97 5.29 2.22 2.56 ns –2 0.45 5.15 0.03 0.84 1.13 0.32 5.24 4.64 1.95 2.25 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 7.19 0.04 1.13 1.52 0.43 7.32 6.40 2.30 2.62 ns –1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns –2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns Std. 0.60 7.19 0.04 1.13 1.52 0.43 7.32 6.40 2.30 2.62 ns –1 0.51 6.12 0.04 0.96 1.29 0.36 6.22 5.44 1.96 2.23 ns –2 0.45 5.37 0.03 0.84 1.13 0.32 5.46 4.78 1.72 1.96 ns Std. 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 ns –1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns –2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns Std. 0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14 ns –1 0.51 3.89 0.04 0.96 1.29 0.36 3.95 3.33 2.22 2.67 ns –2 0.45 3.41 0.03 0.84 1.13 0.32 3.47 2.93 1.95 2.34 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 23 ProASIC3 nano DC and Switching Characteristics Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 5.48 0.04 1.13 1.52 0.43 5.58 5.21 2.31 2.50 ns –1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns –2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns Std. 0.60 5.48 0.04 1.13 1.52 0.43 5.58 5.21 2.31 2.50 ns –1 0.51 4.66 0.04 0.96 1.29 0.36 4.74 4.43 1.96 2.13 ns –2 0.45 4.09 0.03 0.84 1.13 0.32 4.16 3.89 1.72 1.87 ns Std. 0.60 4.33 0.04 1.13 1.52 0.43 4.40 4.14 2.61 3.01 ns –1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns –2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns Std. 0.60 4.33 0.04 1.13 1.52 0.43 4.40 4.14 2.61 3.01 ns –1 0.51 3.69 0.04 0.96 1.29 0.36 3.75 3.52 2.22 2.56 ns –2 0.45 3.24 0.03 0.84 1.13 0.32 3.29 3.09 1.95 2.25 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 3.56 0.04 1.13 1.52 0.43 3.62 3.03 2.30 2.62 ns –1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns –2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns Std. 0.60 3.56 0.04 1.13 1.52 0.43 3.62 3.03 2.30 2.62 ns –1 0.51 3.03 0.04 0.96 1.29 0.36 3.08 2.58 1.96 2.23 ns –2 0.45 2.66 0.03 0.84 1.13 0.32 2.70 2.26 1.72 1.96 ns Std. 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 ns –1 0.51 2.32 0.04 0.96 1.29 0.36 2.36 1.90 2.22 2.67 ns –2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns Std. 0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14 ns –1 0.51 2.32 0.04 0.96 129 0.36 2.36 1.90 2.22 2.67 ns –2 0.45 2.04 0.03 0.84 1.13 0.32 2.07 1.67 1.95 2.34 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 24 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs 3.3 V LVCMOS Wide Range Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option3 Min. V 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 10 10 Drive Strength VIL VIH Max. V Min. V Max. V VOL VOH IOL IOH IIL1 IIH2 Max. V Min. V mA mA µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. R ev i si o n 1 1 2- 25 ProASIC3 nano DC and Switching Characteristics Timing Characteristics Table 2-34 • 3.3 V LVCMOS Wide Range Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 µA 100 µA 100 µA 100 µA 2 mA 4 mA 6 mA 8 mA tDOUT tDP tDIN tPY tPYS tEOUT Std. 0.60 14.73 0.04 1.57 2.18 0.43 –1 0.51 12.53 0.04 1.33 1.85 –2 0.45 11.00 0.03 1.17 Std. 0.60 14.73 0.04 –1 0.51 12.53 –2 0.45 Std. tZL tZH tLZ tHZ Units 14.73 13.16 3.26 3.38 ns 0.36 12.53 11.19 2.77 2.87 ns 1.62 0.32 11.00 9.83 2.43 2.52 ns 1.57 2.18 0.43 14.73 13.16 3.26 3.38 ns 0.04 1.33 1.85 0.36 12.53 11.19 2.77 2.87 ns 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52 ns 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns –1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns –2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns Std. 0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16 ns –1 0.51 8.83 0.04 1.33 1.85 0.36 8.83 7.83 3.17 3.54 ns –2 0.45 7.75 0.03 1.17 1.62 0.32 7.75 6.88 2.78 3.11 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 26 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-35 • 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 µA 100 µA 100 µA 100 µA 2 mA 4 mA 6 mA 8 mA tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns –1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns –2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns Std. 0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56 ns –1 0.51 9.22 0.04 1.33 1.85 0.36 9.22 8.06 2.77 3.03 ns –2 0.45 8.09 0.03 1.17 1.62 0.32 8.09 7.08 2.43 2.66 ns Std. 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 ns –1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns –2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns Std. 0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35 ns –1 0.51 5.77 0.04 1.33 1.85 0.36 5.77 4.87 3.16 3.70 ns –2 0.45 5.06 0.03 1.17 1.62 0.32 5.06 4.27 2.78 3.25 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 1 2- 27 ProASIC3 nano DC and Switching Characteristics Table 2-36 • 3.3 V LVCMOS Wide Range Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 µA 100 µA 100 µA 100 µA 2 mA 4 mA 6 mA 8 mA tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 8.20 0.04 1.57 2.18 0.43 8.20 7.68 3.26 3.38 ns –1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns –2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns Std. 0.60 8.20 0.04 1.57 2.18 0.43 8.20 7.68 3.26 3.38 ns –1 0.51 6.97 0.04 1.33 1.85 0.36 6.97 6.53 2.77 2.87 ns –2 0.45 6.12 0.03 1.17 1.62 0.32 6.12 5.73 2.43 2.52 ns Std. 0.60 6.42 0.04 1.57 2.18 0.43 6.42 6.05 3.72 4.16 ns –1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns –2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns Std. 0.60 6.42 0.04 1.57 2.18 0.43 6.42 6.05 3.72 4.16 ns –1 0.51 5.46 0.04 1.33 1.85 0.36 5.46 5.14 3.17 3.54 ns –2 0.45 4.79 0.03 1.17 1.62 0.32 4.79 4.52 2.78 3.11 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 28 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-37 • 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010 Equivalent Software Default Drive Drive Strength Speed Grade Strength Option1 100 µA 100 µA 100 µA 100 µA 2 mA 4 mA 6 mA 8 mA tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 5.23 0.04 1.57 2.18 0.43 5.23 4.37 3.25 3.56 ns –1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns –2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns Std. 0.60 5.23 0.04 1.57 2.18 0.43 5.23 4.37 3.25 3.56 ns –1 0.51 4.45 0.04 1.33 1.85 0.36 4.45 3.71 2.77 3.03 ns –2 0.45 3.90 0.03 1.17 1.62 0.32 3.90 3.26 2.43 2.66 ns Std. 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 ns –1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns –2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns Std. 0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35 ns –1 0.51 3.35 0.04 1.33 1.85 0.36 3.35 2.69 3.16 3.70 ns –2 0.45 2.94 0.03 1.17 1.62 0.32 2.94 2.36 2.78 3.25 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 1 2- 29 ProASIC3 nano DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-38 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V mA mA Max. mA3 Max. mA3 µA4 µA4 2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-7 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-39 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 10 Notes: 1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF. 2- 30 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-40 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 11.29 0.04 1.43 1.63 0.43 10.64 11.29 2.27 2.29 ns –1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns –2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns Std. 0.60 11.29 0.04 1.43 1.63 0.43 10.64 11.29 2.27 2.29 ns –1 0.51 9.61 0.04 1.22 1.39 0.36 9.05 9.61 1.93 1.95 ns –2 0.45 8.43 0.03 1.07 1.22 0.32 7.94 8.43 1.70 1.71 ns Std. 0.60 7.73 0.04 1.43 1.63 0.43 7.70 7.73 2.60 2.89 ns –1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns –2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns Std. 0.60 7.73 0.04 1.43 1.63 0.43 7.70 7.73 2.60 2.89 ns –1 0.51 6.57 0.04 1.22 1.39 0.36 6.55 6.57 2.21 2.46 ns –2 0.45 5.77 0.03 1.07 1.22 0.32 5.75 5.77 1.94 2.16 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-41 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 8.38 0.04 1.43 1.63 0.43 7.36 8.38 2.27 2.37 ns –1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns –2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns Std. 0.60 8.38 0.04 1.43 1.63 0.43 7.36 8.38 2.27 2.37 ns –1 0.51 7.13 0.04 1.22 1.39 0.36 6.26 7.13 1.93 2.02 ns –2 0.45 6.26 0.03 1.07 1.22 0.32 5.50 6.26 1.69 1.77 ns Std. 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 ns –1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns –2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns Std. 0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98 ns –1 0.51 4.20 0.04 1.22 1.39 0.36 4.01 4.20 2.21 2.54 ns –2 0.45 3.69 0.03 1.07 1.22 0.32 3.52 3.69 1.94 2.23 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 31 ProASIC3 nano DC and Switching Characteristics Table 2-42 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 6.40 0.04 1.43 1.63 0.43 6.16 6.40 2.27 2.29 ns –1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns –2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns Std. 0.60 6.40 0.04 1.43 1.63 0.43 6.16 6.40 2.27 2.29 ns –1 0.51 5.45 0.04 1.22 1.39 0.36 5.24 5.45 1.93 1.95 ns –2 0.45 4.78 0.03 1.07 1.22 0.32 4.60 4.78 1.70 1.71 ns Std. 0.60 5.00 0.04 1.43 1.63 0.43 4.90 5.00 2.60 2.89 ns –1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns –2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns Std. 0.60 5.00 0.04 1.43 1.63 0.43 4.90 5.00 2.60 2.89 ns –1 0.51 4.26 0.04 1.22 1.39 0.36 4.17 4.26 2.21 2.46 ns –2 0.45 3.74 0.03 1.07 1.22 0.32 3.66 3.74 1.94 2.16 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-43 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 3.70 0.04 1.43 1.63 0.43 3.66 3.70 2.27 2.37 ns –1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns –2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns Std. 0.60 3.70 0.04 1.43 1.63 0.43 3.66 3.70 2.27 2.37 ns –1 0.51 3.15 0.04 1.22 1.39 0.36 3.12 3.15 1.93 2.02 ns –2 0.45 2.77 0.03 1.07 1.22 0.32 2.74 2.77 1.69 1.77 ns Std. 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 ns –1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns –2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns Std. 0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98 ns –1 0.51 2.35 0.04 1.22 1.39 0.36 2.38 2.21 2.21 2.54 ns –2 0.45 2.06 0.03 1.07 1.22 0.32 2.09 1.94 1.94 2.23 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 32 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-44 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Max. V VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Max. V Max. V Min. V mA mA Max. mA3 Max. mA3 µA4 µA4 VIH Drive Strength Min. V Min. V 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-8 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-45 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 10 Notes: 1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF. R ev i si o n 1 1 2- 33 ProASIC3 nano DC and Switching Characteristics Timing Characteristics Table 2-46 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 15.36 0.04 1.35 1.90 0.43 13.46 15.36 2.23 1.78 ns –1 0.51 13.07 0.04 1.15 1.61 0.36 11.45 13.07 1.90 1.51 ns –2 0.45 11.47 0.03 1.01 1.42 0.32 10.05 11.47 1.67 1.33 ns Std. 0.60 10.32 0.04 1.35 1.90 0.43 9.92 10.32 2.63 2.78 ns –1 0.51 8.78 0.04 1.15 1.61 0.36 8.44 8.78 2.23 2.37 ns –2 0.45 7.71 0.03 1.01 1.42 0.32 7.41 7.71 1.96 2.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-47 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 11.42 0.04 1.35 1.90 0.43 8.65 11.42 2.23 1.84 ns –1 0.51 9.71 0.04 1.15 1.61 0.36 7.36 9.71 1.89 1.57 ns –2 0.45 8.53 0.03 1.01 1.42 0.32 6.46 8.53 1.66 1.37 ns Std. 0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89 ns –1 0.51 5.56 0.04 1.15 1.61 0.36 4.70 5.56 2.23 2.45 ns –2 0.45 4.88 0.03 1.01 1.42 0.32 4.13 4.88 1.96 2.15 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 34 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-48 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 8.52 0.04 1.35 1.90 0.43 7.99 8.52 2.23 1.78 ns –1 0.51 7.25 0.04 1.15 1.61 0.36 6.80 7.25 1.90 1.51 ns –2 0.45 6.36 0.03 1.01 1.42 0.32 5.97 6.36 1.67 1.33 ns Std. 0.60 6.59 0.04 1.35 1.90 0.43 6.44 6.59 2.63 2.78 ns –1 0.51 5.60 0.04 1.15 1.61 0.36 5.48 5.60 2.23 2.37 ns –2 0.45 4.92 0.03 1.01 1.42 0.32 4.81 4.92 1.96 2.08 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-49 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA 4 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 4.79 0.04 1.35 1.90 0.43 4.27 4.79 2.23 1.84 ns –1 0.51 4.08 0.04 1.15 1.61 0.36 3.63 4.08 1.89 1.57 ns –2 0.45 3.58 0.03 1.01 1.42 0.32 3.19 3.58 1.66 1.37 ns Std. 0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89 ns –1 0.51 2.74 0.04 1.15 1.61 0.36 2.75 2.74 2.23 2.45 ns –2 0.45 2.40 0.03 1.01 1.42 0.32 2.42 2.40 1.95 2.15 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 35 ProASIC3 nano DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-50 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Max. V VIH Drive Strength Min. V Min. V Max. V 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Max. V Min. V Max. mA mA mA3 0.25 * VCCI 0.75 * VCCI 2 2 13 Max. mA3 µA4 µA4 16 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-9 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-51 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 10 Notes: 1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF. 2- 36 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-52 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 12.58 0.04 1.56 2.14 0.43 12.18 12.58 2.67 2.71 ns –1 0.51 10.70 0.04 1.32 1.82 0.36 10.36 10.70 2.27 2.31 ns –2 0.45 9.39 0.03 1.16 1.59 0.32 9.09 9.39 1.99 2.03 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-53 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250 Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83 ns –1 0.51 6.68 0.04 1.32 1.82 0.36 5.49 6.68 2.26 2.41 ns –2 0.45 5.87 0.03 1.16 1.59 0.32 4.82 5.87 1.99 2.12 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-54 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 8.01 0.04 1.56 2.14 0.43 8.03 8.01 2.67 2.71 ns –1 0.51 6.81 0.04 1.32 1.82 0.36 6.83 6.81 2.27 2.31 ns –2 0.45 5.98 0.03 1.16 1.58 0.32 6.00 5.98 2.10 2.03 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-55 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010 Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Std. 0.60 3.76 0.04 1.52 2.14 0.43 3.74 3.76 2.66 2.83 ns –1 0.51 3.20 0.04 1.32 1.82 0.36 3.18 3.20 2.26 2.41 ns –2 0.45 2.81 0.03 1.16 1.59 0.32 2.79 2.81 1.99 2.12 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 37 ProASIC3 nano DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L DOUT Data_out E Y F Core Array G PRE D Q DFN1E1P1 TRIBUF CLKBUF CLK INBUF Enable PRE D Q C DFN1E1P1 INBUF Data E E EOUT B H I A J K INBUF INBUF D_Enable CLK CLKBUF Enable Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 2- 38 R ev i sio n 1 1 Pad Out D ProASIC3 nano Flash FPGAs Table 2-56 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOSUE Enable Setup Time for the Output Data Register G, H tOHE Enable Hold Time for the Output Data Register G, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOESUE Enable Setup Time for the Output Enable Register K, H tOEHE Enable Hold Time for the Output Enable Register K, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tISUE Enable Setup Time for the Input Data Register B, A tIHE Enable Hold Time for the Input Data Register B, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A L, DOUT H, EOUT I, EOUT Note: *See Figure 2-10 on page 2-38 for more information. R ev i si o n 1 1 2- 39 ProASIC3 nano DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear D CC Q DFN1E1C1 EE Data_out FF D Q DFN1E1C1 TRIBUF INBUF Data Core Array Pad Out DOUT Y GG INBUF Enable BB EOUT E E CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered D Q DFN1E1C1 E INBUF CLKBUF CLK Enable INBUF D_Enable CLR Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-11 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 2- 40 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-57 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOSUE Enable Setup Time for the Output Data Register GG, HH tOHE Enable Hold Time for the Output Data Register GG, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOESUE Enable Setup Time for the Output Enable Register KK, HH tOEHE Enable Hold Time for the Output Enable Register KK, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tISUE Enable Setup Time for the Input Data Register BB, AA tIHE Enable Hold Time for the Input Data Register BB, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA LL, DOUT HH, EOUT Note: *See Figure 2-11 on page 2-40 for more information. R ev i si o n 1 1 2- 41 ProASIC3 nano DC and Switching Characteristics Input Register tICKMPWH tICKMPWL CLK 50% 50% Enable 50% 1 50% 50% 50% tIHD tISUD Data 50% 50% 50% 0 tIWPRE 50% tIRECPRE tIREMPRE 50% 50% tIHE Preset tISUE 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-12 • Input Register Timing Diagram Timing Characteristics Table 2-58 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 ns tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 ns tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.22 0.25 0.30 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 42 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD 1 Data_out Enable 50% 50% 0 50% tOWPRE tOHE Preset tOSUE tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tOREMCLR tORECCLR 50% 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-13 • Output Register Timing Diagram Timing Characteristics Table 2-59 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 ns tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 ns tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 43 ProASIC3 nano DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOESUD tOEHD 1 D_Enable Enable Preset 50% 0 50% 50% tOEWPRE 50% tOESUEtOEHE tOEREMPRE tOERECPRE 50% 50% tOEWCLR 50% Clear tOEPRE2Q EOUT 50% 50% tOEREMCLR tOERECCLR 50% 50% tOECLR2Q 50% tOECLKQ Figure 2-14 • Output Enable Register Timing Diagram Timing Characteristics Table 2-60 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.44 0.51 0.59 ns tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 ns tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 ns Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 ns tOERECCLR Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 44 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs DDR Module Specifications Input DDR Module Input DDR INBUF Data A D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-15 • Input DDR Timing Model Table 2-61 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B R ev i si o n 1 1 2- 45 ProASIC3 nano DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 tDDRIHD 6 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 7 5 Figure 2-16 • Input DDR Timing Diagram Timing Characteristics Table 2-62 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.27 0.31 0.37 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.39 0.44 0.52 ns tDDRISUD Data Setup for Input DDR (Fall) 0.28 0.32 0.38 ns Data Setup for Input DDR (Rise) 0.25 0.28 0.33 ns Data Hold for Input DDR (Fall) 0.00 0.00 0.00 ns Data Hold for Input DDR (Rise) 0.00 0.00 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.46 0.53 0.62 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.57 0.65 0.76 ns tDDRIREMCLR Asynchronous Clear Removal time for Input DDR 0.00 0.00 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery time for Input DDR 0.22 0.25 0.30 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 ns tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR 0.36 0.41 0.48 ns tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR 0.32 0.37 0.43 ns FDDRIMAX Maximum Frequency for Input DDR 350.00 350.00 350.00 MHz tDDRIHD Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 46 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Output DDR Module Output DDR A Data_F (from core) X FF1 B CLK CLKBUF E X C X D Data_R (from core) Out 0 X 1 X OUTBUF FF2 B X CLR INBUF C X DDR_OUT Figure 2-17 • Output DDR Timing Model Table 2-63 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B R ev i si o n 1 1 2- 47 ProASIC3 nano DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 1 Data_F 2 tDDROREMCLR Data_R 6 4 3 5 tDDROHD1 7 8 9 10 11 tDDRORECCLR tDDROREMCLR CLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 –2 –1 Std. Units Figure 2-18 • Output DDR Timing Diagram Timing Characteristics Table 2-64 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 ns FDDOMAX Maximum Frequency for the Output DDR 350.00 350.00 350.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 48 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide. A A B A OR2 Y AND2 A Y B B B XOR2 A B C Y A A B C NOR2 B A A Y INV NAND3 A MAJ3 B Y NAND2 XOR3 Y Y 0 MUX2 B Y Y 1 C S Figure 2-19 • Sample of Combinatorial Cells R ev i si o n 1 1 2- 49 ProASIC3 nano DC and Switching Characteristics tPD A NAND2 or Any Combinatorial Logic B Y tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) OUT tPD (FR) 50% tPD GND (RF) Figure 2-20 • Timing Model and Waveforms 2- 50 R ev i sio n 1 1 50% ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-65 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter –2 –1 Std. Units Y = !A tPD 0.40 0.46 0.54 ns Y=A·B tPD 0.47 0.54 0.63 ns Y = !(A · B) tPD 0.47 0.54 0.63 ns Y=A+B tPD 0.49 0.55 0.65 ns NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 ns XOR2 Y = A B tPD 0.74 0.84 0.99 ns MAJ3 Y = MAJ(A, B, C) tPD 0.70 0.79 0.93 ns XOR3 Y = A B C tPD 0.87 1.00 1.17 ns MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 ns AND3 Y=A·B·C tPD 0.56 0.64 0.75 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. VersaTile Specifications as a Sequential Module The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Data D Q Out Data En DFN1 D Out Q DFN1E1 CLK CLK PRE Data D Q Out Data En DFN1C1 D Q Out DFI1E1P1 CLK CLK CLR Figure 2-21 • Sample of Sequential Cells R ev i si o n 1 1 2- 51 ProASIC3 nano DC and Switching Characteristics tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data EN PRE 50% tRECPRE tREMPRE 50% 50% 50% CLR tPRE2Q 50% tREMCLR tRECCLR tWCLR Out 50% 50% 0 tWPRE tHE 50% 50% tHD 50% tSUE 50% 50% 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-22 • Timing Model and Waveforms Timing Characteristics Table 2-66 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 ns tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 ns tHD Data Hold Time for the Core Register 0.00 0.00 0.00 ns tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 ns tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.36 0.41 0.48 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.32 0.37 0.43 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 52 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Global Resource Characteristics A3PN250 Clock Tree Topology Clock delays are device-specific. Figure 2-23 is an example of a global tree used for clock routing. The global tree presented in Figure 2-23 is driven by a CCC located on the west side of the A3PN250 device. It is used to drive all D-flip-flops in the device. Central Global Rib VersaTile Rows CCC Global Spine Figure 2-23 • Example of Global Tree Use in an A3PN250 Device for Clock Routing R ev i si o n 1 1 2- 53 ProASIC3 nano DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-57. Table 2-67 to Table 2-72 on page 2-56 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-67 • A3PN010 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description Min. 1 –1 Max. 2 Min. 1 Std. Max. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.60 0.79 0.69 0.90 0.81 1.06 ns tRCKH Input HIGH Delay for Global Clock 0.62 0.84 0.70 0.96 0.82 1.12 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.22 0.26 0.30 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-68 • A3PN015 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description –1 Std. Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.66 0.91 0.75 1.04 0.89 1.22 ns tRCKH Input HIGH Delay for Global Clock 0.67 0.96 0.77 1.10 0.90 1.29 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.29 0.33 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 54 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Table 2-69 • A3PN020 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description Min. 1 Max. –1 2 Min. 1 Max. Std. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.66 0.91 0.75 1.04 0.89 1.22 ns tRCKH Input HIGH Delay for Global Clock 0.67 0.96 0.77 1.10 0.90 1.29 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.29 0.33 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-70 • A3PN060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description –1 Std. Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.72 0.91 0.82 1.04 0.96 1.22 ns tRCKH Input HIGH Delay for Global Clock 0.71 0.94 0.81 1.07 0.96 1.26 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.23 0.26 0.31 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 55 ProASIC3 nano DC and Switching Characteristics Table 2-71 • A3PN125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description Min. 1 Max. –1 2 Min. 1 Max. Std. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.76 0.99 0.87 1.12 1.02 1.32 ns tRCKH Input HIGH Delay for Global Clock 0.76 1.02 0.87 1.17 1.02 1.37 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-72 • A3PN250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter Description –1 Std. Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units tRCKL Input LOW Delay for Global Clock 0.79 1.02 0.90 1.16 1.06 1.36 ns tRCKH Input HIGH Delay for Global Clock 0.78 1.04 0.88 1.18 1.04 1.39 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 0.75 0.85 1.00 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 0.85 0.96 1.13 ns tRCKSW Maximum Skew for Global Clock 0.26 0.30 0.35 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values. 2- 56 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-73 • ProASIC3 nano CCC/PLL Specification Parameter Minimum Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 Delay Increments in Programmable Delay Blocks 1,2 Typical Maximum Units 350 MHz 350 MHz 2003 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL 4,5 125 MHz Input Cycle-to-Cycle Jitter (peak magnitude) 1.5 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms LockControl = 0 1.6 ns LockControl = 1 0.8 ns Tracking Jitter 7 Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1,2 1.25 15.65 ns Delay Range in Block: Programmable Delay 2 1,2 0.025 15.65 ns Delay Range in Block: Fixed Delay 1,2 VCO Output Peak-to-Peak Period Jitter 2.2 FCCC_OUT6 ns Max Peak-to-Peak Jitter Data 6,8,9 SSO2 SSO4 SSO 8 SSO 16 0.50% 0.50% 0.70% 1.00% 0.75 MHz to 50MHz 50 MHz to 250 MHz 1.00% 3.00% 5.00% 9.00% 250 MHz to 350 MHz 2.50% 4.00% 6.00% 12.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help for more information. 4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 5. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs. 6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 7. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI = 3.3 , VQ/PQ/TQ type of packages, 20 pF load. 9. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of each other. R ev i si o n 1 1 2- 57 ProASIC3 nano DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-24 • Peak-to-Peak Jitter Definition 2- 58 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM512X18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-25 • RAM Models R ev i si o n 1 1 2- 59 ProASIC3 nano DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A1 A0 [R|W]ADDR A2 tBKS tBKH BLK tENS tENH WEN tCKQ1 DOUT|RD Dn D0 D1 D2 tDOH1 Figure 2-26 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK t AS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENH tENS WEN tCKQ2 DOUT|RD Dn D0 D1 tDOH2 Figure 2-27 • RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18. 2- 60 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENS tENH WEN tDS DI0 DIN|WD tDH DI1 Dn DOUT|RD D2 Figure 2-28 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK tAS tAH A0 ADDR A1 A2 tBKS tBKH BLK tENS WEN tDS DI0 DIN DOUT (pass-through) DOUT (pipelined) tDH DI1 Dn DI2 DI0 DI1 DI0 Dn DI1 Figure 2-29 • RAM Write, Output as Write Data (WMODE = 1). Applicable to both RAM4K9 only. R ev i si o n 1 1 2- 61 ProASIC3 nano DC and Switching Characteristics tCYC tCKH tCKL CLK RESET tRSTBQ DOUT|RD Dm Dn Figure 2-30 • RAM Reset. Applicable to both RAM4K9 and RAM512x18. 2- 62 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-74 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address Setup time 0.25 0.28 0.33 ns tAH Address Hold time 0.00 0.00 0.00 ns tENS REN, WEN Setup time 0.14 0.16 0.19 ns tENH REN, WEN Hold time 0.10 0.11 0.13 ns tBKS BLK Setup time 0.23 0.27 0.31 ns tBKH BLK Hold time 0.02 0.02 0.02 ns tDS Input data (DIN) Setup time 0.18 0.21 0.25 ns tDH Input data (DIN) Hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on DOUT (output retained, WMODE = 0) 1.79 2.03 2.39 ns Clock High to New Data Valid on DOUT (flow-through, WMODE = 1) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on DOUT (pipelined) 0.89 1.02 1.20 ns tC2CWWL1 Address collision clk-to-clk delay for reliable write after write on same 0.33 address; applicable to closing edge 0.28 0.25 ns tC2CWWH1 Address collision clk-to-clk delay for reliable write after write on same 0.30 address; applicable to rising edge 0.26 0.23 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same 0.45 address; applicable to opening edge 0.38 0.34 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.49 address; applicable to opening edge 0.42 0.37 ns tRSTBQ RESET Low to Data Out Low on DOUT (flow through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on DOUT (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle time 3.23 3.68 4.32 ns FMAX Maximum Frequency 310 272 231 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. R ev i si o n 1 1 2- 63 ProASIC3 nano DC and Switching Characteristics Table 2-75 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tAS Address setup time 0.25 0.28 0.33 ns tAH Address hold time 0.00 0.00 0.00 ns tENS REN, WEN setup time 0.09 0.10 0.12 ns tENH REN, WEN hold time 0.06 0.07 0.08 ns tDS Input data (WD) setup time 0.18 0.21 0.25 ns tDH Input data (WD) hold time 0.00 0.00 0.00 ns tCKQ1 Clock High to new data valid on RD (output retained) 2.16 2.46 2.89 ns Clock High to new data valid on RD (pipelined) 0.90 1.02 1.20 ns 1 Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38 address; applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44 address; applicable to opening edge ns tRSTBQ RESET LOW to data out LOW on RD (flow-through) 0.92 1.05 1.23 ns RESET LOW to data out LOW on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET removal 0.29 0.33 0.38 ns tRECRSTB RESET recovery 1.50 1.71 2.01 ns tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns tCYC Clock cycle time 3.23 3.68 4.32 ns FMAX Maximum frequency 310 tCKQ2 tC2CRWH 272 231 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for FlashBased cSoCs and FPGAs. 2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values. 2- 64 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-31 • FIFO Model R ev i si o n 1 1 2- 65 ProASIC3 nano DC and Switching Characteristics Timing Waveforms tCYC RCLK tENH tENS REN tBKH tBKS RBLK tCKQ1 RD (flow-through) Dn D0 D1 D2 D0 D1 tCKQ2 RD (pipelined) Dn Figure 2-32 • FIFO Read tCYC WCLK tENS tENH WEN WBLK tBKS tBKH tDS WD DI0 tDH DI1 Figure 2-33 • FIFO Write 2- 66 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs RCLK/ WCLK tMPWRSTB tRSTCK RESET tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-34 • FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Assertion R ev i si o n 1 1 2- 67 ProASIC3 nano DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-36 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA MATCH (Address Counter) (EMPTY) RCLK NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA (Address Counter) WCLK MATCH (FULL) NO MATCH 1st Rising Edge After 1st Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH – 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-38 • FIFO FULL Flag and AFULL Flag Deassertion 2- 68 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs Timing Characteristics Table 2-76 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description –2 –1 Std. Units tENS REN, WEN Setup Time 1.38 1.57 1.84 ns tENH REN, WEN Hold Time 0.02 0.02 0.02 ns tBKS BLK Setup Time 0.22 0.25 0.30 ns tBKH BLK Hold Time 0.00 0.00 0.00 ns tDS Input Data (WD) Setup Time 0.18 0.21 0.25 ns tDH Input Data (WD) Hold Time 0.00 0.00 0.00 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.36 2.68 3.15 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 0.89 1.02 1.20 ns tRCKEF RCLK High to Empty Flag Valid 1.72 1.96 2.30 ns tWCKFF WCLK High to Full Flag Valid 1.63 1.86 2.18 ns tCKAF Clock High to Almost Empty/Full Flag Valid 6.19 7.05 8.29 ns tRSTFG RESET LOW to Empty/Full Flag Valid 1.69 1.93 2.27 ns tRSTAF RESET LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 0.92 1.05 1.23 ns RESET Low to Data Out Low on RD (pipelined) 0.92 1.05 1.23 ns tREMRSTB RESET Removal 0.29 0.33 0.38 ns tRECRSTB RESET Recovery 1.50 1.71 2.01 ns tMPWRSTB RESET Minimum Pulse Width 0.21 0.24 0.29 ns tCYC Clock Cycle Time 3.23 3.68 4.32 ns FMAX Maximum Frequency for FIFO 310 272 231 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 69 ProASIC3 nano DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-39 • Timing Diagram Timing Characteristics Table 2-77 • Embedded FlashROM Access Time Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tSU Address Setup Time 0.53 0.61 0.71 ns tHOLD Address Hold Time 0.00 0.00 0.00 ns tCK2Q Clock to Out 16.23 18.48 21.73 ns FMAX Maximum Clock Frequency 15.00 15.00 15.00 MHz 2- 70 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-12 for more details. Timing Characteristics Table 2-78 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –2 –1 Std. Units tDISU Test Data Input Setup Time 0.53 0.60 0.71 ns tDIHD Test Data Input Hold Time 1.07 1.21 1.42 ns tTMSSU Test Mode Select Setup Time 0.53 0.60 0.71 ns tTMDHD Test Mode Select Hold Time 1.07 1.21 1.42 ns tTCK2Q Clock to Q (data out) 6.39 7.24 8.52 ns tRSTB2Q Reset to Q (data out) 21.31 24.15 28.41 ns FTCKMAX TCK Maximum Frequency 23.00 20.00 17.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.21 0.24 0.28 ns tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. R ev i si o n 1 1 2- 71 ProASIC3 nano DC and Switching Characteristics 2- 72 R ev i sio n 1 1 3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V. When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano Device Family User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on ProASIC3 nano devices. VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on ProASIC3 nano devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank R ev i si o n 1 1 3 -1 Pin Descriptions and Packaging gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL • Output buffer is disabled (with tristate value of high impedance) • Input buffer is disabled (with tristate value of high impedance) • Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano Device Family User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure chapter of the ProASIC3 nano Device Family User’s Guide for an explanation of the naming of global pins. 3- 2 R ev isio n 1 1 ProASIC3 nano Flash FPGAs JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pullup/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-1 for more information. Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200 to 1 k VJTAG at 2.5 V 200 to 1 k VJTAG at 1.8 V 500 to 1 k VJTAG at 1.5 V 500 to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pulldown resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The values in Table 3-1 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 W to 1 kW will satisfy the requirements. R ev i si o n 1 1 3 -3 Pin Descriptions and Packaging Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents User’s Guides ProASIC nano Device Family User’s Guide http://www.microsemi.com/soc/documents/PA3_nano_UG.pdf Packaging The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical drawings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 3- 4 R ev isio n 1 1 4 – Package Pin Assignments 48-Pin QFN Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 1 1 4 -1 Package Pin Assignments 48-Pin QFN 48-Pin QFN Pin Number A3PN010 Function Pin Number A3PN010 Function 1 GEC0/IO37RSB1 36 IO07RSB0 2 IO36RSB1 37 IO06RSB0 3 GEA0/IO34RSB1 38 GDA0/IO05RSB0 4 IO22RSB1 39 IO03RSB0 5 GND 40 GDC0/IO01RSB0 6 VCCIB1 41 IO12RSB1 7 IO24RSB1 42 IO13RSB1 8 IO33RSB1 43 IO15RSB1 9 IO26RSB1 44 IO16RSB1 10 IO32RSB1 45 IO18RSB1 11 IO27RSB1 46 IO19RSB1 12 IO29RSB1 47 IO20RSB1 13 IO30RSB1 48 IO21RSB1 14 IO31RSB1 15 IO28RSB1 16 IO25RSB1 17 IO23RSB1 18 VCC 19 VCCIB1 20 IO17RSB1 21 IO14RSB1 22 TCK 23 TDI 24 TMS 25 VPUMP 26 TDO 27 TRST 28 VJTAG 29 IO11RSB0 30 IO10RSB0 31 IO09RSB0 32 IO08RSB0 33 VCCIB0 34 GND 35 VCC 4- 2 R ev isio n 1 1 ProASIC3 nano Flash FPGAs 48-Pin QFN 48-Pin QFN Pin Number A3PN030Z Function Pin Number A3PN030Z Function 1 IO82RSB1 36 IO25RSB0 2 GEC0/IO73RSB1 37 IO24RSB0 3 GEA0/IO72RSB1 38 IO22RSB0 4 GEB0/IO71RSB1 39 IO20RSB0 5 GND 40 IO18RSB0 6 VCCIB1 41 IO16RSB0 7 IO68RSB1 42 IO14RSB0 8 IO67RSB1 43 IO10RSB0 9 IO66RSB1 44 IO08RSB0 10 IO65RSB1 45 IO06RSB0 11 IO64RSB1 46 IO04RSB0 12 IO62RSB1 47 IO02RSB0 13 IO61RSB1 48 IO00RSB0 14 IO60RSB1 15 IO57RSB1 16 IO55RSB1 17 IO53RSB1 18 VCC 19 VCCIB1 20 IO46RSB1 21 IO42RSB1 22 TCK 23 TDI 24 TMS 25 VPUMP 26 TDO 27 TRST 28 VJTAG 29 IO38RSB0 30 GDB0/IO34RSB0 31 GDA0/IO33RSB0 32 GDC0/IO32RSB0 33 VCCIB0 34 GND 35 VCC R ev i si o n 1 1 4 -3 Package Pin Assignments 68-Pin QFN Pin A1 Mark 68 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 4 R ev isio n 1 1 ProASIC3 nano Flash FPGAs 68-Pin QFN 68-Pin QFN Pin Number A3PN015 Function Pin Number A3PN015 Function 1 IO60RSB2 37 TRST 2 IO54RSB2 38 VJTAG 3 IO52RSB2 39 IO17RSB0 4 IO50RSB2 40 IO16RSB0 5 IO49RSB2 41 GDA0/IO15RSB0 6 GEC0/IO48RSB2 42 GDC0/IO14RSB0 7 GEA0/IO47RSB2 43 IO13RSB0 8 VCC 44 VCCIB0 9 GND 45 GND 10 VCCIB2 46 VCC 11 IO46RSB2 47 IO12RSB0 12 IO45RSB2 48 IO11RSB0 13 IO44RSB2 49 IO09RSB0 14 IO43RSB2 50 IO05RSB0 15 IO42RSB2 51 IO00RSB0 16 IO41RSB2 52 IO07RSB0 17 IO40RSB2 53 IO03RSB0 18 IO39RSB1 54 IO18RSB1 19 IO37RSB1 55 IO20RSB1 20 IO35RSB1 56 IO22RSB1 21 IO33RSB1 57 IO24RSB1 22 IO31RSB1 58 IO28RSB1 23 IO30RSB1 59 NC 24 VCC 60 GND 25 GND 61 NC 26 VCCIB1 62 IO32RSB1 27 IO27RSB1 63 IO34RSB1 28 IO25RSB1 64 IO36RSB1 29 IO23RSB1 65 IO61RSB2 30 IO21RSB1 66 IO58RSB2 31 IO19RSB1 67 IO56RSB2 32 TCK 68 IO63RSB2 33 TDI 34 TMS 35 VPUMP 36 TDO R ev i si o n 1 1 4 -5 Package Pin Assignments 68-Pin QFN 68-Pin QFN Pin Number A3PN020 Function Pin Number A3PN020 Function 1 IO60RSB2 36 TDO 2 IO54RSB2 37 TRST 3 IO52RSB2 38 VJTAG 4 IO50RSB2 39 IO17RSB0 5 IO49RSB2 40 IO16RSB0 6 GEC0/IO48RSB2 41 GDA0/IO15RSB0 7 GEA0/IO47RSB2 42 GDC0/IO14RSB0 8 VCC 43 IO13RSB0 9 GND 44 VCCIB0 10 VCCIB2 45 GND 11 IO46RSB2 46 VCC 12 IO45RSB2 47 IO12RSB0 13 IO44RSB2 48 IO11RSB0 14 IO43RSB2 49 IO09RSB0 15 IO42RSB2 50 IO05RSB0 16 IO41RSB2 51 IO00RSB0 17 IO40RSB2 52 IO07RSB0 18 IO39RSB1 53 IO03RSB0 19 IO37RSB1 54 IO18RSB1 20 IO35RSB1 55 IO20RSB1 21 IO33RSB1 56 IO22RSB1 22 IO31RSB1 57 IO24RSB1 23 IO30RSB1 58 IO28RSB1 24 VCC 59 NC 25 GND 60 GND 26 VCCIB1 61 NC 27 IO27RSB1 62 IO32RSB1 28 IO25RSB1 63 IO34RSB1 29 IO23RSB1 64 IO36RSB1 30 IO21RSB1 65 IO61RSB2 31 IO19RSB1 66 IO58RSB2 32 TCK 67 IO56RSB2 33 TDI 68 IO63RSB2 34 TMS 35 VPUMP 4- 6 R ev isio n 1 1 ProASIC3 nano Flash FPGAs 68-Pin QFN 68-Pin QFN Pin Number A3PN030Z Function Pin Number A3PN030Z Function 1 IO82RSB1 37 TRST 2 IO80RSB1 38 VJTAG 3 IO78RSB1 39 IO40RSB0 4 IO76RSB1 40 IO37RSB0 5 GEC0/IO73RSB1 41 GDB0/IO34RSB0 6 GEA0/IO72RSB1 42 GDA0/IO33RSB0 7 GEB0/IO71RSB1 43 GDC0/IO32RSB0 8 VCC 44 VCCIB0 9 GND 45 GND 10 VCCIB1 46 VCC 11 IO68RSB1 47 IO31RSB0 12 IO67RSB1 48 IO29RSB0 13 IO66RSB1 49 IO28RSB0 14 IO65RSB1 50 IO27RSB0 15 IO64RSB1 51 IO25RSB0 16 IO63RSB1 52 IO24RSB0 17 IO62RSB1 53 IO22RSB0 18 IO60RSB1 54 IO21RSB0 19 IO58RSB1 55 IO19RSB0 20 IO56RSB1 56 IO17RSB0 21 IO54RSB1 57 IO15RSB0 22 IO52RSB1 58 IO14RSB0 23 IO51RSB1 59 VCCIB0 24 VCC 60 GND 25 GND 61 VCC 26 VCCIB1 62 IO12RSB0 27 IO50RSB1 63 IO10RSB0 28 IO48RSB1 64 IO08RSB0 29 IO46RSB1 65 IO06RSB0 30 IO44RSB1 66 IO04RSB0 31 IO42RSB1 67 IO02RSB0 32 TCK 68 IO00RSB0 33 TDI 34 TMS 35 VPUMP 36 TDO R ev i si o n 1 1 4 -7 Package Pin Assignments 100-Pin VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 8 R ev isio n 1 1 ProASIC3 nano Flash FPGAs 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN030Z Function Pin Number A3PN030Z Function Pin Number A3PN030Z Function 1 GND 36 IO51RSB1 71 IO29RSB0 2 IO82RSB1 37 VCC 72 IO28RSB0 3 IO81RSB1 38 GND 73 IO27RSB0 4 IO80RSB1 39 VCCIB1 74 IO26RSB0 5 IO79RSB1 40 IO49RSB1 75 IO25RSB0 6 IO78RSB1 41 IO47RSB1 76 IO24RSB0 7 IO77RSB1 42 IO46RSB1 77 IO23RSB0 8 IO76RSB1 43 IO45RSB1 78 IO22RSB0 9 GND 44 IO44RSB1 79 IO21RSB0 10 IO75RSB1 45 IO43RSB1 80 IO20RSB0 11 IO74RSB1 46 IO42RSB1 81 IO19RSB0 12 GEC0/IO73RSB1 47 TCK 82 IO18RSB0 13 GEA0/IO72RSB1 48 TDI 83 IO17RSB0 14 GEB0/IO71RSB1 49 TMS 84 IO16RSB0 15 IO70RSB1 50 NC 85 IO15RSB0 16 IO69RSB1 51 GND 86 IO14RSB0 17 VCC 52 VPUMP 87 VCCIB0 18 VCCIB1 53 NC 88 GND 19 IO68RSB1 54 TDO 89 VCC 20 IO67RSB1 55 TRST 90 IO12RSB0 21 IO66RSB1 56 VJTAG 91 IO10RSB0 22 IO65RSB1 57 IO41RSB0 92 IO08RSB0 23 IO64RSB1 58 IO40RSB0 93 IO07RSB0 24 IO63RSB1 59 IO39RSB0 94 IO06RSB0 25 IO62RSB1 60 IO38RSB0 95 IO05RSB0 26 IO61RSB1 61 IO37RSB0 96 IO04RSB0 27 IO60RSB1 62 IO36RSB0 97 IO03RSB0 28 IO59RSB1 63 GDB0/IO34RSB0 98 IO02RSB0 29 IO58RSB1 64 GDA0/IO33RSB0 99 IO01RSB0 30 IO57RSB1 65 GDC0/IO32RSB0 100 IO00RSB0 31 IO56RSB1 66 VCCIB0 32 IO55RSB1 67 GND 33 IO54RSB1 68 VCC 34 IO53RSB1 69 IO31RSB0 35 IO52RSB1 70 IO30RSB0 R ev i si o n 1 1 4 -9 Package Pin Assignments 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN060 Function Pin Number A3PN060 Function Pin Number A3PN060 Function 1 GND 36 IO61RSB1 71 GBB2/IO27RSB0 2 GAA2/IO51RSB1 37 VCC 72 IO26RSB0 3 IO52RSB1 38 GND 73 GBA2/IO25RSB0 4 GAB2/IO53RSB1 39 VCCIB1 74 VMV0 5 IO95RSB1 40 IO60RSB1 75 GNDQ 6 GAC2/IO94RSB1 41 IO59RSB1 76 GBA1/IO24RSB0 7 IO93RSB1 42 IO58RSB1 77 GBA0/IO23RSB0 8 IO92RSB1 43 IO57RSB1 78 GBB1/IO22RSB0 9 GND 44 GDC2/IO56RSB1 79 GBB0/IO21RSB0 10 GFB1/IO87RSB1 45 GDB2/IO55RSB1 80 GBC1/IO20RSB0 11 GFB0/IO86RSB1 46 GDA2/IO54RSB1 81 GBC0/IO19RSB0 12 VCOMPLF 47 TCK 82 IO18RSB0 13 GFA0/IO85RSB1 48 TDI 83 IO17RSB0 14 VCCPLF 49 TMS 84 IO15RSB0 15 GFA1/IO84RSB1 50 VMV1 85 IO13RSB0 16 GFA2/IO83RSB1 51 GND 86 IO11RSB0 17 VCC 52 VPUMP 87 VCCIB0 18 VCCIB1 53 NC 88 GND 19 GEC1/IO77RSB1 54 TDO 89 VCC 20 GEB1/IO75RSB1 55 TRST 90 IO10RSB0 21 GEB0/IO74RSB1 56 VJTAG 91 IO09RSB0 22 GEA1/IO73RSB1 57 GDA1/IO49RSB0 92 IO08RSB0 23 GEA0/IO72RSB1 58 GDC0/IO46RSB0 93 GAC1/IO07RSB0 24 VMV1 59 GDC1/IO45RSB0 94 GAC0/IO06RSB0 25 GNDQ 60 GCC2/IO43RSB0 95 GAB1/IO05RSB0 26 GEA2/IO71RSB1 61 GCB2/IO42RSB0 96 GAB0/IO04RSB0 27 GEB2/IO70RSB1 62 GCA0/IO40RSB0 97 GAA1/IO03RSB0 28 GEC2/IO69RSB1 63 GCA1/IO39RSB0 98 GAA0/IO02RSB0 29 IO68RSB1 64 GCC0/IO36RSB0 99 IO01RSB0 30 IO67RSB1 65 GCC1/IO35RSB0 100 IO00RSB0 31 IO66RSB1 66 VCCIB0 32 IO65RSB1 67 GND 33 IO64RSB1 68 VCC 34 IO63RSB1 69 IO31RSB0 35 IO62RSB1 70 GBC2/IO29RSB0 4- 10 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN060Z Pin Number A3PN060Z Pin Number A3PN060Z 1 GND 36 IO61RSB1 71 GBB2/IO27RSB0 2 GAA2/IO51RSB1 37 VCC 72 IO26RSB0 3 IO52RSB1 38 GND 73 GBA2/IO25RSB0 4 GAB2/IO53RSB1 39 VCCIB1 74 VMV0 5 IO95RSB1 40 IO60RSB1 75 GNDQ 6 GAC2/IO94RSB1 41 IO59RSB1 76 GBA1/IO24RSB0 7 IO93RSB1 42 IO58RSB1 77 GBA0/IO23RSB0 8 IO92RSB1 43 IO57RSB1 78 GBB1/IO22RSB0 9 GND 44 GDC2/IO56RSB1 79 GBB0/IO21RSB0 10 GFB1/IO87RSB1 45 GDB2/IO55RSB1 80 GBC1/IO20RSB0 11 GFB0/IO86RSB1 46 GDA2/IO54RSB1 81 GBC0/IO19RSB0 12 VCOMPLF 47 TCK 82 IO18RSB0 13 GFA0/IO85RSB1 48 TDI 83 IO17RSB0 14 VCCPLF 49 TMS 84 IO15RSB0 15 GFA1/IO84RSB1 50 VMV1 85 IO13RSB0 16 GFA2/IO83RSB1 51 GND 86 IO11RSB0 17 VCC 52 VPUMP 87 VCCIB0 18 VCCIB1 53 NC 88 GND 19 GEC1/IO77RSB1 54 TDO 89 VCC 20 GEB1/IO75RSB1 55 TRST 90 IO10RSB0 21 GEB0/IO74RSB1 56 VJTAG 91 IO09RSB0 22 GEA1/IO73RSB1 57 GDA1/IO49RSB0 92 IO08RSB0 23 GEA0/IO72RSB1 58 GDC0/IO46RSB0 93 GAC1/IO07RSB0 24 VMV1 59 GDC1/IO45RSB0 94 GAC0/IO06RSB0 25 GNDQ 60 GCC2/IO43RSB0 95 GAB1/IO05RSB0 26 GEA2/IO71RSB1 61 GCB2/IO42RSB0 96 GAB0/IO04RSB0 27 GEB2/IO70RSB1 62 GCA0/IO40RSB0 97 GAA1/IO03RSB0 28 GEC2/IO69RSB1 63 GCA1/IO39RSB0 98 GAA0/IO02RSB0 29 IO68RSB1 64 GCC0/IO36RSB0 99 IO01RSB0 30 IO67RSB1 65 GCC1/IO35RSB0 100 IO00RSB0 31 IO66RSB1 66 VCCIB0 32 IO65RSB1 67 GND 33 IO64RSB1 68 VCC 34 IO63RSB1 69 IO31RSB0 35 IO62RSB1 70 GBC2/IO29RSB0 R ev i si o n 1 1 4- 11 Package Pin Assignments 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN125 Function Pin Number A3PN125 Function Pin Number A3PN125 Function 1 GND 36 IO93RSB1 71 GBB2/IO43RSB0 2 GAA2/IO67RSB1 37 VCC 72 IO42RSB0 3 IO68RSB1 38 GND 73 GBA2/IO41RSB0 4 GAB2/IO69RSB1 39 VCCIB1 74 VMV0 5 IO132RSB1 40 IO87RSB1 75 GNDQ 6 GAC2/IO131RSB1 41 IO84RSB1 76 GBA1/IO40RSB0 7 IO130RSB1 42 IO81RSB1 77 GBA0/IO39RSB0 8 IO129RSB1 43 IO75RSB1 78 GBB1/IO38RSB0 9 GND 44 GDC2/IO72RSB1 79 GBB0/IO37RSB0 10 GFB1/IO124RSB1 45 GDB2/IO71RSB1 80 GBC1/IO36RSB0 11 GFB0/IO123RSB1 46 GDA2/IO70RSB1 81 GBC0/IO35RSB0 12 VCOMPLF 47 TCK 82 IO32RSB0 13 GFA0/IO122RSB1 48 TDI 83 IO28RSB0 14 VCCPLF 49 TMS 84 IO25RSB0 15 GFA1/IO121RSB1 50 VMV1 85 IO22RSB0 16 GFA2/IO120RSB1 51 GND 86 IO19RSB0 17 VCC 52 VPUMP 87 VCCIB0 18 VCCIB1 53 NC 88 GND 19 GEC0/IO111RSB1 54 TDO 89 VCC 20 GEB1/IO110RSB1 55 TRST 90 IO15RSB0 21 GEB0/IO109RSB1 56 VJTAG 91 IO13RSB0 22 GEA1/IO108RSB1 57 GDA1/IO65RSB0 92 IO11RSB0 23 GEA0/IO107RSB1 58 GDC0/IO62RSB0 93 IO09RSB0 24 VMV1 59 GDC1/IO61RSB0 94 IO07RSB0 25 GNDQ 60 GCC2/IO59RSB0 95 GAC1/IO05RSB0 26 GEA2/IO106RSB1 61 GCB2/IO58RSB0 96 GAC0/IO04RSB0 27 GEB2/IO105RSB1 62 GCA0/IO56RSB0 97 GAB1/IO03RSB0 28 GEC2/IO104RSB1 63 GCA1/IO55RSB0 98 GAB0/IO02RSB0 29 IO102RSB1 64 GCC0/IO52RSB0 99 GAA1/IO01RSB0 30 IO100RSB1 65 GCC1/IO51RSB0 100 GAA0/IO00RSB0 31 IO99RSB1 66 VCCIB0 32 IO97RSB1 67 GND 33 IO96RSB1 68 VCC 34 IO95RSB1 69 IO47RSB0 35 IO94RSB1 70 GBC2/IO45RSB0 4- 12 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN125Z Function Pin Number A3PN125Z Function Pin Number A3PN125Z Function 1 GND 36 IO93RSB1 71 GBB2/IO43RSB0 2 GAA2/IO67RSB1 37 VCC 72 IO42RSB0 3 IO68RSB1 38 GND 73 GBA2/IO41RSB0 4 GAB2/IO69RSB1 39 VCCIB1 74 VMV0 5 IO132RSB1 40 IO87RSB1 75 GNDQ 6 GAC2/IO131RSB1 41 IO84RSB1 76 GBA1/IO40RSB0 7 IO130RSB1 42 IO81RSB1 77 GBA0/IO39RSB0 8 IO129RSB1 43 IO75RSB1 78 GBB1/IO38RSB0 9 GND 44 GDC2/IO72RSB1 79 GBB0/IO37RSB0 10 GFB1/IO124RSB1 45 GDB2/IO71RSB1 80 GBC1/IO36RSB0 11 GFB0/IO123RSB1 46 GDA2/IO70RSB1 81 GBC0/IO35RSB0 12 VCOMPLF 47 TCK 82 IO32RSB0 13 GFA0/IO122RSB1 48 TDI 83 IO28RSB0 14 VCCPLF 49 TMS 84 IO25RSB0 15 GFA1/IO121RSB1 50 VMV1 85 IO22RSB0 16 GFA2/IO120RSB1 51 GND 86 IO19RSB0 17 VCC 52 VPUMP 87 VCCIB0 18 VCCIB1 53 NC 88 GND 19 GEC0/IO111RSB1 54 TDO 89 VCC 20 GEB1/IO110RSB1 55 TRST 90 IO15RSB0 21 GEB0/IO109RSB1 56 VJTAG 91 IO13RSB0 22 GEA1/IO108RSB1 57 GDA1/IO65RSB0 92 IO11RSB0 23 GEA0/IO107RSB1 58 GDC0/IO62RSB0 93 IO09RSB0 24 VMV1 59 GDC1/IO61RSB0 94 IO07RSB0 25 GNDQ 60 GCC2/IO59RSB0 95 GAC1/IO05RSB0 26 GEA2/IO106RSB1 61 GCB2/IO58RSB0 96 GAC0/IO04RSB0 27 GEB2/IO105RSB1 62 GCA0/IO56RSB0 97 GAB1/IO03RSB0 28 GEC2/IO104RSB1 63 GCA1/IO55RSB0 98 GAB0/IO02RSB0 29 IO102RSB1 64 GCC0/IO52RSB0 99 GAA1/IO01RSB0 30 IO100RSB1 65 GCC1/IO51RSB0 100 GAA0/IO00RSB0 31 IO99RSB1 66 VCCIB0 32 IO97RSB1 67 GND 33 IO96RSB1 68 VCC 34 IO95RSB1 69 IO47RSB0 35 IO94RSB1 70 GBC2/IO45RSB0 R ev i si o n 1 1 4- 13 Package Pin Assignments 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN250 Function Pin Number A3PN250 Function Pin Number A3PN250 Function 1 GND 37 VCC 73 GBA2/IO20RSB1 2 GAA2/IO67RSB3 38 GND 74 VMV1 3 IO66RSB3 39 VCCIB2 75 GNDQ 4 GAB2/IO65RSB3 40 IO39RSB2 76 GBA1/IO19RSB0 5 IO64RSB3 41 IO38RSB2 77 GBA0/IO18RSB0 6 GAC2/IO63RSB3 42 IO37RSB2 78 GBB1/IO17RSB0 7 IO62RSB3 43 GDC2/IO36RSB2 79 GBB0/IO16RSB0 8 IO61RSB3 44 GDB2/IO35RSB2 80 GBC1/IO15RSB0 9 GND 45 GDA2/IO34RSB2 81 GBC0/IO14RSB0 10 GFB1/IO60RSB3 46 GNDQ 82 IO13RSB0 11 GFB0/IO59RSB3 47 TCK 83 IO12RSB0 12 VCOMPLF 48 TDI 84 IO11RSB0 13 GFA0/IO57RSB3 49 TMS 85 IO10RSB0 14 VCCPLF 50 VMV2 86 IO09RSB0 15 GFA1/IO58RSB3 51 GND 87 VCCIB0 16 GFA2/IO56RSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO08RSB0 19 GFC2/IO55RSB3 55 TRST 91 IO07RSB0 20 GEC1/IO54RSB3 56 VJTAG 92 IO06RSB0 21 GEC0/IO53RSB3 57 GDA1/IO33RSB1 93 GAC1/IO05RSB0 22 GEA1/IO52RSB3 58 GDC0/IO32RSB1 94 GAC0/IO04RSB0 23 GEA0/IO51RSB3 59 GDC1/IO31RSB1 95 GAB1/IO03RSB0 24 VMV3 60 IO30RSB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO29RSB1 97 GAA1/IO01RSB0 26 GEA2/IO50RSB2 62 GCA1/IO27RSB1 98 GAA0/IO00RSB0 27 GEB2/IO49RSB2 63 GCA0/IO28RSB1 99 GNDQ 28 GEC2/IO48RSB2 64 GCC0/IO26RSB1 100 VMV0 29 IO47RSB2 65 GCC1/IO25RSB1 30 IO46RSB2 66 VCCIB1 31 IO45RSB2 67 GND 32 IO44RSB2 68 VCC 33 IO43RSB2 69 IO24RSB1 34 IO42RSB2 70 GBC2/IO23RSB1 35 IO41RSB2 71 GBB2/IO22RSB1 36 IO40RSB2 72 IO21RSB1 4- 14 R ev i sio n 1 1 ProASIC3 nano Flash FPGAs 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A3PN250Z Function Pin Number A3PN250Z Function Pin Number A3PN250Z Function 1 GND 37 VCC 73 GBA2/IO20RSB1 2 GAA2/IO67RSB3 38 GND 74 VMV1 3 IO66RSB3 39 VCCIB2 75 GNDQ 4 GAB2/IO65RSB3 40 IO39RSB2 76 GBA1/IO19RSB0 5 IO64RSB3 41 IO38RSB2 77 GBA0/IO18RSB0 6 GAC2/IO63RSB3 42 IO37RSB2 78 GBB1/IO17RSB0 7 IO62RSB3 43 GDC2/IO36RSB2 79 GBB0/IO16RSB0 8 IO61RSB3 44 GDB2/IO35RSB2 80 GBC1/IO15RSB0 9 GND 45 GDA2/IO34RSB2 81 GBC0/IO14RSB0 10 GFB1/IO60RSB3 46 GNDQ 82 IO13RSB0 11 GFB0/IO59RSB3 47 TCK 83 IO12RSB0 12 VCOMPLF 48 TDI 84 IO11RSB0 13 GFA0/IO57RSB3 49 TMS 85 IO10RSB0 14 VCCPLF 50 VMV2 86 IO09RSB0 15 GFA1/IO58RSB3 51 GND 87 VCCIB0 16 GFA2/IO56RSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO08RSB0 19 GFC2/IO55RSB3 55 TRST 91 IO07RSB0 20 GEC1/IO54RSB3 56 VJTAG 92 IO06RSB0 21 GEC0/IO53RSB3 57 GDA1/IO33RSB1 93 GAC1/IO05RSB0 22 GEA1/IO52RSB3 58 GDC0/IO32RSB1 94 GAC0/IO04RSB0 23 GEA0/IO51RSB3 59 GDC1/IO31RSB1 95 GAB1/IO03RSB0 24 VMV3 60 IO30RSB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO29RSB1 97 GAA1/IO01RSB0 26 GEA2/IO50RSB2 62 GCA1/IO27RSB1 98 GAA0/IO00RSB0 27 GEB2/IO49RSB2 63 GCA0/IO28RSB1 99 GNDQ 28 GEC2/IO48RSB2 64 GCC0/IO26RSB1 100 VMV0 29 IO47RSB2 65 GCC1/IO25RSB1 30 IO46RSB2 66 VCCIB1 31 IO45RSB2 67 GND 32 IO44RSB2 68 VCC 33 IO43RSB2 69 IO24RSB1 34 IO42RSB2 70 GBC2/IO23RSB1 35 IO41RSB2 71 GBB2/IO22RSB1 36 IO40RSB2 72 IO21RSB1 R ev i si o n 1 1 4- 15 5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the ProASIC3 nano datasheet. Revision Revision 11 (January 2013) Changes Page The "ProASIC3 nano Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43219). 1-III Added a Note stating "VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to Table 2-1 • Absolute Maximum Ratings (SAR 38326). 2-1 Added a note to Table 2-2 · Recommended Operating Conditions 1, 2 (SAR 43646): 2-2 The programming temperature range supported is Tambient = 0°C to 85°C. The note in Table 2-73 • ProASIC3 nano CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42570). 2-57 Figure 2-32 • FIFO Read and Figure 2-33 • FIFO Write are new (SAR 34847). 2-66 Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40288). NA Live at Power-Up (LAPU) has been replaced with ’Instant On’. Revision 10 The "Security" section was modified to clarify that Microsemi does not support read(September 2012) back of programmed data. Revision 9 (March 2012) 1-1 The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 34668). I, 1-1 Notes indicating that A3P015 is not recommended for new designs have been added (SAR 36761). I-IV Notes indicating that nano-Z devices are not recommended for use in new designs have been added. The "Devices Not Recommended For New Designs" section is new (SAR 36702). The Y security option and Licensed DPA Logo were added to the "ProASIC3 nano Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34726). III Corrected the Commercial Temperature range to reflect a range of 0°C to 70°C instead of –20°C to 70°C in the "ProASIC3 nano Ordering Information", "Temperature Grade Offerings", and the "Speed Grade and Temperature Grade Matrix" sections (SAR 37097). III-IV The following sentence was removed from the "Advanced Architecture" section: "In addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V) programming of IGLOO nano devices via an IEEE 1532 JTAG interface" (SAR 34688). 1-3 The "Specifying I/O States During Programming" section is new (SAR 34698). 1-7 R ev i si o n 1 1 5 -1 Datasheet Information Revision Revision 9 (continued) Changes Page The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture" section of the Global Resources chapter in the IProASIC3 nano FPGA Fabric User's Guide (SAR 34736). 2-9 Figure 2-3 has been modified for the DIN waveform; the Rise and Fall time label has been changed to tDIN (37114). 2-13 The notes regarding drive strength in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section tables were revised for clarification. They now state that the minimum drive strength for the default software configuration when run in wide range is ±100 µA. The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 34759). 2-17, 2-25 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34888). 2-22 Added values for minimum pulse width and removed the FRMAX row from Table 2-67 through Table 2-72 in the "Global Tree Timing Characteristics" section. Use the software to determine the FRMAX for the device you are using (SAR 36956). 2-54 through 2-56 Table 2-73 • ProASIC3 nano CCC/PLL Specification was updated. A note was added indicating that when the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available (SAR 34823). 2-57 The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" tables, Figure 2-34 • FIFO Reset, and the FIFO "Timing Characteristics" tables were revised to ensure consistency with the software names (SAR 35743). 2-60, 2-63, 2-67, 2-69 Reference was made to a new application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 34871). The "Pin Descriptions and Packaging" chapter has been added (SAR 34772). 3-1 July 2010 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "ProASIC3 nano Device Status" table on page II indicates the status for each device in the device family. N/A Revision 8 (April 2010) References to differential inputs were removed from the datasheet, since ProASIC3 nano devices do not support differential inputs (SAR 21449). N/A The "ProASIC3 nano Device Status" table is new. 5- 2 II The JTAG DC voltage was revised in Table 2-2 • Recommended Operating Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming voltage (operation mode) was changed from 3.45 V to 3.6 V (SAR 25220). 2-2 The highest temperature in Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays was changed to 100ºC. 2-5 The typical value for A3PN010 was revised in Table 2-7 • Quiescent Supply Current Characteristics. The note was revised to remove the statement that values do not include I/O static contribution. 2-6 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Revision Revision 8 (continued) Changes The following tables were updated with available information: Table 2-8 · Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings; Table 2-9 · Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1; Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices; Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels; Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF); Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF) Page 2-6 through 2-18 Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide range data and correct the formulas in the table notes (SAR 21348). 2-19 The text introducing Table 2-24 • Duration of Short Circuit Event before Failure was revised to state six months at 100° instead of three months at 110° for reliability concerns. The row for 110° was removed from the table. 2-20 Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was revised to give values with Schmitt trigger disabled and enabled (SAR 24634). The temperature for reliability was changed to 100ºC. 2-21 Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range and the timing tables in the "Single-Ended I/O Characteristics" section were updated with available information. The timing tables for 3.3 V LVCMOS wide range are new. 2-22 The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a 5 V– tolerant input buffer and push-pull output buffer." 2-30 Values for tDDRISUD and FDDRIMAX were updated in Table 2-62 • Input DDR Propagation Delays. Values for FDDOMAX were added to Table 2-64 • Output DDR Propagation Delays (SAR 23919). 2-46, 2-48 Table 2-67 • A3PN010 Global Resource through Table 2-70 • A3PN060 Global Resource were updated with available information. 2-54 through 2-55 Table 2-73 • ProASIC3 nano CCC/PLL Specification was revised (SAR 79390). R ev i si o n 1 1 2-57 5 -3 Datasheet Information Revision Changes Revision 7 (Jan 2010) Page All product tables and pin tables were updated to show clearly that A3PN030 is Product Brief Advance available only in the Z feature at this time, as A3PN030Z. The nano-Z feature grade devices are designated with a Z at the end of the part number. v0.7 N/A Packaging Advance v0.6 N/A The "68-Pin QFN" and "100-Pin VQFP" pin tables for A3PN030 were removed. Only the Z grade for A3PN030 is available at this time. Revision 6 (Aug 2009) The note for A3PN030 in the "ProASIC3 nano Devices" table was revised. It Product Brief Advance states A3PN030 is available in the Z feature grade only. I v0.6 Packaging v0.5 Advance The "68-Pin QFN" pin table for A3PN030 is new. The "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin tables for A3PN030Z are new. 3-7 4-3, 4-7, 4-9 The "100-Pin VQFP" pin table for A3PN060Z is new. 4-11 The "100-Pin VQFP" pin table for A3PN125Z is new 4-13 The "100-Pin VQFP" pin table for A3PN250Z is new. 4-15 Revision 5 (Mar 2009) All references to speed grade –F were removed from this document. N/A Product Brief Advance The"I/Os with Advanced I/O Standards" section was revised to add definitions of v0.5 hot-swap and cold-sparing. 1-7 Revision 4 (Feb 2009) The "100-Pin VQFP" pin table for A3PN030 is new. 3-10 Packaging Advance v0.4 Revision 3 (Feb 2009) The "100-Pin QFN" section was removed. N/A Packaging Advance v0.3 Revision 2 (Nov 2008) The "ProASIC3 nano Devices" table was revised to change the maximum user Product Brief Advance I/Os for A3PN020 and A3PN030. The following table note was removed: "Six chip (main) and three quadrant global networks are available for A3PN060 and v0.4 above." The QN100 package was removed for all devices. The "Device Marking" section is new. Revision 1 (Oct 2008) The A3PN030 device was added to product tables and replaces A3P030 entries Product Brief Advance that were formerly in the tables. v0.3 The "Wide Range I/O Support" section is new. 5- 4 I N/A III I to IV 1-7 The "I/Os Per Package" table was updated to add the following information to table note 4: "For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only." II The "ProASIC3 nano Products Available in the Z Feature Grade" section was updated to remove QN100 for A3PN250. IV The "General Description" section was updated to give correct information about number of gates and dual-port RAM for ProASIC3 nano devices. 1-1 R ev isio n 1 1 ProASIC3 nano Flash FPGAs Revision Revision 1 (cont’d) DC and Switching Characteristics Advance v0.2 Changes Page The device architecture figures, Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125) through Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250), were revised. Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM (A3PN010 and A3PN030) is new. 1-3 through 1-4 The "PLL and CCC" section was revised to include information about CCC-GLs in A3PN020 and smaller devices. 1-6 Table 2-2 • Recommended Operating Conditions 1, 2 was revised to add VMV to the VCCI row. The following table note was added: "VMV pins must be connected to the corresponding VCCI pins." 2-2 The values in Table 2-7 • Quiescent Supply Current Characteristics were revised for A3PN010, A3PN015, and A3PN020. 2-6 A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide 2-16, 2-18 range, as specified in the JESD8-B specification," was added to Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels, Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF), and Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF). 3.3 V LVCMOS Wide Range was added to Table 2-21 • I/O Output Buffer 2-19, 2-20 Maximum Resistances 1 and Table 2-23 • I/O Short Currents IOSH/IOSL. Packaging Advance v0.2 The "48-Pin QFN" pin diagram was revised. 4-2 Note 2 for the "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin diagrams was added/changed to "The die attach paddle of the package is tied to ground (GND)." 4-2, 4-5, 4-9 The "100-Pin VQFP" pin diagram was revised to move the pin IDs to the upper left corner instead of the upper right corner. 4-9 R ev i si o n 1 1 5 -5 Datasheet Information Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "ProASIC3 nano Device Status" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information. 5- 6 R ev isio n 1 1 Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. 51700111-11/01.13