Allegro A6809 Dabic-iv, 10-bit serial-input, latched source driver Datasheet

Data Sheet
26182.124B
6809 AND
6810
DABiC-IV, 10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6810xA
OUT 8
1
18
OUT 9
OUT 7
2
17
OUT 10
OUT 6
3
16
SERIAL
DATA OUT
CLOCK
4
GROUND
5
LATCHES
CLK
REGISTER
VBB 15
LOAD
SUPPLY
REGISTER
14
SERIAL
DATA IN
LATCHES
LOGIC
SUPPLY
6
VDD
STROBE
7
ST
OUT 5
OUT 4
BLNK 13
BLANKING
12
OUT 1
8
11
OUT 2
9
10
OUT 3
Dwg. PP-029
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
IOUT ......................... -40 mA to +15 mA
Input Voltage Range,
VIN ....................... -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
The A6809– and A6810– devices combine 10-bit CMOS shift
registers, accompanying data latches and control circuitry with bipolar
sourcing outputs and pnp active pull downs. Designed primarily to
drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings
also allow these devices to be used in many other peripheral power
driver applications. The A6809– and A6810– feature an increased data
input rate (compared with the older UCN/UCQ5810-F) and a controlled output slew rate. The A6809xLW and A6810xLW are identical
except for pinout.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
A CMOS serial data output permits cascade connections in applications requiring additional drive lines. Similar devices are avail-able as
the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).
The A6809– and A6810– output source drivers are npn Darlingtons, capable of sourcing up to 40 mA. The controlled output slew rate
reduces electromagnetic noise, which is an important consideration in
systems that include telecommunications and/or microprocessors and
to meet government emissions regulations. For inter-digit blanking, all
output drivers can be disabled and all sink drivers turned on with a
BLANKING input high. The pnp active pull-downs will sink at least
2.5 mA.
All devices are available in two temperature ranges for optimum
performance in commercial (suffix S-) or industrial (suffix E-) applications. The A6810– is provided in three package styles for through-hole
DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area
surface-mount PLCC (suffix -EP). The A6809– is provided in the
SOIC (suffix -LW) only. Copper lead frames, low logic-power dissipation, and low output-saturation voltages allow all devices to source
25 mA from all outputs continuously over the maximum operating
temperature range.
FEATURES
■ Controlled Output Slew Rate ■ Low Output-Saturation Voltages
■ High-Speed Data Storage
■ Low-Power CMOS Logic
■ 60 V Minimum
and Latches
Output Breakdown
■ Improved Replacements
■ High Data Input Rate
for TL4810–, UCN5810–,
■ PNP Active Pull-Downs
and UCQ5810–
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6810SLW .
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL OUTPUT DRIVER
V
TYPICAL INPUT CIRCUIT
VDD
BB
OUTN
IN
Dwg. EP-021-19
A6809xLW
Dwg. EP-010-5
OUT 10
OUT 6
3
LOGIC SUPPLY
7
VDD
STROBE
8
ST
OUT 5
OUT 4
REGISTER
LOAD SUPPLY
15
SERIAL
DATA IN
CLOCK
4
NC
5
GROUND
6
LOGIC
SUPPLY
7
STROBE
8
18
CLK
LATCHES
LATCHES
BLNK 14
BLANKING
13
OUT 1
9
12
OUT 2
10
11
OUT 3
V BB 17
REGISTER
NC
15
SERIAL
DATA IN
LATCHES
BLNK 14
ST
Dwg. PP-029-9
LOAD
SUPPLY
16
REGISTER
V DD
SERIAL
DATA OUT
BLANKING
13
NC
16
OUT1
6
BB
SERIAL
DATA OUT
12
NO
CONNECTION
V
17
11
5
REGISTER
10
GROUND
CLK
9
4
OUT 5
CLOCK
NO
CONNECTION
3
NC 18
LATCHES
A6810xEP
OUT10
19
19
2
20
OUT 7
1
OUT 9
2
20
OUT 6
OUT 8
1
Dwg. PP-059
OUT 8
1
20
OUT 9
OUT 7
2
19
OUT 10
OUT 6
3
18
SERIAL
DATA OUT
CLOCK
4
LATCHES
CLK
GROUND
5
LOGIC SUPPLY
6
VDD
STROBE
7
ST
OUT 5
OUT 4
REGISTER
VBB 17
REGISTER
16
LATCHES
NO
CONNECTION
BLNK 15
LOAD SUPPLY
SERIAL
DATA IN
BLANKING
14
OUT 1
8
13
OUT 2
9
12
OUT 3
10
NC
NC 11
NO
CONNECTION
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
A6810xLW
2.5
SUFFIX 'EP', R θJA = 59°C/W
2.0
SUFFIX 'A', R θJA = 60°C/W
1.5
1.0
0.5
SUFFIX 'LW', R θJA = 70°C/W
0
25
50
75
100
125
AMBIENT TEMPERATURE IN °C
Dwg. PP-029-2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1998, 2000 Allegro MicroSystems, Inc.
150
Dwg. GP-024-1
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V DD
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
SERIAL
DATA OUT
BLANKING
MOS
BIPOLAR
LOAD
SUPPLY
VBB
GROUND
OUT 1 OUT 2 OUT 3
OUT N
Dwg. FP-013-1
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
Output Contents
IN-1 IN Blanklng
I1 I2 I3 ... IN-1 IN
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
www.allegromicro.com
X = Irrelevant
X
P = Present State
X
...
X
R = Previous State
L
L
... L
L
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6809SLW & A6810S-) or over operating
temperature range (A6809ELW & A6810E-), VBB = 60 V unless otherwise noted.
Limits @ VDD = 3.3 V
Characteristic
Output Leakage Current
Symbol
ICEX
Test Conditions
VOUT = 0 V
Limits @ VDD = 5 V
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
—
<-0.1
-15
—
<-0.1
-15
µA
57.5
58.3
—
57.5
58.3
—
V
VOUT(1)
IOUT = -25 mA
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
1.0
1.5
V
Output Pull-Down Current
IOUT(0)
VOUT = 5 V to VBB
2.5
5.0
—
2.5
5.0
—
mA
Input Voltage
VIN(1)
2.2
—
—
3.3
—
—
V
VIN(0)
—
—
1.1
—
—
1.7
V
Output Voltage
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
IIN(1)
VIN = VDD
—
<0.01
1.0
—
<0.01
1.0
µA
IIN(0)
VIN = 0 V
—
<-0.01
-1.0
—
<-0.01
-1.0
µA
IIN = -200 µA
—
-0.8
-1.5
—
-0.8
-1.5
V
VOUT(1)
IOUT = -200 µA
2.8
3.05
—
4.5
4.75
—
V
VOUT(0)
IOUT = 200 µA
—
0.15
0.3
—
0.15
0.3
V
10
33
—
10
33
—
MHz
VIK
fc
IDD(1)
All Outputs High
—
0.25
0.75
—
0.3
1.0
mA
IDD(0)
All Outputs Low
—
0.25
0.75
—
0.3
1.0
mA
IBB(1)
All Outputs High, No Load
—
1.5
3.0
—
1.5
3.0
mA
IBB(0)
All Outputs Low
—
0.2
20
—
0.2
20
µA
tdis(BQ)
CL = 30 pF, 50% to 50%
—
0.7
2.0
—
0.7
2.0
µs
ten(BQ)
CL = 30 pF, 50% to 50%
—
1.8
3.0
—
1.8
3.0
µs
tp(STH-QL)
RL = 2.3 kΩ, CL ≤ 30 pF
—
0.7
2.0
—
0.7
2.0
µs
tp(STH-QH)
RL = 2.3 kΩ, CL ≤ 30 pF
—
1.8
3.0
—
1.8
3.0
µs
Output Fall Time
tf
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
µs
Output Rise Time
tr
RL = 2.3 kΩ, CL ≤ 30 pF
2.4
—
12
2.4
—
12
µs
Output Slew Rate
dV/dt
RL = 2.3 kΩ, CL ≤ 30 pF
4.0
—
20
4.0
—
20
V/µs
IOUT = ±200 µA
—
50
—
—
50
—
ns
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
50%
STROBE
BLANKING
E
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
OUT N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t dis(BQ)
t en(BQ)
tr
tf
90%
OUT N
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
10%
DATA
Dwg. WP-030
NOTE – Timing is representative of a 10 MHz clock. Significantly higher speeds are attainable.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
www.allegromicro.com
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6810EA & A6810SA
Dimensions in Inches
(controlling dimensions)
18
0.014
0.008
10
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
0.920
0.880
9
0.005
BSC
MIN
0.210
MAX
0.150
0.115
0.015
MIN
0.022
0.014
Dwg. MA-001-18A in
Dimensions in Millimeters
(for reference only)
18
0.355
0.204
10
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
23.37
22.35
9
0.13
BSC
MIN
5.33
MAX
3.81
2.93
0.39
MIN
0.558
0.356
Dwg. MA-001-18A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6810EEP & A6810SEP
Dimensions in Inches
(controlling dimensions)
13
9
0.021
0.013
8
14
0.169
0.141
0.395
0.385
0.032
0.026
INDEX AREA
0.356
0.350
0.050
0.169
0.141
BSC
18
4
19
20
1
2
3
0.356
0.350
0.020
MIN
0.395
0.385
0.180
0.165
Dimensions in Millimeters
(for reference only)
Dwg. MA-005-20A in
13
9
0.533
0.331
10.03
9.78
0.812
0.661
INDEX AREA
9.042
8.890
1.27
4.29
3.58
8
14
4.29
3.58
BSC
18
4
19
0.51
MIN
4.57
4.20
20
1
2
3
9.042
8.890
10.03
9.78
Dwg. MA-005-20A mm
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
NOTES: 1. Exact body and lead configuration at vendor’s
option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
6809 AND 6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
A6809ELW, A6809SLW, A6810ELW, & A6810SLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.5118
0.4961
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-20 in
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
13.00
12.60
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000