ACS257MS Radiation Hardened Quad 2-Input Multiplexer with Three-State Outputs November 1997 Features Description • QML Qualified Per MIL-PRF-38535 Requirements The Radiation Hardened ACS257MS is a Quad 2-Channel multiplexer which selects four bits of data from one of two sources under the control of a single select pin. The Output Enable input is active LOW and controls all outputs. When OE is set HIGH, all outputs are configured into a high impedance state, regardless of all other input conditions. All inputs are buffered and the outputs are designed for balanced propagation delay and transition times. • 1.25Micron Radiation Hardened SOS CMOS • Radiation Environment - Latch-up Free Under any Conditions - Total Dose . . . . . . . . . . . . . . . . . . . . . . 3 x 105 RAD(Si) - SEU Immunity . . . . . . . . . . . <1 x 10-10 Errors/Bit/Day - SEU LET Threshold . . . . . . . . . . . >100MeV/(mg/cm2) The ACS257MS is fabricated on a CMOS Silicon on Sapphire (SOS) process, which provides an immunity to Single Event Latch-up and the capability of highly reliable performance in any radiation environment. These devices offer significant power reduction and faster performance when compared to ALSTTL types. • Input Logic Levels . . .VIL = (0.3)(VCC), VIH = (0.7)(VCC) • Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8mA • Quiescent Supply Current. . . . . . . . . . . . . . . . . . .400µA • Propagation Delay - Enable to Output . . . . . . . . . . . . . . . . . . . . . . . . . 13ns - Input or Address to Output . . . . . . . . . . . . . . . . . 14ns Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Applications Detailed Electrical Specifications for the ACS257 are contained in SMD 5962-98008. A “hot-link” is provided on our homepage with instructions for downloading. http://www.intersil.com/data/sm/index.htm • 4-Bit Source Selection • Data Routing • High Frequency Switching Ordering Information SMD PART NUMBER TEMP. RANGE (oC) INTERSIL PART NUMBER 5962F9800801VEC ACS257DMSR-02 N/A ACS257D/Sample-02 PACKAGE CASE OUTLINE -55 to 125 16 Ld SBDIP CDIP2-T16 25 16 Ld SBDIP CDIP2-T16 5962F9800801VXC ACS257KMSR-02 -55 to 125 16 Ld Flatpack CDFP4-F16 N/A ACS257K/Sample-02 25 16 Ld Flatpack CDFP4-F16 N/A ACS257HMSR-02 25 Die N/A Pinouts ACS257 (SBDIP) TOP VIEW S 1 ACS257 (FLATPACK) TOP VIEW 16 VCC S 1 16 VCC 1I0 2 15 OE 1I0 2 15 OE 1I1 3 14 4I0 1I1 3 14 4I0 1Y 4 13 4I1 1Y 4 13 4I1 2I0 5 12 4Y 2I0 5 12 4Y 11 3I0 2I1 6 11 3I0 2Y 7 10 3I1 GND 8 9 3Y 2I1 6 2Y 7 10 3I1 GND 8 9 3Y CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 File Number 4429 ACS257MS Die Characteristics PASSIVATION DIE DIMENSIONS: Type: Phosphorous Silicon Glass (PSG) Thickness: 1.30µm ±0.15µm Size: 2390µm x 2390µm (94 mils x 94 mils) Thickness: 525µm ±25µm (20.6 mils ±1 mil) Bond Pad: 110µm x 110µm (4.3 x 4.3 mils) SPECIAL INSTRUCTIONS: METALLIZATION: Al Metal 1 Thickness: 0.7µm ±0.1µm Metal 2 Thickness: 1.0µm ±0.1µm Bond VCC First ADDITIONAL INFORMATION: Worst Case Density: <2.0 x 105 A/cm2 Transistor Count: 212 SUBSTRATE POTENTIAL: Unbiased Insulator Metallization Mask Layout ACS257MS 1I0 S VCC OE 1I1 4I 0 1Y 4I 1 2I 0 4Y 2I 1 3I 0 2Y GND 3Y 3I 1 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 2