ACT5271 64-Bit Superscaler Microprocessor Features ■ ■ Full militarized QED RM5271 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle ■ ● Single cycle repeat rate for common single precision operations and some double precision operations ● Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations ● Single cycle repeat rate for single precision combined multiplyadd operation ● 150, 200, 250 MHz operating frequencies – Consult Factory for latest speeds ● 345 Dhrystone2.1 MIPS maximum ● SPECInt95 7.3, SPECfp95 8.3 maximum ■ High performance system interface compatible with RM7000, RM5270, RM5260, RM5261, R4600, R4700 and R5000 to 125MHz memory bus operation for a 1000MBps bandwidth from CPU to L2 cache and main memory ● 64-bitmultiplexed system address/data bus for optimum price/ performance with high performance write protocols to maximize uncached write bandwidth ● Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9) ● IEEE 1149.1 JTAG boundary scan ■ point multiply-add instruction increases performance in signal processing and graphics applications ● Conditional moves to reduce branch frequency ● Index address modes (register + register) instruction/data -both 2 way set associative indexed, physically tagged ● Write-back and write-through on per page basis ● Pipeline restart on first double for data cache misses ● Virtually ■ Integrated secondary cache controller (R5000 compatible) ● ■ ■ Supports 512K or 2MByte block write-through secondary Integrated memory management unit associative joint TLB (shared by I and D translations) ● 48 dual entries map 96 pages ● Variable page size (4KB to 16MB in 4x increments) Embedded application enhancements ● Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction ● I and D cache locking by set ● Optional dedicated exception vector for interrupts Integrated on-chip caches ● 32KB/32KB MIPS IV instruction set ● Floating ● Up ■ High-performance floating point unit - up to 532 MFLOPS ■ Fully static CMOS design with power down logic ● Standby reduced power mode with WAIT instruction Watts typical power @ 200MHz ● 2.5V core with 3.3V IO’s ● 4.2 ■ 208-lead CQFP, cavity-up package (F17) ■ 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint 179-pin PGA package (Future Product) (P10) ● Fully ■ BLOCK DIAGRAM Preliminary eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5271 REV 1 12/22/98 DESCRIPTION addition to this standard pipeline, the ACT5271 uses an extended seven stage pipeline for floating-point operations. Like the ACT5270 and R5000, the ACT5271 does virtual to physical translation in parallel with cache access. The Aeroflex ACT5271 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32 KByte 2-way set associative instruction cache, a 32 KByte 2-way set associative data cache, and a high-performance 64-bit system interface with support for an optional external secondary cache. The ACT5271 can issue both an integer and a floating point instruction in the same cycle. The ACT5271 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.The ACT5271 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large secondary cache (up to 2MB) provide outstanding price/performance Integer Unit Like the other members of the ACT52xx family and R5000, the ACT5271 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5271 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5271 datasheet, these instructions are integer multiply-accumulate and 3-operand integer multiply. The ACT5271 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/ divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/divide operations, and the program counter(PC). HARDWARE OVERVIEW The ACT5271 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the ACT5271 are briefly described below. Register File The ACT5271 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. Superscalar Dispatch The ACT5271 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5271 provides unparalleled price/performance in computationally intensive embedded applications. ALU The ACT5271 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all tions in a single processor cycle. CPU Registers Like all MIPS ISA processors, the ACT5271 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. For additional Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark ACT5271, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.0 July 1998). Pipeline For integer operations, loads, stores, and other non-floating-point operations, the ACT5271 uses the simple 5-stage pipeline also found in the ACT52xx family, R4600, R4700, and R5000. In Aeroflex Circuit Technology 2 SCD5271 REV 1 12/22/98 Plainview NY (516) 694-6700 Package Information – "F17" – CQFP 208 Leads 1.131 (28.727) SQ 1.109 (28.169) SQ 53 104 105 .0236 (.51) .0158 (.49) 52 .010R MIN .015 (.381) .009 (.229) .010R MIN .130 (3.302) MAX 1.009 (25.63) .9998 (25.37) 51 Spaces at .0197 (51 Spaces at .50) 0°±5° .100 (2.540) .080 (2.032) .009 (.253) .007 (.178) .035 (.889) .025 (.635) Detail "A" 1 156 Pin 1 Chamfer 208 157 .055 (1.397) REF .960 (24.384) SQ REF Detail "A" .005 (.127) .008 (.258) 1.331 (33.807) 1.269 (32.233) .115 (2.921) MAX .055 (1.397) .045 (1.143) Units: Inches (Millimeters) Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction. Future Package – "P10" – PGA 179 Pins (Advanced) Bottom View 1 2 3 4 5 6 7 8 Side View 9 10 11 12 13 14 15 16 17 18 .100 BSC V U T R P N M L 1.700 1.840 BSC 1.880 K J .018 H G F E D C B A .050 1.700 BSC .221 MAX 1.840 1.880 Aeroflex Circuit Technology 3 SCD5271 REV 1 12/22/98 Plainview NY (516) 694-6700 ACT5271 Microprocessor CQFP Pinouts – "F17" Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Aeroflex Circuit Technology Function Vcc (3.3V) NC NC Vcc (3.3V) Vss SysAD4 SysAD36 SysAD5 SysAD37 Vcc (2.5V) Vss SysAD6 SysAD38 Vcc (3.3V) Vss SysAD7 SysAD39 SysAD8 SysAD40 Vcc (2.5V) Vss SysAD9 SysAD41 Vcc (3.3V) Vss SysAD10 SysAD42 SysAD11 SysAD43 Vcc (2.5V) Vss SysAD12 SysAD44 Vcc (3.3V) Vss SysAD13 SysAD45 SysAD14 SysAD46 Vcc (2.5V) Vss SysAD15 SysAD47 Vcc (3.3V) Vss ModeClock JTDO JTDI JTCK JTMS Vcc (3.3V) Vss Pin # 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Function NC NC NC Vcc (3.3V) Vss ModeIn RdRdy* WrRdy* ValidIn* ValidOut* Release* VccP VssP SysClock Vcc (2.5V) Vss Vcc (3.3V) Vss Vcc (2.5V) Vss SysCmd0 SysCmd1 SysCmd2 SysCmd3 Vcc (3.3V) Vss SysCmd4 SysCmd5 Vcc (3.3V) Vss SysCmd6 SysCmd7 SysCmd8 SysCmdP Vcc (2.5V) Vss Vcc (2.5V) Vss Vcc (3.3V) Vss Int0* Int1* Int2* Int3* Int4* Int5* Vcc (3.3V) Vss NC NC NC NC Pin # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 4 Function Vcc (3.3V) NMI* ExtRqst* Reset* ColdReset* VccOK BigEndian Vcc (3.3V) Vss SysAD16 SysAD48 Vcc (2.5V) Vss SysAD17 SysAD49 SysAD18 SysAD50 Vcc (3.3V) Vss SysAD19 SysAD51 Vcc (2.5V) Vss SysAD20 SysAD52 SysAD21 SysAD53 Vcc (3.3V) Vss SysAD22 SysAD54 Vcc (2.5V) Vss SysAD23 SysAD55 SysAD24 SysAD56 Vcc (3.3V) Vss SysAD25 SysAD57 Vcc (2.5V) Vss SysAD26 SysAD58 SysAD27 SysAD59 Vcc (3.3V) Vss NC NC Vss Pin # 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function NC NC NC NC Vcc (3.3V) Vss SysAD28 SysAD60 SysAD29 SysAD61 Vcc (2.5V) Vss SysAD30 SysAD62 Vcc (3.3V) Vss SysAD31 SysAD63 SysADC2 SysADC6 Vcc (2.5V) Vss SysADC3 SysADC7 Vcc (3.3V) Vss SysADC0 SysADC4 Vcc (2.5V) Vss SysADC1 SysADC5 SysAD0 SysAD32 Vcc (3.3V) Vss SysAD1 SysAD33 Vcc (2.5V) Vss SysAD2 SysAD34 SysAD3 SysAD35 Vcc (3.3V) Vss NC NC NC NC Vcc (3.3V) Vss SCD5271 REV 1 12/22/98 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Sample Ordering Information Part Number Screening Speed (MHz) Package ACT-5271PC-150F17C Commercial Temperature 150 208 Lead CQFP ACT-5271PC-200F17I Industrial Temperature 200 208 Lead CQFP ACT-5271PC-250F17T Military Temperature 250 208 Lead CQFP ACT-5271PC-250F17M Military Screening 250 208 Lead CQFP Part Number Breakdown ACT– 5271 PC – 200 F17 M Aeroflex Circuit Technology Screening Base Processor Type C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable Package Type & Size Cache Style PC = Primary Cache Maximum Pipeline Freq. 150 = 150MHz 200 = 200MHz 250 = 250MHz 266 = 266MHz (Future option) Surface Mount Package F17 = 1.120" SQ 208 Lead CQFP F24 = 1.120" SQ Inverted 208 Lead CQFP Thru-Hole Package P10 = 1.86"SQ PGA 179 pins with shoulder (Advanced) * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: [email protected] Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology 5 SCD5271 REV 1 12/22/98 Plainview NY (516) 694-6700