ACT–F1M32 High Speed 32 Megabit Boot Block FLASH Multichip Module CIRCUIT TECHNOLOGY www.aeroflex.com/act1.htm Features ■ 4 Low Voltage/Power Intel 1M x 8 FLASH Die in One MCM Package ■ Overall Configuration is 1M x 32 ■ +5V Operation (Standard) or +3.3V (Consult Factory) ■ Access Times of 80, 100 and 120 nS ( 5V VCC) ■ +5V or +12V Programing ■ Erase/Program Cycles ● 100,000 Commercial ● 10,000 Military and Industrial ■ Sector Architecture (Each Die) ● One 16K Protected Boot Block (Bottom Boot Block Standard, Top Boot Block Special Order) ● Two 8K Parameter Blocks ● One 96K Main Block ● Seven 128K Main Blocks Block Diagram – CQFP(F14) ■ ■ ■ ■ ■ Single Block Erase (All bits set to 1) Hardware Data Protection Feature Independent Boot Block Locking MIL-PRF-38534 Compliant MCMs Available Packaging – Hermetic Ceramic ● 68 Lead, .94" x .94" x .180" Dual-Cavity Small Outline Gull Wing, Aeroflex code# "F14" (Drops into the 68 Lead JEDEC .99"SQ CQFJ footprint) ■ Internal Decoupling Capacitors for Low Noise Operation ■ Commercial, Industrial and Military Temperature Ranges Pin Description Standard Configuration CE1 I/O0-31 CE4 A0–19 CE3 CE2 WP WE OE A0 – A19 RP 1Mx8 1Mx8 1Mx8 1Mx8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 Data I/O Address Inputs WE Write Enables CE1-4 Chip Enables OE Output Enable WP Write Protect RP Reset/Powerdown VCC Power Supply GND Ground NC Not Connected Block Diagram – CQFP(F14) Pin Description Optional Configuration WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4 RP OE A0 – A19 1Mx8 1Mx8 1Mx8 1Mx8 8 8 8 8 I/O0-7 I/O8-15 I/O16-23 I/O24-31 I/O0-31 Data I/O A 0–19 Address Inputs WE1-4 Write Enable CE1-4 Chip Enables OE Output Enable RP Reset/Powerdown VCC Power Supply GND Ground NC Not Connected General Description Utilizing Intel’s SmartVoltage Boot Block Flash Memory SmartDie™, the ACT–F1M32 is a high speed, 32 megabit CMOS flash multichip module (MCM) designed for full temperature range military, space, or high reliability applications. The ACT-F1M32 consists of four high-performance Intel X28F800BV 8 Mbit (8,388,608 bit) memory die. Each die contains separately erasable blocks, including a hardware lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each), and 8 main blocks (one block of 98,304 bytes and seven blocks of 131,072 bytes) This defines the boot block flash family architecture. The command register is written by bringing WE to a logic low level (VIL), while CE is low and OE is high (VIH). Reading is eroflex Circuit Technology - Advanced Multichip Modules © SCD1661B REV A 1/16/97 General Description, Cont’d, accomplished by chip Enable (CE) and Output Enable (OE) being logically active. Access time grades of 80nS, 100nS and 120nS maximum are standard. The ACT–F1M32 is packaged in a hermetically sealed co-fired ceramic 68 lead, .94" SQ Ceramic Gull Wing CQFP package. This allows operation in a military environment temperature range of -55°C to +125°C. The ACT–F1M32 provides program and erase capability at 5V or 12V and allows reads with Vcc at 5V or 3.3V(Not tested). Since many designs read from flash memory a large percentage of the time, read operation using 3.3V can provide great power savings. Consult the factory for 3.3V tested parts. In applications where read performance is critical, faster access times are obtainable with the 5V VCC part detailed herein. For program and erase operations, 5V Vpp operation eliminates the need for in system voltage converters. The 12V Vpp operation provides reduced (approx 60%) program and erase times where 12V is available in the system. For design simplicity, however, connect Vcc and Vpp to the same 5V ±10% source. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. The boot block is located at either the bottom (Standard) or the top (Special Order) of the address map in order to accommodate different microprocessor protocols for boot code location. Locking and unlocking of the boot block is controlled by WP and/or RP. Intel's boot block architecture provides a flexible solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM; the parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing RAM requirements. For Detail Information regarding the operation of the 28F800BV Memory die, see the Intel datasheet (order number 290539-002). SmartDie™ is a Trademark of Intel Corporation Aeroflex Circuit Technology 2 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 Absolute Maximum Ratings Parameter Range Units -55 to +125 °C Storage Temperature Range -65 to +150 °C Voltage on Any Pin with Respect to GND (except VCC, VPP, A9 and RP) (1) -2.0 to +7.0 V -2.0 to +13.5 V -2.0 to +14.0 V Case Operating Temperature Range Voltage on Pins A9 or RP with Respect to GND (except VCC, VPP, A9 and RP) (1,2) VPP Program Voltage with Respect to GND during Block Erase/ and Word/Byte Write (1,2) Vcc Supply Voltage with Respect to Ground (1) -2.0 to +7.0 V 100 mA Output Short Circuit Current (3) Notes: 1. Minimum DC voltage is -0.5V on input/output pins. During Transitions, inputs may undershoot to -2.0V for periods < 20nS. Maximum DC voltage on input/output pins is Vcc + 0.5V, which may overshoot to Vcc + 2.0V for periods < 20nS. 2. Maximum DC voltage on Vpp may overshoot to +14.0V for periods < 20nS. Maximum DC voltage on RP or A9 may overshoot to VCC + 0.5V for periods <20nS 3. Output shorted for no more than 1 second. No more than one output shorted at one time. NOTICE: Stresses above those listed under "Absolute Maximums Rating" may cause permanent damage. These are stress rating only. Operation beyond the "Operation Conditions" is not recommended and extended exposure beyond the "Operation Conditions" may effect device reliability. Recommended Operating Conditions Symbol VCC Parameter Minimum Maximum Units +4.5 +5.5 V 5V Power Supply Voltage (10%) 3.3V Power Supply Voltage (±0.3V) (Consult Factory) +3.0 +3.6 V VIH Input High Voltage (3.3V & 5V VCC) +2.0 Vcc + 0.5 V V IL Input Low Voltage (3.3V & 5V VCC) -0.5 +0.8 V Operating Temperature (Military) -55 +125 °C TA Capacitance (f = 1MHz, TA = 25°C) Symbol Maximum Units A0 – A19 Capacitance 50 pF COE OE Capacitance 50 pF CCE CAD Parameter CE Capacitance 20 pF CRP RP Capacitance 50 pF CWE WE Capacitance 60 pF CWP WP Capacitance 50 pF CI/O I/O0 – I/O31 Capacitance 20 pF Capacitance Guaranteed by design, but not tested. DC Characteristics – CMOS Compatible (TA = -55°C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) +3.3V VCC (1) Parameter Input Load Current Output Leakage Current Sym Conditions Typical +5.0V VCC Standard Min Max Min Max +1 IIL VCC = VCCMax., VIN = VCC or GND -1 +1 -1 ILO VCC = VCCMax., VIN = VCC or GND -10 +10 -10 Units µA +10 µA VCC = VCCMax., CE = RP = WP = VCC ± 0.2V 440 600 µA VCC = VCCMax., VIN = VCC or GND, RP = GND ± 0.2V 32 32 µA VCC = VCCMax., CE = GND, f = 10MHz (5V), 5MHz (3.3V), IOUT = 0 mA, Inputs = GND ± 0.2V or VCC ± 0.2V 120 260 mA ICCW1 VPP = VPPH 1 (at 5V), Word Write in Progress (x32) 120 200 mA ICCW2 Vcc Standby Current ICCS Vcc Deep Power-Down Current ICCD Vcc Read Current ICCR Vcc Write Current VPP = VPPH 2 (at 12V), Word Write in Progress (x32) 100 180 mA Vcc Erase Current ICCE1 VPP = VPPH 1 (at 5V),Block Erase in Progress 120 180 mA ICCE2 VPP = VPPH 2 (at 12V),Block Erase in Progress 100 160 mA Vcc Erase Suspend Current ICCES CE = VIH, Block Erase Suspend 32 48 mA VPP < VPPH 2 60 60 µA VPP Standby Current Aeroflex Circuit Technology IPPS 3 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 DC Characteristics – CMOS Compatible (TA = -55°C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) +3.3V VCC (1) Parameter Sym Conditions +5.0V VCC Typical Min Standard Max Min Units Max µA IPPD RP = GND ± 0.2V 40 40 VPP Read Current IPPR VPP > VPPH 2 800 800 µA VPP Write Current IPPW1 VPP = VPPH 1 (at 5V), Word Write in Progress (x32) 120 120 mA VPP Deep Power Down Current IPPW2 VPP = VPPH 2 (at 12V), Word Write in Progress (x32) 100 100 mA VPP Erase Current IPPE1 VPP = VPPH 1 (at 5V), Block Erase in Progress 120 100 mA IPPE2 VPP = VPPH 2 (at 12V), Block Erase in Progress 100 80 mA VPP Erase Suspend Current IPPES VPP = VPPH , Block Erase Suspend in Progress 800 800 µA 2 2 mA 0.45 0.45 V RP Boot Block Unlock Current IRP RP = VHH , VPP = 12V Output Low Voltage VOL VCC = VCCMin., IOL = 5.8 mA (5V), 2 mA (3.3V) VOH1 VCC = VCCMin., IOH = -2.5 mA 0.85 x VCC VOH2 VCC = VCCMin., IOH = -100 µA VCC 0.4V VPP Lock-Out Voltage VPPLK Complete Write Protection 0.0 1.5 0.0 1.5 V VPP (Program/Erase Operations) VPPH1 VPP = at 5V 4.5 5.5 4.5 5.5 V 11.4 12.6 11.4 12.6 V 0 2.0 0 2.0 V 11.4 12.6 11.4 12.6 V Output High Voltage VPP (Program/Erase Operations) VPPH2 VPP = at 12V VCC Erase/Write Lock Voltage VLKO Locked Condition RP Unlock Voltage VHH Boot Block Write/Erase, VPP = 12V 0.85 x VCC V VCC 0.4V V Notes: 1. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not tested). AC Characteristics – Write/Erase/Program Operations – WE Controlled (TA = -55°C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) +3.3V VCC Symbol Parameter (2) +4.5V to +5.5V VCC Typical JEDEC Standard 120nS 80nS 100nS 120nS Min Max Min Max Min Max Min Max Units Write Cycle Time tAVAV 120 80 100 120 nS RP High Recovery to WE Going Low tPHWL 1.5 .45 .45 .45 µS CE Setup to WE Going Low Boot Block Unlock Setup to WE Going High(1) tELWL 0 0 0 0 nS tPHHWH 200 100 100 100 nS tVPWH 200 100 100 100 nS tAVWH 90 60 60 60 nS Data Setup to WE Going High tDVWH 70 60 60 60 nS WE Pulse Width tWLWH 90 60 60 60 nS Data Hold Time from WE High tWHDX 0 0 0 0 nS Address Hold Time from WE High tWHAX 0 0 0 0 nS VPP Setup to WE Going High (1) Address Setup to WE Going High CE Hold Time from WE High tWHEH 0 0 0 0 nS WE Pulse Width High tWHWL 30 20 20 20 nS tWHQV1 6 6 6 6 µS Duration of Erase Operation (Boot) (1) tWHQV2 0.3 0.3 0.3 0.3 Sec Duration of Erase Operation (Parameter) (1) tWHQV3 0.3 0.3 0.3 0.3 Sec Duration of Erase Operation (Main) (1) tWHQV4 0.6 0.6 0.6 0.6 Sec tQVVL tQVPH tPHBR 0 0 0 0 nS 0 0 0 0 nS Duration of Word Write Operation VPP Hold from Valid SRD (1) RP VHH Hold from Valid SRD (1) Boot Block Lock Delay (1) (1) (x32) 200 100 100 100 nS Notes: 1. Guaranteed by design, not tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not tested). Aeroflex Circuit Technology 4 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 AC Characteristics – Write/Erase/Program Operations, CE Controlled (TA = -55°C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) +3.3V VCC (2) Symbol Parameter JEDEC Standard +4.5V to +5.5V VCC Typical Units 120nS 80nS 100nS 120nS Min Max Min Max Min Max Min Max Write Cycle Time tAVAV 120 80 100 120 nS RP High Recovery to CE Low tPHEL 1.5 .45 .45 .45 µS WE Setup to CE Going Low Boot Block Unlock Setup to CE Going High (1) tWLEL 0 0 0 0 nS tPHHEH 200 100 100 100 nS tVPEH 200 100 100 100 nS Address Setup to CE Going High tAVEH 90 60 60 60 nS Data Setup to CE Going High tDVEH 70 60 60 60 nS CE Pulse Width tELEH 90 60 60 60 nS V PP Setup to CE Going High (1) Data Hold Time from CE High tEHDX 0 0 0 0 nS Address Hold Time from CE High tEHAX 0 0 0 0 nS WE Hold Time from CE High tEHWH 0 0 0 0 nS CE Pulse Width High tEHEL 20 20 20 20 nS Duration of Word Write Operation (1) Duration of Erase Operation (Boot) (x32) (1) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) V PP Hold from Valid SRD (1) (1) (1) RP VHH Hold from Valid SRD (1) Boot Block Lock Delay (1) tEHQV1 6 6 6 6 µS tEHQV2 0.3 0.3 0.3 0.3 Sec tEHQV3 0.3 0.3 0.3 0.3 Sec tEHQV4 0.6 0.6 0.6 0.6 Sec tQVVL 0 0 0 0 nS tQVPH 0 0 0 0 nS tPHBR 200 100 100 100 nS NOTES: 1. Sampled, but not 100% tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested). AC Characteristics – Read Only Operations (TA = -55°C to +125°C, VCC = +4.5V to + 5.5V(5V Operation), or +3.0V to +3.6V(3.3V Operation), Unless otherwise specified) +3.3V VCC (2) Symbol Parameter JEDEC Standard Read Cycle Time tAVAV +4.5V to +5.5V VCC Typical Units 120nS 80nS Min Max Min Max 120 80 100nS Min Max 100 120nS Min Max 120 nS Address to Output Delay tAVQV 120 80 100 120 nS CE to Output Delay tELQV 120 80 100 120 nS RP to Output Delay tPHQV 1.5 .45 .45 .45 µS OE to Output Delay tGLQV 65 40 40 40 nS 30 nS 30 nS CE to Output in Low Z (1) tELQX CE to Output in High Z (1) tEHQZ OE to Output in Low Z (1) tGLQX OE to Output in High Z (1) tGHQZ Output Hold from Address, CE, or OE Change, Whichever Occurs First (1) 0 0 55 0 0 45 tOH 0 0 30 0 30 0 30 0 0 30 0 nS 0 nS nS Notes: 1. Guaranteed by design, but not tested. 2. Performance at VCC = +4.5V to +5.5V is guaranteed. Performance at VCC = +3.3V is typical (Not Tested). Aeroflex Circuit Technology 5 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 AC Test Circuit Test Configuration Component Values VCC Test Configuration CL (pF) R1 (Ω) R2 (Ω) 3.3V Standard Test 50 990 770 5V Standard Test 50 580 390 R1 Device Under Test NOTES: CL includes jig capacitance. OUT CL R2 Parameter Typical Units Input Pulse Level 0 – 3.0 V 5 nS 1.5 V Input Rise and Fall Input and Output Timing Reference Level AC Waveforms for Write and Erase Operations, WE Controlled VCC Power-up Standby Write Write Program or Valid Address & Data (Program) Erase Setup Command or Erase Confirm Command Automated Program or Erase Delay Read Status Register Data Write Read Array Command V IH Addresses AIN AIN V IL tAVAV tAVWH tWHAX V IH CE V IL tELWL tWHEH V IH OE V IL tWHWL tWHQV1,2,3,4 V IH WE V IL tWLWH tWHDX t DVWH V IH Data V IL High Z tPHWL DIN Valid SRD DIN tPHHWH tQVPH tVPWH tQVVL DIN V HH 6.5V V IH RP V IL V IH WP V IL V PPH2 VPP V PPH1 V PPLK V IL Aeroflex Circuit Technology 6 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 AC Waveforms for Write and Erase Operations, CE Controlled Write Write Program or Valid Address & Data (Program) Erase Setup Command or Erase Confirm Command V CC Power-up Standby Automated Program or Erase Delay Read Status Register Data Write Read Array Command V IH Addresses AIN AIN VIL tAVAV tAVEH tEHAX V IH WE VIL tWLEL tEHWH V IH OE VIL tEHEL tEHQV1,2,3,4 V IH CE VIL tELEH tEHDX tDVEH V IH High Z Data tPHEL VIL DIN Valid SRD DIN tPHHEH tQVPH tVPEH tQVVL DIN V HH 6.5V V IH RP VIL V IH WP VIL V PPH2 VPP V PPH1 V PPLK VIL AC Waveform For Read Operations V IH Standby Device and Address Selection Addresses Outputs Enabled Data Valid Standby Addresses Stable V IL tAVAV V IH CE V IL tEHQZ V IH OE V IL tGHQZ V IH tGLQV WE V IL tELQV tGLQX tELQX V OH Data tOH High Z High Z Valid Output V OL tAVQV V IH tPHQV RP V IL Aeroflex Circuit Technology 7 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 Pin Numbers & Functions 68 Pins — Dual-Cavity CQFP (Standard Configuration) Pin # Function Pin # Function Pin # Function Pin # Function 1 GND 18 GND 35 OE 52 GND 2 CE3 19 I/O8 36 CE2 53 I/O23 3 A5 20 I/O9 37 A17 54 I/O22 4 A4 21 I/O10 38 WP 55 I/O21 5 A3 22 I/O11 39 NC 56 I/O20 6 A2 23 I/O12 40 NC 57 I/O19 7 A1 24 I/O13 41 A18 58 I/O18 8 A0 25 I/O14 42 A19 59 I/O17 9 RP 26 I/O15 43 VPP 60 I/O16 10 I/O0 27 VCC 44 I/O31 61 VCC 11 I/O1 28 A11 45 I/O30 62 A10 12 I/O2 29 A12 46 I/O29 63 A9 13 I/O3 30 A13 47 I/O28 64 A8 14 I/O4 31 A14 48 I/O27 65 A7 15 I/O5 32 A15 49 I/O26 66 A6 16 I/O6 33 A16 50 I/O25 67 WE 17 I/O7 34 CE1 51 I/O24 68 CE4 Consult Factory for Special order (Optional Configuration): Pin 38 - WE2, Pin 39 - WE3, Pin 40 - WE4 and Pin 67 - WE1 "F14" — CQFP Dual-Cavity Flat Package Pin 9 0.990 SQ ±.010 0.940 SQ ±.010 Pin 10 0.180 MAX 0.01R Pin 61 Pin 60 0.015 ±.002 .010 ±.008 .040 .008 +.002 -.001 0.750 Detail “A” Pin 26 Pin 44 Pin 27 0.800 REF Pin 43 See Detail “A” All dimensions in inches Aeroflex Circuit Technology 8 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information Model Number Screening Speed Package ACT–F1M32B–080F14C Commercial (0°C to +70°C) 80 nS CQFP ACT–F1M32B–100F14C Commercial (0°C to +70°C) 100 nS CQFP ACT–F1M32B–120F14C Commercial (0°C to +70°C) 120 nS CQFP ACT–F1M32B–080F14I Industrial (-40°C to +85°C) 80 nS CQFP ACT–F1M32B–100F14I Industrial (-40°C to +85°C) 100 nS CQFP ACT–F1M32B–120F14I Industrial (-40°C to +85°C) 120 nS CQFP ACT–F1M32B–080F14M Military (-55°C to +125°C) 80 nS CQFP ACT–F1M32B–100F14M Military (-55°C to +125°C) 100 nS CQFP ACT–F1M32B–120F14M Military (-55°C to +125°C) 120 nS CQFP ACT–F1M32B–080F14Q DESC Drawing Pending MIL-PRF-38534 Compliant 80 nS CQFP ACT–F1M32B–100F14Q DESC Drawing Pending MIL-PRF-38534 Compliant 100 nS CQFP ACT–F1M32B–120F14Q DESC Drawing Pending MIL-PRF-38534 Compliant 120 nS CQFP Part Number Breakdown ACT– F 1M 32 B– 080 F14 M Aeroflex Circuit Technology Screening Memory Type C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screened * Q = MIL-PRF-38534 Compliant/SMD if applicable S = SRAM F = FLASH EEPROM E = EEPROM D = Dynamic RAM Memory Depth, Locations Package Type & Size Surface Mount Packages F14 = .94" SQ 68 Lead\Dual-Cavity CQFP Memory Width, Bits Pinout Options B = Bottom Boot Block (Standard), T= Top Boot Block (Special Order) * Screened to the individual test methods of MIL-STD-883 Memory Speed, ns (+5V VCC) Specifications subject to change without notice Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: [email protected] 9 SCD1661B REV A 1/16/97 Plainview NY (516) 694-6700