ACT–F512K32 High Speed
16 Megabit FLASH Multichip Module
CIRCUIT TECHNOLOGY
www.aeroflex.com
Features
■ 4 Low Power 512K x 8 FLASH Die in One MCM
■ Industry Standard Pinouts
■ Packaging – Hermetic Ceramic
Package
■ TTL Compatible Inputs and CMOS Outputs
■ Access Times of 60, 70, 90, 120 and 150ns
■ +5V Programing, 5V ±10% Supply
■ 100,000 Erase/Program Cycles
■ Low Standby Current
■ Page Program Operation and Internal Program
Control Time
■ Sector Architecture (Each Die)
● 8 Equal size sectors of 64K bytes each
● Any Combination of Sectors can be erased with
one command sequence
● Supports full chip erase
■ Embedded Erase and Program Algorithms
■ MIL-PRF-38534 Compliant MCMs Available
68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
● 66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
● 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
■ Internal Decoupling Capacitors for Low Noise
Operation
■ Commercial, Industrial and Military Temperature
Ranges
■ DESC SMD# 5962–94612
Released (P3,P7,F5)
●
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4
OE
A0 – A18
512Kx8
512Kx8
512Kx8
512Kx8
8
8
8
8
I/O 0-7
I/O8-15
I/O 16-23
I/O24-31
Pin Description
I/O0-31
Data I/O
A0–18 Address Inputs
WE1-4 Write Enables
CE1-4
Chip Enables
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
General Description
The ACT–F512K32 is a high
speed, 16 megabit CMOS flash
multichip
module
(MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 512K x 32bits, 1M x 16bits
or 2M x 8bits device and is input
TTL
and
output
CMOS
compatible.
The
command
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The
ACT–F512K32
is
packaged in a hermetically
eroflex Circuit Technology - Advanced Multichip Modules © SCD1665 REV B 6/29/01
General Description, Cont’d,
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm
which is an internal algorithm that
automatically preprograms the array, (if it is not
already programmed) before executing the
erase operation. During erase, the device
automatically times the erase pulse widths and
verifies proper cell margin.
Each die in the module or any individual
sector of the die is typically erased and verified
in 1.5 seconds (if already completely
preprogrammed).
Each die also features a sector erase
architecture. The sector mode allows for 64K
byte blocks of memory to be erased and
reprogrammed without affecting other blocks.
The ACT-F512K32 is erased when shipped
from the factory.
The device features single 5.0V power
supply operation for both read and write
functions. lnternally generated and regulated
voltages are provided for the program and
erase operations. A low VCC detector
automatically inhibits write operations on the
loss of power. The end of program or erase is
detected by Data Polling of D7 or by the Toggle
Bit feature on D6. Once the end of a program
or erase cycle has been completed, the device
internally resets to the read mode.
All bits of each die, or all bits within a
sector
of
a
die,
are
erased
via
Fowler-Nordhiem
tunneling.
Bytes
are
programmed one byte at a time by hot electron
injection.
DESC Standard Military Drawing (SMD)
numbers are released.
sealed co-fired ceramic 66 pin, 1.08"SQ PGA
or a 68 lead, .88"SQ Ceramic Gull Wing CQFP
package for operation over the temperature
range of -55°C to +125°C and military
environment.
Each flash memory die is organized as
512KX8 bits and is designed to be
programmed in-system with the standard
system 5.0V Vcc supply. A 12.0V VPP is not
required for write or erase operations. The
MCM can also be reprogrammed with standard
EPROM programmers (with the proper socket).
The standard ACT–F512K32 offers access
times between 60ns and 150ns, allowing
operation of high-speed microprocessors
without wait states. To eliminate bus
contention, the device has separate chip
enable (CE) and write enable (WE). The
ACT-F512K32 is command set compatible with
JEDEC standard
4
Mbit
EEPROMs.
Commands are written to the command
register using standard microprocessor write
timings. Register contents serve as input to an
internal state-machine which controls the
erase and programming circuitry. Write cycles
also internally latch addresses and data
needed for the programming and erase
operations.
Reading data out of the device is similar to
reading from 12.0V Flash or EPROM devices.
The ACT-F512K32 is programmed by
executing the program command sequence.
This will invoke the Embedded Program
Algorithm which is an internal algorithm that
automatically times the program pulse widths
and verifies proper cell margin. Typically, each
sector can be programmed and verified in less
than one second. Erase is accomplished by
Aeroflex Circuit Technology
2
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
z
Absolute Maximum Ratings
Parameter
Symbol
Range
Units
Case Operating Temperature
TC
-55 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Supply Voltage Range
VCC
-2.0 to +7.0
V
Signal Voltage Range (Any Pin Except A9) Note 1
VG
-2.0 to +7.0
V
Maximum Lead Temperature (10 seconds)
-
300
°C
Data Retention
-
10
Years
-
100,000 Minimum
VID
-2.0 to +14.0
Endurance (Write/Erase cycles)
A9 Voltage for sector protect, Note 2
V
Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0v for periods of up to
20ns. Maximum DC voltage on input and I/O pins is VCC + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to
VCC + 2.0V for periods up to 20 ns.
Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.
Normal Operating Conditions
Symbol
Parameter
Minimum
Maximum
A
Units
VCC
Power Supply Voltage
+4.5
+5.5
V
VIH
Input High Voltage
+2.0
VCC + 0.5
V
VIL
Input Low Voltage
-0.5
+0.8
V
TA
Operating Temperature (Military)
-55
+125
°C
VID
A9 Voltage for sector protect
11.5
12.5
V
Capacitance
(V IN= 0V, f = 1MHz, Tc = 25°C)
Symbol
Maximum
Units
A0 – A16 Capacitance
50
pF
COE
OE Capacitance
50
pF
CWE
Write Enable Capacitance
CQFP(F5) Package
20
pF
C AD
Parameter
PGA(P3,P7) Package
20
pF
C CE
Chip Enable Capacitance
20
pF
CI/O
I/O0 – I/O31 Capacitance
20
pF
Parameters Guaranteed but not tested
DC Characteristics – CMOS Compatible
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C, unless otherwise indicated)
Parameter
Input Leakage Current
Output Leakage Current
Active Operating Supply Current for Read (1)
Sym
ILI
Speeds 60, 70, 90, 120 & 150ns
Conditions
Minimum
VCC = 5.5V, ViN = GND to VCC
Maximum
Units
10
µA
ILOX32 VCC = 5.5V, ViN = GND to VCC
10
µA
ICC 1
CE = VIL, OE = VIH, f = 5MHz
190
mA
Active Operating Supply Current for Program or Erase (2)
ICC 2
CE = VIL, OE = VIH
240
mA
Standby Supply Current
ICC 4
VCC = 5.5V, CE = VIH, f = 5MHz
6.5
mA
Static Supply Current (4)
ICC 3
VCC = 5.5V, CE = VIH
0.6
mA
Output Low Voltage
VOL
IOL = +8.0 mA, VCC = 4.5V
0.45
V
Output High Voltage
VOH
IOH = –2.5 mA, VCC = 4.5V
Low Power Supply Lock-Out Voltage (4)
VLKO
4.2
V
V
0.85 x VCC
3.2
Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 5 MHz). The frequency
component typically is less than 2 mA/MHz, with OE at VIN.
Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress.
Note 3. DC Test conditions: VIL = 0.3V, VIH = VCC - 0.3V, unless otherwise indicated
Note 4. Parameter Guaranteed but not tested.
Aeroflex Circuit Technology
3
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol
Parameter
–60
–70
–90
–120
–150
JEDEC Stand’d Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tAVAV
tRC
Address Access Time
tAVQV
tACC
60
60
70
70
90
90
120
120
150
150
Units
ns
ns
Chip Enable Access Time
tELQV
tCE
60
70
90
120
150
ns
Output Enable to Output Valid
tGLQV
tOE
30
35
35
50
55
ns
Chip Enable to Output High Z (1)
tEHQZ
tDF
20
20
20
30
35
ns
Output Enable High to Output High Z (1)
tGHQZ
tDF
20
20
20
30
35
ns
Output Hold from Address, CE or OE Change, Whichever is First
tAXQX
tOH
0
0
0
0
0
ns
Note 1. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, WE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Symbol
Parameter
–60
JEDEC Stand’d Min Max
–70
–90
–120
–150
Min Max
Min Max
Min Max
Min Max
Units
Write Cycle Time
tAVAC
tWC
60
70
90
120
150
ns
Chip Enable Setup Time
tELWL
tCE
0
0
0
0
0
ns
Write Enable Pulse Width
tWLWH
tWP
40
45
45
50
50
ns
Address Setup Time
tAVWL
tAS
0
0
0
0
0
ns
Data Setup Time
tDVWH
tDS
40
45
45
50
50
ns
Data Hold Time
tWHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tWLAX
tAH
45
45
45
50
50
ns
Write Enable Pulse Width High
tWHWL
tWPH
20
20
20
20
20
ns
Duration of Byte Programming
tWHWH1
Sector Erase Time
tWHWH2
Chip Erase Time
tWHWH3
Read Recovery Time before Write (2)
14
14
TYP 14 TYP 14
30
30
120
tGHWL
0
tVCE
Vcc Setup Time (2)
TYP
120
0
50
50
14 TYP
120
0
50
50
TYP
30
120
0
50
Chip Programming Time
30
Sec
120
Sec
0
50
50
µs
30
µs
50
50
µs
50
Sec
Output Enable Setup Time (2)
tOES
0
0
0
0
0
ns
Output Enable Hold Time (1) (2)
tOEH
10
10
10
10
10
ns
Notes: 1. For Toggle and Data Polling. 2. Guaranteed by design, but not tested.
AC Characteristics – Write/Erase/Program Operations, CE Controlled
(Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C)
Parameter
Symbol
–60
JEDEC Stand’d Min Max
–90
–120
–150
Min Max
Min Max
Min Max
70
90
120
150
ns
Units
Write Cycle Time
tAVAC
tWC
Write Enable Setup Time
tWLEL
tWS
0
0
0
0
0
ns
Chip Enable Pulse Width
tELEH
tCP
40
45
45
50
50
ns
Address Setup Time
tAVEL
tAS
0
0
0
0
0
ns
Data Setup Time
tDVEH
tDS
40
45
45
50
50
ns
Data Hold Time
tEHDX
tDH
0
0
0
0
0
ns
Address Hold Time
tELAX
tAH
45
45
45
50
50
ns
tEHEL
tCPH
20
20
20
20
20
Chip Enable Pulse Width High
60
–70
Min Max
14 TYP 14 TYP
14
TYP 14 TYP 14
ns
TYP
µs
Duration of Byte Programming Operation
tWHWH1
Sector Erase Time
tWHWH2
30
30
30
30
30
Sec
Chip Erase Time
tWHWH3
120
120
120
120
120
Sec
50
Sec
Read Recovery Time Before Write (1)
tGHEL
0
0
50
Chip Programming Time
0
50
0
50
0
50
µs
1. Guaranteed by design, but not tested.
Aeroflex Circuit Technology
4
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
If the device is deselected during erasure or
programming, the device will draw active current until the
operation is completed.
Device Operation
The ACT-F512K32 MCM is composed of four, four
megabit Flash chips. The following description is for the
individual flash device, is applicable to each of the four
memory chips inside the MCM. Chip 1 is distinguished by
CE1 and I/O1-7, Chip 2 by CE2 and I/08-15, Chip 3 by CE3
and I/016-23, and Chip 4 by CE4 and I/024-31.
Programming of the ACT-F512K32 is accomplished by
executing the program command sequence.
The
program algorithm, which is an internal algorithm,
automatically times the program pulse widths and verifies
proper cell status. Sectors can be programed and
verified in less than one second. Erase is accomplished
by executing the erase command sequence. The erase
algorithm, which is internal, automatically preprograms
the array if it is not already programed before executing
the erase operation.
During erase, the device
automatically times the erase pulse widths and verifies
proper cell status. The entire memory is typically erased
and verified in 1.5 seconds (if pre-programmed). The
sector mode allows for 64K byte blocks of memory to be
erased and reprogrammed without affecting other blocks.
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the command, along with address and data
information needed to execute the command. The
command register is written by bringing WE to a logic low
level (VIL), while CE is low and OE is at VIH. Addresses
are latched on the falling edge of WE or CE, whichever
happens later. Data is latched on the rising edge of the
WE or CE whichever occurs first.
Standard
microprocessor write timings are used. Refer to AC
Program Characteristics and Waveforms, Figures 3,
8 and 13.
Command Definitions
Bus Operation
Device operations are selected by writing specific
address and data sequences into the command register.
Table 3 defines these register command sequences.
READ
The ACT-F512K32 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output-Enable (OE)
is the output control and should be used to gate data to
the output pins of the chip selected. Figure 7 illustrates
AC read timing waveforms.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for reads
until the command register contents are altered.
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data.
The device will automatically
power-up in the read/reset state. In this case, a
command sequence is not required to read data.
Standard Microprocessor read cycles will retrieve array
data. This default value ensures that no spurious
alteration of the memory content occurs during the power
transition. Refer to the AC Read Characteristics and
Figure 7 for the specific timing parameters.
OUTPUT DISABLE
With Output-Enable at a logic high level (VIH), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The ACT-F512K32 standby mode consumes less than
6.5 mA. In the standby mode the outputs are in a high
impedance state, independent of the OE input.
Table 2 – Sector Addresses Table
Table 1 – Bus Operations
Operation
READ
CE OE WE A0 A1 A6 A9
L
L
H
A0 A1 A6 A9
A16
Address Range
DOUT
SA0
0
0
0
00000h – 0FFFFh
SA1
0
0
1
10000h – 1FFFFh
SA2
0
1
0
20000h – 2FFFFh
SA3
0
1
1
30000h – 3FFFFh
SA4
1
0
0
40000h – 4FFFFh
SA5
1
0
1
50000h – 5FFFFh
SA6
1
1
0
60000h – 6FFFFh
SA7
1
1
1
70000h – 7FFFFh
STANDBY
H
X
X
X
X
X
X
HIGH Z
OUTPUT DISABLE
L
H
H
X
X
X
X
HIGH Z
WRITE
L
H
L
A0 A1 A6 A9
ENABLE SECTOR
PROTECT
L
VID
L
X
X
X
VID
X
VERIFY SECTOR
PROTECT
L
L
H
L
H
L
VID
Code
Aeroflex Circuit Technology
A18 A17
I/O
DIN
5
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
Table 3 — Commands Definitions
Command
Sequence
Bus
Write
Cycles
Required
First Bus Write Second Bus Write Third Bus Write
Cycle
Cycle
Cycle
Addr
Data
Read/Reset
1
XXXH
F0H
Addr
Read/Reset
4
5555H
AAH
2AAAH
Autoselect
4
5555H
AAH
2AAAH
Data
Fourth Bus
Read/Write Cycle
Addr
Data
Addr
Data
55H
5555H
F0H
RA
RD
55H
5555H
90H
Fifth Bus Write Sixth Bus Write
Cycle
Cycle
Addr
Data
Addr
Data
Byte Program
6
5555H
AAH
2AAAH
55H
5555H
A0H
PA
PD
Chip Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
Sector Erase
6
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume
Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
BYTE PROGRAMING
Chip erase does not require the user to program the
Embedded Erase Algorithm (Figure 4) sequence the
device automatically will program and verify the entire
memory for an all zero data pattern prior to electrical
erase. The chip erase is performed sequentially one
sector at a time. Note: Post Erase data state is all "1"s.
The system is not required to provide any controls or
timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to
read the mode. See Figures 4 and 9.
The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever occurs first) begins
programming. Upon executing the Embedded Program
Algorithm command sequence the system is not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin. The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched.
Therefore, the device requires that a valid address to the
device be supplied by the System at this time. Data
Polling must be performed at the memory location which
is being programmed.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a “1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still “0". Only erase operations
can convert “0"s to “1"s.
Figure 3, 8 and 13 illustrates the programming algorithm
using typical command strings and bus operations.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
80µs from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Please note: Do not attempt to write an invalid
command sequence during the sector erase operation.
otherwise, it wili terminate the sector erase operation
and the device will reset back into the read mode.
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command (30H) to addresses in other sectors desired to
be concurrently erased. The time between writes must
be less than 80µs, otherwise that command will not be
accepted. A time-out of 80µs from the rising edge of
the WE pulse for the last sector erase command will
initiate the sector erase.
If another sector erase
command is written within the 80µs time-out window the
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command. Two more"unlock" write cycles are
then followed by the chip erase command.
Aeroflex Circuit Technology
6
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
VIH or WE = VIH. To initiate a write cycle CE and WE
must be logical zero while OE is a logical one.
timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (1 to 8).
Sector erase does not require the user to program the
device prior to erase.
The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is not required to provide any
controls or timings during these operations. Post Erase
data state is all "1"s.
The automatic sector erase begins after the 80µs time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on D7 is “1" at which time the device returns to
read mode. During the execution of the Sector Erase
command, only the Erase Suspend and Erase Resume
commands are allowed. All other commands will reset
the device to read mode. Data Polling must be
performed at an address within any of the sectors being
erased.
POWER-UP WRITE INHIBIT
Power-up of the device with WE = CE = VIL and OE =
VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the
read mode on power-up.
Write Operation Status
D7
DATA POLLING
The ACT-F512K32 features Data Polling as a method to
indicate to the host that the internal algorithms are in
progress or completed. During the program algorithm,
an attempt to read the device will produce compliment
data of the data last written to D7. During the erase
algorithm, an attempt to read the device will produce a
"0" at the D7 Output. Upon completion of the erase
algorithm an attempt to read the device will produce a
"1" at the D7 Output.
For chip Erase, the Data Polling is valid after the rising
edge of the sixth WE pulse in the six write pulse
sequence. For sector erase, the Data Polling is valid
after the last rising edge of the sector erase WE pulse.
Data polling must be performed at a sector address
within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid.
Once the algorithm operation is close to being
completed, data pins (D7) change asynchronously while
the output enable (OE) is asserted low. This means that
the device is driving status information on D7 at one
instance of time and then that byte's valid data at the
next instant of time. Depending on when the system
samples the D7 Output, it may read the status or valid
data. Even if the device has completed internal
algorithm operation and D7 has a valid data, the data
outputs on D0 - D6 may be still invalid. The valid data on
D0 - D7 will be read on the successive read attempts.
The Data Polling feature is only active during the
programming algorithm, erase algorithm, or sector erase
time-out.
See Figures 6 and 10
Data Protection
The ACT-F512K32 is designed to offer protection
against accidental erasure or programming caused by
spurious system level singles that may exist during
power transitions.
During power up the device
automatically resets the internal state machine in the
read mode. Also, with its control register architecture,
alteration of the memory content only occurs after
successful completion of specific multi-bus cycle
command sequences.
The device also incorporates several features to prevent
inadvertent write cycles resulting from Vcc power-up
and power-down transitions or system noise.
LOW Vcc WRITE INHIBIT
To avoid initiation of a write cycle during Vcc power-up
and power-down, a write cycle is locked out for VCC less
than 3.2V (typically 3.7V). If VCC < VLKO, the command
register is disabled and all internal program/erase
circuits are disabled. Under this condition the device will
reset to read mode. Subsequent writes will be ignored
until the Vcc level is greater than VLKO. It is the users
responsibility to ensure that the control pins are logically
correct to prevent unintentional writes when Vcc is
above 3.2V.
D6
TOGGLE BIT
The ACT-F512K32 also features the "Toggle Bit" as a
method to indicate to the host system that algorithms
are in progress or completed.
During a program or erase algorithm cycle, successive
attempts to read data from the device will result in D6
toggling between one and zero. Once the program or
erase algorithm cycle is completed, D6 Will stop toggling
and valid data will be read on successive attempts.
During programming the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four write pulse
sequence. For chip erase the Toggle Bit is valid after the
rising edge of the sixth WE pulse in the six write pulse
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5ns (typical) on OE, CE or
WE will not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding anyone of OE = VIL, CE =
Aeroflex Circuit Technology
7
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
sequence. For Sector erase, the Toggle Bit is valid after
the last rising edge of the sector erase WE pulse. The
Toggle Bit is active during the sector time out.
See Figure 1 and 5.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 with CE and OE at VIL and WE at VIH. Scanning the
sector addresses (A16, A17, and A18) while (A6, A1, A0)
= (0, 1, 0,) will produce a logical "1" code at device
output D0 for a protected sector. Otherwise the device
will read 00H for unprotected sector. In this mode, the
lower order addresses, except for 0, A1, and A6 are don't
care.
It is also possible to verify if a sector is protected during
the sector protection operation. This is done by setting
A6 = CE = OE = VIL and WE = VIH (A9 remains high at
VID). Reading the device at address location XXX2H,
where the higher order addresses (AL8, A17, and A16)
define a particular sector, will produce 01H at data
outputs (D0 - D7) for a protected sector.
D5
EXCEEDED TIMING LIMITS
D5 will indicate if the program or erase time has
exceeded the specified limits. Under these conditions
D5 will produce a "1". The Program or erase cycle was
not successfully completed. Data Polling is the only
operation function of the device under this condition.
The CE circuit will partially power down the device under
these conditions by approximately 8 mA per chip. The
OE and WE pins will control the output disable functions
as shown in Table 1. To reset the device, write the reset
command sequence to the device. This allows the
system to continue to use the other active sectors in the
device.
SECTOR UNPROTECT
The ACT-F512K32 also features a sector unprotect
mode, so that a protected sector may be unprotected to
incorporate any changes in the code. All sectors should
be protected prior to unprotecting any sector.
To activate this mode, the programming equipment must
force Vid on control pins OE, CE, and address pin A9.
The address pins A6, A16, and A12 should be set to VIH.
The unprotection mechanism begins on the falling edge
of the WE pulse and is terminated with the rising edge of
the same.
It is also possible to determine if a sector is unprotected
in the system by writing the autoselect command and A6
is set at VIH. Performing a read operation at address
location XXX2H, where the higher order addresses (A18,
A17, and A16) define a particular sector address, will
produce 00H at data outputs (D0-D7) for an unprotected
sector.
D3
SECTOR ERASE TIMER
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. D3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, D3 may be
used to determine if the sector erase timer window is still
open. If D3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If D3 is low ("0"), the device will accept
additional sector erase commands. To ensure the
command has been accepted, the software should
check the status of D3 prior to and following each
subsequent sector erase command. If D3 were high on
the second status check, the command may not have
been accepted. See Table 4
Sector Protection
Algorithims
SECTOR PROTECTION
The ACT-F512K32 features hardware sector protection
which will disable both program and erase operations to
an individual sector or any group of sectors. To activate
this mode, the programming equipment must force VID
on control pin OE and address pin A9. The sector
addresses should be set using higher address lines A18,
A17, and A16. The protection mechanism begins on the
falling edge of the WE pulse and is terminated with the
rising edge of the same.
Aeroflex Circuit Technology
8
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
Table 4 — Hardware Sequence Flags
In Progress
Status
D7
D6
Auto-Programming
D7
Toggle
0
0
0
Toggle
0
1
D7
Toggle
1
1
0
Toggle
1
1
Programming in Auto Erase
Exceeding Time Limits
Auto-Programming
Programming in Auto Erase
D 5 D3
D2 – D0
D
D
Figure 1
AC Waveforms for Toggle Bit During Embedded Algorithm Operations
A
CE
tOEH
WE
tOES
OE
Data
D0-D7
D6=Toggle
D6=Toggle
D6
Stop Toggle
D0-D7
Valid
tOE
Figure 2
AC Test Circuit
Current Source
IOL
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
CL =
50 pF
Parameter
Typical
Input Pulse Level
0 – 3.0
V
5
ns
Input Rise and Fall
IOH
Units
Input and Output Timing Reference Level
1.5
V
Output Lead Capacitance
50
pF
Current Source
Notes:
1) V Z is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical
resistance load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
9
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 3
Programming Algorithm
Bus
Operations
Command
Sequence
Comments
Program
Valid Address/Data Sequence
Standby
Write
Read
Data Polling to Verify Programming
Standby
Compare Data Output to Data Expected
Start
Write Program Command Sequence
(See Below)
A
Data Poll Device
Increment
Address
No
Last Address
?
Yes
Programming Complete
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Programming Address/Program Data
Aeroflex Circuit Technology
10
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Bus
Operations
Figure 4
Erase Algorithm
Command
Sequence
Comments
Standby
Write
Erase
Read
Data Polling to Verify Erasure
Standby
Compare Output to FFH
Start
Write Erase Command Sequence
(See Below)
A
Data Poll or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command)
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command)
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Sector Address/30H
Additional Sector
Erase Commands
are Optional
Sector Address/30H
Aeroflex Circuit Technology
11
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 5
Toggle Bit Algorithm
Figure 6
Data Polling Algorithm
Start
Read Byte
D0-D7
Address = VA
D6 = Toggle
?
Start
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
Read Byte
D0-D7
Address = VA
No
D7 = Data
?
No
D5 = 1
?
D5 = 1
?
Yes
Yes
Read Byte
D0-D7
Address = VA
D7 =
Toggle?
(Note 1)
No
Pass
No
Fail
Yes
Pass
Fail
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Aeroflex Circuit Technology
A
Yes
Read Byte
D0-D7
Address = VA
D6 =
Toggle?
(Note 1)
Yes
No
Yes
No
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
Note 1. D7 is rechecked even if D 5 = "1" because D7 may change
simultaneously with D5.
12
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 7
AC Waveforms for Read Operations
tRC
Addresses
Addresses Stable
tACC
CE
tDF
OE
tOE
WE
tCE
tOH
High Z
Outputs
Output Valid
A
High Z
Figure 8
Write/Erase/Program
Operation, WE Controlled
Data Polling
Addresses
5555H
PA
PA
tWC
tAS
tRC
tAH
CE
tGHWL
OE
tWP
tWHWH1
tWPH
WE
tCE
tDF
tOE
tDH
AOH
Data
D7
PD
DOUT
tDS
t OH
5.0V
tCE
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the deviced.
4. Dout is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Aeroflex Circuit Technology
13
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 9
AC Waveforms Chip/Sector
Erase Operations
Data Polling
tAH
5555H
Addresses
2AAAH
5555H
5555H
2AAAH
SA
tAS
CE
tGHWL
OE
tWP
WE
tCE
tWPH
tDH
A
AAH
Data
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCE
Notes:
1. SA is the sector address for sector erase.
Figure 10
AC Waveforms for Data Polling
During Embedded Algorithm Operations
tCH
CE
tDF
tOE
OE
tOEH
tCE
WE
tOH
*
DQ7
DQ7
DQ7=
Valid Data
High Z
t WHWH1 or 2
DQ0-DQ6
DQ0–DQ6
Valid Data
DQ0–DQ6=Invalid
tOE
* DQ7=Valid Data (The device has completed the Embedded operation).
Aeroflex Circuit Technology
14
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 11
Sector Protection Algorithm
Start
Set Up Sector Address
(A18, A17, A16)
PLSCNT = 1
OE = VID
A9 = V ID, CE = VIL
A
Activate WE Pulse
Time Out 100µs
Increment
PLSCNT
Power Down OE
WE = V IH
CE = OE = VIL
A9 Should Remain VID
Read From Sector
Address = SA, A0 = 0, A1 = 1, A6 = 0
No
No
Data = 01H
?
PLSCNT = 25?
Yes
Yes
Device Failure
Protect
Another
Sector?
Yes
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
Aeroflex Circuit Technology
15
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 12
Sector Unprotect Algorithm
Start
Protect All Sectors
Verify 98403/98406
Device Code
PLSCNT = 1
Set Up Sector Address
Unprotected Mode
(A5 = VIH, A9 = V IL)
A
Set OE = VID OR VSP
WE = VSP
Activate CE Pulse
Increment
PLSCNT
Time Out 5 mS
Set OE = VIL, WE = VIH
A6 = VIH, A9 = VID OR VSP
Setup Sector Address SA0
Set A1, A0 = 1, 0
CE = VIL
Read Data
From Device
No
Increment
Sector Address
No
Data = 00H
?
Yes
No
Sector
Address = SA7
?
PLSCNT = 1000
?
Yes
Device Failure
Yes
Notes:
SA0 = Sector Address for initial sector
SA7 = Sector Address for last sector
Please refer to Table 2 for details
Remove VID OR VSP from A9
Sector Unprotect
Completed
Aeroflex Circuit Technology
16
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Figure 13
Alternate CE Controlled Programming Operation Timings
Data Polling
Addresses
5555H
PA
PA
t WC
tAS
tAH
WE
t GHEL
OE
tCP
CE
tWHWH1
t CPH
tWS
tDH
AOH
Data
A
D7
PD
DOUT
tDS
5.0V
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the 0utput of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
Aeroflex Circuit Technology
17
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Pin Numbers & Functions
66 Pins — PGA
Pin#
Function
Pin#
Function
Pin#
Function
Pin#
Function
1
I/O8
18
A15
35
I/O25
52
WE3
2
I/O9
19
Vcc
36
I/O26
53
CE3
3
I/O10
20
CE1
37
A7
54
GND
4
A14
21
NC
38
A12
55
I/O19
5
A16
22
I/O3
39
NC
56
I/O31
6
A11
23
I/O15
40
A13
57
I/O30
7
A0
24
I/O14
41
A8
58
I/O29
8
A18
25
I/O13
42
I/O16
59
I/O28
9
I/O0
26
I/O12
43
I/O17
60
A1
10
I/O1
27
OE
44
I/O18
61
A2
11
I/O2
28
A17
45
VCC
62
A3
12
WE2
29
WE1
46
CE4
63
I/O23
13
CE2
30
I/O7
47
WE4
64
I/O22
14
GND
31
I/O6
48
I/O27
65
I/O21
15
I/O11
32
I/O5
49
A4
66
I/O20
16
A10
33
I/O4
50
A5
17
A9
34
I/O24
51
A6
A
"P3" — 1.08" SQ PGA Type (without shoulder) Package
"P7" — 1.08" SQ PGA Type (with shoulder) Package
Bottom View (P7 & P3)
Side View
(P7)
Side View
(P3)
1.085 SQ
MAX
1.000
.185
MAX
.600
.025
.035
Pin 56
.050
1.030
1.040
.100
Pin 1
1.030
1.040
.100
.020
.016
1.000
.020
.016
Pin 66
.180
TYP
Pin 11
.180
TYP
.100
.160
MAX
All dimensions in inches
Aeroflex Circuit Technology
18
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
Pin Numbers & Functions
68 Pins — CQFP Package
Pin#
Function
Pin#
Function
Pin#
Function
Pin#
Function
1
GND
18
GND
35
OE
52
GND
2
CE3
19
I/O8
36
CE2
53
I/O23
3
A5
20
I/O9
37
A17
54
I/O22
4
A4
21
I/O10
38
WE2
55
I/O21
5
A3
22
I/O11
39
WE3
56
I/O20
6
A2
23
I/O12
40
WE4
57
I/O19
7
A1
24
I/O13
41
A18
58
I/O18
8
A0
25
I/O14
42
NC
59
I/O17
9
NC
26
I/O15
43
NC
60
I/O16
10
I/O0
27
VCC
44
I/O31
61
VCC
11
I/O1
28
A11
45
I/O30
62
A10
12
I/O2
29
A12
46
I/O29
63
A9
13
I/O3
30
A13
47
I/O28
64
A8
14
I/O4
31
A14
48
I/O27
65
A7
15
I/O5
32
A15
49
I/O26
66
A6
16
I/O6
33
A16
50
I/O25
67
WE1
17
I/O7
34
CE1
51
I/O24
68
CE4
"F5" — Single-Cavity CQFP
Top View
Pin 9
0.990 SQ
±.010
0.880 SQ
±.010
Pin 10
Side View
0.160
MAX
Pin 61
Pin 60
0.010
REF
0.015
±.002
0.946
±.010
.010 R
1°-7°
0.040
Detail “A”
0.050
TYP
Pin 26
Pin 27
0.010
±.005
Pin 44
0.800 REF
Pin 43
See Detail “A”
All dimensions in inches
Aeroflex Circuit Technology
19
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
DESC Drawing Number
Speed
Package
ACT–F512K32N–060P3Q
5962–9461205HXX*
60 ns
PGA
ACT–F512K32N–070P3Q
5962–9461204HXX
70 ns
PGA
ACT–F512K32N–090P3Q
5962–9461203HXX
90 ns
PGA
ACT–F512K32N–120P3Q
5962–9461202HXX
120 ns
PGA
ACT–F512K32N–150P3Q
5962–9461201HXX
150 ns
PGA
ACT–F512K32N–060P7Q
5962–9461205HUX*
60 ns
PGA
ACT–F512K32N–070P7Q
5962–9461204HUX
70 ns
PGA
ACT–F512K32N–090P7Q
5962–9461203HUX
90 ns
PGA
ACT–F512K32N–120P7Q
5962–9461202HUX
120 ns
PGA
ACT–F512K32N–150P7Q
5962–9461201HUX
150 ns
PGA
ACT–F512K32N–060F5Q
5962–9461205HMX*
60 ns
CQFP
ACT–F512K32N–070F5Q
5962–9461204HMX
70 ns
CQFP
ACT–F512K32N–090F5Q
5962–9461203HMX
90 ns
CQFP
ACT–F512K32N–120F5Q
5962–9461202HMX
120 ns
CQFP
ACT–F512K32N–150F5Q
5962–9461201HMX
150 ns
CQFP
* Pending
Part Number Breakdown
ACT– F 512K 32 N– 090 F5 Q
Aeroflex Circuit
Technology
Screening
Memory Type
C = Commercial Temp, 0°C to +70°C
I = Industrial Temp, -40°C to +85°C
T = Military Temp, -55°C to +125°C
M = Military Temp, -55°C to +125°C, Screened *
Q = MIL-PRF-38534 Compliant/SMD if applicable
F = FLASH EEPROM
Memory Depth
Memory Width, Bits
Package Type & Size
Surface Mount Packages
Thru-Hole Packages
F5 = .88"SQ 68 Lead
P3 = 1.075"SQ PGA 66 Pins W/O Shoulder
Single-Cavity CQFP
P7 = 1.075"SQ PGA 66 Pins With Shoulder
Options
N = None
* Screened to the individual test methods of MIL-STD-883
Memory Speed, ns
Specification subject to change without notice
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: 1-(800) 843-1553
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11830
Aeroflex Circuit Technology
20
SCD1665 REV B 6/29/01 Plainview NY (516) 694-6700
A