ACT-SF128K32 High Speed 128Kx32 SRAM / 128Kx32 Flash Multichip Module CIRCUIT TECHNOLOGY FLASH MEMORY FEATURES ■ Sector Architecture (Each Die) ●8 Equal Sectors of 16K bytes each combination of sectors can be erased with one command sequence. ● Any +5V Programing, +5V Supply ■ Embedded Erase and Program Algorithms ■ Hardware and Software Write Protection ■ Page Program Operation and Internal Program Control Time. ■ 10,000 Erase/Program Cycles 66–Lead, PGA-Type, 1.385"SQ x 0.245"max, Aeroflex code# P3,P7 without/with shoulders C F LE X LA ISO 9001 E I NC . A E RO ■ S ● www.aeroflex.com B FEATURES ■ 4 – 128K x 8 SRAMs & 4 – 128K x 8 Flash Die in One MCM ■ Access Times of 25ns (SRAM) and 60ns (Flash) or 35ns (SRAM) and 70ns or 90ns (Flash) ■ Organized as 128K x 32 of SRAM and 128K x 32 of Flash Memory with Common Data Bus ■ Low Power CMOS ■ Input and Output TTL Compatible Design ■ MIL-PRF-38534 Compliant MCMs Available ■ Decoupling Capacitors and Multiple Grounds for Low Noise ■ Commercial, Industrial and Military Temperature Ranges ■ Industry Standard Pinouts ■ TTL Compatible Inputs and Outputs ■ Packaging – Hermetic Ceramic RTIFIE D Block Diagram – PGA Type Package (P3 & P7) FWE1 SWE1 FWE2 SWE2 FWE3 SWE3 FWE4 SWE4 OE A0–A16 SCE FCS PIN DESCRIPTION I/O0-31 Data I/O A0–16 Address Inputs FWE1-4 Flash Write Enables SWE1-4 SRAM Write Enables 128K X 8 FLASH 128K X 8 SRAM I/O0-7 128K X 8 FLASH 128K X 8 SRAM I/O8-15 128K X 8 FLASH 128K X 8 SRAM I/O16-23 128K X 8 FLASH 128K X 8 SRAM FCE Flash Chip Enable SCE SRAM Chip Enable OE Output Enable NC Not Connected VCC Power Supply GND Ground I/O24-31 eroflex Circuit Technology - Advanced Multichip Modules © SCD3850 REV A 5/20/98 Absolute Maximum Ratings Symbol Rating TC TSTG Range Units Operating Temperature -55 to +125 °C Storage Temperature -65 to +150 °C -0.5 to +7 V 300 °C VG Maximum Signal Voltage to Ground TL Maximum Lead Temperature (10 seconds) Parameter Flash Data Retention 10 Years Flash Endurance (Write/Erase Cycles) 10,000 Normal Operating Conditions Symbol Parameter Minimum Maximum Units VCC Power Supply Voltage +4.5 +5.5 V VIH Input High Voltage +2.2 VCC + 0.3 V VIL Input Low Voltage -0.5 +0.8 V Capacitance (VIN = 0V, f = 1MHz, TC = 25°C) Symbol Parameter Maximum Units A0 – A18 Capacitance 80 pF OE Capacitance 80 pF CWE1-4 F/S Write Enable Capacitance 30 pF CCE F/S Chip Enable Capacitance 50 pF CI/O I/O0 – I/O31 Capacitance 30 pF CAD COE This parameter is guaranteed by design but not tested DC Characteristics (VCC = 5.0V, VSS = 0V, TC = -55°C to +125°C) Parameter Sym Conditions Min Max Units Input Leakage Current ILI VCC = Max, VIN = 0 to VCC 10 µA Output Leakage Current ILO FCE = SCE = VIH, OE = VIH, VOUT = 0 to VCC 10 µA 550 mA SRAM Operating Supply Current x 32 I x32 SCE = VIL, OE = VIH, f = 5MHz, VCC = CC Max, FCE = VIH Mode Standby Current ISB FCE = SCE = VIH, OE = VIH, f = 5MHz, VCC = Max 80 mA SRAM Output Low Voltage VOL IOL = 8 mA, VCC = Min, FCE = VIH 0.4 V SRAM Output High Voltage VOH IOH = -4.0 mA, , VCC = Min, FCE = VIH Flash Vcc Active Current for Read (1) ICC1 FCE = VIL, OE = VIH, SCE = VIH 220 mA Flash Vcc Active Current for Program or Erase (2) ICC2 FCE = VIL, OE = VIH, SCE = VIH 280 mA Flash Output Low Voltage VOL IOL = 12 mA, VCC = Min, SCE = VIH 0.45 V Flash Output High Voltage VOH1 IOH = -2.5 mA, , VCC = Min, SCE = VIH Flash Low Vcc Lock Out Voltage VLKO 2.4 V 0.85 x VCC 3.2 V 4.2 V Notes: 1) The ICC current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less than 2mA/MHz, with OE at VIH 2) ICC active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V Aeroflex Circuit Technology 2 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 SRAM AC Characteristics (VCC = 5.0V, VSS= 0V, TC = -55°C to +125°C) Read Cycle Parameter Symbol –025 Min Max –035 Min Max 25 35 Units ns Read Cycle Time tRC Address Access Time tAA 25 35 ns Chip Select Access Time tACE 25 35 ns Output Hold from Address Change tOH Output Enable to Output Valid tOE Chip Select to Output in Low Z * tCLZ 3 3 ns Output Enable to Output in Low Z * tOLZ 0 0 ns Chip Deselect to Output in High Z * tCHZ 12 20 ns Output Disable to Output in High Z * tOHZ 12 20 ns –025 Min Max –035 Min Max 0 0 15 ns 20 ns * Parameters guaranteed by design but not tested Write Cycle Parameter Symbol Units Write Cycle Time tWC 25 35 ns Chip Select to End of Write tCW 20 25 ns Address Valid to End of Write tAW 20 25 ns Data Valid to End of Write tDW 15 20 ns Write Pulse Width tWP 20 25 ns Address Setup Time tAS 0 0 ns Output Active from End of Write * tOW 0 0 ns Write to Output in High Z * tWHZ Data Hold from Write Time tDH 0 0 ns Address Hold Time tAH 0 0 ns 10 20 ns * Parameters guaranteed by design but not tested SRAM Truth Table Mode SCE OE SWE Data I/O Power Standby H X X High Z Standby Read L L H Data Out Active Output Disable L H H High Z Active Write L X L Data In Active Aeroflex Circuit Technology 3 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 Timing Diagrams — SRAM Write Cycle Timing Diagrams Read Cycle Timing Diagrams Write Cycle (SWE Controlled, OE = VIH) Read Cycle 1 (SCE = OE = VIL, SWE = VIH) tWC tRC A0-16 A0-16 tAA tAW tCW tOH DI/O Previous Data Valid tAH SCE Data Valid tAS tWP SWE tWHZ tOW tDH tDW SEE NOTE DI/O Data Valid Read Cycle 2 (SWE = VIH) tRC Write Cycle (SCE Controlled, OE = VIH ) A0-16 tWC tAA A0-16 tAH tAW SCE tACE tAS tCHZ tCLZ SEE NOTE SCE tOHZ SWE tCW SEE NOTE OE tWP tOE SEE NOTE tOLZ SEE NOTE DI/O tDW Data Valid High Z DI/O Data Valid Note: Guaranteed by design, but not tested. DON’T CARE UNDEFINED tDH AC Test Circuit Current Source AC Test Conditions IOL VZ ~ 1.5 V (Bipolar Supply) To Device Under Test CL = 50 pF Parameter Typical Units Input Pulse Level 0 – 3.0 V Input Rise and Fall 5 ns Input and Output Timing Reference Level 1.5 V IOH Current Source Notes: 1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology 4 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 Flash AC Characteristics – Read Only Operations (Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Symbol –60 –70 –90 Units JEDEC Stand’d Min Max Min Max Min Max Parameter Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC 60 60 70 70 90 90 ns ns Chip Enable Access Time tELQV tCE 60 70 90 ns Output Enable to Output Valid tGLQV tOE 30 35 40 ns Chip Enable to Output High Z (1) tEHQZ tDF 20 20 25 ns Output Enable High to Output High Z(1) tGHQZ tDF 20 20 25 ns Output Hold from Address, CE or OE Change, Whichever is First tAXQX tOH 0 0 0 ns Note 1. Guaranteed by design, but not tested Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled (Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Parameter Symbol JEDEC Stand’d –60 –70 –90 Min Max Min Max Min Max Units Write Cycle Time tAVAC tWC 60 70 90 ns Chip Enable Setup Time tELWL tCE 0 0 0 ns Write Enable Pulse Width tWLWH tWP 30 35 45 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 30 30 45 ns Data Hold Time tWHDX tDH 0 0 0 ns Address Hold Time tWLAX tAH 45 45 45 ns Chip Enable Hold Time tWHEH tCH 0 0 0 ns Write Enable Pulse Width High tWHWL tWPH 20 Duration of Byte Programming Operation tWHWH1 Sector Erase Time tWHWH2 Chip Erase Time tWHWH3 Read Recovery Time before Write 14 20 TYP 14 60 Vcc Setup Time tVCE Output Enable Setup Time tOES Output Enable Hold Time1 tOEH 14 60 120 tGHWL 20 TYP 120 0 0 0 50 50 50 12.5 10 12.5 10 ns TYP µs 60 Sec 120 Sec µs µs 12.5 10 Sec ns Note: 1. For Toggle and Data Polling. Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled (Vcc = 5.0V, Vss = 0V, TC = -55°C to +125°C) Parameter Symbol JEDEC Stand’d –60 –70 –90 Min Max Min Max Min Max Units Write Cycle Time tAVAC tWC 60 70 90 ns Write Enable Setup Time tWLEL tWS 0 0 0 ns Chip Enable Pulse Width tELEH tCP 35 35 50 ns Address Setup Time tAVEL tAS 0 0 0 ns Data Setup Time tDVEH tDS 30 30 50 ns Data Hold Time tEHDX tDH 0 0 0 ns Address Hold Time tELAX tAH 45 45 50 ns Write Enable Hold from Write Enable High tEHWH tWH 0 0 0 ns Chip Enable Pulse Width High tEHEL tCPH 20 Duration of Byte Programming tWHWH1 Sector Erase Time tWHWH2 Chip Erase Time tWHWH3 Read Recovery Time tGHEL Chip Programming Time Aeroflex Circuit Technology 14 20 TYP 60 20 TYP 14 60 120 0 120 0 12.5 5 14 ns TYP µs 60 Sec 120 Sec 12.5 Sec 0 12.5 SCD3850 REV A 5/20/98 ns Plainview NY (516) 694-6700 AC Waveforms for Flash Memory Read Operations tRC Addresses Addresses Stable tACC FCE tDF OE tOE FWE tCE tOH High Z Outputs Output Valid High Z Write/Erase/Program Operation for Flash Memory, FWE Controlled Data Polling Addresses 5555H PA tWC tAS PA tRC tAH FCE tGHWL OE tWP tWHWH1 tWPH FWE tCE tDF tOE tDH AOH Data PD D7 DOUT tDS tOH 5.0V tCE Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 6 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 AC Waveforms Chip/Sector Erase Operations for Flash Memory Data Polling tAH 5555H Addresses 2AAAH 5555H 5555H 2AAAH SA tAS FCE tGHWL OE tWP FWE tCE tWPH tDH AAH Data 55H 80H AAH 55H 10H/30H tDS VCC tVCE Notes: 1. SA is the sector address for sector erase. AC Waveforms for Data Polling During Embedded Algorithm Operations for Flash Memory tCH FCE tDF tOE OE tOEH tCE FWE tOH * DQ7 DQ7 DQ7= Valid Data High Z tWHWH1 or 2 DQ0-DQ6 DQ0–DQ6 Valid Data DQ0–DQ6=Invalid tOE * DQ7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 7 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 Write/Erase/Program Operation for Flash Memory, FCE Controlled Data Polling Addresses 5555H PA tWC tAS PA tAH FCE tGHWL OE tCP FWE tWHWH1 tCPH tWS tDH AOH Data PD D7 DOUT tDS 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the 0utput of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 8 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 Pin Numbers & Functions 66 Pins — PGA-Type Pin # Function Pin # Function Pin # Function Pin # Function 1 I/O8 18 A15 35 I/O25 52 FWE3 2 I/O9 19 Vcc 36 I/O26 53 SWE3 3 I/O10 20 FCE 37 A7 54 GND 4 A14 21 SCE 38 A12 55 I/O19 5 A16 22 I/O3 39 SWE1 56 I/O31 6 A11 23 I/O15 40 A13 57 I/O30 7 A0 24 I/O14 41 A8 58 I/O29 8 NC 25 I/O13 42 I/O16 59 I/O28 9 I/O0 26 I/O12 43 I/O17 60 A1 10 I/O1 27 OE 44 I/O18 61 A2 11 I/O2 28 NC 45 VCC 62 A3 12 FWE2 29 FWE1 46 SWE4 63 I/O23 13 SCE2 30 I/O7 47 FWE4 64 I/O22 14 GND 31 I/O6 48 I/O27 65 I/O21 15 I/O11 32 I/O5 49 A4 66 I/O20 16 A10 33 I/O4 50 A5 17 A9 34 I/O24 51 A6 "P3" — 1.08" SQ PGA Type Package Standard (without shoulders) "P7" — 1.08" SQ PGA Type Package (with shoulders on Pins 1, 11, 56 & 66) Bottom View (P7 & P3) Side View (P7) Side View (P3) 1.085 SQ MAX 1.000 TYP .600 TYP .185 MAX .025 .035 Pin 1 Pin 56 .050 DIA TYP .100 TYP .100 TYP .020 .016 .020 .016 1.000 TYP Pin 66 Pin 11 .145 MIN .165 MIN .100 TYP .160 MAX All dimensions in inches Aeroflex Circuit Technology 9 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700 CIRCUIT TECHNOLOGY Ordering Information Model Number DESC Part Number Speed Package ACT-SF128K32N–26P1X TBD 25(S) / 60(F) ns 1.08"sq PGA-Type ACT-SF128K32N–37P1X TBD 35(S) / 70(F) ns 1.08"sq PGA-Type ACT-SF128K32N–39P1X TBD 35(S) / 90(F) ns 1.08"sq PGA-Type Note: (S) = Speed for SRAM, (F) = Speed for FLASH Part Number Breakdown ACT– SF 128K 32 N– 26 P1 M Aeroflex Circuit Technology Memory Type SF = SRAM Flash Combo Module Screening C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C Screened * Q = MIL-PRF-38534 Compliant/SMD Memory Depth, Locations Memory Width, Bits Package Types & Sizes Pinout Options N = none Thru-Hole Packages P3 = 1.08"SQ PGA 66 Pins WO/Shoulder P7 = 1.08"SQ PGA 66 Pins W/Shoulder Memory Speed (Code) 26 = 25ns SRAM / 60ns FLASH 37 = 35ns SRAM / 70ns FLASH 39 = 35ns SRAM / 90ns FLASH * Screened to the individual test methods of MIL-STD-883 Specifications subject to change without notice. Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Aeroflex Circuit Technology 10 SCD3850 REV A 5/20/98 Plainview NY (516) 694-6700