a FEATURES Programmable Sinusoidal Oscillator Synthesized Synchronous Reference Output Programmable Output Frequency Range: 2 kHz–20 kHz “Loss-of-Signal” Indicator 20-Pin PLCC Package Low Cost APPLICATIONS Excitation Source for: Resolvers Synchros LVDTs RVDTs Pressure Transducers Load Cells AC Bridges GENERAL DESCRIPTION The AD2S99 programmable sinusoidal oscillator provides sine wave excitation for resolvers and a wide variety of ac transducers. The AD2S99 also provides a synchronous reference output signal (3 V p-p square wave) that is phase locked to its SIN and COS inputs. In an application, the SIN and COS inputs are connected to the transducer’s secondary windings. The synchronous reference output compensates for temperature and cabling dependent phase shifts and eliminates the need for external preset phase compensation circuits. The synchronous reference output can be used as a zero crossing reference for resolver-to-digital converters such as Analog Devices’ AD2S80A, AD2S82A, AD2S83 and AD2S90. The AD2S99 is packaged in a 20-pin PLCC and operates over –40°C to +85°C. Programmable Oscillator AD2S99 FUNCTIONAL BLOCK DIAGRAM PUSH/ PULL O/P STAGE EXC EXC TO TRANSDUCER FBIAS SEL1 FREQUENCY SELECT SINE WAVE GENERATOR SEL2 AD2S99 SYNREF SYNCHRONOUS REFERENCE PHASE DETECT LOGIC SIN LOS COS FROM TRANSDUCER PRODUCT HIGHLIGHTS Dynamic Phase Compensation The AD2S99 dynamically compensates for any phase variation in a transducer by phase locking its synchronous reference output to the transducer’s secondary windings. Programmable Excitation Frequency The excitation frequency is easily programmed to 2 kHz, 5 kHz, 10 kHz, or 20 kHz by using the frequency select pins. Intermediate frequencies are available by adding an external resistor. Signal Loss Detection The AD2S99 has the ability to detect if both the transducer secondary winding connections become disconnected from its SIN and COS inputs. The “LOS” output pin pulls high when a signal loss is detected. Integration The AD2S99 integrates the transducer excitation, synchronous reference, and loss of signal detection functions into a small, cost effective package. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD2S99–SPECIFICATIONS (V = 64.75 V to 65.25 V @ –408C to +858C unless otherwise noted) S Parameter Min FREQUENCY OUTPUT RANGE 2 kHz 5 kHz 10 kHz 20 kHz Typ Max ±3 Amplitude ±3 Power Supply Rejection Ratio 2 ±3 Capacitive Drive Total Harmonic Distortion EXC, EXC POWER SUPPLIES VDD VSS Quiescent Current IDD, ISS TEMPERATURE RANGE Operating Storage SEL1 VSS VSS GND GND ± 10 ± 20 ±5 ± 10 % % % % AP Grade @ +25°C AP Grade –40°C to +85°C BP Grade @ +25°C BP Grade –40°C to +85°C ± 10 ± 20 ±5 ± 10 % % % % V p-p/V AP Grade @ +25°C AP Grade –40°C to +85°C BP Grade @ +25°C BP Grade –40°C to +85°C Output Variation as Function of Change in Power Supply Voltage ± 200 V rms V p-p mV EXC to GND, EXC to GND Square Wave 8 mA rms RLOAD = 500 Ω EXC to EXC CLOAD = 1000 pF 1000 pF –25 1.8 –45 2.0 2.2 +45 V rms Degrees ± 10 ± 10 Degrees Degrees AGND V dc 0.7 V dc V dc 0.6 0.8 V rms ±8 +5.25 –5.25 ± 15 V dc V dc mA +85 +150 °C °C VDD 0.5 +4.75 –4.75 SEL2 VSS GND VSS GND dB VSS LOS OUTPUT Output Low Voltage Output High Voltage SIN, COS LOS Threshold Hz Hz Hz Hz 0.002 ANALOG OUTPUTS Amplitude EXC, EXC SYNREF SYNREF OFFSET Current Drive Capability EXC, EXC VS = ± 5 V FREQUENCY SELECT INPUTS SEL1, SEL21 Test Conditions 2000 5000 10000 20000 ACCURACY Frequency ANALOG INPUTS SIN, COS Amplitude Phase Lock Range Additional Phase Delay Units –40 –65 AP Grade BP Grade IOL = 400 µA 50 kΩ Pull Up to VDD (Open Drain Output) No Load NOTES 1 Frequency select pins SEL1 and SEL2 must be connected to appropriate voltage levels before power is applied. Specifications subject to change without notice. –2– REV. B AD2S99 PIN DESIGNATIONS ABSOLUTE MAXIMUM RATINGS* VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V Operating Temperature . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Analog Input Voltages (SIN and COS) . . . . . . . . . VSS – 0.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to VDD + 0.3 V Frequency Select (SEL1, SEL2) . . . . . . . . . . . . . . VSS – 0.4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND + 0.4 V *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Power Supply Voltage (VDD to VSS) . . . . . . ± 4.75 V to ± 5.25 V Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ± 10% Frequency Select (SEL1 and SEL2) . . . . . . . . . VSS to AGND Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C ORDERING GUIDE VDD AGND EXC EXC VSS VSS NOTES 1 Pins 6 and 16 must be connected together. 2 Pins 19 and 20 must be connected together. 3 Resolver Reference two (EXC) is 180° phase advanced with respect to Resolver Reference one (EXC). 3 2 1 20 19 NC 4 SIN 5 AD2S99 DGND 6 COS 7 TOP VIEW (Not to Scale) NC 8 VSS SEL2 VSS PIN CONFIGURATION 18 EXC 17 EXC 16 AGND 15 NC 14 NC 9 10 11 12 13 NC *P = PLCC. VDD P-20A P-20A 12 161 17 18 192 202 Frequency Select 2 Frequency Select 1 External Frequency Adjust Pin Resolver Output SIN Digital Ground Resolver Output COS Synthesized Reference Output Indicates When Both the SIN and COS Are Below the Threshold. Positive Power Supply Analog Ground Resolver Reference One Resolver Reference Two3 Negative Power Supply Negative Power Supply LOS –40°C to +85°C –40°C to +85°C SEL2 SEL1 FBIAS SIN DGND COS SYNREF LOS FBIAS AD2S99AP AD2S99BP 1 2 3 5 61 7 10 11 SEL1 Package Option* Description NC Temperature Range Mnemonic SYNREF Model Pin No. NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S99 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– WARNING! ESD SENSITIVE DEVICE AD2S99 CONNECTING THE AD2S99 OSCILLATOR 20 Refer to Figure 1. Positive supply voltage VDD should be connected to Pin 12 and negative supply voltage VSS should be connected to both Pins 19 and 20. Reversal of these power supplies will destroy the device. The appropriate voltage level for the power supplies is ± 5 V dc ± 5%. Both VSS Pins (19 and 20) must be connected together, and Digital Ground (Pin 6) must be connected to Analog Ground (Pin 16) locally at the AD2S99. 18 FREQUENCY – kHz 16 VSS NC 16 EXC VSS 15 NC 14 NC NC SYNREF REF NC = NO CONNECT 8 12 16 20 24 ADDITIONAL RESISTANCE – kΩ RESISTOR PULLUP TO VDD FROM FBIAS 28 AD2S99 OSCILLATOR OUTPUT STAGE COS The output of the AD2S99 oscillator consists of two sinusoidal signals, EXC, and EXC. EXC is 180° phase advanced with respect to EXC. The excitation winding of a transducer should be connected across EXC (Pin 17) and EXC (Pin 18). 11 12 13 4.7µF 0.1µF 4 Figure 2. Typical Added Resistance Value 100nF 50kΩ VDD 6 0 SIN AGND 8 10 8 0 EXC 7 9 .. . RX * VSS 17 AD2S99 10 4 RESOLVER 18 5 12 2 20 19 4 6 0.1µF NC COS 1 VDD SIN DGND 2 LOS NC SEL2 FBIAS 3 SEL1 4.7µF 14 TO AD2S80/ AD2S90 REF INPUT With low impedance transducers, it may be necessary to increase the output current drive of the AD2S99. In such an instance, an external buffer amplifier can be used to provide gain (as needed), and additional current drive for the excitation output (either EXC or EXC) of the AD2S99, providing a single ended drive to the transducer. Refer to Figures 6, 7 and 8 for sample buffer configurations. 100kΩ SEL2 = GND ] –5kHz MODE SEL1 = V SS ] INCREASE RX TO LOWER OUTPUT FREQUENCY (SEE GRAPH) *RX IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES. FIXED FREQUENCIES ONLY REQUIRE A LINK. The amplitude modulated SIN and COS output signals from a resolver should be connected as feedback signals to the AD2S99. The SYNREF output compensates for any primary to secondary phase errors in the resolver. These errors can degrade the accuracy of a Resolver-to-Digital Converter (R/D Converter). Figure 1. Typical Configuration It is recommended that decoupling capacitors are connected in parallel between VDD and Analog Ground and VSS and Analog Ground in close proximity to the AD2S99. The recommended values for the decoupling capacitors are 100 nF (ceramic) and 4.7 µF (tantalum). When multiple AD2S99s are used, separate decoupling capacitors should be used for each AD2S99. SIN, from the resolver, should be connected to the AD2S99 SIN input and COS should be connected to the AD2S99 COS input. The SIN Lo, COS Lo (resolver signal returns) should be connected to AGND and the R/D Converter as applicable. FREQUENCY ADJUSTMENT The output frequency of the AD2S99 is programmable to four standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and SEL2 pins. The output can also be adjusted to provide intermediate frequencies by connecting a resistor from the FBIAS pin to the positive supply VDD. The FBIAS pin is connected directly to VDD during normal operation. A graph showing the typical added resistance values for various intermediate frequencies is provided in Figure 2. The procedure for obtaining an intermediate frequency is: The synthesized reference (SYNREF) from the AD2S99 should be connected to the reference input pin of the R/D Converter. The SYNREF signal is a square wave at the oscillator frequency of amplitude ± 3 V p-p and is phase coherent with the SIN and COS inputs. If this signal is used to drive the reference input of the AD2S90 R/D Converter, a coupling capacitor and resistor to GND must be connected between the SYNREF output of the AD2S99 and the REF input of the R/D Converter (see Figure 3). Please read the appropriate R/D Converter data sheets for further clarification. 1. Set the output frequency via the SEL1, SEL2 pins to the frequency immediately above the required intermediate frequency. LOSS OF SIGNAL 2. Connect the frequency adjust pin FBIAS to VDD via an external resistor. During normal operation when both the SIN and COS signals on the resolver secondary windings are connected to the AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a Logic Lo (<0.7 V). If both the SIN and COS signals on the resolver secondary windings fall below the LOS threshold level of the AD2S99, the LOS pin of the AD2S99 will pull up to a Logic Hi (VDD) level. For example: to obtain an output frequency of 8 kHz, set the nominal output frequency to 10 kHz by connecting SEL1 to GND and SEL2 to VSS. Connect FBIAS to VDD via a 6 kΩ resistor (refer to Figure 2). –4– REV. B AD2S99 shields should also be terminated at the AD2S90 AGND pin. The SYNREF output of the AD2S99 should be connected to the REF input pin of the AD2S90 via a 0.1 µF capacitor with a 100 kΩ resistor to GND. This is to block out any dc offset in the SYNREF signal. For more detailed information please refer to the AD2S90 data sheet. AD2S99/AD2S90 TYPICAL CONFIGURATION Figure 3 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S90 Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S90 should be 2 V rms ± 10%. All the analog ground signals should be star connected to the AD2S90 AGND pin. If shielded twisted pair cables are used for the resolver signals, the VDD VSS 4.7µF NC = NO CONNECT SEL2 = GND SEL1 = VSS FOUT = 5kHz 3 NC 4 SIN 5 DGND 6 COS 7 VSS SEL2 2 VSS SEL1 FBIAS 0.1µF 1 20 19 18 17 AD2S99 16 TOP VIEW (Not to Scale) EXC EXC AGND 15 NC NC 8 14 NC NC VDD LOS NC SYNREF 9 10 11 12 13 50kΩ 0.1µF VDD 4.7µF 0.1µF 100kΩ VDD 18 17 16 15 14 S4 S2 S2 R2 REF COS S4 S3 S3 20 COS 1 AGND RESOLVER S1 2 SIN 3 SIN LO 4 VDD VDD 13 VSS 12 SIN S1 R4 19 REF COS LO 5 DGND 11 AD2S90 10 TOP VIEW (Not to Scale) 9 6 7 8 POWER RETURN Figure 3. AD2S99 and AD2S90 Example Configuration REV. B –5– 0.1µF 4.7µF 0.1µF 4.7µF VSS AD2S99 Coupling capacitor C3, and resistor to GND R3, between the SYNREF output of the AD2S99 and the REF input pin of the AD2S82A are optional. For additional information on selecting component values for the AD2S82A, please refer to the AD2S82A data sheet or the application note “Passive Component Selection and Dynamic Modeling for the AD2S80 Series Resolver-to-Digital Converters” (AN-266). AD2S99/AD2S82A TYPICAL CONFIGURATION Figure 4 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S82A Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S82A should be 2 V rms ± 10%. All the analog ground signals should be star connected to the AD2S82A AGND pin. If shielded twisted pair cables are used for the resolver signals, the shields should also be terminated at the AD2S82A AGND pin. R3, C3 OPTIONAL C3 SYNREF VELOCITY OUTPUT COS C5 R5 R3 COS R2 REF –5V 4.7µF C1 SIN C2 R1 RESOLVER C4 R6 AGND NC VDD LOS NC 10 11 12 13 14 NC SEL1 = GND SEL2 = VSS FOUT = 10kHz VCO I/P DEMOD I/P A GND VCO O/P 35 DATA LOAD AD2S82A 34 COMP DB4 13 TOP VIEW (Not to Scale) 33 SC2 LOS 32 SC1 DIGITAL GND 31 ENABLE BYTE SELECT LSB DB16 DB15 DB14 DB13 DB12 DB11 DB7 16 DB10 DB8 17 DIGITAL OUTPUT DATA 18 19 20 21 22 23 24 25 26 27 28 DGND +VL +5V –12V 36 BUSY DB9 NC = NO CONNECT 4.7µF 38 RC DB3 12 DB5 14 0.1µF 39 10µF –VS 37 DIR DB6 15 50k 0.1µF 44 43 42 41 40 DB2 11 15 NC 9 1 INTEGRATOR I/P 16 NC 9 MSB DB1 10 2 DEMOD O/P TOP VIEW (Not to Scale) EXC 3 INTEGRATOR O/P 17 8 4 REFERENCE I/P AD2S99 +12V 7 5 AC ERROR O/P 18 EXC SIG GND 0.1µF +VS VSS SEL1 10µF 20 19 VSS FBIAS FBIAS 1 SEL2 2 SYNREF NC 8 3 6 SIN I/P COS I/P AGND 0.1µF NC 4 SIN 5 DGND 6 COS 7 AGND 0V R4 SIN 30 INHIBIT 29 NC +5V 0.1µF 10µF Figure 4. AD2S99 and AD2S82A Example Configuration –6– REV. B AD2S99 shields should also be terminated at the AD2S93 AGND pin. The SYNREF output of the AD2S99 cannot be used as the REF input signal for the AD2S93. The zero crossing reference for the AD2S93 should be taken from the primary winding of the LVDT through a phase lead or lag network. The phase compensation network ensures that the REF input is phase coherent with the A and B input signals to the AD2S93. AD2S99/AD2S93 TYPICAL CONFIGURATION Figure 5 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S93 LVDT-to-Digital Converter. The maximum level of the A and B transducer input signals to the AD2S93 should be 1 V rms ± 20%. All the analog ground signals should be star connected to the AD2S93 AGND pin. If shielded twisted pair cables are used for the LVDT signals, the VDD VSS NC = NO CONNECT 3 2 NC 4 SIN 5 DGND 6 COS 7 VSS 1 20 19 18 AD2S99 17 TOP VIEW (Not to Scale) 16 EXC EXC AGND 15 NC NC 8 SEL2 = GND SEL1 = VSS FOUT = 5kHz 4.7µF VSS SEL2 SEL1 FBIAS 0.1µF 14 NC NC VDD NC SYNREF LOS 9 10 11 12 13 VDD 50kΩ 0.1µF LOS 4.7µF C1 C4 R6 C3 C2 R2 R5 B B 18 VDD 17 AGND 2 DIFF DIR 14 3 GAIN NULL 13 4 LOS OVR 12 AD2S93 9 10 11 NC 8 UNR 7 DGND 15 CLKOUT 6 NC TOP VIEW (Not to Scale) 5 DMODOUT VDD 0.1µF 4.7µF 0.1µF 4.7µF VSS 16 A 1 CS A LVDT R7 28 SCLK SEC DATA PRI DMODIN NC INTIN 21 20 19 ACERROR 27 23 22 VGAIN NC 26 REF 25 24 VEL PHASE COMP VSS NC = NO CONNECT Figure 5. AD2S99 and AD2S93 Example Configuration REV. B –7– COS VSS VSS SEL1 NC 8 14 NC 6 7 SSM2142 5 2 8 1 RESOLVER * NC NC VDD LOS 3 9 10 11 12 13 SYNREF NC 15 NC AD2S99 TOP VIEW (Not to Scale) DGND 6 14 NC 9 7 5 NC = NO CONNECT 10 11 12 13 NC = NO CONNECT C1978b–10–6/95 SIN * 4 COS 15 NC NC 8 20 19 NC COS 7 REF +VS 18 EXC EXC 17 AGND 16 SIN 16 AGND TOP VIEW (Not to Scale) 1 VDD AD2S99 2 LOS SIN 5 DGND 6 3 NC 4 VOUT 18 EXC EXC 17 NC 4 SEL2 20 19 FBIAS 1 VOUT = 2VRMS SYNREF 2 VSS SEL1 SEL2 3 VSS FBIAS AD2S99 –VS *OPTIONAL; CONSULT APPROPRIATE ANALOG DEVICES DATA SHEET. Figure 6. Sample Buffer Configuration Figure 8. The SSM2142 as a Single Ended to Differential Driver R2 PIN 17 EXC VIN R1 VOUT OUTLINE DIMENSIONS PIN 16 AGND RESOLVER Dimensions shown in inches and (mm). R2 VOUT = 2VRMS x – ––– R1 ( ) PLCC (P-20A) R2 PIN 18 EXC VIN R1 0.048 (1.21) 0.042 (1.07) VOUT 0.048 (1.21) 0.042 (1.07) PIN 16 AGND EXC PIN 17 OP279 3 RESOLVER R1 0.050 (1.27) BSC R2 ( 18 A SUITABLE AMPLIFIER FOR ABOVE IS THE OP279 0.330 (8.38) 0.290 (7.37) 14 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) PRINTED IN U.S.A. Figure 7. Sample Buffer Configurations 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 9 0.020 (0.50) R 0.025 (0.63) 0.015 (0.38) TOP VIEW 8 ) R2 VOUT = 2VRMS x 2 x – ––– R1 0.180 (4.57) 0.165 (4.19) 19 PIN 1 IDENTIFIER 4 OP279 0.056 (1.42) 0.042 (1.07) –8– REV. B