AD AD50651 Fully accurate, 16-bit, unbuffered vout, quad spi interface, 2.7 v to 5.5 v nanodac in a tssop Datasheet

Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI
Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
AD5066
FEATURES
Total unadjusted error for the part is <0.8 mV. Zero code error
for the part is 0.05 mV typically.
Low power quad 16-bit nanoDAC, ±1 LSB INL
Low total unadjusted error of ±0.1 mV typically
Low zero code error of 0.05 mV typically
Individually buffered reference pins
2.7 V to 5.5 V power supply
Specified over full code range of 0 to 65535
Power-on reset to zero scale or midscale
Per channel power-down with 3 power-down functions
Hardware LDAC with software LDAC override function
CLR function to programmable code
Small 16-lead TSSOP
The AD5066 contains a power-down feature that reduces the
current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in powerdown mode.
The outputs of all DACs can be updated simultaneously using
the hardware LDAC function, with the added functionality of
user software selectable DAC channels to update simultaneously.
There is also an asynchronous CLR that clears all DACs to a
software-selectable code—0 V, midscale, or full scale.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
2.
3.
4.
5.
6.
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
GENERAL DESCRIPTION
Quad channel available in 16-lead TSSOP, ±1 LSB INL.
Individually buffered voltage reference pins.
TUE = ±0.8 mV max and zero code error = 0.1 mV max.
High speed serial interface with clock speeds up to 50 MHz.
Three power-down modes available to the user.
Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
The AD5066 is a low power, 16-bit quad-channel, unbuffered
voltage output nanoDAC® offering relative accuracy specifications of ±1 LSB INL with individual reference pins and can
operate from a single 2.7 V to 5.5 V supply. The AD5066 also
offers a differential accuracy specification of ±1 LSB DNL.
Reference buffers are also provided on-chip. The part uses a
versatile 3-wire, low power Schmitt trigger serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and most DSP interface
standards. The AD5066 incorporates a power-on reset circuit
that ensures the DAC output powers up to zero scale or
midscale and remains there until a valid write to the device
takes place.
Part No.
AD5666
AD5025/AD5045/AD50651
AD5024/AD5044/AD50641
AD50621
AD50631
AD5061
AD5040/AD50601
1
Description
Quad,16-bit buffered DAC,16 LSB INL, TSSOP
Dual,12-/14-/16-bit buffered nanoDAC,
TSSOP
Quad 16-bit nanoDAC, TSSOP
Single, 16-bit nanoDAC, SOT-23
Single, 16-bit nanoDAC, MSOP
Single,16-bit nanoDAC, ±4 LSB INL, SOT-23
14-/16-bit nanoDAC, SOT-23
±1 LSB INL
FUNCTIONAL BLOCK DIAGRAM
VREF A VREF B
VDD
AD5066
SCLK
SYNC
INTERFACE
LOGIC
DIN
INPUT
REGISTER
DAC
REGISTER
DAC A
VOUTA
INPUT
REGISTER
DAC
REGISTER
DAC B
VOUTB
INPUT
REGISTER
DAC
REGISTER
DAC C
VOUTC
INPUT
REGISTER
DAC
REGISTER
DAC D
VOUTD
POWER-ON RESET
LDAC CLR
POR
POWER-DOWN LOGIC
VREF C VREF D
GND
06845-001
LDAC
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
AD5066
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Architecture....................................................................... 15
Applications ....................................................................................... 1
Reference Buffer ......................................................................... 15
General Description ......................................................................... 1
Serial Interface ............................................................................ 15
Product Highlights ........................................................................... 1
Input Shift Register .................................................................... 15
Functional Block Diagram .............................................................. 1
Power-On Reset .......................................................................... 17
Revision History ............................................................................... 2
Clear Code Register ................................................................... 18
Specifications..................................................................................... 3
LDAC Function ........................................................................... 18
AC Characteristics ........................................................................ 4
Power Supply Bypassing and Grounding ................................ 19
Timing Characteristics ................................................................ 5
Microprocessor Interfacing ....................................................... 19
Absolute Maximum Ratings ............................................................ 6
Applications Information .............................................................. 21
ESD Caution .................................................................................. 6
Using a Reference as a Power Supply ....................................... 21
Pin Configuration and Function Descriptions ............................. 7
Bipolar Operation....................................................................... 21
Typical Performance Characteristics ............................................. 8
Using the AD5066 with a Galvanically Isolated Interface .... 21
Terminology .................................................................................... 14
Outline Dimensions ....................................................................... 22
Theory of Operation ...................................................................... 15
Ordering Guide .......................................................................... 22
Digital-to-Analog Converter .................................................... 15
REVISION HISTORY
8/10—Rev. 0 to Rev. A
Change to Minimum SYNC High Time, Single
Channel Update Parameter, Table 4 ............................................... 5
7/09—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD5066
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.0 V ≤ VREFA, VREFB, VREFC, VREFD ≤ VDD − 0.4 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE2
Resolution
Relative Accuracy (INL)
Min
IDD
Normal Mode6
All Power-Down Modes7
Min
16
Differential Nonlinearity (DNL)
Total Unadjusted Error (TUE)
Zero-Code Error
Zero-Code Error Drift3
Full-Scale Error
Gain Error
Gain Error Drift3
DC Crosstalk3
OUTPUT CHARACTERISTICS3
Output Voltage Range
DC Output Impedance (Normal
Mode)
DC Output Impedance
Output Connected to 100 kΩ
Network
Output Connected to 1 kΩ
Network
Power-Up Time4
DC PSRR
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS3
Input Current5
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
POWER REQUIREMENTS
VDD
A Grade1
Typ
Max
B Grade1
Typ
Max
16
±0.5
±0.5
±0.2
±0.1
0.05
±0.5
±0.01
±0.005
±0.5
1
5
0
±4
±4
±1
±0.8
0.1
Unit
Bits
LSB
Conditions/Comments
±1
±2
±1
±0.8
0.1
5
±0.5
±0.5
±0.2
±0.1
0.05
±0.5
±0.01
±0.005
±0.5
1
5
LSB
mV
mV
µV/°C
% FSR
% FSR
ppm
μV
25
5
25
μV
ppm of FSR/°C
Due to single-channel full-scale
output change
Due to powering down (per channel)
VREF
±0.05
±0.05
VREF
VDD = 2.7 V, VREF = 2 V
All 0s loaded to the DAC register
All 1s loaded to the DAC register
8
8
V
kΩ
Output impedance tolerance ± 10%
100
100
kΩ
DAC in power-down mode
Output impedance tolerance ± 20 kΩ
1
1
kΩ
Output impedance tolerance ± 400 Ω
2.9
−120
2.9
−120
µs
dB
VDD ± 10%, DAC = full scale
VDD − 0.4
±1
V
µA
MΩ
Per DAC channel
Per DAC channel
±1
0.8
µA
V
V
pF
5.5
V
3
mA
µA
2
0.002
40
0
±0.05
±0.05
TA = −40°C to +105°C
TA = −40°C to +125°C
VDD − 0.4
±1
2
0.002
40
±1
0.8
2.2
2.2
4
2.7
4
5.5
2.5
0.4
3
2.7
2.5
0.4
1
All digital inputs at 0 V or VDD
DAC active, excludes load current
VIH = VDD and VIL = GND
Temperature range is −40°C to +125°C, typical at 25°C.
Linearity calculated using a code range of 0 to 65,535; output unloaded.
Guaranteed by design and characterization; not production tested.
4
Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded.
5
Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.
6
Interface inactive. All DACs active. DAC outputs unloaded.
7
All four DACs powered down.
2
3
Rev. A | Page 3 of 24
AD5066
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 2.0 V ≤ VREFA, VREFB, VREFC, VREFD ≤ VDD − 0.4 V all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
DYNAMIC PERFORMACE
Output Voltage Settling Time
Typ
Max
Unit
Conditions/Comments3
7.5
10
µs
Output Voltage Settling Time
12
15
µs
¼ to ¾ scale settling to ±2 LSB, single channel update, output
unloaded
¼ to ¾ scale settling to ±2 LSB, all channel update, output
unloaded
Slew Rate
Digital-to-Analog Glitch Impulse
Reference Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion
Output Noise Spectral Density
1.7
3
−70
0.02
1.7
3.7
5.4
−83
30
25
4.7
Output Noise
Min
V/µs
nV-sec
dB
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
nV/√Hz
μV p-p
1 LSB change around major carry
VREF = 3 V ± 0.5 V p-p, frequency = 60 Hz to 20 MHz
VREF = 3 V ± 0.2 V p-p, frequency = 10 kHz
DAC code = 0x8000, 1 kHz
DAC code = 0x8000, 10 kHz
0.1 Hz to 10 Hz
1
Temperature range is −40°C to +125°C, typical at +25°C.
See the Terminology section.
3
Guaranteed by design and characterization; not production tested.
2
Rev. A | Page 4 of 24
AD5066
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, VDD = 2.7 V to
5.5 V, all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Set-Up Time
Data Set-Up Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Single Channel Update
All Channel Update
SYNC Rising Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
CLR Pulse Width Low
SCLK Falling Edge to LDAC Falling Edge
CLR Pulse Activation Time
Min
20
10
10
17
5
5
5
Typ
Max
30
3
8
17
20
20
10
10
10.6
t9
t10
t11
t12
t13
t14
Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
t1
t9
SCLK
t8
t3
t4
t2
t7
SYNC
t5
D IN
t6
D B 31
DB0
t 13
t 10
LDAC1
t 11
LDAC2
CLR
V O UT
t 12
t14
1A S Y N C H R O N O U S L D A C U P D A T E M O D E .
2S Y N C H R O N O U S L D A C U P D A T E M O D E .
Figure 2. Serial Write Operation
Rev. A | Page 5 of 24
Unit
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
06845-003
1
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
AD5066
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
Digital Input Voltage to GND
VOUTx to GND
VREFx to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ MAX)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
Reflow Soldering Peak Temperature
SnPb
Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
+150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
(TJ MAX − TA)/θJA
150.4°C/W
240°C
260°C
Rev. A | Page 6 of 24
AD5066
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC 1
16 SCLK
SYNC
2
15 DIN
VDD
3
14 GND
VREF A
5
AD5066
TOP VIEW
(Not to Scale)
13 VOUTB
12 VOUTD
VOUTA 6
11 VREF D
VOUTC 7
10 CLR
POR 8
9
VREF C
06845-004
VREF B 4
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
2
SYNC
3
VDD
4
5
6
7
8
VREFB
VREFA
VOUTA
VOUTC
POR
9
10
VREFC
CLR
11
12
13
14
15
VREFD
VOUTD
VOUTB
GND
DIN
16
SCLK
Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs.
When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd
clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but
the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of
SYNC acts as an interrupt, and the write sequence is ignored by the device.
Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF
capacitor in parallel with a 0.1 µF capacitor to GND.
External Reference Voltage Input for DAC B.
External Reference Voltage Input for DAC A.
Unbuffered Analog Output Voltage from DAC A.
Unbuffered Analog Output Voltage from DAC C.
Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying
this pin to VDD powers the DAC outputs to midscale.
External Reference Voltage Input for DAC C.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
External Reference Voltage Input for DAC D.
Unbuffered Analog Output Voltage from DAC D.
Unbuffered Analog Output Voltage from DAC B.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 50 MHz.
Rev. A | Page 7 of 24
AD5066
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.3
0.4
0.2
MAX INL
0.3
0.1
0
INL (LSB)
INL ERROR (LSB)
0.2
–0.1
–0.2
0.1
0
MIN INL
–0.1
–0.2
VDD = 5V
VREF = 4.096V
TA = 25°C
–0.3
–0.5
0
10,000
20,000
VDD = 5V
TA = 25°C
–0.4
30,000
40,000
CODE
50,000
60,000
–0.5
06845-105
–0.4
2
Figure 4. INL Error vs. Code
5
Figure 7. INL vs. Reference Input Voltage
0.5
0.3
VDD = 5V
VREF = 4.096V
TA = 25°C
0.2
0.4
0.3
0.1
0.2
DNL (LSB)
DNL ERROR (LSB)
3
4
REFERENCE VOLTAGE (V)
06845-108
–0.3
0
–0.1
0.1
MAX DNL
0
–0.1
MIN DNL
–0.2
–0.2
–0.3
VDD = 5.5V
TA = 25°C
–0.4
10,000
20,000
30,000
40,000
CODE
50,000
60,000
–0.5
2
80
TOTAL UNADJUSTED ERROR (µV)
100
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
VDD = 5V
VREF = 4.096V
TA = 25°C
–0.06
60
40
MAX TUE
20
0
–20
MIN TUE
–40
–60
VDD = 5.5V
TA = 25°C
–80
–0.07
10,000
20,000
30,000 40,000
CODE
50,000
60,000
–100
06845-107
TOTAL UNADJUSTED ERROR (mV)
0.03
0
5
Figure 8. DNL vs. Reference Input Voltage
Figure 5. DNL Error vs. Code
–0.05
3
4
REFERENCE VOLTAGE (V)
2
Figure 6. Total Unadjusted Error vs. Code
3
4
REFERENCE VOLTAGE (V)
Figure 9. Total Unadjusted Error vs. Reference Input Voltage
Rev. A | Page 8 of 24
5
06845-110
0
06845-106
–0.4
06845-109
–0.3
AD5066
1.2
0.010
1.0
0.8
0.6
GAIN ERROR (%FSR)
0.005
DNL (LSB)
0.4
0
0.2
MAX DNL
0
–0.2
MIN DNL
–0.4
–0.6
–0.005
–1.2
–40
06845-111
3
4
REFERENCE VOLTAGE (V)
5
–20
Figure 10. Gain Error Vs. Reference Input Voltage
0.09
80
ZERO-SCALE ERROR (mV)
0.08
0.07
0.06
0.05
0.04
0.03
VDD = 5.5V
TA = 25°C
100
120
100
120
60
MAX TUE
40
20
0
–20
MIN TUE
–40
–60
VDD = 5V
VREF = 4.096V
–80
0.01
5
–100
–40
06845-112
0
3
4
REFERENCE VOLTAGE (V)
80
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 11. Zero-Code Error Vs. Reference Input Voltage
06845-115
TOTAL UNADJUSTED ERROR (µV)
100
2
20
40
60
TEMPERATURE (°C)
Figure 13. DNL vs. Temperature
0.10
0.02
0
06845-114
–1.0
–0.010
2
VDD = 5V
VREF = 4.096V
–0.8
VDD = 5.5V
TA = 25°C
Figure 14. Total Unadjusted Error vs. Temperature
1.2
50
1.0
40
MAX INL
0.8
30
0.6
20
0
–0.2
MIN INL
–0.4
–0.6
–0.8
–1.0
–1.2
–40
VDD = 5V
VREF = 4.096V
–20
0
10
0
–10
–20
–30
–40
20
40
60
TEMPERATURE (°C)
80
100
120
–50
–40
Figure 12. INL vs. Temperature
VDD = 5V
VREF = 4.096V
–20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 15. Zero-Code Error vs. Temperature
Rev. A | Page 9 of 24
120
06845-116
ZERO-SCALE ERROR (µV)
0.2
06845-113
INL (LSB)
0.4
AD5066
0.0020
7
0.0015
VDD = 5V
DAC OUTPUT UNLOADED
TA = 25°C
6
0.0010
GAIN ERROR (%FSR)
5
HITS
0.0005
0
4
3
–0.0005
2
–0.0010
–20
0
1
20
40
60
TEMPERATURE (°C)
80
100
120
0
2.45
Figure 16. Gain Error vs. Temperature
2.55
2.60
IDD POWER-UP (mA)
2.50
2.65
2.70
06845-120
–0.0020
–40
VDD = 5V
VREF = 4.096V
06845-117
–0.0015
Figure 19. IDD Histogram VDD = 5.5 V
0.010
60
VDD = 5V
TA = 25°C
DAC OUTPUT UNLOADED
50
+125°C IDD POWERDOWN
+25°C IDD POWERDOWN
–40°C IDD POWERDOWN
ERROR (%FSR)
0.005
40
HITS
FULL-SCALE ERROR
0
30
20
GAIN ERROR
–0.005
VDD = 5V
VREF = 4.096V
TA = 25°C
2.7
3.2
3.7
4.2
VDD (V)
4.7
0
06845-118
–0.010
5.2
0.2
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
0.4
0.6
0.8
IDD POWERDOWN (µA)
1.0
06845-139
10
Figure 20. IDD Power-Down Histogram
20
5
4
IDD (mA)
15
10
3
2
VDD = 5V
VREF = 4.096V
TA = 25°C
1
0
2.7
3.7
4.7
VDD (V)
0
0
Figure 18. Zero-Code Error vs. Supply Voltage
10,000
20,000
30,000
40,000
DAC CODE
Figure 21. IDD vs. Code
Rev. A | Page 10 of 24
50,000
60,000
06845-121
5
06845-119
ZERO-SCALE Error (µV)
VDD = 5.5V
VREF = 4.096V
TA = 25°C
AD5066
1/4 TO 3/4
3.0
OUTPUT VOLTAGE (V)
4
IDD (mA)
3.5
VDD = 5.5V
VREF = 4.096V
TA = 25°C
CODE = MIDSCALE
3
2
2.5
2.0
1.5
3/4 TO 1/4
1.0
VDD = 4.5V
VREF = 4.096V
OUTPUT AMPLIFIER = AD797
TA = 25°C
DAC LOAD = 9pF
1
0.5
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
0
06845-122
0
–40
0
1
2
Figure 22. IDD vs. Temperature
3
4
5
6
TIME (µs)
7
8
9
10
Figure 25. Settling Time
5
VREF = 4.096V
TA = 25°C
CODE = MIDSCALE
VDD
IDD (mA)
4
VREF
3
2
VOUT
1
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
CH1 2.00V
CH3 2.00V
CH2 2.00V
M10.00ms
T 30.20%
A CH1
640mV
06845-126
0
2.7
06845-123
VREF = 4.096V
TA = 25°C
Figure 26. POR to 0 V
Figure 23. IDD vs. Supply Voltage
10
VDD = 5.5V
VREF = 4.096V
TA = 25°C
VDD
8
4
VOUT
2
0
0
1
2
3
4
DIGITAL INPUT VOLTAGE (V)
5
6
CH1 2.00V
CH3 2.00V
CH2 2.00V
M10.00ms
T 30.20%
Figure 27. POR to MS
Figure 24. IDD vs. Digital Input Voltage
Rev. A | Page 11 of 24
A CH1
640mV
06845-127
VDD = 5.5V
VREF = 4.096V
06845-124
IDD (mA)
VREF
6
06845-125
5
AD5066
15
CH1 = SCLK
VDD = 5V
VREF = 4.096V
TA = 25°C
10
CH2 = VOUT
GLITCH AMPLITUDE (mV)
1
VDD = 5V
POWER-UP TO MIDSCALE
OUTPUT UNLOADED
2
5
0
–5
CH2 500mV
M2µs
T 55%
A CH2
1.2V
–15
–2
06845-128
CH1 5V
0
2
Figure 28. Exiting PD to MS
4
TIME (µs)
6
8
Figure 31. Digital Crosstalk
20
15
VDD = 5V
VREF = 4.096V
TA = 25°C
15
GLITCH AMPLITUDE (mV)
5
0
–5
2
4
TIME (µs)
6
5
0
–5
–10
–15
8
10
–20
–2
0
Figure 29. Glitch
6
8
10
4
VDD = 5V
VREF = 4.096V
TA = 25°C
3
OUTPUT VOLTAGE (µV)
10
5
0
–5
2
1
0
–1
–2
–10
VDD = 5V
VREF = 4.096V
TA = 25°C
–3
0
2
4
6
TIME (µs)
8
10
06845-130
GLITCH AMPLITUDE (mV)
4
TIME (µs)
Figure 32. DAC-to-DAC Crosstalk
15
–15
–2
2
06845-132
0
10
Figure 30. Analog Crosstalk
–4
0
1
2
3
4
5
6
Time (Seconds)
Figure 33. 1/f Noise
Rev. A | Page 12 of 24
7
8
9
10
06845-133
–15
–2
VDD = 5V
VREF = 4.096V
TA = 25°C
CODE = 0x8000 TO 0x7FFF
OUTPUT UNLOADED WITH 5kΩ AND 200pF
06845-129
GLITCH AMPLITUDE (mV)
10
–10
10
06845-131
–10
AD5066
0
VDD = 5V,
TA = 25ºC
DAC LOADED WITH MIDSCALE
VREF = 3.0V ± 200mV p-p
–10
–20
CH1 PEAK TO PEAK
155mV
VOUT
VOUT LEVEL (dB)
–30
–40
–50
–60
LAST SCLK
–70
–80
–100
5
20
10
50
30
40
FREQUENCY (kHz)
CH1 50.0mV
55
Figure 34. Total Harmonic Distortion
CH2 5.00V
M4.00µs
T 9.800%
A CH2
1.80V
06845-137
VDD = 5V
VREF = 4.096V
TA = 25°C
06845-016
–90
Figure 37. Glitch Upon Entering Power Down
CH1 PEAK TO PEAK
159mV
CLR
VOUT
VOUT
LAST SCLK
CH2 2.00V
M2.00ms
T 10.20%
A CH1
1.80V
CH1 50.0mV
Figure 35. Hardware CLR
2.8
1/4 TO 3/4
2.4
2.2
2.0
1.8
3/4 TO 1/4
1.6
VDD = 4.5V
VREF = 4.096V
TA = 25°C
1.0
1.5
1.6
1.7
1.8
1.9
2
2.1
TIME (µs)
2.2
2.3
2.4
06845-136
OUTPUT VOLTAGE (V)
2.6
1.2
M4.00µs
T 9.800%
A CH2
Figure 38. Glitch Upon Exiting Power Down
3.0
1.4
CH2 5.00V
Figure 36. Slew Rate
Rev. A | Page 13 of 24
1.80V
06845-138
CH1 5.00V
06845-135
VDD = 5V
VREF = 4.096V
TA = 25°C
AD5066
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy or INL is a measure of the maximum
deviation in LSBs from a straight line passing through the
endpoints of the DAC transfer function. Figure 4, Figure 5,
and Figure 6 show typical INL vs. code plots.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity. Figure 7, Figure 8, and Figure 9 show typical DNL vs.
code plots.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5066, because the output of the DAC cannot go below
0 V. Zero-code error is expressed in millivolts. Figure 17 shows
a typical zero-code error vs. supply voltage plot.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(SYNC held high). It is specified in nanovolts per second and
measured with one simultaneous DIN and SCLK pulse loaded
to the DAC.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nanovolts per second.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in microvolts
per degrees Celsius.
Full-Scale Error
Full-scale error is a measure of the output error when a fullscale code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be VREF − 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nanovolts
per second and is measured when the digital input code is
changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Figure 28.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. DC PSRR is the ratio of the
change in VOUT to a change in VDD for full-scale output of the
DAC. It is measured in decibels.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nanovolts per second.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nanovolts per second.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as
the reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in
decibels.
Rev. A | Page 14 of 24
AD5066
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
SERIAL INTERFACE
The AD5066 is a quad 16-bit, serial input, voltage output
nanoDAC. The part operates from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5066 in a 32-bit word format via
a 3-wire serial interface. The AD5066 incorporates a power-on
reset circuit to ensure the DAC output powers up to a known
output state. The devices also have a software power-down mode
that reduces the typical current consumption to typically 400 nA.
The AD5066 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. See Figure 2 for a timing diagram
of a typical write sequence.
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
D
VOUT  VREFIN   N 
2 
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register (0 to 65,535).
N is the DAC resolution.
DAC ARCHITECTURE
The DAC architecture of the AD5066 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 39. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either GND or the VREF buffer
output. The remaining 12 bits of the data word drive the S0 to
S11 switches of a 12-bit voltage mode R-2R ladder network.
VOUT
2R
2R
2R
2R
2R
2R
2R
S0
S1
S11
E1
E2
E15
12-BIT R-2R LADDER
FOUR MSBs DECODED
INTO 15 EQUAL
SEGMENTS
06845-005
VREF
INPUT SHIFT REGISTER
The input shift register is 32 bits wide (see Figure 40). The first
four bits are don’t cares. The next four bits are the command
bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address
bits, A3 to A0 (see Table 8), and finally the bit data-word. The
data-word comprises of a 16-bit input code followed by four don’t
care bits (see Figure 40). These data bits are transferred to the
Input register on the 32nd falling edge of SCLK. Commands can
be executed on individually selected DAC channels or on all DACs.
Table 7. Command Definitions
C3
0
0
Command
C2 C1 C0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
Description
Write to Input Register n
Transfer contents of Input Register n to
DAC Register n
Write to Input Register n and update all
DAC Registers
Write to Input Register n and update
DAC Register n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Reserved
Reserved
Reserved
Table 8. DAC Input Register Address Bits
Figure 39. DAC Ladder Structure
REFERENCE BUFFER
The AD5066 operates with an external reference. Each of the
four on-board DACs has a dedicated voltage reference pin that
is buffered. The reference input pin has an input range of 2 V
to VDD − 0.4 V. This input voltage is then used to provide a
buffered reference for the DAC core.
A3
0
0
0
0
1
Address (n)
A2
A1
0
0
0
0
0
1
0
1
1
1
A0
0
1
0
1
1
Selected DAC Channel
DAC A
DAC B
DAC C
DAC D
All DACs
DB31 (MSB)
X
X
X
C3
C2
C1
C0
A3
A2
A1
A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X
X
X
X
DATA BITS
COMMAND BITS
06845-007
X
DB0 (LSB)
ADDRESS BITS
Figure 40. Input Shift Register Content
Rev. A | Page 15 of 24
AD5066
When Bit DB9 and Bit DB8 in the control register are set to 0,
the part is configured in normal mode with its normal power
consumption of 2.5 mA at 5 V. However, for the three powerdown modes, the supply current falls to 0.4 µA if all the channels
are powered down. Not only does the supply current fall, but
the output pin is also internally switched from the output of the
DAC to a resistor network of known values. This has the advantage
that the output impedance of the part is known while the part
is in power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ or
a 100 kΩ resistor, or it is left open-circuited (three-state). The
output stage is illustrated in Figure 41.
DAC
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if SYNC is brought high before the
32nd falling edge, this acts as an interrupt to the write sequence.
The input shift register is reset, and the write sequence is seen
as invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 42).
Power-Down Modes
The AD5066 can be configured through software, in one of
four different modes: normal mode (default) and three separate
power-down modes (see Table 9). Any or all DACs can be
powered down. Command 0100 is reserved for the powerdown function (see Table 7). These power-down modes are
software-programmable by setting two bits, Bit DB9 and
Bit DB8, in the input shift register. Table 9 shows how the state
of the bits corresponds to the mode of operation of the device.
Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, DB0) to 1. See Table 10 for the contents of the input
shift register during power-down/power-up operation.
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
06845-008
The write sequence begins by bringing the SYNC line low.
Bringing the SYNC line low enables the DIN and SCLK input
buffers. Data from the DIN line is clocked into the 32-bit shift
register on the falling edge of SCLK. The serial clock frequency
can be as high as 50 MHz, making the AD5066 compatible with
high speed DSPs. On the 32nd falling clock edge, the last data bit
is clocked in, and the programmed function is executed, that is,
a change in the input register contents (see Table 8) and/or a
change in the mode of operation. At this stage, the SYNC line
can be kept low or be brought high. In either case, it must be
brought high for a minimum of 2 μs (single-channel update, see
the t8 parameter in Table 4) before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Idle SYNC high between write sequences for even lower power
operation of the part.
Figure 41. Output Stage During Power-Down Mode
The bias generator, DAC core, and other associated linear
circuitry are shut down when all channels are powered down.
However, the contents of the DAC register are unaffected when
in power-down mode. The time to exit power-down mode is
typically 2.9 µs (see Figure 27).
Table 9. Modes of Operation
DB9
0
DB8
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
SCLK
SYNC
DB31
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
DB0
VALID WRITE SEQUENCE:
OUTPUT UPDATES ON THE 32ND FALLING EDGE
Figure 42. SYNC Interrupt Facility
Rev. A | Page 16 of 24
06845-017
DIN
AD5066
POWER-ON RESET
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
The AD5066 contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the POR
pin low, the AD5066 output powers up to 0 V; by connecting
the POR pin high, the AD5066 output powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
DB31 to
DB28
X
Don’t
cares
LSB
DB27 DB26 DB25 DB24
0
1
0
0
Command bits (C2 to C0)
DB23 to
DB20
X
Address bits
(A3 to A0)—
don’t cares
DB10 to
DB19
X
Don’t
cares
DB9 DB8
PD1 PD0
Power-down
mode
Rev. A | Page 17 of 24
DB4 to
DB7
X
Don’t
cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Power-down/power-up channel
selection—set bit to 1 to select
AD5066
CLEAR CODE REGISTER
The AD5066 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly (see
Table 11). This function can be used in system calibration to
load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the control register (see Table 11).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 7).
Table 11. Clear Code Register
DB1 (CR1)
0
0
1
1
DB0 (CR0)
0
1
0
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
The part exits clear code mode on the 32nd falling edge of the
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time (the falling edge of CLR to when
the output starts to change) is typically 10.6 µs. See Table 13 for
contents of the input shift register during the loading clear code
register operation.
LDAC FUNCTION
Hardware LDAC Pin
Synchronous LDAC: LDAC is held permanently low. After new
data is read, the DAC registers are updated on the falling edge
of the 32nd SCLK pulse, provided LDAC is held low.
Asynchronous LDAC: LDAC is held high then pulsed low to
update. The outputs are not updated at the same time that the
input registers are written to. When LDAC is pulsed low, the
DAC registers are updated with the contents of the input
registers.
Command 0001, 0010 and 0011 (see Table 7) update the DAC
Register/Registers, regardless of the level of the LDAC pin
Software LDAC Function
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel is
0; that is, the LDAC pin works normally. Setting the bits to 1
updates the DAC channel regardless of the state of the hardware
LDAC pin, so that it effectively sees the hardware LDAC pin
as being tied low (see Table 12 for the LDAC register mode of
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.
Table 12. Load LDAC Register
LDAC Bits
(DB3 to
DB0)
0
1
1
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 2. There are two
methods of using the hardware LDAC pin: synchronously
(LDAC permanently low) and asynchronously (LDAC pulsed).
LDAC
Pin
1/0
X1
LDAC Operation
Determined by LDAC pin
DAC channels update, overrides the LDAC
pin; DAC channels see LDAC as 0
X = don’t care.
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 14). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
Table 13. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
DB27
DB26
DB25
DB24
0
1
0
1
Command bits (C3 to C0)
DB23
X
DB22
DB21
DB20
X
X
X
Address bits (A3 to A0)
DB2 to DB19
X
Don’t cares
LSB
DB1
DB0
1/0
1/0
Clear code register
(CR1 to CR0)
Table 14. 32-Bit Input Shift Register Contents for LDAC Overwrite Function
MSB
DB31
to DB28
X
Don’t cares
LSB
DB27 DB26 DB25 DB24
0
1
1
0
Command bits (C3 to C0)
DB23 to DB20
X
Address bits (A3 to A0)—don’t cares
Rev. A | Page 18 of 24
DB4
to DB19
X
Don’t cares
DB3
DB2
DB1
DB0
DAC D
DAC C
DAC B
DAC A
Setting LDAC bit to 1 override LDAC pin
AD5066
POWER SUPPLY BYPASSING AND GROUNDING
AD5066 to 68HC11/68L11 Interface
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5066 should
have separate analog and digital sections. If the AD5066 is in a
system where other devices require an AGND-to-DGND connection, make the connection at one point only and as close as
possible to the AD5066.
Figure 44 shows a serial interface between the AD5066 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5066, and the MOSI output drives
DIN of the DAC. A port line (PC7) drives the SYNC signal.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Shield the clocks and other fast switching digital
signals from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at
right angles to each other to reduce feedthrough effects through
the board. The best board layout technique is the microstrip
technique, where the component side of the board is dedicated
to the ground plane only, and the signal traces are placed on
the solder side. However, this is not always possible with a
2-layer board.
AD5066*
SYNC
DIN
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
DIN
The setup conditions for correct operation of this interface are
as follows: The 68HC11/68L11 is configured with its CPOL bit
as 0, and the CPHA bit as 1. When data is being transmitted to
the DAC, the SYNC line is taken low (PC7). When the 68HC11/
68L11 is configured as described previously, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5066, PC7 is left
low after the first eight bits are transferred, and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
06845-009
TSCLK0
SCK
Figure 44. AD5066 to 68HC11/68L11 Interface
Figure 43 shows a serial interface between the AD5066 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the
AD5066, the setup for the interface is as follows: DT0PRI
drives the DIN pin of the AD5066, TSCLK0 drives the SCLK
of the parts, and TFS0 drives SYNC.
DT0PRI
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5066 to Blackfin® ADSP-BF53X Interface
TFS0
PC7
MOSI
MICROPROCESSOR INTERFACING
ADSP-BF53x*
AD5066*
06845-010
Bypass the power supply to the AD5066 with 10 µF and 0.1 µF
capacitors. The capacitors should be physically as close as
possible to the device, with the 0.1 µF capacitor, ideally, right up
against the device. The 10 µF capacitors are the tantalum bead
type. It is important that the 0.1 µF capacitor has low effective
series resistance and low effective series inductance, typical of
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
68HC11/68L11*
Figure 43. AD5066 to Blackfin ADSP-BF53X Interface
Rev. A | Page 19 of 24
AD5066
80C51/80L51*
AD5066*
P3.3
SYNC
TxD
SCLK
RxD
DIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 45. AD5066 to 80C512/80L51 Interface
AD5066 to MICROWIRE Interface
Figure 46 shows an interface between the AD5066 and any
MICROWIRE-compatible device. Serial data is clocked into
the AD5066 on the falling edge of the SCLK.
MICROWIRE*
AD5066*
CS
SYNC
SK
DIN
SO
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. AD5066 to MICROWIRE Interface
Rev. A | Page 20 of 24
06845-012
Figure 45 shows a serial interface between the AD5066 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,
RxD drives DIN on the AD5066, and a bit-programmable pin on
the port (P3.3) drives the SYNC signal. When data is to be
transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51
transmit data in 8-bit bytes only; thus, only eight falling clock
edges occur in the transmit cycle. To load data to the DAC, P3.3
is left low after the first eight bits are transmitted, and a second,
third, and fourth write cycle is initiated to transmit the second,
third, and fourth byte of data. P3.3 is taken high following the
completion of this cycle. The 80C51/80L51 output the serial
data in a format that has the LSB first. The AD5066 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
06845-011
AD5066 to 80C51/80L51 Interface
AD5066
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY
R2 = 10kΩ
+5V
R1 = 10kΩ
+5.5V
+5V
VREF
VREF
AD820/
OP295
±5V
VOUT
VDD
10µF
0.1µF
–5V
AD5066
06845-014
Because the supply current required by the AD5066 is extremely
low, an alternative option is to use a voltage reference to supply
the required voltage to the parts (see Figure 47). This is especially useful if the power supply is quite noisy or if the system
supply voltages are at some value other than 5 V or 3 V, for
example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5066. If the low dropout REF195 is used, it
must supply 2.5 mA of current to the AD5066 with no load on
the output of the DAC.
3-WIRE
SERIAL INTERFACE
15V
Figure 48. Bipolar Operation with the AD5066
REF195
5V
4.5V
VDD
USING THE AD5066 WITH A GALVANICALLY
ISOLATED INTERFACE
VREF
SYNC
SCLK
AD5066
VOUTx = 0V TO 4.5V
DIN
06845-013
3-WIRE
SERIAL
INTERFACE
REF194
Figure 47. REF195 as a Power Supply to the AD5066
BIPOLAR OPERATION
The AD5066 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 48. The circuit gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achieved
using an AD8638 or AD8639 the output amplifier.
The output voltage for any input code can be calculated as
follows:
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so
the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 49). The power supply to the
part also needs to be isolated, which is done by using a
transformer. On the DAC side of the transformer, a 5 V
regulator provides the 5 V supply required for the AD5066.
5V
REGULATOR
10µF
POWER

 D   R1 + R2 
 R2 
VO = VDD × 
×
 − VDD × 

 R1 
 65,536   R1 

VDD
SCLK
VIA
VOA
SCLK
ADuM1300
AD5066
SDI
VIB
VOB
SYNC
DATA
VIC
VOC
DIN
VOUTx
GND
06845-015
where:
D = the input code in decimal (0 to 65,535).
VDD = 5 V.
R1 = R2 = 10 kΩ.
 10 × D 
VO = 
 −5V
 65,536 
0.1µF
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Figure 49. AD5066 with a Galvanically Isolated Interface
Rev. A | Page 21 of 24
AD5066
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeter
ORDERING GUIDE
Model1
AD5066BRUZ
AD5066BRUZ-REEL7
AD5066ARUZ
AD5066ARUZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Z = RoHS Compliant Part.
Rev. A | Page 22 of 24
Package
Option
RU-16
RU-16
RU-16
RU-16
Power-On
Reset to Code
Zero
Zero
Zero
Zero
Accuracy
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
Resolution
16 bits
16 bits
16 bits
16 bits
AD5066
NOTES
Rev. A | Page 23 of 24
AD5066
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06845-0-8/10(A)
Rev. A | Page 24 of 24