AD AD5172BRM50 256-position, one-time programmable, dual-channel, i2c digital potentiometer Datasheet

256-Position, One-Time Programmable,
Dual-Channel, I2C Digital Potentiometers
AD5172/AD5173
2-channel, 256-position potentiometers
One-time programmable (OTP) set-and-forget resistance
setting provides a low cost alternative to EEMEM
Unlimited adjustments prior to OTP activation
OTP overwrite allows dynamic adjustments with userdefined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm
Fast settling time: tS = 5 μs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1 (AD5173)
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 μA maximum
Wide operating temperature: −40°C to +125°C
FUNCTIONAL BLOCK DIAGRAMS
A1
W1
B1
FUSE
LINKS
VDD
1
GND
A2
W2
B2
2
RDAC
REGISTER 2
RDAC
REGISTER 1
/8
SDA
SERIAL INPUT
REGISTER
SCL
04103-001
FEATURES
Figure 1. AD5172 Functional Block Diagram
W1
B1
W2
B2
APPLICATIONS
FUSE
LINKS
VDD
1
GND
AD0
AD1
SDA
SCL
RDAC
REGISTER 1
ADDRESS
DECODE
2
RDAC
REGISTER 2
/8
SERIAL INPUT
REGISTER
04103-002
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Figure 2. AD5173 Functional Block Diagram
GENERAL DESCRIPTION
The AD5172/AD5173 are dual-channel, 256-position, one-time
programmable (OTP) digital potentiometers1 that employ fuse
link technology to achieve memory retention of resistance
settings. OTP is a cost-effective alternative to EEMEM for users
who do not need to program the digital potentiometer setting
in memory more than once. These devices perform the same
electronic adjustment function as mechanical potentiometers or
variable resistors but with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance.
before permanently setting the resistance value. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5172/
AD5173 have a unique temporary OTP overwrite feature that
allows for new adjustments even after a fuse is blown. However,
the OTP setting is restored during subsequent power-up conditions. This allows users to treat these digital potentiometers as
volatile potentiometers with a programmable preset.
The AD5172/AD5173 are programmed using a 2-wire, I2C®compatible digital interface. Unlimited adjustments are allowed
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
AD5172/AD5173
TABLE OF CONTENTS
Features .............................................................................................. 1
Programming the Variable Resistor and Voltage ................... 15
Applications ....................................................................................... 1
Programming the Potentiometer Divider ............................... 16
Functional Block Diagrams ............................................................. 1
ESD Protection ........................................................................... 17
General Description ......................................................................... 1
Terminal Voltage Operating Range ......................................... 17
Revision History ............................................................................... 2
Power-Up Sequence ................................................................... 17
Specifications..................................................................................... 3
Power Supply Considerations ................................................... 17
Electrical Characteristics: 2.5 kΩ ............................................... 3
Layout Considerations ............................................................... 18
2
Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 4
I C Interface .................................................................................... 19
Timing Characteristics ................................................................ 6
Write Mode ................................................................................. 19
Absolute Maximum Ratings............................................................ 7
Read Mode .................................................................................. 19
ESD Caution .................................................................................. 7
I2C Controller Programming .................................................... 20
Pin Configurations and Function Descriptions ........................... 8
I2C-Compatible, 2-Wire Serial Bus .......................................... 21
Typical Performance Characteristics ............................................. 9
Level Shifting for Different Voltage Operation ...................... 22
Test Circuits ..................................................................................... 14
Outline Dimensions ....................................................................... 23
Theory of Operation ...................................................................... 15
Ordering Guide .......................................................................... 23
One-Time Programming (OTP) .............................................. 15
REVISION HISTORY
4/09—Rev. G to Rev. H
Changes to DC Characteristics—Rheostat Mode Parameter and
to DC Characteristics—Potentiometer Divider Mode Parameter,
Table 1 ................................................................................................ 3
12/08—Rev. F to Rev. G
Changes to OTP Supply Voltage Parameter, Table 1.................... 3
Changes to OTP Supply Voltage Parameter, Table 2.................... 5
Changes to Table 5 and Table 6 ....................................................... 8
Changes to One-Time Programming (OTP) Section ................ 15
Changes to Power Supply Considerations Section, Figure 46,
and Figure 46 Caption.................................................................... 17
Changes to Ordering Guide .......................................................... 23
7/08—Rev. E to Rev. F
Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3
Updated Fuse Blow Condition to 400 ms Throughout ............... 5
1/08—Rev. D to Rev. E
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 1
Changes to OTP Supply Voltage and OTP Supply Current in
Table 1 ................................................................................................ 3
Changes to OTP Supply Voltage and OTP Supply Current in
Table 2 ................................................................................................ 5
Added OTP Program Time in Table 3 ........................................... 6
Changes to Table 4 ............................................................................ 7
Changes to Table 5 and Table 6 ....................................................... 8
Inserted Figure 30 ........................................................................... 13
Replaced One-Time Programming (OTP) Section ................... 15
Replaced Power Supply Considerations Section ........................ 17
Deleted Device Programming Software Section ........................ 20
Replaced I2C-Compatible, 2-Wire Serial Bus Section ............... 21
Changes to Ordering Guide .......................................................... 23
6/06—Rev. C to Rev. D
Changes to Features ..........................................................................1
Changes to One-Time Programming (OTP) Section................ 15
Changes to Figure 44 and Figure 45............................................. 17
Changes to Power Supply Considerations Section .................... 18
Changes to Figure 46 and Figure 47............................................. 18
Changes to Device Programming Software Section .................. 19
Updated Outline Dimensions ....................................................... 24
6/05—Rev. B to Rev. C
Added Footnote 8, Footnote 9, and Footnote 10 to Table 1 ........3
Added Footnote 8 to Table 2 ............................................................5
Changes to Table 5 and Table 6 .......................................................9
Changes to Power Supply Considerations Section .................... 17
Changes to I2C-Compatible 2-Wire Serial Bus Section ............ 23
Added Level Shifting for Different Voltage Operation Section ...... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
10/04—Rev. A to Rev. B
Updated Format ................................................................. Universal
Changes to Specifications .................................................................3
Changes to One-Time Programming (OTP) Section................ 13
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 44 and Figure 45............................................. 15
Changes to Figure 46 and Figure 47............................................. 16
11/03—Rev. 0 to Rev. A
Changes to Electrical Characteristics—2.5 kΩ..............................3
11/03—Revision 0: Initial Version
Rev. H | Page 2 of 24
AD5172/AD5173
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance 3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE 4
Differential Nonlinearity 5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range 6
Capacitance A, B 7
Capacitance W7
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
∆RAB
(∆RAB/RAB)/∆T
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−2
−14
−20
±0.1
±2
+2
+14
+55
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔVW/VW)/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
35
160
Code = 0x00, VDD = 5 V
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
GND
IA_SD
ICM
f = 1 MHz, measured to
GND, code = 0x80
f = 1 MHz, measured to
GND, code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VIH
VIL
VDD = 5 V
VDD = 5 V
0.7 VDD
−0.5
VIH
VIL
IIL
CIL
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
2.1
CW
Shutdown Supply Current 8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High 9
Input Logic Low9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage9, 10
Supply Current
OTP Supply Current9, 11, 12
Power Dissipation 13
Power Supply Sensitivity
VDD_RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
PSS
DYNAMIC CHARACTERISTICS 14
Bandwidth, −3 dB
Total Harmonic Distortion
BW
THDW
±0.1
±0.6
15
−5.5
4.5
200
+1.5
+2
0
12
VDD
45
V
pF
60
pF
0.01
1
1
μA
nA
VDD + 0.5
+0.3 VDD
V
V
0.6
±1
V
V
μA
pF
5
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.0 V, TA = 25°C
VIH = 5 V or VIL = 0 V, VDD = 5 V
VDD = 5 V ± 10%,
code = midscale
Code = 0x80
VA = 1 V rms, VB = 0 V,
f = 1 kHz
Rev. H | Page 3 of 24
2.7
5.6
LSB
LSB
ppm/°C
LSB
LSB
5.7
3.5
100
±0.02
4.8
0.1
5.5
5.8
6
33
±0.08
V
V
μA
mA
μW
%/%
MHz
%
AD5172/AD5173
Parameter
VW Settling Time
Resistor Noise Voltage Density
Symbol
tS
eN_WB
Conditions
VA = 5 V, VB = 0 V, ±1 LSB
error band
RWB = 1.25 kΩ, RS = 0 Ω
Typ 1
1
Min
Max
3.2
Unit
μs
nV/√Hz
1
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
2
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance 3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE 4
Differential Nonlinearity 5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range 6
Capacitance A, B 7
Capacitance W7
Shutdown Supply Current 8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High 9
Input Logic Low9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance7
Symbol
Conditions
Min
Typ 1
Max
Unit
R-DNL
R-INL
ΔRAB
(ΔRAB/RAB)/ΔT
RWB
RWB, VA = no connect
RWB, VA = no connect
TA = 25°C
−1
−2.5
−20
±0.1
±0.25
+1
+2.5
+20
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔVW/VW)/ΔT
VWFSE
VWZSE
VA, VB, VW
CA, CB
35
160
Code = 0x00, VDD = 5 V
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
GND
IA_SD
ICM
f = 1 MHz, measured to
GND, code = 0x80
f = 1 MHz, measured to
GND, code = 0x80
VDD = 5.5 V
VA = VB = VDD/2
VIH
VIL
VDD = 5 V
VDD = 5 V
0.7 VDD
−0.5
VIH
VIL
IIL
CIL
VDD = 3 V
VDD = 3 V
VIN = 0 V or 5 V
2.1
CW
±0.1
±0.3
15
−1
1
+1
+1
0
2.5
VDD
LSB
LSB
ppm/°C
LSB
LSB
45
V
pF
60
pF
0.01
1
5
Rev. H | Page 4 of 24
200
1
μA
nA
VDD + 0.5
+0.3 VDD
V
V
0.6
±1
V
V
μA
pF
AD5172/AD5173
Parameter
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage9, 10
Supply Current
OTP Supply Current9, 11, 12
Power Dissipation 13
Symbol
VDD_RANGE
VDD_OTP
IDD
IDD_OTP
PDISS
Power Supply Sensitivity
PSS
DYNAMIC CHARACTERISTICS 14
Bandwidth, −3 dB
BW
Total Harmonic Distortion
THDW
VW Settling Time
tS
Resistor Noise Voltage Density
eN_WB
Conditions
TA = 25°C
VIH = 5 V or VIL = 0 V
VDD_OTP = 5.0 V, TA = 25°C
VIH = 5 V or VIL = 0 V,
VDD = 5 V
VDD = 5 V ± 10%,
code = midscale
RAB = 10 kΩ, code = 0x80
RAB = 50 kΩ, code = 0x80
RAB = 100 kΩ, code = 0x80
VA = 1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = 5 V, VB = 0 V, ±1 LSB
error band
RWB = 5 kΩ, RS = 0 Ω
1
Min
2.7
5.6
Typ 1
5.7
3.5
100
±0.02
Max
Unit
5.5
5.8
6
33
V
V
μA
mA
μW
±0.08
%/%
600
100
40
0.1
kHz
kHz
kHz
%
2
μs
9
nV/√Hz
Typical specifications represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
VA = VDD, VB = 0 V, wiper (VW) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.
However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use VDD = 5 V.
2
Rev. H | Page 5 of 24
AD5172/AD5173
TIMING CHARACTERISTICS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS 1
SCL Clock Frequency
Bus-Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA
Symbol
fSCL
t1
t2
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT 2
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
OTP Program Time
1
2
Conditions
Min
After this period, the first clock
pulse is generated.
t3
t4
t5
t6
t7
t8
t9
t10
t11
Typ
Max
Unit
400
kHz
μs
μs
1.3
0.6
1.3
0.6
0.6
μs
μs
μs
μs
ns
ns
ns
μs
ms
0.9
100
300
300
0.6
400
See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).
The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
t8
t6
t2
t9
SCL
t2
t4
t3
t8
t7
t10
t5
t9
t1
P
S
S
2
Figure 3. I C Interface Detailed Timing Diagram
Rev. H | Page 6 of 24
P
04103-0-039
SDA
AD5172/AD5173
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to GND
VA, VB, VW to GND
Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx 1
Pulsed
Continuous
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Thermal Resistance 2
θJA for 10-Lead MSOP
Rating
−0.3 V to +7 V
VDD
±20 mA
±5 mA
0 V to 7 V
−40°C to +125°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
260°C
20 sec to 40 sec
200°C/W
1
The maximum terminal current is bound by the maximum current handling
of the switches, the maximum power dissipation of the package, and the
maximum applied voltage across any two of the A, B, and W terminals at a
given resistance.
2
The package power dissipation is (TJMAX − TA)/θJA.
Rev. H | Page 7 of 24
AD5172/AD5173
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
W2 3
GND 4
VDD 5
B1 1
10 W1
AD5172
9
B2
AD0 2
TOP VIEW
(Not to Scale)
8
A2
W2 3
7
SDA
6
SCL
GND 4
04103-045
A1 2
VDD 5
Figure 4. AD5172 Pin Configuration
10 W1
AD5173
9
B2
TOP VIEW
(Not to Scale)
8
AD1
7
SDA
6
SCL
04103-046
B1 1
Figure 5. AD5173 Pin Configuration
Table 5. AD5172 Pin Function Descriptions
Table 6. AD5173 Pin Function Descriptions
Pin
No.
1
2
3
4
5
Mnemonic
B1
A1
W2
GND
VDD
Pin
No.
1
2
Mnemonic
B1
AD0
3
4
5
W2
GND
VDD
6
SCL
6
SCL
7
SDA
8
AD1
9
10
B2
W1
7
8
9
10
SDA
A2
B2
W1
Description
B1 Terminal. GND ≤ VB1 ≤ VDD.
A1 Terminal. GND ≤ VA1 ≤ VDD.
W2 Terminal. GND ≤ VW2 ≤ VDD.
Digital Ground.
Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, VDD needs to be a minimum
of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum
is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up
resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the VIH minimum is 0.7 V × VDD.
A2 Terminal. GND ≤ VA2 ≤ VDD.
B2 Terminal. GND ≤ VB2 ≤ VDD.
W1 Terminal. GND ≤ VW1 ≤ VDD.
Rev. H | Page 8 of 24
Description
B1 Terminal. GND ≤ VB1 ≤ VDD.
Programmable Address Bit 0 for Multiple
Package Decoding.
W2 Terminal. GND ≤ VW2 ≤ VDD.
Digital Ground.
Positive Power Supply. Specified for
operation from 2.7 V to 5.5 V. For OTP
programming, VDD needs to be a minimum
of 5.6 V but no more than 5.8 V and to be
capable of driving 100 mA.
Serial Clock Input. Positive-edge triggered.
Requires a pull-up resistor. If this pin is driven
directly from a logic controller without a
pull-up resistor, ensure that the VIH minimum
is 0.7 V × VDD.
Serial Data Input/Output. Requires a pull-up
resistor. If this pin is driven directly from a
logic controller without a pull-up resistor,
ensure that the VIH minimum is 0.7 V × VDD.
Programmable Address Bit 1 for Multiple
Package Decoding.
B2 Terminal. GND ≤ VB2 ≤ VDD.
W1 Terminal. GND ≤ VW1 ≤ VDD.
AD5172/AD5173
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
2.0
TA = 25°C
RAB = 10kΩ
VDD = 2.7V
0.5
0
VDD = 5.5V
–0.5
–1.0
0
32
64
96
128
160
192
224
–0.2
–0.3
0
32
64
96
128
160
192
CODE (DECIMAL)
Figure 6. R-INL vs. Code vs. Supply Voltages
Figure 9. DNL vs. Code vs. Temperature
224
256
1.0
TA = 25°C
RAB = 10kΩ
VDD = 2.7V
0.1
0
–0.1
–0.2
VDD = 5.5V
–0.3
0
32
64
96
128
160
192
224
0.6
0.4
VDD = 5.5V
0.2
0
VDD = 2.7V
–0.2
–0.4
–0.6
04103-007
POTENTIOMETER MODE INL (LSB)
0.3
0.2
TA = 25°C
RAB = 10kΩ
0.8
04103-004
RHEOSTAT MODE DNL (LSB)
–0.1
–0.5
256
–0.4
–0.8
–1.0
256
0
32
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 7. R-DNL vs. Code vs. Supply Voltages
Figure 10. INL vs. Code vs. Supply Voltages
256
0.5
0.5
RAB = 10kΩ
0.3
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
0.2
0.1
0
–0.1
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
–0.2
04103-005
–0.3
–0.4
0
32
64
96
128
160
192
224
TA = 25°C
RAB = 10kΩ
0.4
POTENTIOMETER MODE DNL (LSB)
0.4
POTENTIOMETER MODE INL (LSB)
VDD = 2.7V; TA = –40°C, +25°C, +85°C, +125°C
0
CODE (DECIMAL)
0.4
–0.5
0.1
–0.4
0.5
–0.5
0.2
0.3
0.2
0.1
VDD = 2.7V
0
–0.1
VDD = 5.5V
–0.2
–0.3
04103-008
–2.0
04103-003
–1.5
0.3
04103-006
1.0
RAB = 10kΩ
0.4
POTENTIOMETER MODE DNL (LSB)
RHEOSTAT MODE INL (LSB)
1.5
–0.4
–0.5
256
0
32
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 8. INL vs. Code vs. Temperature
Figure 11. DNL vs. Code vs. Supply Voltages
Rev. H | Page 9 of 24
256
AD5172/AD5173
4.50
2.0
RAB = 10kΩ
1.0
0.5
0
VDD = 5.5V
TA = –40°C, +25°C, +85°C, +125°C
–0.5
–1.0
0
32
64
96
128
160
192
224
VDD = 2.7V, VA = 2.7V
1.50
VDD = 5.5V, VA = 5.0V
0.75
–25
–10
5
20
35
50
65
80
110
TEMPERATURE (°C)
Figure 12. R-INL vs. Code vs. Temperature
Figure 15. Zero-Scale Error vs. Temperature
125
10
RAB = 10kΩ
0.2
IDD, SUPPLY CURRENT (µA)
0.3
VDD = 2.7V, 5.5V; TA = –40°C, +25°C, +85°C, +125°C
0.1
0
–0.1
–0.2
04103-010
–0.3
–0.4
0
32
64
96
128
160
192
224
VDD = 5V
1
VDD = 3V
0.1
–40
256
–7
26
59
92
TEMPERATURE (°C)
Figure 13. R-DNL vs. Code vs. Temperature
Figure 16. Supply Current vs. Temperature
120
RAB = 10kΩ
1.0
0.5
0
VDD = 5.5V, VA = 5.0V
–0.5
VDD = 2.7V, VA = 2.7V
–1.0
04103-011
–1.5
–25
–10
5
20
35
50
65
80
95
110
100
80
40
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
20
0
–20
125
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
60
04103-014
1.5
RHEOSTAT MODE TEMPCO (ppm/°C)
RAB = 10kΩ
–2.0
–40
125
CODE (DECIMAL)
2.0
FSE, FULL-SCALE ERROR (LSB)
95
CODE (DECIMAL)
0.4
RHEOSTAT MODE DNL (LSB)
2.25
0
–40
256
0.5
–0.5
3.00
04103-013
–2.0
04103-009
–1.5
3.75
04103-012
ZSE, ZERO-SCALE ERROR (LSB)
RHEOSTAT MODE INL (LSB)
RAB = 10kΩ
VDD = 2.7V
TA = –40°C, +25°C, +85°C, +125°C
1.5
0
32
64
96
128
160
192
224
TEMPERATURE (°C)
CODE (DECIMAL)
Figure 14. Full-Scale Error vs. Temperature
Figure 17. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
Rev. H | Page 10 of 24
256
AD5172/AD5173
0
RAB = 10kΩ
0x80
–6
40
0x40
–12
30
GAIN (dB)
20
0x20
–18
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
10
0
0x10
–24
0x08
–30
0x04
–36
0x02
–42
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
–20
–30
0
32
64
96
128
160
192
224
0x01
–48
04103-050
–10
04103-047
POTENTIOMETER MODE TEMPCO (ppm/°C)
50
–54
–60
256
1k
10k
Figure 18. AD5172 Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
Figure 21. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
0
0x80
0x40
–12
0x20
–18
0x80
–6
0x40
–12
0x20
–18
0x10
–24
0x08
0x04
–30
GAIN (dB)
–36
0x02 0x01
–42
0x10
–24
0x08
–30
0x04
–36
0x02
–42
0x01
04103-048
–54
–60
10k
100k
1M
04103-051
–48
–48
–54
–60
1k
10M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 22. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
0
0x80
–6
–6
–12
0x40
–12
–18
0x20
–18
GAIN (dB)
0x10
–24
0x08
–30
0x04
–36
0x02
0x01
–42
100kΩ
60kHz
50kΩ
120kHz
–24
10kΩ
570kHz
2.5kΩ
2.2MHz
–30
–36
–42
–48
04103-049
–48
–54
–60
1k
10k
100k
04103-052
GAIN (dB)
1M
FREQUENCY (Hz)
–6
GAIN (dB)
100k
CODE (DECIMAL)
–54
–60
1k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 20. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 23. −3 dB Bandwidth at Code = 0x80
Rev. H | Page 11 of 24
10M
AD5172/AD5173
10
1
VDD = 5.5V
VW2
0.1
VDD = 2.7V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
04103-056
04103-057
0.01
VW1
5.0
DIGITAL INPUT VOLTAGE (V)
Figure 24. Supply Current vs. Digital Input Voltage
Figure 27. Analog Crosstalk
VW
VW
04103-053
04103-058
SCL
Figure 25. Digital Feedthrough
Figure 28. Midscale Glitch, Code 0x80 to Code 0x7F
VW2
VW
VW1
SCL
04103-055
04103-054
IDD, SUPPLY CURRENT (mA)
TA = 25°C
Figure 26. Digital Crosstalk
Figure 29. Large-Signal Settling Time
Rev. H | Page 12 of 24
AD5172/AD5173
T
CHANNEL 1
MAXIMUM:
103mA
CHANNEL 1
MINIMUM:
–1.98mA
04103-062
1
CH1 20.0mA
M 200ns
A CH1
T
588.000ns
32.4mA
Figure 30. OTP Program Energy for Single Fuse
Rev. H | Page 13 of 24
AD5172/AD5173
TEST CIRCUITS
Figure 31 to Figure 38 illustrate the test circuits that define the test conditions used in the product specification tables (see Table 1 and Table 2).
W
B
AD8610
OFFSET
GND
VMS
B
2.5V
Figure 31. Potentiometer Divider Nonlinearity Error (INL, DNL)
A
Figure 35. Test Circuit for Gain vs. Frequency
RSW =
DUT
IW
0.1V
ISW
CODE = 0x00
W
W
0.1V
ISW
B
VMS
B
GND TO VDD
04103-016
NC = NO CONNECT
VOUT
–5V
NC
DUT
+5V
DUT
W
04103-019
V+
VIN
04103-015
A
A
V+ = VDD
1LSB = V+/2N
04103-020
DUT
Figure 36. Incremental On Resistance
Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL)
NC
DUT
VDD
A
DUT
VW
I W = VDD /R NOMINAL
GND B
B
RW = [VMS1 – VMS2]/I W
NC
04103-017
VMS1
NC = NO CONNECT
Figure 33. Wiper Resistance
Figure 37. Common-Mode Leakage Current
A1
RDAC1
VA
VDD
A
V+
B
W
V+ = VDD ± 10%
ΔVMS
PSRR (dB) = 20 log
ΔVDD
ΔVMS%
PSS (%/%) =
ΔVDD%
(
VMS
)
VIN
NC
VDD
A2
RDAC2
W1
W2
B1
04103-018
DUT
VCM
VSS
CTA = 20 log[VOUT/VIN]
NC = NO CONNECT
Figure 38. Analog Crosstalk
Figure 34. Power Supply Sensitivity (PSS, PSSR)
Rev. H | Page 14 of 24
VOUT
B2
04103-022
W
ICM
04103-021
A
VMS2
W
AD5172/AD5173
THEORY OF OPERATION
A
SCL
I2C INTERFACE
SDA
DECODER
MUX
DAC
REG
W
B
COMPARATOR
FUSES
EN
FUSE
REG
04103-026
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 39. Detailed Functional Block Diagram
The AD5172/AD5173 are 256-position, digitally controlled
variable resistors (VRs) that employ fuse link technology to
achieve memory retention of the resistance setting.
Table 7. Validation Status
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5172/AD5173 presets to midscale
during initial power-on. After the wiper is set to the desired
position, the resistance can be permanently set by programming
the T bit high, with the proper coding (see Table 8 and Table 9),
and one-time VDD_OTP. The fuse link technology of the AD517x
family of digital potentiometers requires VDD_OTP to be between
5.6 V and 5.8 V to blow the fuses to achieve a given nonvolatile
setting. However, during operation, VDD can be 2.7 V to 5.5 V. As a
result, an external supply is required for one-time programming.
The user is allowed only one attempt to blow the fuses. If the user
fails to blow the fuses during this attempt, the structure of the
fuses can change such that they may never be blown, regardless
of the energy applied during subsequent events. For details, see
the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 39
shows a detailed functional block diagram.
E0
0
0
1
1
Status
Ready for programming.
Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.
Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance (RAB) of the VR has 256 contact points
accessed by the wiper terminal and the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the
256 possible settings.
A
A
W
B
A
W
B
W
B
04103-027
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function is activated, the device
powers up at the user-defined permanent setting.
E1
0
1
Figure 40. Rheostat Mode Configuration
Assuming a 10 kΩ part is used, the first connection of the wiper
starts at the B terminal for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between Terminal W and Terminal B. The second connection is the first tap point, which
corresponds to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 ×
50 Ω) for Data 0x01. The third connection is the next tap point,
representing 178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so
on. Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Rev. H | Page 15 of 24
AD5172/AD5173
When RAB is 10 kΩ and the B terminal is open circuited, the
output resistance, RWA, is set according to the RDAC latch
codes, as listed in Table 9.
A
RS
RS
Table 9. Codes and Corresponding RWA Resistance
D (Dec)
255
128
1
0
RS
W
B
04103-028
LATCH
AND
DECODER
PROGRAMMING THE POTENTIOMETER DIVIDER
Figure 41. AD5172/AD5173 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between W and B is
RWB (D ) =
D
× R AB + 2 × RW
128
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
The digital potentiometer easily generates a voltage divider at
wiper to B and at wiper to A, proportional to the input voltage
at A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
W
VO
B
Table 8. Codes and Corresponding RWB Resistance
RWB (Ω)
9961
5060
139
100
Voltage Output Operation
VI
In summary, if RAB is 10 kΩ and the A terminal is open circuited,
the output resistance, RWB, is set according to the RDAC latch
codes, as listed in Table 8.
D (Dec)
255
128
1
0
Output State
Full scale
Midscale
1 LSB
Zero scale
Typical device-to-device matching is process-lot dependent
and can vary up to ±30%. Because the resistance element is
processed using thin-film technology, the change in RAB with
temperature has a very low temperature coefficient of 35 ppm/°C.
RS
RDAC
RWA (Ω)
139
5060
9961
10,060
Output State
Full scale (RAB – 1 LSB + RW)
Midscale
1 LSB
Zero scale (wiper contact resistance)
04103-029
D7
D6
D5
D4
D3
D2
D1
D0
Figure 42. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper to B, starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the
256 positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
VW (D) =
D
256 − D
V +
VB
256 A
256
(3)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact may occur.
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Unlike in
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RWA and RWB, not on the absolute
values. Therefore, the temperature drift reduces to 15 ppm/°C.
RWA (D ) =
256 – D
× R AB + 2 × RW
128
VW (D) =
(2)
Rev. H | Page 16 of 24
R (D )
RWB (D)
VA + WA
VB
R AB
R AB
(4)
AD5172/AD5173
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as
shown in Figure 43 and Figure 44.
GND
LOGIC
04103-030
340Ω
rack-mount power supply) must be rated at 5.6 V to 5.8 V and
must be able to provide a 100 mA transient current for 400 ms
for successful one-time programming. When programming
is completed, the VDD_OTP supply must be removed to allow
normal operation at 2.7 V to 5.5 V; the device consumes only
microamps of current.
APPLY FOR OTP ONLY
5.7V
R1
10kΩ
Figure 43. ESD Protection of Digital Pins
VDD
2.7V
A, B, W
04103-031
AD5172/
AD5173
P1 = P2 = FDV302P, NDS0610
Figure 44. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
Figure 46. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
The AD5172/AD5173 VDD to GND power supply defines the
boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or GND are
clamped by the internal forward-biased diodes (see Figure 45).
VDD
A
W
04103-032
B
GND
P2
C2
0.1µF
04103-035
GND
P1
C1
10µF
Figure 45. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 45), it
is important to power VDD/GND before applying voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally and
may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, digital inputs, and then VA/VB/VW. The
relative order of powering VA, VB, VW, and the digital inputs is
not important, as long as they are powered after VDD/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time programming and normal operating voltage supplies are applied to
the same VDD terminal of the device. The AD5172/AD5173
employ fuse link technology that requires 5.6 V to 5.8 V to blow
the internal fuses to achieve a given setting, but normal VDD can
be 2.7 V to 5.5 V. Such dual-voltage requirements need isolation
between the supplies if VDD is lower than the required VDD_OTP.
The fuse programming supply (either an on-board regulator or
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-channel MOSFETs is recommended for the isolation of the supply. As shown in Figure 46,
this assumes that the 2.7 V system voltage is applied first and
that the P1 and P2 gates are pulled to ground, thus turning on
P1 and then P2. As a result, VDD of the AD5172/AD5173
approaches 2.7 V. When the AD5172/AD5173 setting is found,
the factory tester applies the VDD_OTP to both the VDD and the
MOSFET gates, thus turning P1 and P2 off. To program the
AD5172/AD5173 while the 2.7 V source is protected, execute
the OTP command at this time. When the OTP is completed,
the tester withdraws the VDD_OTP, and the setting of the AD5172
or AD5173 is fixed permanently.
The AD5172/AD5173 achieve the OTP function by blowing
internal fuses. Always apply the 5.6 V to 5.8 V one-time program voltage requirement at the first fuse programming attempt.
Failure to comply with this requirement may lead to changing
the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD + 0.5 V.
Poor PCB layout introduces parasitics that can affect fuse
programming. Therefore, it is recommended to add a 1 μF to
10 μF tantalum capacitor in parallel with a 1 nF ceramic capacitor
as close as possible to the VDD pin. The type and value chosen for
both capacitors are important. These capacitors work together to
provide both fast responsiveness and large supply current handling
with minimum supply droop during transients. As a result,
these capacitors increase the OTP programming success by not
inhibiting the proper energy needed to blow the internal fuses.
Additionally, C1 minimizes transient disturbance and low
frequency ripple, whereas C2 reduces high frequency noise
during normal operation.
Rev. H | Page 17 of 24
AD5172/AD5173
LAYOUT CONSIDERATIONS
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
VDD
C1
10µF
+
C2
0.1µF
VDD
AD5172
GND
04103-036
In PCB layout, it is a good practice to employ compact, minimum
lead length design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths should
have low resistance and low inductance.
Figure 47. Power Supply Bypassing
Rev. H | Page 18 of 24
AD5172/AD5173
I2C INTERFACE
WRITE MODE
Table 10. AD5172 Write Mode
S
0
1
W
A
A0 SD
T 0 OW X
Instruction byte
X
X
A
D7 D6 D5 D4 D3 D2 D1 D0
Data byte
A
P
0 1 1 AD1 AD0 W
Slave address byte
A
A0 SD
T 0 OW X
Instruction byte
X
X
A
D7 D6 D5 D4 D3 D2 D1 D0
Data byte
A
P
R
A
D7 D6 D5 D4 D3 D2 D1 D0
Instruction byte
A
E1 E0
X
X X X
Data byte
X
X
A
P
0 1 1 AD1 AD0 R
Slave address byte
A
D7 D6 D5 D4 D3 D2 D1 D0
Instruction byte
A
E1 E0
X
X X X
Data byte
X
X
A
P
0 1 1 1
1
Slave address byte
Table 11. AD5173 Write Mode
S
0
1
READ MODE
Table 12. AD5172 Read Mode
S
0
1
0 1 1 1
1
Slave address byte
Table 13. AD5173 Read Mode
S
0
1
Table 14. SDA Bits Descriptions
Bit
S
P
A
AD0, AD1
X
W
R
A0
SD
T
OW
D7, D6, D5, D4, D3, D2, D1, D0
E1, E0
Description
Start condition.
Stop condition.
Acknowledge.
Package pin-programmable address bits.
Don’t care.
Write.
Read.
RDAC subaddress select bit.
Shutdown connects wiper to B terminal and open circuits the A terminal. It does not change the
contents of the wiper register.
OTP programming bit. Logic 1 programs the wiper permanently.
Overwrites the fuse setting and programs the digital potentiometer to a different setting. Upon
power-up, the digital potentiometer is preset to either midscale or fuse setting, depending on
whether the fuse link was blown.
Data bits.
OTP validation bits.
00 = ready to program.
10 = fatal error. Some fuses not blown. Do not retry. Discard this unit.
11 = programmed successfully. No further adjustments are possible.
Rev. H | Page 19 of 24
AD5172/AD5173
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
1
9
9
1
9
1
SCL
0
1
0
1
1
1
1
R/W
A0
SD
T
0
OW
X
X
X
ACK BY
AD5172
START BY
MASTER
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5172
ACK BY
AD5172
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
STOP BY
MASTER
FRAME 3
DATA BYTE
04103-040
SDA
Figure 48. Writing to the RDAC Register—AD5172
1
9
9
1
9
1
SCL
0
1
0
1
1
AD1 AD0 R/W
A0
SD
T
0
OW
X
X
ACK BY
AD5173
START BY
MASTER
X
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5173
ACK BY
AD5173
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
STOP BY
MASTER
FRAME 3
DATA BYTE
04103-041
SDA
Figure 49. Writing to the RDAC Register—AD5173
Read Bit Patterns
1
9
9
1
9
1
SCL
0
1
0
1
1
1
1 R/W
D7
D6
D5
D4
D3
D2
D1
ACK BY
AD5172
START BY
MASTER
D0
E1
E0
X
X
X
X
X
X
NO ACK
BY MASTER
ACK BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
FRAME 2
INSTRUCTION BYTE
STOP BY
MASTER
FRAME 3
DATA BYTE
04103-042
SDA
Figure 50. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172
1
9
9
1
9
1
SCL
0
1
0
1
1 AD1 AD0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK BY
AD5173
START BY
MASTER
FRAME 1
SLAVE ADDRESS BYTE
D0
E1
E0
X
X
X
FRAME 2
INSTRUCTION BYTE
FRAME 3
DATA BYTE
Figure 51. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173
Rev. H | Page 20 of 24
X
X
X
NO ACK
BY MASTER
ACK BY
MASTER
STOP BY
MASTER
04103-043
SDA
AD5172/AD5173
I2C-COMPATIBLE, 2-WIRE SERIAL BUS
This section describes how the 2-wire, I2C-compatible serial bus
protocol operates.
The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high (see Figure 48 and Figure 49).
The following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit determines
whether data is read from or written to the slave device). The
AD5172 has a fixed slave address byte, whereas the AD5173
has two configurable address bits, AD0 and AD1 (see Figure 48
and Figure 49).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its serial register. If the
R/W bit is high, the master reads from the slave device. If the
R/W bit is low, the master writes to the slave device.
In write mode, the second byte is the instruction byte. The first
bit (MSB) of the instruction byte is the RDAC subaddress select
bit. Logic low selects Channel 1; logic high selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A while shorting the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. It is important to note that the shutdown
operation does not disturb the contents of the register. When
brought out of shutdown, the previous setting is applied to the
RDAC. In addition, during shutdown, new settings can be
programmed. When the part is returned from shutdown, the
corresponding VR setting is applied to the RDAC.
The third MSB, T, is the OTP programming bit. A logic high
blows the polyfuses and programs the resistor setting permanently.
The OTP program time is 400 ms.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic high,
OW allows the RDAC setting to be changed even after the internal
fuses are blown. However, when OW is returned to Logic 0, the
position of the RDAC returns to the setting prior to the overwrite.
Because OW is not static, if the device is powered off and on,
the RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses had been
permanently set.
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 3).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from the write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, transitions on the
SDA line must occur during the low period of SCL and remain
stable during the high period of SCL (see Figure 50 and Figure 51).
Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC values
of both channels, they must program the first channel in write
mode and then change to read mode to read the first channel
value. After that, the user must return to write mode with the
second channel selected and read the second channel value in
read mode. It is not necessary for users to issue the Frame 3
data byte in write mode for subsequent readback operations.
Refer to Figure 50 and Figure 51 for the programming format.
Following the data byte, the validation byte contains two validation bits, E0 and E1 (see Table 7). These bits signify the status of
the one-time programming (see Figure 50 and Figure 51).
After all data bits are read or written, the master establishes a
stop condition. A stop condition is defined as a low-to-high
transition on the SDA line while SCL is high. In write mode,
the master pulls the SDA line high during the 10th clock pulse to
establish a stop condition (see Figure 48 and Figure 49). In read
mode, the master issues a no acknowledge for the ninth clock
pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10th clock pulse and then brings the
SDA line high to establish a stop condition (see Figure 50 and
Figure 51).
A repeated write function provides the user with the flexibility
of updating the RDAC output multiple times after addressing
and instructing the part only once. For example, after the RDAC
has acknowledged its slave address and instruction bytes in write
mode, the RDAC output is updated on each successive byte. If
different instructions are needed, however, the write/read mode
must restart with a new slave address, instruction, and data byte.
Similarly, a repeated read function of the RDAC is also allowed.
The remainder of the bits in the instruction byte are don’t cares
(see Figure 48 and Figure 49).
Rev. H | Page 21 of 24
AD5172/AD5173
Multiple Devices on One Bus (AD5173 Only)
Figure 52 shows four AD5173 devices on the same serial bus.
Each has a different slave address because the states of the AD0
and AD1 pins are different. This allows each device on the bus to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully
I2C-compatible interface.
5V
RP
SDA
MASTER
SCL
5V
5V
5V
If the SCL and SDA signals come from a low voltage logic
controller and are below the minimum VIH level (0.7 V × VDD),
level shift the signals for read/write communications between
the AD5172/AD5173 and the controller. Figure 53 shows one
of the implementations. For example, when SDA1 is at 2.5 V,
M1 turns off, and SDA2 becomes 5 V. When SDA1 is at 0 V,
M1 turns on, and SDA2 approaches 0 V. As a result, proper
level shifting is established. It is best practice for M1 and M2
to be low threshold N-channel power MOSFETs, such as the
FDV301N from Fairchild Semiconductor.
VDD2 = 5V
VDD1 = 2.5V
SCL
AD1
SDA
SCL
AD1
SDA
SCL
SDA
AD1
RP
SCL
RP
RP
RP
AD1
AD0
AD0
AD0
AD0
AD5173
AD5173
AD5173
AD5173
04103-044
SDA
G
D
S
SDA1
2
Figure 52. Multiple AD5173 Devices on One I C Bus
M1
SCL1
G
SDA2
D
S
SCL2
M2
2.5V
CONTROLLER
2.7V TO 5.5V
AD5172/
AD5173
Figure 53. Level Shifting for Different Voltage Operation
Rev. H | Page 22 of 24
04103-061
RP
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
AD5172/AD5173
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
6
5
5.15
4.90
4.65
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.05
1.10 MAX
0.33
0.17
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 54. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5172BRM2.5
AD5172BRM2.5-RL7
AD5172BRMZ2.5 2
AD5172BRM10
AD5172BRM10-RL7
AD5172BRMZ102
AD5172BRMZ10-RL72
AD5172BRM50
AD5172BRMZ502
AD5172BRMZ50-RL72
AD5172BRM100
AD5172BRMZ1002
AD5172BRMZ100-RL72
AD5173BRM2.5
AD5173BRM2.5-RL7
AD5173BRMZ2.52
AD5173BRMZ2.5-RL72
AD5173BRM10
AD5173BRM10-RL7
AD5173BRMZ102
AD5173BRMZ10-RL72
AD5173BRM50
AD5173BRM50-RL7
AD5173BRMZ502
AD5173BRMZ50-RL72
AD5173BRM100
AD5173BRM100-RL7
AD5173BRMZ1002
RAB (kΩ)
2.5
2.5
2.5
10
10
10
10
50
50
50
100
100
100
2.5
2.5
2.5
2.5
10
10
10
10
50
50
50
50
100
100
100
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
1
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
DCY
DCY
DCR
DCZ
DCZ
DCT
DCT
DCX
DCU
DCU
DCW
DCV
DCV
DCM
DCM
DCH
DCH
DCQ
DCQ
DCL
DCL
DCN
DCN
DCJ
DCJ
DCP
DCP
DCK
The part has a YWW or #YWW label and an assembly lot number label on the bottom side of the package. The Y shows the year that the part was made; for example,
Y = 5 means the part was made in 2005. WW shows the work week that the part was made.
2
Z = RoHS Compliant Part.
Rev. H | Page 23 of 24
AD5172/AD5173
NOTES
Purchase of licensed I2C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04103-0-4/09(H)
Rev. H | Page 24 of 24