AD AD5291BRUZ-100 256-/1024-position, digital potentiometer Datasheet

256-/1024-Position, Digital Potentiometers with
Maximum ±1% R-Tolerance Error and 20-TP Memory
AD5291/AD5292
FEATURES
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
FUNCTIONAL BLOCK DIAGRAM
VDD
RESET
POWER-ON
RESET
AD5291/
AD5292
VLOGIC
RDAC
REGISTER
SCLK
SYNC
SERIAL
INTERFACE
DATA
W
OTP
MEMORY
BLOCK
DIN
A
B
SDO
RDY
VSS
EXT_CAP
GND
07674-001
Single-channel, 256-/1024-position resolution
20 kΩ, 50 kΩ, and 100 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error (resistor
performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
±9 V to ±16.5 V dual-supply operation
SPI-compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory
Figure 1.
GENERAL DESCRIPTION
The AD5291 and AD5292 are single-channel, 256-/1024position digital potentiometers1 that combine industry leading
variable resistor performance with nonvolatile memory (NVM)
in a compact package. These devices are capable of operating
across a wide voltage range, supporting both dual supply
operation at ±10.5 V to ±16.5 V and single supply operation at
+21 V to +33 V, while ensuring less than 1% end-to-end resistor
tolerance error and offering 20-time programmable (20-TP)
memory.
The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.
1
The AD5291 and AD5292 device wiper settings are controllable
through the SPI digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
20-TP memory. The AD5291 and AD5292 do not require any
external voltage supply to facilitate fuse blow, and there are 20
opportunities for permanent programming. During 20-TP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
The AD5291 and AD5292 are available in a compact 14-lead
TSSOP package. The part is guaranteed to operate over the
extended industrial temperature range of −40°C to +105°C.
The terms digital potentiometer and RDAC are used interchangeably.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
AD5291/AD5292
TABLE OF CONTENTS
Features .............................................................................................. 1
20-TP Memory ........................................................................... 23
Applications....................................................................................... 1
Write Protection ......................................................................... 23
Functional Block Diagram .............................................................. 1
Basic Operation .......................................................................... 24
General Description ......................................................................... 1
20-TP Readback and Spare Memory Status ........................... 24
Revision History ............................................................................... 2
Shutdown Mode ......................................................................... 24
Specifications..................................................................................... 3
Resistor Performance Mode...................................................... 25
Electrical Characteristics—AD5291 .......................................... 3
Reset ............................................................................................. 25
Resistor Performance Mode Code Range ................................. 4
SDO Pin and Daisy-Chain Operation..................................... 25
Electrical Characteristics—AD5292 .......................................... 6
RDAC Architecture.................................................................... 25
Resistor Performance Mode Code Range ................................. 7
Programming the Variable Resistor......................................... 26
Interface Timing Specifications.................................................. 8
Programming the Potentiometer Divider............................... 26
Absolute Maximum Ratings.......................................................... 10
EXT_CAP Capacitor.................................................................. 27
Thermal Resistance .................................................................... 10
Terminal Voltage Operating Range ......................................... 27
ESD Caution................................................................................ 10
Applications Information .............................................................. 28
Pin Configuration and Function Descriptions........................... 11
High Voltage DAC...................................................................... 28
Typical Performance Characteristics ........................................... 12
Programmable Voltage Source with Boosted Output ........... 28
Test Circuits..................................................................................... 21
High Accuracy DAC .................................................................. 28
Theory of Operation ...................................................................... 22
Variable Gain Instrumentation Amplifier .............................. 28
Serial Data Interface................................................................... 22
Audio Volume Control .............................................................. 29
Shift Register ............................................................................... 22
Outline Dimensions ....................................................................... 30
RDAC Register............................................................................ 22
Ordering Guide .......................................................................... 30
REVISION HISTORY
9/10—Rev. C to Rev. D
Changes to SDO Pin and Daisy-Chain Operation Section....... 25
3/10—Rev. B to Rev. C
Changes to Revision History........................................................... 2
Changes to Figure 3 and Figure 4 Captions .................................. 9
3/10—Rev. A to Rev. B
Changes to Data Sheet Title ............................................................ 1
Changes to General Description Section ...................................... 1
Changes to Theory of Operation Section.................................... 22
12/09—Rev. 0 to Rev. A
Added 50 kΩ and 100 kΩ specifications .........................Universal
Changes to Features Section............................................................ 1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Added Table 3 ....................................................................................5
Changes to Table 4.............................................................................6
Changes to Table 5.............................................................................7
Added Table 6 ....................................................................................8
Change to Table 7 ..............................................................................8
Changes to Absolute Maximum Rating Section ........................ 10
Changes Table 9 .............................................................................. 11
Changes to Typical Performance Characteristics Section ........ 12
Changes to Ordering Guide .......................................................... 30
4/09—Revision 0: Initial Version
Rev. D | Page 2 of 32
AD5291/AD5292
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5291
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance (R-Perf Mode) 3
Nominal Resistor Tolerance (Normal Mode)
Resistance Temperature Coefficient 4
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
Differential Nonlinearity 5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient4
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range 6
Capacitance A, Capacitance B4
Capacitance W4
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
Input Logic Low4
Input Current
Input Capacitance4
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
Logic Supply Current
OTP Store Current4, 7
OTP Read Current4, 8
Power Dissipation 9
Power Supply Rejection Ratio
Symbol
Conditions
Min
N
R-DNL
R-INL
RWB, VA = NC
8
−1
−1
∆RAB/RAB
See Table 2, Table 3
−1
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
VA, VB, VW
CA, CB
±0.5
60
8
−0.5
−0.5
Code = half-scale; See Figure 41
Code = full scale
Code = zero scale
Max
Unit
+1
+1
Bits
LSB
LSB
+1
%
±7
35
Code = full-scale; See Figure 38
Code= zero scale
N
DNL
INL
Typ 1
%
ppm/°C
100
Ω
+0.5
+0.5
Bits
LSB
LSB
1.5
−2
0
ppm/°C
+0.25
2
LSB
LSB
VDD
85
V
pF
65
pF
±1
nA
VSS
ICM
f = 1 MHz, measured to GND,
code = half-scale
f = 1 MHz, measured to GND,
code = half-scale
VA = VB = VW
VIH
JEDEC compliant
VLOGIC = 2.7 V to 5.5 V
VIL
VLOGIC = 2.7 V to 5.5 V
0.8
V
IIL
CIL
VIN = 0 V or VLOGIC
±1
μA
pF
VOH
RPULL_UP = 2.2 kΩ to VLOGIC
VOL
RPULL_UP = 2.2 kΩ to VLOGIC
GND + 0.4 V
V
+1
μA
pF
33
±16.5
2
V
V
μA
μA
V
μA
mA
CW
2.0
V
5
VLOGIC − 0.4
V
−1
COL
5
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
ILOGIC_PROG
VSS = 0 V
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
ILOGIC_FUSE_READ
VIH = 5 V or VIL = GND
25
PDISS
PSRR
VIH = 5 V or VIL = GND
∆VDD/∆VSS = ±15 V ± 10%
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
8
VDD/VSS = ±16.5 V
VDD/VSS = ±16.5 V
Rev. D | Page 3 of 32
9
±9
−2
2.7
0.1
−0.1
1
25
0.103
0.039
0.021
5.5
10
mA
110
μW
%/%
AD5291/AD5292
Parameter
Symbol
Conditions
DYNAMIC CHARACTERISTICS5, 10
Bandwidth
BW
−3 dB, code = half-scale
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale,
board capacitance = 170 pF
Code = full-scale, normal mode
Code = full-scale, R-Perf mode
Code = half-scale, normal mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half-scale, R-Perf mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half-scale, TA = 25°C, 0 kHz
to 200 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Total Harmonic Distortion
VW Settling Time
THDW
tS
Resistor Noise Density
eN_WB
Min
Typ 1
Max
Unit
kHz
520
210
105
dB
−93
−101
−106
750
2.5
ns
μs
μs
2.5
7
14
μs
5
9
16
nV/√Hz
10
18
27
1
Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x02 to code 0xFF or between RWA at code 0xFD to
code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3
Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4
Guaranteed by design and characterization, not subject to production test.
5
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment.
7
Different from operating current; supply current for fuse program lasts approximately 550 μs.
8
Different from operating current; supply current for fuse read lasts approximately 550 μs.
9
PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10
All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2
RESISTOR PERFORMANCE MODE CODE RANGE
Table 2.
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
|VDD − VSS| = 30 V to 33 V
RWB
RWA
From 0x5A
From 0x00
to 0xFF
to 0xA5
From 0x23
From 0x00
to 0xFF
to 0xDC
From 0x1E
From 0x00
to 0xFF
to 0xE1
RAB = 20 kΩ
|VDD − VSS| = 26 V to 30 V
|VDD − VSS| = 22 V to 26 V
RWB
RWA
RWB
RWA
From 0x7D
From 0x00
From 0x7D
From 0x00
to 0xFF
to 0x82
to 0xFF
to 0x82
From 0x2D
From 0x00
From 0x23
From 0x00
to 0xFF
to 0xD2
to 0xFF
to 0xDC
From 0x19
From 0x00
From 0x17
From 0x00
to 0xFF
to 0xE6
to 0xFF
to 0xE8
Rev. D | Page 4 of 32
|VDD − VSS| = 21 V to 22 V
RWB
RWA
N/A
N/A
From 0x23
to 0xFF
From 0x17
to 0xFF
From 0x00
to 0xDC
From 0x00
to 0xE8
AD5291/AD5292
Table 3.
Resistor Tolerance
per Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
RAB = 50 kΩ
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWA
RWB
RWA
RWB
From 0x2A
From 0x00
From 0x37
From 0x00
to 0xFF
to 0xD5
to 0xFF
to 0xC8
From 0x11
From 0x00
From 0x16
From 0x00
to 0xFF
to 0xEE
to 0xFF
to 0xE9
From 0x0A
From 0x00
From 0x0D
From 0x00
to 0xFF
to 0xF5
to 0xFF
to 0xF2
Rev. D | Page 5 of 32
RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
From 0x1E
From 0x00
From 0x14
From 0x00
to 0xFF
to 0xE1
to 0xFF
to 0xEB
From 0x0A
From 0x00
From 0x0A
From 0x00
to 0xFF
to 0xF5
to 0xFF
to 0xF5
From 0x07
From 0x00
From 0x07
From 0x00
to 0xFF
to 0xF8
to 0xFF
to 0xF8
AD5291/AD5292
ELECTRICAL CHARACTERISTICS—AD5292
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS,
−40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance (R-Perf Mode) 3
Nominal Resistor Tolerance (Normal
Mode) 4
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
Differential Nonlinearity 5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient4
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance A, Capacitance B 6
Capacitance W5
Symbol
Conditions
Min
N
R-DNL
R-INL
RWB, VA = NC
RAB =50 kΩ, 100 kΩ
R-INL
R-INL
∆RAB/RAB
RAB =20 kΩ , |VDD − VSS| = 26 V to 33 V
RAB =20 kΩ , |VDD − VSS| = 21 V to 26 V
See Table 5 and Table 6
RW
4
Input Logic Low
Input Current
Input Capacitance4
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
Logic Supply Current
OTP Store Current6, 7
OTP Read Current6, 8
Power Dissipation 9
Power Supply Rejection Ratio6
Unit
10
−1
−2
+1
+2
Bits
LSB
LSB
−2
−3
−1
+2
+3
+1
LSB
LSB
%
Code = full scale; See Figure 38
Code= zero scale
N
DNL
INL
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
CA, CB
±0.5
±7
%
35
ppm/°C
60
10
−1
−1.5
Code = half scale; See Figure 41
Code = full scale
Code = zero scale
VA, VB, VW
ICM
f = 1 MHz, measured to GND,
code = half scale
f = 1 MHz, measured to GND,
code = half scale
VA = VB = VW
VIH
JEDEC compliant
VLOGIC = 2.7 V to 5.5 V
CW
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
Max
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
Typ 1
100
Ω
+1
+1.5
Bits
LSB
LSB
5
ppm/°C
−8
0
+1
8
LSB
LSB
VSS
VDD
V
85
pF
65
pF
±1
nA
2.0
V
VIL
VLOGIC = 2.7 V to 5.5 V
0.8
V
IIL
CIL
VIN = 0 V or VLOGIC
±1
μA
pF
VOH
RPULL_UP = 2.2 kΩ to VLOGIC
VOL
RPULL_UP = 2.2 kΩ to VLOGIC
GND + 0.4
V
+1
μA
pF
33
±16.5
2
V
V
μA
μA
V
μA
mA
5
VLOGIC − 0.4
V
−1
COL
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
ILOGIC_PROG
5
VSS = 0 V
VDD/VSS = ±16.5 V
VDD/VSS = ±16.5 V
9
±9
−2
2.7
0.1
−0.1
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
1
25
ILOGIC_FUSE_READ
VIH = 5 V or VIL = GND
25
PDISS
PSSR
VIH = 5 V or VIL = GND
∆VDD/∆VSS = ±15 V ± 10%
8
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Rev. D | Page 6 of 32
0.103
0.039
0.021
5.5
10
mA
110
μW
%/%
AD5291/AD5292
Parameter
Symbol
Conditions
DYNAMIC CHARACTERISTICS5, 10
Bandwidth
BW
−3 dB
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Total Harmonic Distortion
VW Settling Time
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale, board
capacitance = 170 pF
Code = full-scale, normal mode
Code = full-scale, R-Perf mode
Code = half-scale, normal mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half-scale, R-Perf mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half-scale, TA = 25°C, 0 kHz to
200 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
tS
Resistor Noise Density
Min
eN_WB
Typ 1
Max
Unit
kHz
520
210
105
dB
−93
−101
−106
750
2.5
ns
μs
μs
2.5
7
14
μs
5
9
16
nV/√Hz
10
18
27
1
Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x00B to code 0x3FF or between RWA at code 0x3F3 to
code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with
a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3
Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4
Guaranteed by design and characterization, not subject to production test.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment.
7
Different from operating current; supply current for fuse program lasts approximately 550 μs.
8
Different from operating current; supply current for fuse read lasts approximately 550 μs.
9
PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10
All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2
RESISTOR PERFORMANCE MODE CODE RANGE
Table 5.
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
|VDD − VSS| = 30 V to 33 V
RWB
RWA
From 0x15E From 0x000
to 0x3FF
to 0x2A1
From 0x8C
From 0x000
to 0x3FF
to 0x373
From 0x5A
From 0x000
to 0x3FF
to 0x3A5
RAB = 20 kΩ
|VDD − VSS| = 26 V to 30 V
|VDD − VSS| = 22 V to 26 V
RWB
RWA
RWB
RWA
From 0x1F4 From 0x000 From 0x1F4 From 0x000
to 0x3FF
to 0x20B
to 0x3FF
to 0x20B
From 0xB4
From 0x000 From 0xFA
From 0x000
to 0x3FF
to 0x34B
to 0x3FF
to 0x305
From 0x64
From 0x000 From 0x78
From 0x000
to 0x3FF
to 0x39B
to 0x3FF
to 0x387
Rev. D | Page 7 of 32
|VDD − VSS| = 21 V to 22 V
RWB
RWA
N/A
N/A
From 0xFA
to 0x3FF
From 0x78
to 0x3FF
From 0x000
to 0x305
From 0x000
to 0x387
AD5291/AD5292
Table 6.
Resistor
Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
RAB = 50 kΩ
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
From 0x08C From 0x000 From 0x0B4 From 0x000
to 0x3FF
to 0x35F
to 0x3FF
to 0x31E
From 0X03C From 0x000 From 0x050 From 0x000
to 0x3FF
to 0x3C3
to 0x3FF
to 0x3AF
From 0X028 From 0x000 From 0x032 From 0x000
to 0x3FF
to 0x3D7
to 0x3FF
to 0x3CD
RAB = 100 kΩ
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
From 0x04B From 0x000 From 0x064 From 0x000
to 0x3FF
to 0x3B4
to 0x3FF
to 0x39B
From 0x028 From 0x000 From 0x028 From 0x000
to 0x3FF
to 0x3D7
to 0x3FF
to 0x3D7
From 0x019 From 0x000 From 0x019 From 0x000
to 0x3FF
to 0x3E6
to 0x3FF
to 0x3E6
INTERFACE TIMING SPECIFICATIONS
VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10 4
t114
Limit 1
20
10
10
10
5
5
1
400 3
14
1
40
t124
t124
t
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
2.4
μs max
RDY low time, RDAC register write command execute time (R-Perf mode)
410
ns max
RDY low time, RDAC register write command execute time (normal mode)
8
ms max
RDY low time, memory program execute time
t124
1.5
ms min
Software/hardware reset
t134
450
ns max
RDY low time, RDAC register readback execute time
t134
1.3
ms max
RDY low time, memory readback execute time
t144
450
ns max
SCLK rising edge to SDO valid
tRESET
tPOWER-UP 5
20
2
ns min
ms max
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
124
1
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Maximum SCLK frequency is 50 MHz.
Refer to t12 and t13 for RDAC register and memory commands operations.
4
RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
5
Maximum time after VLOGIC is equal to 2.5 V.
2
3
0
0
C3
C2
C1
C0
D9
D8
DB0 (LSB)
D7
D6
D5
D4
DATA BITS
CONTROL BITS
Figure 2. Shift Register Content
Rev. D | Page 8 of 32
D3
D2
D1
D0
07674-003
DB9 (MSB)
AD5291/AD5292
Timing Diagrams
t4
SCLK
t2
t7
t1
t9
t3
t8
SYNC
t5
t6
X
X
C3
C2
D7
D6
D2
D1
D0
SDO
t11
t10
t12
RDY
tRESET
07674-004
DIN
RESET
Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1
SCLK
t9
SYNC
DIN
X
X
C3
D0
D0
X
X
C3
D1
D0
t14
X
t11
RDY
X
t13
Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1
Rev. D | Page 9 of 32
C3
D1
D0
07674-005
SDO
AD5291/AD5292
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 8.
Parameter
VDD to GND
VSS to GND
VLOGIC to GND
VDD to VSS
VA, VB, VW to GND
Digital Input and Output Voltage to GND
EXT_CAP Voltage to GND
IA, IB, IW
Continuous
RAB = 20 kΩ
RAB = 50 kΩ, 100 kΩ
Pulsed 1
Frequency > 10 kHz
Frequency ≤ 10 kHz
Operating Temperature Range 4
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
Rating
−0.3 V to +35 V
+0.3 V to − 25 V
−0.3 V to + 7 V
35 V
VSS − 0.3 V, VDD+ 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +7 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Table 9. Thermal Resistance
±3 mA
±2mA
Package Type
14-Lead TSSOP
MCC 2 /d 3
MCC2/√d3
−40°C to +105°C
150°C
−65°C to +150°C
1
θJA
931
θJC
20
JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow).
ESD CAUTION
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Maximum continuous current
3
Pulse duty factor.
4
Includes programming of OTP memory.
Rev. D | Page 10 of 32
Unit
°C/W
AD5291/AD5292
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET 1
A 3
W 4
B 5
14 RDY
AD5291/
AD5292
TOP VIEW
Not to Scale
13 SDO
12 SYNC
11 SCLK
10 DIN
VDD 6
9
GND
EXT_CAP 7
8
VLOGIC
07674-006
VSS 2
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
2
VSS
3
4
5
6
7
8
A
W
B
VDD
EXT_CAP
VLOGIC
9
10
GND
DIN
11
SCLK
12
SYNC
13
SDO
14
RDY
Description
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory
default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the
logic high transition. Tie RESET to VLOGIC if not used.
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF
ceramic capacitors and 10 μF capacitors.
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
Terminal B of RDAC. VSS ≤ VB ≤ VDD.
Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
Ground Pin, Logic Ground Reference.
Serial Data Input. The AD5291 and AD5292 have a 16-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 50 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The
selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high
before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the DAC.
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data
from the shift register in daisy-chain mode or in readback mode.
Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from
the RDAC register or memory.
Rev. D | Page 11 of 32
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
0.6
0.4
0.2
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.6
–0.8
128
256
384
512
640
768
896
1023
CODE (Decimal)
–1.0
07674-106
384
512
640
768
896
1023
0.6
TEMPERATURE = 25°C
0.5
0.4
0.4
0.3
0.3
DNL (LSB)
0.5
0.2
0.1
0.2
0.1
0
0
–0.1
–0.1
–0.2
–0.2
+105°C
384
512
640
768
896
1023
–0.3
07674-007
+25°C
–40°C
256
CODE (Decimal)
20kΩ
50kΩ
100kΩ
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
1.0
1.0
20kΩ
50kΩ
100kΩ
RAB = 20kΩ
0.8
0.8
0.6
0.6
0.4
TEMPERATURE = 25°C
INL (LSB)
0.4
0.2
0
0.2
0
–0.2
–0.2
–0.4
128
256
384
512
640
768
896
1023
CODE (Decimal)
–0.6
0
128
256
384
512
640
CODE (Decimal)
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292)
768
896
1023
07674-216
0
–0.4
+105°C
+25°C
–40°C
–0.6
07674-010
INL (LSB)
256
Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
RAB = 20kΩ
128
128
CODE (Decimal)
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0
0
07674-211
0
07674-215
–0.8
RAB = 20kΩ
–1.0
DNL (LSB)
0
–0.4
–0.3
TEMPERATURE = 2 5°C
0.6
0.4
0.6
20kΩ
50kΩ
100kΩ
0.8
INL (LSB)
INL (LSB)
1.0
–40°C
+25°C
+105°C
Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
Rev. D | Page 12 of 32
AD5291/AD5292
0.15
0.15
0.10
0.05
0.05
DNL (LSB)
0.10
0
–0.05
–0.15
–0.15
384
512
640
768
896
1023
CODE (Decimal)
Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292)
128
0.5
0.2
INL (LSB)
0.6
0
512
640
768
–0.2
–1.0
–0.6
256
384
512
640
768
896
1023
CODE (Decimal)
1023
TEMPERATURE = 25°C
20kΩ
50kΩ
100kΩ
+105°C
+25°C
–40°C
896
0
–0.5
128
384
0.8
1.0
0
256
Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
RAB = 20kΩ
–1.5
–0.8
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
0.6
0.6
RAB = 20kΩ
TEMPERATURE = 2 5°C
0.5
0.4
0.4
0.3
0.3
DNL (LSB)
0.5
0.2
0.1
0.2
0.1
0
0
–0.1
–0.2
0
128
256
384
512
640
768
20kΩ
50kΩ
100kΩ
–0.2
+105°C
+25°C
–40°C
896
1023
CODE (Decimal)
Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
–0.3
0
128
256
384
512
640
CODE (Decimal)
768
896
1023
07674-203
–0.1
07674-015
DNL (LSB)
0
CODE (Decimal)
07674-014
INL (LSB)
1.5
–0.20
07674-213
256
07674-207
128
+105°C
+25°C
–40°C
0
TEMPERATURE = 25°C
–0.05
–0.10
–0.20
20kΩ
50kΩ
100kΩ
0
–0.10
07674-011
DNL (LSB)
RAB = 20kΩ
Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Rev. D | Page 13 of 32
AD5291/AD5292
0.6
0.4
0.4
0.2
0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
128
256
384
512
640
768
896
1023
CODE (Decimal)
–0.8
07674-018
–0.8
384
512
640
768
896
1023
20kΩ
50kΩ
100kΩ
0.04
0
DNL (LSB)
–0.05
–0.04
–0.10
–0.08
–0.15
–0.12
128
256
384
512
640
768
896
1023
CODE (Decimal)
07674-019
0
0.30
0.25
0.20
0.20
0.15
0.15
0.10
0.10
INL (LSB)
0.25
0.05
0
–0.05
–0.10
512
640
768
896
1023
20kΩ
50kΩ
100kΩ
TEMPERATURE = 2 5°C
–0.15
64
96
128
160
192
224
255
CODE (Decimal)
Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
07674-008
RAB = 20kΩ
–0.20
32
384
0
–0.10
0
256
0.05
–0.05
–0.15
128
CODE (Decimal)
+105°C
+25°C
–40°C
0
Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292)
0.30
–0.16
07674-205
TEMPERATURE = 25°C
RAB = 20kΩ
–0.20
–0.20
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-218
DNL (LSB)
256
0.08
0
INL (LSB)
128
Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
–40°C
+25°C
+105°C
0.05
0
CODE (Decimal)
Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292)
0.10
TEMPERATURE = 2 5°C
0
–0.2
0
20kΩ
50kΩ
100kΩ
0.6
INL (LSB)
INL (LSB)
0.8
–40°C
+25°C
+105°C
RAB = 20kΩ
07674-209
0.8
Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. D | Page 14 of 32
AD5291/AD5292
0.14
RAB = 20kΩ
TEMPERATURE = 25°C
0.12
0.10
0.10
0.08
0.08
0.06
0.06
0.04
0.02
0.02
0
0
–0.02
–0.02
–0.04
–0.04
0
32
64
+105°C
+25°C
–40°C
–0.06
96
128
160
192
224
255
CODE (Decimal)
0.25
0
32
64
96
128
160
192
224
255
CODE (Decimal)
0.25
+105°C
+25°C
–40°C
–0.06
20kΩ
50kΩ
100kΩ
Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.20
0.20
0.15
0.15
INL (LSB)
INL (LSB)
0.04
07674-212
DNL (LSB)
0.12
07674-009
DNL (LSB)
0.14
0.10
0.05
0
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
0.10
0.05
0
–0.05
–0.05
0
32
64
96
128
160
192
224
255
CODE (Decimal)
Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291)
0.02
0.02
0.01
0.01
0
0
–0.02
64
96
128
160
192
224
255
Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
0.03
–0.01
32
CODE (Decimal)
+105°C
+25°C
–40°C
0
DNL (LSB)
DNL (LSB)
0.03
–0.10
07674-012
–0.10
07674-217
RAB = 20kΩ
–0.03
20kΩ
50kΩ
100kΩ
TEMPERATURE = 2 5°C
–0.01
–0.02
–0.03
–0.04
–0.04
0
32
64
96
128
160
CODE (Decimal)
192
224
255
–0.05
07674-013
–0.05
Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291)
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-214
RAB = 20kΩ
Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. D | Page 15 of 32
AD5291/AD5292
0.25
0.20
0.15
0.15
0.10
0.10
0.05
0.05
INL (LSB)
0.20
0
–0.05
–0.05
–0.10
–0.15
–0.15
20kΩ
50kΩ
100kΩ
–0.20
RAB = 20kΩ
–0.25
0
32
64
96
128
160
192
224
255
CODE (Decimal)
–0.25
0
32
64
96
128
160
192
224
255
CODE (Decimal)
Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.14
+105°C
TEMPERATURE = 2 5°C
0.12
0.10
0.10
0.08
0.08
0.06
0.06
DNL (LSB)
0.12
0.04
0.02
0.04
0.02
0
0
–0.02
–0.02
20kΩ
50kΩ
100kΩ
–0.04
–0.04
RAB = 20kΩ
0
32
64
96
128
160
192
224
255
CODE (Decimal)
0.20
0.15
0.10
0.10
0.05
0.05
INL (LSB)
0.15
0
–0.05
–0.10
–0.10
–0.15
–0.15
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291)
–0.20
07674-020
0
64
96
128
160
192
224
255
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
0
–0.05
–0.20
32
CODE (Decimal)
+105°C
+25°C
–40°C
0
Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.20
–0.06
07674-017
–0.06
07674-204
+25°C
–40°C
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-210
0.14
DNL (LSB)
0
–0.10
–0.20
INL (LSB)
TEMPERATURE = 2 5°C
07674-208
+105°C
+25°C
–40°C
07674-016
INL (LSB)
0.25
Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. D | Page 16 of 32
AD5291/AD5292
0.03
+105°C
+25°C
–40°C
TEMPERATURE = 25°C
0.02
0.02
0.01
0.01
0
0
DNL (LSB)
–0.01
–0.02
–0.03
–0.02
–0.03
–0.04
RAB = 20kΩ
32
64
96
128
160
192
224
255
–0.05
CODE (Decimal)
0
300
250
200
150
100
IDD
0
224
255
VDD = ±15V
0.16
0.14
0.12
0.1
0.08
0.06
0.04
ISS
0
07674-022
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
0
Figure 37. Supply Current (IDD, ISS, ILOGIC) vs. Temperature
700
POTENTIOMETER MODE TEMPCO (ppm/°C)
20kΩ
50kΩ
100kΩ
500
400
300
200
100
0
256
64
512
128
CODE (Decimal)
768
192
1.0
1.5
2.0
2.5
3.0
3.5
DIGITAL INPUT VOLTAGE (V)
700
VDD = 30V,
VSS= 0V
600
0.5
4.0
4.5
5.0
Figure 40. Supply Current ILOGIC vs. Digital Input Voltage
1023 AD5292
255 AD5291
VDD = 30V
VSS= 0V
20kΩ
50kΩ
100kΩ
600
500
400
300
200
100
07674-024
RHEOSTAT MODE TEMPCO (ppm/°C)
192
0.02
–50
–40 –30 –20 –10 0
0
0
160
0.18
ILOGIC
50
128
0.20
SUPPLY CURRENT I LOGIC (mA)
350
96
Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
VDD/VSS = ±15V
VLOGIC = +5V
400
64
CODE (Decimal)
Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
450
32
07674-031
0
07674-021
–0.05
20kΩ
50kΩ
100kΩ
07674-206
–0.04
SUPPLY CURRENT (nA)
–0.01
0
0
0
256
64
512
128
CODE (Decimal)
768
192
1023 AD5292
255 AD5291
Figure 41. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
Figure 38. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
Rev. D | Page 17 of 32
07674-023
DNL (LSB)
0.03
AD5291/AD5292
–5
–5
0x200 (0x80)
–10
0x100 (0x40)
–10
0x100 (0x40)
–15
0x080 (0x20)
–15
–20
0x080 (0x20)
–20
0x040 (0x10)
–25
–30
0x010 (0x04)
–40
0x008 (0x02)
0x010 (0x04)
–45
0x004 (0x01)
0x008 (0x02)
–50
–30
–35
0x020 ( 0x08)
–35
0x020 ( 0x08)
–40
0x002
–55
0x004 (0x01)
0x002
–50
10
0x001
–60
0x001
100
1k
10k
100k
1M
FREQUENCY (Hz)
–65
–67.5
1
07674-025
–45
0
10k
1M
100k
–20
0x080 (0x20)
0x040 (0x10)
PSRR (dB)
GAIN (dB)
1k
100kΩ
20kΩ
50kΩ
–10
–10 0x100 (0x40)
–20
100
Figure 45. 100 kΩ Gain vs. Frequency vs. Code
AD5292 (AD5291)
0x200 (0x80)
10
FREQUENCY (Hz)
Figure 42. 20 kΩ Gain vs. Frequency vs. Code
0
AD5292 (AD5291)
0x040 (0x10)
–25
GAIN (dB)
GAIN (dB)
0
AD5292 (AD5291)
0x200 (0x80)
07674-201
0
0x020 ( 0x08)
–30
0x010 (0x04)
–40
0x008 (0x02)
–30
–40
–50
0x004 (0x01)
–50
–60
1k
10k
100k
1M
FREQUENCY (Hz)
–70
100
0
VDD/VSS = ±15V
CODE = HALF SCALE
VIN = 1V rms
Noise BW = 22kHz
20kΩ
50kΩ
100kΩ
–40
–45
–60
–60
–80
–75
–100
–90
–120
–105
–120
100
–140
0.001
1k
10k
FREQUENCY (Hz)
1M
VDD/VSS = ±15V,
CODE = HALF SCALE
fIN = 1kHz
NOISE BW = 22kHz
20kΩ
50kΩ
100kΩ
–20
100k
07674-027
THD + N (dB)
–30
100k
Figure 46. Power Supply Rejection Ratio vs. Frequency
THD + N (dB)
–15
10k
FREQUENCY (Hz)
Figure 43. 50 kΩ Gain vs. Frequency vs. Code
0
1k
07674-026
100
Figure 44. THD + Noise vs. Frequency
0.01
0.1
1
AMPLITUDE (V rms)
Figure 47. THD + Noise vs. Amplitude
Rev. D | Page 18 of 32
10
07674-220
–60
10
0x001
07674-200
0x002
AD5291/AD5292
900,000
800,000
8
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
600,000
500,000
400,000
300,000
200,000
6
5
4
20kΩ
3
50kΩ
2
100kΩ
1
100,000
8
16
32
64
16
32
CODE (Decimal)
8
128
256
512 AD5292
128 AD5291
64
0
07674-222
0
0
0
0
256
64
Figure 48. Bandwidth vs Code vs Net Capacitance
512
128
CODE (Decimal)
768
192
1023 AD5292
255 AD5291
Figure 51. Theoretical Maximum Current vs. Code
35
1.2
30
VDD/VSS = ±15V
VLOGIC = +5V
VA = VDD
VB = VSS
1.0
25
0.8
20
0.6
VOLTAGE (V)
15
10
20kΩ
50kΩ
100kΩ
0.4
0.2
0
5
–0.2
0
–0.4
0
0.2
0.4
0.6
TIME (ms)
0.8
1.0
1.2
–0.8
–2
0
2
4
6
8
10
12
14
16
TIME (µs)
Figure 49. IDD Waveform While Blowing/Reading Fuse
35
Figure 52. Maximum Transition Glitch
40
VWB, CODE: FULL SCALE,
NORMAL MODE
VDD/VSS = 30V/0V
VLOGIC = 5V
VA = VDD
VB = VSS
24
16
VOLTAGE (μV)
VOLTAGE (V)
20
VWB, CODE: FULL SCALE,
R-PERF MODE
15
10
SYNC
0
–8
TIME (µs)
–24
–32
07674-033
15
13
12
11
9
10
8
7
6
4
3
2
1
0
–5
5
0
14
20kΩ
50kΩ
100kΩ
20kΩ
50kΩ
100kΩ
VWB, CODE: HALF-SCALE,
NORMAL MODE
VWB, CODE: HALF-SCALE,
R-PERF MODE
–1
8
–16
5
–2
VDD/VSS = ±15V
VA = VDD
VB = VSS
CODE = HALF CODE
32
30
25
07674-035
–0.2
07674-034
–0.6
–5
–0.4
Figure 50. 20kΩ Large-Signal Settling Time from Code Zero Scale
–40
–0.5
0
5
10
15
20
25
TIME (µs)
30
Figure 53. Digital Feedthrough
Rev. D | Page 19 of 32
35
40
45
07674-032
SUPPLY CURRENT I DD (mA)
BANDWIDTH (Hz)
700,000
0
VDD/VSS = 30V/0V
VA = VDD
VB = VSS
7
07674-029
20k – 0pF
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
50k – 75pF
THEORETICAL IWB_MAX (mA)
1,000,000
AD5291/AD5292
NUMBER OF CODES (AD5291)
3
2
1
TIME (ms)
Figure 54. VEXT_CAP Waveform While Reading Fuse Or Calibration
8
NUMBER OF CODES (AD5291)
2
07674-037
17.2
16.0
14.8
13.6
12.4
11.2
10.0
8.8
7.6
6.4
5.2
4.0
2.8
1.6
0.4
0
–0.8
150
25.0
100
12.5
50
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
VA = VDD
VB = VSS
TEMPERATURE = 25°C
20kΩ
50kΩ
17.5
3
–2.0
VOLTAGE (V)
37.5
20.0
VDD/VSS = ±15V
VLOGIC = +5V
TIME (ms)
200
0
Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature
6
–2
50.0
0
–40 –30 –20 –10 0
07674-036
8.6
8.0
7.4
6.8
6.2
5.6
5.0
4.4
3.8
3.2
2.6
2.0
1.4
0.8
0.2
–1.0
–0.4
0
250
100kΩ
80
70
15.0
60
12.5
50
10.0
40
7.5
30
5.0
20
2.5
10
0
21
0
26
30
33
VOLTAGE VDD/VSS
Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage
Figure 55. VEXT_CAP Waveform While Writing Fuse
Rev. D | Page 20 of 32
NUMBER OF CODES (AD5292)
VOLTAGE (V)
4
–1
20kΩ
50kΩ
100kΩ
62.5
NUMBER OF CODES (AD5292)
5
300
VDD/VSS = ±15V
07674-056
75.0
VDD/VSS = ±15V
VLOGIC = +5V
07674-219
6
AD5291/AD5292
TEST CIRCUITS
Figure 58 to Figure 63 define the test conditions used in the Specifications section.
NC
IW
VDD
B
A
V+ ~
VMS
W
B
07674-041
VMS
Figure 61. Power Supply Sensitivity (PSS, PSRR)
Figure 58. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
+15V
A
DUT
V+
VIN
W
W
DUT
B
VMS
2.5V
+15V
B
+
IWB
A = NC
–
RW =
GND
GND
0.1V
IWB
RWB
2
VDD
DUT
A
VSS GND
B
ICM
W
VSS TO VDD
+15V
–15V
GND
0.1V
NC
07674-043
CODE = 0x00
W
–15V
–15V
NC
RWB=
VOUT
Figure 62. Gain vs. Frequency
Figure 59. Potentiometer Divider Nonlinearity Error
(INL, DNL)
DUT
OP42
B
OFFSET
GND
07674-042
A
V+ = VDD
1LSB = V+/2N
07674-047
NC = NO CONNECT
V+ = VDD ± 10%
∆VMS
PSRR (dB) = 20 log ∆V
DD
∆VMS%
PSS (%/%) =
∆VDD%
07674-044
VA
+15V
GND
NC = NO CONNECT
–15V
Figure 63. Common-Mode Leakage Current
Figure 60. Wiper Resistance
Rev. D | Page 21 of 32
07674-048
DUT
A
W
AD5291/AD5292
THEORY OF OPERATION
For the AD5291, the lower two RDAC data bits are don’t cares if
the RDAC register is read from or written to. Data is loaded MSB
first (Bit DB15). The four control bits determine the function of
the software command (see Table 11). Figure 3 shows a timing
diagram of a typical AD5291 and AD5292 write sequence.
The AD5291 and AD5292 digital potentiometers are designed to
operate as true variable resistors for analog signals that remain
within the terminal voltage range of VSS < VTERM < VDD. The
patented ±1% resistor tolerance feature helps to minimize the total
RDAC resistance error, which reduces the overall system error
by offering better absolute matching and improved open-loop
performance. The digital potentiometer wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing as many value changes as
necessary to place the potentiometer wiper in the correct
position. The RDAC register can be programmed with any
position setting using the standard SPI interface by loading the
16-bit data-word. Once a desirable position is found, this value
can be stored in a 20-TP memory register. Thereafter, the wiper
position is always restored to that position for subsequent powerup. The storing of 20-TP data takes approximately 6 ms; during
this time, the shift register is locked, preventing any changes from
taking place. The RDY pin identifies the completion of this 20TP storage.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is
loaded from the DIN pin. When SYNC returns high, the serial
data-word is decoded according to the commands in Table 11.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5291 and AD5292 have an
internal counter that counts a multiple of 16 bits (a frame) for
proper operation. For example, AD5291 and AD5292 work with
a 32-bit word but does not work properly with a 31-bit or 33-bit
word. The AD5291 and AD5292 do not require a continuous
SCLK, when SYNC is high, and all serial interface pins should
be operated at close to the VLOGIC supply rails to minimize
power consumption in the digital input buffers.
SERIAL DATA INTERFACE
RDAC REGISTER
The AD5291 and AD5292 contain a serial interface (SYNC,
SCLK, DIN and SDO) that is compatible with SPI interface
standards, as well as most DSPs. The part allows writing of data
via the serial interface to every register.
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of
the variable resistor. The RDAC register is a standard logic register;
there is no restriction on the number of changes allowed.
SHIFT REGISTER
The AD5291 and AD5292 shift register is 16 bits wide (see
Figure 2). The 16-bit input word consists of two unused bits
(set to 0), followed by four control bits, and 10 RDAC data bits.
Table 11. Command Operation Truth Table
D7
X
D7
X
Data Bits [DB9:DB0]1
D6
D5
D4
D3
X
X
X
X
D6
D5
D4
D3
X
X
X
X
D2
X
D2
X
D1
X
D12
X
D0
X
D02
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
D4
D3
D2
D1
D0
1
0
X
X
X
X
X
X
D3
D2
D1
D0
1
1
1
X
X
X
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
X
X
X
X
D0
0
1
2
Command Bits [DB13:DB10]
C3
C2
C1
C0
0
0
0
0
0
0
0
1
0
0
1
0
D9
X
D9
X
D8
X
D8
X
3
0
0
1
1
X
4
0
1
0
0
5
0
1
0
6
0
1
7
0
8
1
Command
1
2
X = don’t care.
In the AD5291, this bit is a don’t care.
Rev. D | Page 22 of 32
Operation
NOP command: do nothing.
Write contents of serial data to RDAC.
Read RDAC wiper setting from the SDO
output in the next frame.
Store wiper setting: store RDAC setting
to 20-TP memory.
Reset: refresh RDAC with 20-TP stored
value.
Read contents of 20-TP memory, or
status of 20-TP memory, from the SDO
output in the next frame.
Write contents of serial data to control
register.
Read control register from the SDO
output in the next frame.
Software shutdown.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown mode).
AD5291/AD5292
20-TP MEMORY
WRITE PROTECTION
Once a desirable wiper position is found, the contents of the
RDAC register can be saved into a 20-TP memory register
(see Table 12). Thereafter, the wiper position is always set at that
position for any future on-off-on power supply sequence. The
AD5291 and AD5292 have an array of 20 one-time programmable
(OTP) memory registers. When the desired word is programmed
to 20-TP memory, the device automatically verifies that the
program command was successful. The verification process
includes margin testing. Bit C3 of the control register can be
polled to verify that the fuse program command was successful.
Programming data to 20-TP memory consumes approximately
25 mA for 550 μs and takes approximately 8 ms to complete.
During this time, the shift register is locked, preventing any
changes from taking place. The RDY pin can be used to monitor
the completion of the 20-TP memory program and verification.
No change in supply voltage is required to program the 20-TP
memory. However, a 1 μF capacitor on the EXT_CAP pin is
required (see Figure 68). Prior to 20-TP activation, the AD5291
and AD5292 preset to midscale on power-up.
On power-up, the shift register write commands for both the
RDAC register and the 20-TP memory register are disabled.
The RDAC write protect bit, C1 of the control register (see
Table 13 and Table 14), is set to 0 by default. This disables any
change of the RDAC register content regardless of the software
commands, except that the RDAC register can be refreshed
from the 20-TP memory using the software reset command
(Command 4) or through hardware by the RESET pin. To enable
programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control
register, must first be programmed. This is accomplished by
loading the shift register with Command 6 (see Table 11). To
enable programming of the 20-TP memory block bit, C0 of the
control register (set to 0 by default) must first be set to 1.
Table 12. Write and Read to RDAC and 20-TP Memory
DIN
0x1803
0x0500
0x0800
0x0C00
SDO
0xXXXX
0x1803
0x0500
0x0100
0x1C00
0x0000
0x0C00
0x000X
Action
Enable update of wiper position and 20-TP memory contents through digital interface.
Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
Prepare data read from the RDAC register.
Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits
contain the contents of the RDAC register (0x100).
Prepare data read from the control register.
NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control
register. If Bit C3 = 1, the fuse program command is successful.
Table 13. Control Register Bit Map1
DB9
X
1
DB8
X
DB7
X
DB6
X
DB5
X
DB4
X
DB3
C3
DB2
C2
DB1
C1
X = don’t care.
Table 14. Control Register Function
Bit Name
C0
C1
C2
C3
1
Description
20-TP program enable
0 = 20-TP program disabled (default)
1 = enable device for 20-TP program
RDAC register write protect
0 = wiper position frozen to value in memory (default) 1
1 = allow update of wiper position through digital Interface
Calibration enable
0 = resistor performance mode enabled (default)
1 = normal mode enabled
20-TP memory program success
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed.
Rev. D | Page 23 of 32
DB0
C0
AD5291/AD5292
BASIC OPERATION
read-only Memory Address 0x14 and Memory Address 0x15
using Command 5. The data bytes read back from Memory
Address 0x014 and Memory Address 0x015 are thermometer
encoded versions of the address of the last programmed
memory location.
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the shift register with Command 1 (see Table 11) and the desired
wiper position data. When the desired wiper position is determined, the user can load the shift register with Command 3
(see Table 11), which stores the wiper position data in the 20-TP
memory register. After 6 ms, the wiper position is permanently
stored in the 20-TP memory. The RDY pin can be used to monitor the completion of this 20-TP program. Table 12 provides a
programming example, listing the sequence of serial data input
(DIN) words with the serial data output appearing at the SDO
pin in hexadecimal format.
If no memory location has been programmed, then the address
generated is −1.
20-TP READBACK AND SPARE MEMORY STATUS
SHUTDOWN MODE
It is possible to read back the contents of any of the 20-TP
memory registers through SDO by using Command 5 (see
Table 11). The lower five LSB bits (D0 to D4) of the data byte
select which memory location is to be read back (see Table 16).
Data from the selected memory location are clocked out of the
SDO pin during the next SPI operation, where the last 10 bits
contain the contents of the specified memory location.
The AD5291 and AD5292 can be placed in shutdown mode by
executing the software shutdown command, Command 8 (see
Table 11), and setting the LSB, D0, to 1. This feature places the
RDAC in a special state in which Terminal A is open-circuited,
and Wiper W is connected to Terminal B. The contents of the
RDAC register are unchanged by entering shutdown mode.
However, all commands listed in Table 11 are supported while
in shutdown mode. Execute Command 8 (see Table 11), and set
the LSB, D0, to 0 to exit shutdown mode.
It is also possible to calculate the address of the most recently
programmed memory location by reading back the contents of
For the example outlined in Table 15, the address of the last
programmed location is calculated as
(Number of Bits = 1 in Memory Address 0x14) + (Number
of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17
(0x10)
Table 15. Example 20-TP Memory Readback
DIN
0x1414
0x1415
SDO
0xXXXX
0x03FF
0x0000
0x1410
0x0000
0x00FF
0x0000
0xXXXX
Action
Prepares data read from Memory Address 0x14.
Prepares data read from Memory Address 0x15. Sends 16-bit word out of SDO, where the last 10 bits contain the
contents of Memory Address 0x14.
NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x15.
Prepares data read from memory location 0x10.
NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (17).
Table 16. Memory Map of Command 5
D9
X
X
X
X
X
…
X
X
X
X
X
1
2
D8
X
X
X
X
X
…
X
X
X
X
X
Data Bits [DB9:DB0] 1
D7 D6 D5 D4 D3
X
X
X
0
0
X
X
X
0
0
X
X
X
0
0
X
X
X
0
0
X
X
X
0
0
… … … … …
X
X
X
0
1
X
X
X
0
1
X
X
X
1
0
X
X
X
1
0
X
X
X
1
0
D2
0
0
0
0
1
…
0
1
0
1
1
D1
0
0
1
1
0
…
0
1
1
0
0
D0
0
1
0
1
0
…
1
0
1
0
1
Register Contents
1st programmed wiper location (0x00)
2nd programmed wiper location (0x01)
3rd programmed wiper location (0x02)
4th programmed wiper location (0x03)
5th programmed wiper location (0x04)
…
10th programmed wiper location (0x09)
15th programmed wiper location (0x0E)
20th programmed wiper location (0x13)
Programmed memory status (thermometer encoded) 2 (0x14)
Programmed memory status (thermometer encoded)2 (0x15)
X = don’t care.
Allows the user to calculate the remaining spare memory locations.
Rev. D | Page 24 of 32
AD5291/AD5292
RESISTOR PERFORMANCE MODE
VLOGIC
AD5291/
AD5292
MOSI
MICROCONTROLLER
SCLK
SS
DIN
U1
SYNC
AD5291/
AD5292
RP
2.2kΩ
DIN
SDO
SCLK
SDO
U2
SCLK
SYNC
07674-050
This mode activates a new, patented 1% end-to-end resistor
tolerance that ensures a ±1% resistor tolerance on each code,
that is, code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2
(AD5291) or Table 5 (AD5292) to check which codes achieve
±1% resistor tolerance. The resistor performance mode is
activated by programming Bit C2 of the control register (see
Table 13 and Table 14). The typical settling time is shown in
Figure 50.
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
RESET
SDO PIN AND DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
control register using Command 2, Command 5 and Command 7,
respectively (see Table 11) or the SDO pin can be used in daisychain mode. Data is clocked out of SDO on the rising edge of
SCLK. The SDO pin contains an open-drain N-channel FET
that requires a pull-up resistor if this pin is used. To place the
pin in high impedance and minimize the power dissipation
when the pin is used, the 0x8001 data word followed by
Command 0 should be sent to the part. Table 17 provides a
sample listing for the sequence of the serial data input (DIN).
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 64, users need to
tie the SDO pin of one package to the DIN pin of the next
package. Users may need to increase the clock period, because
the pull-up resistor and the capacitive loading at the SDO-toDIN interface may require additional time delay between
subsequent devices.
Figure 64. Daisy-Chain Configuration Using SDO
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented
the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5291 and AD5292 employ
a three-stage segmentation approach, as shown in Figure 65.
The AD5291 and AD5292 wiper switches are designed with the
transmission gate CMOS topology and with the gate voltages
derived from VDD and VSS.
A
RL
RL
RW
W
RW
8-/10-BIT
ADDRESS
DECODER
RM
RL
RM
RL
B
Figure 65. Simplified RDAC Circuit
Table 17. Minimize Power Dissipation at SDO Pin
1
SDO1
0xXXXX
0xXXXX
High impedance
SW
RM
When two AD5291 and AD5292 devices are daisy-chained, 32
bits of data are required. The first 16 bits go to U2, and the
second 16 bits go to U1. Hold the SYNC pin low until all 32 bits
are clocked into their respective shift registers. The SYNC pin is
then pulled high to complete the operation.
DIN
0xXXXX
0x8001
0x0000
RM
07674-051
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291 and AD5292 can also be
reset through software by executing Command 4 (see Table 11).
If no 20-TP memory location is programmed, then the RDAC
register loads with midscale upon reset. The control register is
restored with default bits; see Table 14.
Action
Last user command sent to the digipot
Prepares the SDO pin to be placed in high impedance mode
The SDO pin is placed in high impedance
X is don’t care.
Rev. D | Page 25 of 32
AD5291/AD5292
PROGRAMMING THE VARIABLE RESISTOR
where:
Rheostat Operation—1% Resistor Tolerance
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
A
W
B
A
W
B
W
B
07674-052
A
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024
tap points accessed by the wiper terminal. The 8-/10-bit data in
the RDAC latch is decoded to select one of the 256/1024
possible wiper settings. The AD5291 and AD5292 contain an
internal ±1% resistor performance mode that can be disabled or
enabled (this is enabled by default), by programming Bit C2 of
the control register (see Table 13 and Table 14). The digitally
programmed output resistance between the W terminal and the
A terminal, RWA, and between the W terminal and B terminal,
RWB, is internally calibrated to give a maximum of ±1% absolute
resistance error across a wide code range. As a result, the
general equations for determining the digitally programmed
output resistance between the W terminal and B terminal are
AD5291:
RWB (D) =
D
× R AB
256
(1)
D
× R AB
1024
(2)
AD5292:
RWB (D ) =
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
the wiper to B and at the wiper to A that is proportional to the
input voltage at A to B, as shown in Figure 67. Unlike the polarity
of VDD to GND, which must be positive, voltage across A to B,
W to A, and W to B can be at either polarity.
VIN
A
W
VOUT
B
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is
equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1024 positions of the potentiometer divider.
The general equations defining the output voltage at VW with
respect to ground for any valid input voltage applied to Terminal A
and Terminal B are
VW (D) =
AD5291:
256 − D
× R AB
256
(3)
1024 − D
× R AB
1024
(4)
AD5292:
RWA (D) =
PROGRAMMING THE POTENTIOMETER DIVIDER
AD5291:
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces a
digitally controlled complementary resistance, RWA. RWA is also
calibrated to give a maximum of 1% absolute resistance error.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for
this operation are
RWA (D ) =
In the zero-scale condition, a finite total wiper resistance of 120 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W
and Terminal B, to the maximum continuous current of ±3 mA or
to the pulse current specified in Table 8. Otherwise, degradation
or possible destruction of the internal resistors may occur.
07674-053
The AD5291 and AD5292 operate in rheostat mode when only
two terminals are used as a variable resistor. The unused
terminal can be left floating or tied to the W terminal, as shown in
Figure 66.
D
256 − D
× VA +
× VB
256
256
(5)
1024 − D
D
×VA +
× VB
1024
1024
(6)
AD5292:
VW (D) =
If using the AD5291 and AD5292 in voltage divider mode as
shown in Figure 67, then the ±1% resistor tolerance calibration
feature reduces the error when matching with discrete resistors.
However, it is recommended to disable the internal ±1% resistor
tolerance calibration feature by programming Bit C2 of the
control register (see Table 13 and Table 14) to optimize wiper
position update rate. In this configuration, the RDAC is ratiometric and resistor tolerance error does not affect performance.
Rev. D | Page 26 of 32
AD5291/AD5292
Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, RWA and RWB, and
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 μF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 68) on power-up and throughout the operation
of the AD5291 and AD5292.
AD5291/
AD5292
EXT_CAP
C1
1µF
OTP
MEMORY
BLOCK
07674-054
GND
Figure 68. Hardware Setup for EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the
AD5291 and AD5292 define the boundary conditions for
proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W
that exceed VDD or VSS are clamped by the internal forwardbiased diodes (see Figure 69).
The ground pins of the AD5291 and AD5292 devices are
primarily used as a digital ground reference. To minimize the
digital ground bounce, the AD5291 and AD5292 ground
terminals should be joined remotely to the common ground.
The digital input control signals to the AD5291 and AD5292
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the Specifications section.
Power-Up Sequence
To ensure that the AD5291 and AD5292 power up correctly, a
1 μF capacitor must be connected to the EXT_CAP pin. Because
there are diodes to limit the voltage compliance at Terminal A,
Terminal B, and Terminal W (see Figure 69), it is important to
power VDD and VSS first before applying any voltage to Terminal A,
Terminal B, and Terminal W. Otherwise, the diode is forwardbiased such that VDD and VSS are powered up unintentionally.
The ideal power-up sequence is GND, VSS, VLOGIC and VDD, the
digital inputs, and then VA, VB, and VW. The order of powering
up VA, VB, VW, and the digital inputs is not important as long as
they are powered after VDD, VSS, and VLOGIC.
Regardless of the power-up sequence and the ramp rates of the
power supplies, after VLOGIC is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.
VDD
A
W
VSS
07674-055
B
Figure 69. Maximum Terminal Voltages Set by VDD and V SS
Rev. D | Page 27 of 32
AD5291/AD5292
APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
HIGH ACCURACY DAC
The AD5292 can be configured as a high voltage DAC, with
output voltage as high as 33 V. The circuit is shown in Figure 70.
The output is
It is possible to configure the AD5292 as a high accuracy DAC
by optimizing the resolution of the device over a specific
reduced voltage range. This is achieved by placing external
resistors on either side of the RDAC, as shown in Figure 72.
The improved ±1% R-Tolerance specification greatly reduces
error associated with matching to discrete resistors.
⎡
D
× ⎢1.2 V ×
1024 ⎢⎣
⎛ R2 ⎞⎤
⎜1 + ⎟⎥
⎜ R ⎟
1 ⎠⎥
⎝
⎦
(7)
where D is the decimal code from 0 to 1023.
VOUT (D ) =
VDD
VDD
U2
U1
AD5292
AD8512
AD5292
U1B
20kΩ
V–
B
AD8512
R2
20kΩ
VOUT
B
07674-153
VARIABLE GAIN INSTRUMENTATION AMPLIFIER
For applications that require high current adjustments such as a
laser diode or tunable laser, a boosted voltage source can be
considered; see Figure 71.
U3 2N7002
VIN
The AD8221 in conjunction with the AD5291 and AD5292 and
the ADG1207, as shown in Figure 73, make an excellent
instrumentation amplifier for use in data acquisition systems.
The data acquisition system’s low distortion and low noise
enable it to condition signals in front of a variety of ADCs.
ADG1207
VOUT
U1
CC
AD5292
U2
OP184
SIGNAL
RBIAS
VDD
+VIN1
IL
AD5292
+VIN4
–VIN1
LD
07674-155
B
OP1177
Figure 72. Optimizing Resolution
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
W
VOUT
V+
±1%
R3
Figure 70. High Voltage DAC
A
VDD
U2
V–
R2
R1
R1
AD8221
–VIN4
VSS
Figure 71. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VOUT to
be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N-channel
FET (U3). The N-Channel FET power handling must be adequate
to dissipate (VIN − VOUT) × IL power. This circuit can source a
maximum of 100 mA with a 33 V supply.
VOUT
07674-156
U1A
V+
D1
(8)
R1 + ((1024 − D )1024) × RAB + R3
VDD
RBIAS
ADR512
R3 + (D 1024 × RAB ) ×V DD
07674-154
VOUT (D) =
Figure 73. Data Acquisition System
The gain can be calculated by using Equation 9.
Rev. D | Page 28 of 32
G(D) = 1 +
49.4 kΩ
(D 1024) × R
(9)
AB
AD5291/AD5292
The configuration to reduce zipper noise is shown in Figure 74,
and the results of using this configuration is shown in Figure 75.
The input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B. U6 is
used to establish the signal zero reference. The upper limit of
the comparator is set above its offset and, therefore, the output
pulses high whenever the input falls between 2.502 V and 2.497 V
(or 0.005 V window) in this example. This output is AND’ed
with the SYNC signal such that the AD5291 and AD5292
updates whenever the signal crosses the window. To avoid a
constant update of the device, the SYNC signal should be
programmed as two pulses, rather than as one.
AUDIO VOLUME CONTROL
The excellent THD performance and high voltage capability
make the AD5291 and AD5292 ideal for a digital volume
control as an audio attenuator or gain amplifier. A typical
problem in these systems is that a large step change in the
volume level at any arbitrary time can lead to an abrupt
discontinuity of the audio signal causing an audible zipper
noise. To prevent this, a zero-crossing window detector can be
inserted to the SYNC line to delay the device update until the
audio signal crosses the window. Because the input signal can
operate on top of any dc level rather than absolute zero volt
level, zero-crossing in this case means the signal is ac-coupled,
and the dc offset level is the signal zero reference point.
In Figure 75, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
C1
VIN 1µF
5V
R1
100kΩ
R2
200Ω
R4
90kΩ
+15V
+5V
–15V
U4B
U3
VCC
ADCMP371
GND
5V
U6
V+
AD8541
V–
VDD
AD5292
A
C2
0.1µF
4
+5V
7408
5
6 1
+15V
VSS
U4A
7408
2
W
20kΩ
SYNC
SCLK
SCLK
SDIN
SDIN
B
VOUT
–15V
SYNC
GND
07674-157
R3
100kΩ
U5
V+
V–
Figure 74. Audio Volume Control with Zipper Noise Reduction
1
2
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
07674-158
R5
10kΩ
C3
0.1µF
U2
VCC
ADCMP371
GND
U1
Figure 75. Zipper Noise Detector
Rev. D | Page 29 of 32
AD5291/AD5292
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
8°
0°
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5291BRUZ-20
AD5291BRUZ-20-RL7
AD5291BRUZ-50
AD5291BRUZ-50-RL7
AD5291BRUZ-100
AD5291BRUZ-100-RL7
AD5292BRUZ-20
AD5292BRUZ-20-RL7
AD5292BRUZ-50
AD5292BRUZ-50-RL7
AD5292BRUZ-100
AD5292BRUZ-100-RL7
EVAL-AD5292EBZ
1
RAB (kΩ)
20
20
50
50
100
100
20
20
50
50
100
100
Resolution
256
256
256
256
256
256
1,024
1,024
1,024
1,024
1,024
1,024
Memory
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Z = RoHS Compliant Part.
Rev. D | Page 30 of 32
Package Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Evaluation Board
Package Option
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
AD5291/AD5292
NOTES
Rev. D | Page 31 of 32
AD5291/AD5292
NOTES
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07674-0-9/10(D)
Rev. D | Page 32 of 32