AD AD5399YRM Twos complement, dual 12-bit dac with internal ref and fast settling time Datasheet

Twos Complement, Dual 12-Bit DAC
with Internal REF and Fast Settling Time
AD5399
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VTP
AD5399
VDD
×2
X2
×2
DECODER SW
DRIVER A
AGND
The AD5399 is available in the compact 1.1 mm low profile
MSOP-10 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +105°C.
VBZ – 2V = 0V
12
DAC A
REGISTER
ADDR
DECODE
VOUTB
DAC B
REGISTER
EN
12
A0
16-BIT
SDI
03469-B-001
CLK
POWER-ON
RESET
D15...D0
Figure 1.
VOUT = ((D – 2048)/4096 × 4 V) + 2 V for 0 ≤ D ≤ 4095, where D
is the decimal code.
Table 1. Examples of Twos Complement Codes
Twos Complement
2047
2046
1
0
4095
2049
2048
D
4095
4094
2049
2048
2047
1
0
Scale
+FS
+FS – 1 LSB
BZS + 1 LSB
BZS
BZS – 1 LSB
–FS + 1 LSB
–FS
VOUT (V)
4.000
3.999
2.001
2.000
1.999
0.001
0.000
FS = Full Scale, BZS = Bipolar Zero Scale.
4.0
3.5
3.0
VOUT = [(0 – 2048)/4096 × 4V] + 2V
2.5
VOUT (V)
The AD5399 is the industry-first dual 12-bit digital-to-analog
converter that accepts twos complement digital coding with 2 V
dc offset for single-supply operation. Augmented with a built-in
precision reference and a solid buffer amplifier, the AD5399 is
the smallest self-contained 12-bit precision DAC that fits many
general-purpose as well as DSP specific applications. The twos
complement programming facilitates the natural coding
implementation commonly found in DSP applications, and
allows operation in single supply. The AD5399 provides a 2 V
reference output, VREF, for bipolar zero monitoring. It can also
be used for other on-board components that require a precision
reference. The device is specified for operation from 5 V ± 10%
single supply with bipolar output swing from 0 V to 4 V
centered at 2 V.
VBZ + 2V = 4V
DECODER SW
DRIVER B
12
CS
APPLICATIONS
GENERAL DESCRIPTION
VOUTA
VREF 2V
DGND
Single-supply bipolar converter operations
General-purpose DSP applications
Digital gain and offset controls
Instrumentation level settings
Disk drive control
Precision motor control
VBZ(VREF) = 2V
2.0
1.5
1.0
0.5
0
0
512
1024
1536
2048
2560
3072
TWOS COMPLEMENT CODE
3584
4096
03469-B-002
2-channel 12-bit DAC
Twos complement facilitates bipolar applications
Bipolar zero with 2 V dc offset
Built-in 2.000 V precision reference with 10 ppm/°C typ TC
Buffered voltage output: 0 V to 4 V
Single-supply operation: 4.5 V to 5.5 V
Fast 0.8 µs settling time typ
Ultracompact MSOP-10 package
Monotonic DNL < ±1 LSB
Optimized accuracy at zero scale
Power-on reset to VREF
3-wire serial data input
Extended temperature range: –40°C to +105°C
Figure 2. Output vs. Twos Complement Code
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5399
TABLE OF CONTENTS
Specifications..................................................................................... 3
Typical Performance Characteristics ..............................................7
Electrical Characteristics ............................................................. 3
Operation......................................................................................... 10
Absolute Maximum Ratings............................................................ 4
Power-Up/Power-Down Sequence .......................................... 10
ESD Caution.................................................................................. 4
Outline Dimensions ....................................................................... 12
Pin Configuration and Function Descriptions............................. 5
Ordering Guide .......................................................................... 12
Timing Characteristics..................................................................... 6
REVISION HISTORY
6/04—Data sheet changed from Rev. C to Rev. D
Correction to Table 7 Caption ...................................................... 11
3/04—Data sheet changed from Rev. B to Rev. C
Changes to Specifications ................................................................ 3
Changes to Table 4............................................................................ 5
Replaced Figures 4 and 5 ................................................................. 6
Changes to Operation Section ...................................................... 10
Changes to Table 6.......................................................................... 10
11/03—Data sheet changed from Rev. A to Rev. B
Changes to Table 5 notes ................................................................. 5
Changes to Figures 8 and 9.............................................................. 7
Changes to Figure 12........................................................................ 8
Added Power-Up/Power-Down section...................................... 10
3/03—Data sheet changed from Rev. 0 to Rev. A
Change to Table 1 ............................................................................. 1
2/03—Revision 0: Initial Version
Rev. D | Page 2 of 12
AD5399
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 5 V ± 10%, –40°C < TA < +105°C, unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
Resolution
Differential Nonlinearity Error
Symbol
Integral Nonlinearity Error
Positive Full-Scale Error
Bipolar Zero-Scale Error
Negative Full-Scale Error
ANALOG OUTPUTS
Nominal Positive Full-Scale
Positive Full-Scale Tempco2
INL
V+FSE
VBZSE
V–FSE
Conditions
N
DNL
Codes 2048 to 2052, due to int. op amp offset
Nominal VBZ Output Voltage
Bipolar Zero Output Resistance2
VBZ Output Voltage Tempco
VOUTA/B
TCVOUTA/B
VBZ
RBZ
TCVBZ
Nominal Peak-to-Peak Output Swing
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Current
Input Capacitance2
POWER SUPPLIES
Power Supply Range
Supply Current
Supply Current in Shutdown
|V+FS| + |V–FS|
Power Dissipation3
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS2
Settling Time
Digital Feedthrough
Bipolar Zero-Scale Glitch
Capacitive Load Driving Capability
INTERFACE TIMING CHARACTERISTICS2, 4
SCLK Cycle Frequency
SCLK Clock Cycle Time
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SCLK Active Edge Setup Time
SCLK to CS Hold Time
Repeat Programming, CS High Time
PDISS
PSS
VIH
VIL
IIL
CIL
VDD RANGE
IDD
IDD_SHDN
tS
Q
G
CL
tCYC
t1
t2, t3
t4
t5
t6
t7
t8
Code = 0xF
Code = 0x000
Code = 0x800
Code = 0x7FF
Code = 0x7FF, TA = 0°C to 70°C
Code = 0xFF, TA = –40°C to +105°C
Min
Typ1
Max
Unit
12
–1
–1.2
–0.4
–0.75
–0.75
–0.75
±0.5
±0.5
±0.02
–0.15
–0.15
–0.15
+1
+1.2
+0.4
+0.75
+0.75
+0.75
Bits
LSB
LSB
%FS
%FS
%FS
%FS
–40
–60
1.995
TA = 0°C to 70°C
TA = –40°C to +105°C
Code 0x7FF to Code 0x800
–40
–60
VDD = 5 V
VDD = 5 V
VIN = 0 V or 5 V, VDD = 5 V
2.4
4
±10
±10
2.000
1
±10
±10
4
+40
+60
2.004
+40
+60
0.8
±1
V
V
µA
pF
5.5
2.6
100
500
13
+0.006
V
mA
µA
µA
mW
%/%
1000
µs
nV-s
nV-s
pF
5
4.5
VIH = VDD or VIL = 0 V
VIH = VDD or VIL = 0 V, B14 = 0, TA = 0°C to 105°C
VIH = VDD or VIL = 0 V, B14 = 0, TA = –40°C to 0°C
VIH = VDD or VIL = 0 V, VDD = 5.5 V
∆VDD = 5 V ± 10%
–0.006
0.1% error band
1.8
10
100
9
+0.003
0.8
10
10
No oscillation
33
Clock level low or high
1
30
15
5
0
5
0
30
V
ppm/°C
ppm/°C
V
Ω
ppm/°C
ppm/°C
V
MHz
ns
ns
ns
ns
ns
ns
ns
Typical values represent average readings at 25°C and VDD = 5 V.
Guaranteed by design and not subject to production test.
3
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
4
See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using VDD = 5 V. Input logic should have a 1 V/µs minimum slew rate.
2
Rev. D | Page 3 of 12
AD5399
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VOUTA, VOUTB, VBZ to GND
Digital Input Voltages to GND
Operating Temperature Range
Maximum Junction Temperature (TJ MAX)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance, θJA, MSOP-10
Rating
–0.3 V, +7.5 V
0 V, VDD
0 V, VDD + 0.3 V
–40°C to +105°C
150°C
–65°C to +150°C
300°C
(TJ MAX – TA)/θJA
206°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 4 of 12
AD5399
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK 1
SDI 2
10 CS
AD5399
9
VTP
8 VDD
TOP VIEW
VOUTB 4 (Not to Scale) 7 AGND
V
5
6 VBZ
OUTA
03469-B-003
DGND 3
Figure 3. MSOP-10 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
CLK
SDI
DGND
VOUTB
VOUTA
VBZ
AGND
VDD
VTP
CS
Description
Serial Clock Input. Positive edge triggered.
Serial Data Input. MSB first format.
Digital Ground.
DAC B Voltage Output (A0 = Logic 1).
DAC A Voltage Output (A0 = Logic 0).
2 V, Virtual Bipolar Zero (Active Output).
Analog Ground.
Positive Power Supply. Specified for operation at 5 V.
Connect to VDD. Reserved for factory testing.
Chip Select (Frame Sync Input). Allows clock and data to shift into the shift register when CS goes from high to low.
After the 16th clock pulse, it is not necessary to bring CS high to shift the data to the output. However, CS should be
brought high any time after the 16th clock positive edge in order to allow the next programming cycle.
Table 5. Serial Data-Word Format
ADDR
B15
A0
MSB
A0
B14
X
B13
SD
B12
0
DATA
B11
D11
B10
D10
…
…
B3
D3
B2
D2
B1
D1
B0
D0
LSB
Address Bit. Logic low selects DAC A and logic high selects DAC B.
Both channels are shut down when the SD bit is high. However, the A0 bit must be at the same state for shutdown
activation and deactivation. See the Shutdown Function section.
X
Don’t Care.
SD
Shutdown Bit. Logic high puts both DAC outputs and VBZ into high impedance. A0 bit must be at the same state for
shutdown activation and deactivation.
0
B12 must be 0.
D0–D11
Data Bits.
Rev. D | Page 5 of 12
AD5399
TIMING CHARACTERISTICS
1
SDI
A0
X
SD
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
SCLK
0
03469-C-001
1
CS
0
Figure 4. Timing Diagram
1
SDI
Dx
Dx
Dx
0
t4
1
t5
t2
t3
0
t6
t7
t1
CS
t8
0
tS
1
VOUT
0
Figure 5. Detailed Timing Diagram
Rev. D | Page 6 of 12
±1LSB
ERROR
BAND
03469-C-002
SCLK
1
Dx
AD5399
TYPICAL PERFORMANCE CHARACTERISTICS
10
2.3
VDD = 5V
TA = 25°C
8
6
2.2
SUPPLY CURRENT (mA)
DAC B
4
2
INL (LSB)
VDD = 5V
0
–2
DAC A
–4
–6
2.1
2.0
1.9
0
512
1024
1536
2048
2560
CODE (Decimal)
3072
3584
4096
1.8
–60
Figure 6. Integral Nonlinearity Errors
1.00
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 9. Supply Current vs. Temperature
2.4
VDD = 5V
TA = 25°C
0.75
–40
03469-B-009
–10
03469-B-006
–8
VDD = 5V
TA = 25°C
SUPPLY CURRENT, IDD (mA)
2.3
0.50
DAC A, B
DNL (LSB)
0.25
0
–0.25
–0.50
2.2
2.1
2.0
1.9
0
512
1024
1536
2048
2560
CODE (Decimal)
3072
3584
4096
1.8
2
Figure 7. Differential Nonlinearity Errors
1.96
4
5
6
DIGITAL INPUT VOLTAGE, VIH (V)
7
Figure 10. Supply Current vs. Digital Input Voltage
4.5
TA = 25°C
VDD = 5V
4.0 TA = 25°C
1.92
CODE = 0x555
SUPPLY CURRENT (mA)
3.5
1.88
1.84
CODE = 0x7FF
3.0
2.5
CODE = 0x000
2.0
1.5
1.0
1.80
1.76
2
3
4
5
SUPPLY VOLTAGE (V)
6
7
0
10k
Figure 8. Supply Current vs. Supply Voltage
100k
1M
10M
CLOCK FREQUENCY (Hz)
Figure 11. Supply Current vs. Clock Frequency
Rev. D | Page 7 of 12
100M
03469-B-011
0.5
03469-B-008
SUPPLY CURRENT (mA)
3
03469-B-010
–1.00
03469-B-007
–0.75
AD5399
1000
70
VDD = 5V
SS = 345
25°C to 85°C
100
NUMBER OF DEVICES
SHUTDOWN CURRENT (µA)
60
10
1
50
40
30
20
–20
0
20
40
60
80
100
SHUTDOWN TEMPERATURE (°C)
120
140
0
–45–40–35–30–25–20–15–10 –5 0 5 10 15 20 25 30 35 40
TEMPCO (ppm/°C)
Figure 12. Shutdown Current vs. Temperature
Figure 15. VBZ Temperature Coefficient (TA = 25°C to 85°C)
20
100
VDD = 5V
18 TA = 25°C
CURRENT SINKING
CODE = 0x000 = 2V
SS = 345
25°C to 105°C
80
NUMBER OF DEVICES
LOAD CURRENT (mA)
16
14
12
CURRENT SOURCING
10 CODE = 0x000 = 2V
8
6
4
60
40
–4
–2
0
2
4
∆VOUT (mV)
6
8
10
03469-B-013
20
CURRENT SINKING
CODE = 0x800 = 0V
2
0
–6
03469-B-015
–40
0
–15 –10 –5
0
5
10 15 20 25 30
TEMPCO (ppm/°C)
35
40
45
50
03469-B-016
0.1
–60
03469-B-012
10
Figure 16. VBZ Temperature Coefficient (TA = 25°C to 105°C)
Figure 13. Load Current vs. Voltage Drop
40
0.5
VDD = 5V
0.4 BURN-IN TEMPERATURE = 125°C
35
SS = 345
–40°C to +25°C
0.3
NUMBER OF DEVICES
30
V+FS
0.1
0
V–FS
–0.1
VBZS
VBZ
–0.2
25
20
15
10
–0.3
–0.5
0
200
400
600
800
HOURS OF OPERATION
1000
1200
Figure 14. Long-Term Drift
0
–45–40–35–30–25–20–15–10 –5 0 5 10 15 20 25 30 35 40
TEMPCO (ppm/°C)
Figure 17. VBZ Temperature Coefficient (TA = –40°C to +25°C)
Rev. D | Page 8 of 12
03469-B-017
5
–0.4
03469-B-014
∆VOUT (mV)
0.2
AD5399
VOUT: 0.5V/DIV
100
90
90
TRACE 1: NO LOAD
TRACE 2 (WITH RINGING):
CL = 2nF
RL = 1kΩ
CLK: 5V/DIV
CLK: 5V/DIV
10
03469-B-018
10
0%
0%
Figure 18. Large Signal Settling (0.5 µs/DIV)
Figure 20. Capacitive Load Output Performance (2 µs/DIV)
100
90
CS: 5V/DIV
0%
03469-B-019
VOUT: 50mV/DIV
10
VOUT: 1V/DIV
03469-B-020
100
Figure 19. Midscale Glitch and Digital Feedthrough (2 µs/DIV)
Rev. D | Page 9 of 12
AD5399
The AD5399 provides a 12-bit, twos complement, dual voltage
output, digital-to-analog converter (DAC). It has an internal
reference with 2 V bipolar zero dc offset, where 0 ≤ VOUT ≤ 4 V.
1kΩ
The output transfer equation is
LOGIC
03469-B-021
OPERATION
Figure 21. Equivalent ESD Protection Circuit
C1
10µF
VDD
VTP
C2
0.1µF
where:
D is the 12-bit decimal code and not the twos complement code.
VOUT is with respect to ground.
Table 6. Input Logic Control Truth Table
CLK
CS
Register Activity
L
H
P
16th P
H
H
L
L
No Shift Register Effect
No Shift Register Effect
Shift One SDI Bit into the SR
Transfer SR Data into DAC Register and Update
the Output
P = Positive Edge, X = Don't Care, SR = Shift Register.
The data setup and data hold times in the Specifications table
determine the timing requirements. The internal power-on reset
circuit clears the serial input registers to all 0s, and sets the two
DAC registers to a VBZ (zero code) of 2 V.
AGND
(D–2048)/4096 × 4V + 2V
2V
Figure 22. Basic Connection
POWER-UP/POWER-DOWN SEQUENCE
Like most CMOS devices, it is recommended to power VDD and
ground prior to any digital signals. The ideal power-up
sequence is GND, VDD, and digital signals. The reverse sequence
applies to the power-down condition.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at VDD to minimize any
transient disturbance and to filter any low frequency ripple (see
Figure 23). Users should not apply switching regulators for VDD
due to the power supply rejection ratio degradation over
frequency.
AD5399
VDD
VDD
+ C2
Software shutdown B13 turns off the internal REF and
amplifiers. The output is close to zero potential, and the digital
circuitry remains active such that new data can be written.
Therefore, the DAC register is refreshed with the new data once
the shutdown bit is deactivated.
All digital inputs are ESD protected with a series input resistor
and parallel Zener, as shown in Figure 21, that apply to digital
input pins CLK, SDA, and CS. The basic connection is shown in
Figure 22.
VOUTA
VBZ(VREF)
10µF
C1
0.1µF
AGND
DGND
03469-B-023
In data programming, the data is loaded MSB first on the
positive clock edge (SCLK) after chip select (CS) goes from high
to low. The digital word is 16 bits wide, with the MSB, B15, as an
address bit (DAC A: A0 = 0; DAC B: A0 = 1). B14 is don’t care,
B13 is a shutdown bit, B12 must be logic low, and the last 12 bits
are data bits. An internal counter allows data transferred from
the shift register to the output after the 16th positive clock edge
while CS stays low (see Figure 5). After the 16th clock pulse, it is
not necessary to bring CS high to shift the data to the output.
However, CS should be brought high anytime after the 16th clock
positive edge in order to allow the next programming cycle.
AD5399
CS
CLK
SDI DGND
03469-B-022
5V
VOUT = ((D – 2048)/4096 × 4 V) + 2 V
Figure 23. Power Supply Bypassing and Grounding Connection
Grounding
The DGND and AGND pins of the AD5399 refer to the digital
and analog ground references. To minimize the digital ground
bounce, the DGND terminal should be joined remotely at a
single point to the analog ground plane, as shown in Figure 23.
Rev. D | Page 10 of 12
AD5399
Shutdown Function
The AD5399 shutdown function allows both DACs to be
shutdown simultaneously. However, the A0 and SD bits work in
tandem, and the A0 logic state must be the same for shutdown
activation and deactivation (see Table 7).
For users whose logic signals may be in three-state (random
levels) during power-up initialization, it is recommended to put
a pull-up resistor at the CS pin to disable chip select (Figure 24).
This avoids inadvertent shutdown as well as the inability to
deactivate shutdown due to an unknown A0 state. The resistor
value depends on the digital controller’s output impedance.
Table 7. Shutdown Activation and Deactivation Sequence.
2
3
Data-Word
in Binary
0X10 XXXX
XXXX XXXX
1X00 XXXX
XXXX XXXX
0X00 XXXX
XXXX XXXX
Shutdown Status
Activate shutdown on both DACs.
5V
Both DACs remain at shutdown.
Deactivate shutdown. Both DACs
resume normal operation.
The A0 bit (MSB) must be in the same state when activating and deactivating
shutdown.
Rev. D | Page 11 of 12
C1
10µF
C2
0.1µF
VDD
R1
300kΩ
VTP
AD5399
VOUTA
CS
(D–2048)/4096 × 4V + VBZ
VBZ(VREF)
CLK
2V
SDI DGND AGND
03469-B-022
Sequence
of Events
1
Figure 24. Disable CS for Random Logic Mode
AD5399
OUTLINE DIMENSIONS
3.00 BSC
6
10
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
0.15
0.00
1.10 MAX
0.27
0.17
SEATING
PLANE
0.23
0.08
8°
0°
0.80
0.60
0.40
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 25. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Models
AD5399YRM
AD5399YRM-REEL7
Temperature Range
–40°C to +105°C
–40°C to +105°C
Package Description
MSOP
MSOP
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03469–0–6/04(D)
Rev. D | Page 12 of 12
Package Option
RM-10
RM-10
Branding
DSB
DSB
Ordering Quantity
50
1,000