32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V AD5535B Data Sheet FEATURES GENERAL DESCRIPTION High integration 32-channel, 14-bit denseDAC® with integrated high voltage output amplifier Guaranteed monotonic Housed in 15 mm × 15 mm CSP_BGA package Full-scale output voltage programmable from 50 V to 200 V via reference input 550 µA drive capability Integrated silicon diode for temperature monitoring DSP-/microcontroller-compatible serial interface 1.2 MHz channel update rate Asynchronous RESET facility –10°C to +85°C temperature range The AD5535B is a 32-channel, 14-bit denseDAC® with an on-chip high voltage output amplifier. This device is targeted for optical micro-electromechanical systems. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Each amplifier can source 550 µA, which is ideal for the deflection and control of optical MEMS mirrors. The selected digital-to-analog converter (DAC) register is written to via the 3-wire interface. The serial interface operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. The device is operated with AVCC = 4.75 V to 5.25 V, DVCC = 2.7 V to 5.25 V, V+ = 4.75 V to 5.25 V, and VPP of up to 225 V. REF_IN is buffered internally on the AD5535B and should be driven from a stable reference source. APPLICATIONS Optical microelectromechanical systems (MEMS) Optical crosspoint switches Micropositioning applications using piezoelectric actuators Level setting in automotive test and measurement FUNCTIONAL BLOCK DIAGRAM AVCC DVCC RESET VPP REF_IN V+ PGND ANODE AD5535B CATHODE DAC R1 VOUT0 RF 14-BIT BUS DAC R1 DAC_GND DAC R1 AGND VOUT30 RF DAC R1 INTERFACE CONTROL LOGIC SCLK DIN VOUT31 RF 10852-001 DGND VOUT1 RF SYNC Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5535B Data Sheet TABLE OF CONTENTS Features ...................................................................................... 1 DAC Section ........................................................................ 12 Applications ............................................................................... 1 Reset Function .................................................................... 12 General Description ................................................................. 1 Serial Interface .................................................................... 12 Functional Block Diagram ...................................................... 1 Microprocessor Interfacing ............................................... 12 Revision History ....................................................................... 2 Applications ............................................................................. 14 Specifications............................................................................. 3 MEMS Mirror Control Application ................................. 14 Timing Characteristics ........................................................ 5 IPC-2221-Compliant Board Layout ................................. 14 Absolute Maximum Ratings .................................................... 6 Power Supply Decoupling Recommendations ..................... 15 ESD Caution .......................................................................... 6 Guidelines for Printed Circuit Board Layout...................... 15 Pin Configuration and Function Descriptions ..................... 7 Outline Dimensions ............................................................... 16 Typical Performance Characteristics ..................................... 9 Ordering Guide ................................................................... 16 Terminology ............................................................................ 11 Functional Description .......................................................... 12 REVISION HISTORY 4/13—Rev. 0 to Rev. A Change to General Description Section ......................................... 1 Changes to DAC Section ................................................................12 Changes to MEMS Mirror Control Application Section ...........14 1/13—Revision 0: Initial Version Rev. A | Page 2 of 16 Data Sheet AD5535B SPECIFICATIONS VPP = 215 V; V+ = 5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V; all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter DC PERFORMANCE 3 Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero Code Voltage Output Offset Error Offset Drift Voltage Gain Gain Temperature Coefficient 1 Channel-to-Channel Gain Match 4 OUTPUT CHARACTERISTICS Output Voltage Range3 Output Impedance Resistive Load4, 5 Capacitive Load4 Short-Circuit Current DC Crosstalk4 DC Power Supply Rejection (PSRR), VPP Long-Term Drift Min –1 49 0.5 50 5 –200 –5 Max +1 1 +1 51 +5 1 VPP − 1 50 1 200 0.55 3 70 0.25 4 60 60 5 5 10 3 1 LSB Step Slew Rate Unit Bits % of FSR LSB V V mV/°C V/V ppm/°C ppm/°C % V Ω MΩ pF mA LSB dB LSB µs µs µs µs V/µs V/µs kHz µV/√Hz mV p-p 30 4.5 1 Test Conditions/Comments Guaranteed monotonic Due to DAC Due to DAC and amplifier Outputs at midscale, measured over 30 days at 25°C No load 200 pF load No load 200 pF load No load 200 pF load Measured at 10 kHz 1 LSB change around major carry Positive Transition Negative Transition Analog Crosstalk Digital Feedthrough VOLTAGE REFERENCE, REF_IN 6 Input Voltage Range4 Input Impedance 14 ±0.1 ±0.5 0.5 –1 AC CHARACTERISTICS4 Settling Time ¼ to ¾ Scale Step –3 dB Bandwidth Output Noise Spectral Density 0.1 Hz to 10 Hz Output Noise Voltage Digital-to-Analog Glitch Impulse K Grade 2 Typ 15 8 2.5 2 nV-sec nV-sec µV-sec nV-sec AVCC and V+ must exceed REF_IN by 1.15 V minimum 1 4.096 60 Rev. A | Page 3 of 16 V kΩ AD5535B Parameter TEMPERATURE MEASUREMENT DIODE4 Peak Inverse Voltage, PIV Forward Diode Drop, VF Forward Diode Current, IF VF Temperature Coefficient, TC DIGITAL INPUTS4 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and SYNC Only) Input Capacitance POWER SUPPLY VOLTAGES VPP 1 V+ AVCC DVCC POWER SUPPLY CURRENTS 7 IPP All Channels at Full-Scale All Channels at Zero-Scale I+ AICC DICC Data Sheet Min K Grade 2 Typ 0.65 Max Unit Test Conditions/Comments 5 0.8 100 V V µA mV/°C Cathode to anode IF = 100 µA, anode to cathode Anode to cathode Anode to cathode ±10 0.8 10 µA V V mV pF 225 V 5.25 5.25 5.25 V V V 60 35 1.7 20 0.6 µA/channel µA/channel mA mA mA −2.20 ±5 2.0 200 (50 × REF_IN) + 1 4.75 4.75 2.7 50 25 1.2 17.5 0.25 See the Terminology section. K Grade temperature range: −10°C to +85°C; typical = +25°C. 3 Linear output voltage range: 7 V to VPP − 1 V. 4 Guaranteed by design and characterization, not production tested. 5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section. 6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to VPP − 1 V. 7 Outputs unloaded. 1 2 Rev. A | Page 4 of 16 Data Sheet AD5535B TIMING CHARACTERISTICS VPP = 210 V; V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1, 2, 3 fUPDATE fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 t9 A Grade 1.2 30 13 13 15 50 10 10 5 200 20 Unit MHz max MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments Channel update rate SCLK frequency SCLK high pulse width SCLK low pulse width SYNC falling edge to SCLK falling edge setup time SYNC low time SYNC high time DIN setup time DIN hold time 19th SCLK falling edge to SYNC falling edge for next write RESET pulse width See Figure 2. Guaranteed by design and characterization, not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2. 1 2 t1 SCLK 1 5 4 16 17 18 1 19 t2 t5 SYNC 3 2 t3 t4 t6 t8 t7 DIN LSB MSB 10852-002 RESET t9 Figure 2. Serial Interface Timing Diagram Rev. A | Page 5 of 16 AD5535B Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VPP to AGND V+ to AGND AVCC to AGND, DAC_GND DVCC to DGND Digital Inputs to DGND REF_IN to AGND, DAC_GND VOUT0 to VOUT31 to AGND ANODE/CATHODE to AGND, DAC_GND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 124-Lead CSP_BGA Package, θJA Thermal Impedance Lead Temperature Soldering ESD Human Body Model Machine Model Field Induced Charged Device Model Rating 0.3 V to 240 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to DVCC + 0.3 V −0.3 V to AVCC + 0.3 V –0.3 V to VPP + 0.3 V −0.3 V to +7 V −0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION −10°C to +85°C −65°C to +150°C 150°C 40°C/W JEDEC industry standard J-STD-020 2.5 kV 250 V 400 V Rev. A | Page 6 of 16 Data Sheet AD5535B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 6 7 8 9 10 11 12 13 14 A B B C C D D E F G E F G H H J J K K L L M N M N P P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 10852-003 1 2 3 4 A Figure 3. Pin Configuration Table 4. Pin Assignments Pin No. A1 A2 A4 A6 A8 A10 A12 A14 B1 B3 B5 B7 B9 B11 B13 C2 C12 C14 D1 D13 E2 E4 E6 E8 E10 E12 E14 F3 F5 F7 F9 F13 G14 Mnemonic NC VOUT1 VOUT7 VOUT11 VOUT16 VOUT20 VOUT25 NC VOUT0 VOUT4 VOUT9 VOUT13 VOUT17 VOUT21 VOUT26 VOUT3 VOUT22 VOUT29 VOUT2 VOUT23 VOUT5 VOUT8 VOUT12 VOUT15 VOUT19 VOUT24 VOUT31 VOUT6 VOUT10 VOUT14 VOUT18 VOUT30 VOUT28 Pin No. H1 H2 H4 to H11 H13 J3 to J12 K1 K2 K3 to K14 L1 L2 L3 to L13 L14 M1 to M12 M13 M14 N1 N2 N3 N4 N5 to N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 to P13 P14 Rev. A | Page 7 of 16 Mnemonic VPP VPP AGND VOUT27 AGND V+ V+ AGND NC NC AGND DAC_GND AGND AVCC AVCC PGND PGND CATHODE ANODE AGND NC REF_IN DAC_GND RESET DVCC DGND TEST DIN SCLK SYNC AGND NC AD5535B Data Sheet Table 5. Pin Function Descriptions Mnemonic AGND AVCC VPP V+ PGND DGND DVCC DAC_GND REF_IN VOUT0 to VOUT31 ANODE CATHODE SYNC SCLK DIN TEST RESET NC Description Analog GND Pins. Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. Output Amplifier High Voltage Supply. Voltage range from (REF_IN × 50) + 1 V to 225 V. V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V. Output Amplifier Ground Reference Pins. Digital GND Pins. Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for All DACs. Reference Voltage for Channel 0 to Channel 31. Reference input range is 1 V to 4 V and can be used to program the fullscale output voltage from 50 V to 200 V. Analog Output Voltages from the 32 Channels. Anode of Internal Diode for Diode Temperature Measurement. Cathode of Internal Diode for Diode Temperature Measurement. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in upon the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. The pin operates at clock speeds of up to 30 MHz. Internal pull-up device on logic input; therefore, it can be left floating and defaults to a logic high condition. Serial Data Input. Data must be valid upon the falling edge of SCLK. For normal operation, tie this pin low. Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is loaded to the DACs. No Connect. Do not connect to these pins. Rev. A | Page 8 of 16 Data Sheet AD5535B TYPICAL PERFORMANCE CHARACTERISTICS 16 1.00 VPP = 60V V+ = AVCC = +5V REF_IN = 1V TA = 25°C 12 0.50 4 0 –4 0.25 0 –0.25 –8 –0.50 –12 –0.75 0 2048 4096 6144 8192 10240 12288 –1.00 10852-018 –16 14336 16384 INPUT CODE 0 4096 6144 8192 10240 12288 14336 16384 INPUT CODE Figure 7. DNL with Full-Scale Range = 200 V Figure 4. Integral Nonlinearity (INL) with Full-Scale Range = 50 V 1.00 1.00 VPP = 60V V+ = AVCC = +5V REF_IN = 1V TA = 25°C CHANNEL 2 10kΩ DAC 0.50 DNL ERROR (LSB) 0.50 0.25 0 –0.25 0 –0.75 –0.75 4096 6144 8192 10240 12288 14336 16384 INPUT CODE CH2 5V M 500ns 4096 6144 8192 10240 INPUT CODE 12288CH1 1433621.6V 16384 Figure 8. Short-Circuit Current Limit Timing 1.00 VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25°C 12 CHANNEL 1 0CH1 5V 2048 Figure 5. Differential Nonlinearity (DNL) with Full-Scale Range = 50 V 16 T –1.00 10852-019 2048 CHANNEL 2 –0.25 –0.50 –1.00 AMP 0.25 –0.50 0 CHANNEL 1 0.75 10852-008 0.75 T 0.75 0.50 DNL ERROR (LSB) 8 4 0 –4 20 –0.25 –0.50 1 –12 –0.75 0 2048 4096 6144 8192 10240 12288 INPUT CODE 14336 16384 10852-020 –8 –16 Figure 6. INL with Full-Scale Range = 200 V CHANNEL 2 AREA 11 µV-sec 0.25 VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V VOUT = 100V TA = 25°C CHANNEL 1: CHANNEL OUTPUT SLEW CHANNEL 2: AC CROSSTALK –1.00 0CH1 50V 2048 200mV M 10µs 4096 CH2 6144 8192 10240 12288 INPUT CODE CH116384 14336 Figure 9. Worst-Case Adjacent Channel Crosstalk Rev. A | Page 9 of 16 10852-009 DNL ERROR (LSB) 2048 10852-021 DNL ERROR (LSB) INL ERROR (LSB) 8 INL ERROR (LSB) VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25°C 0.75 AD5535B Data Sheet 0.04 VPP = 210V V+ = AVCC = +5.25V 0.03 REF_IN = 4.096V TA = 25°C 140 DC CROSSTALK (V) 0.02 100 80 60 –4 –3 –2 –1 0 1 2 SOURCE/SINK CURRENT (mA) Figure 10. Output Amplifier Source and Sink Capability VICTIM CHANNEL = 31 –0.03 VOUT31 = MIDSCALE FULL-SCALE TRANSITION ON OTHER CHANNELS IN SEQUENCE. –0.04 0 5 10 15 30 180 0pF 160 140 OUTPUT VOLTAGE (V) 11.0 OFFSET ERROR (mV) 25 Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output, Switching All Other Channels in Sequence VPP = 210V V+ = AVCC = +5.25V 11.5 REF_IN = 4.096V 10.5 10.0 9.5 9.0 100pF 120 100 200pF 80 60 VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25°C 1/4 FULL-SCALE TO 3/4 FULL-SCALE STEP 40 8.5 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 10852-028 20 8.0 –10 Figure 11. Offset Error vs. Temperature VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V –1.2 –1.3 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 10852-029 –1.4 –1.5 –10 0 0 0.02 0.04 0.06 0.08 TIME (ms) Figure 14. Settling Time vs. Capacitive Load –1.1 GAIN ERROR (%) 20 CHANNEL NUMBER 12.0 –1.0 –0.01 –0.02 VPP = 210V V+ = AVCC = +5.25V REF_IN = 4.096V VOUT = 70V TA = 25°C 0 –5 0 10852-025 20 0.01 Figure 12. Gain Error vs. Temperature Rev. A | Page 10 of 16 0.10 10852-026 40 10852-022 OUTPUT VOLTAGE (V) 120 Data Sheet AD5535B TERMINOLOGY Integral Nonlinearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range. Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. DC Crosstalk The dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSB. Output Voltage Settling Time The time taken from when the last data bit is clocked into the DAC until the output has settled to within ±0.5 LSB of its final value. Measured for a step change of ¼ to ¾ full scale. Zero Code Voltage A measure of the output voltage present at the device output with all 0s loaded to the DAC. It includes the offset of the DAC and the output amplifier and is expressed in V. Digital-to-Analog Glitch Impulse The area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-sec when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Offset Error Calculated by taking two points in the linear region of the transfer function, drawing a line through these points, and extrapolating back to the y-axis. It is expressed in V. Voltage Gain Calculated from the change in output voltage for a change in code, multiplied by 16,384, and divided by the REF_IN voltage. This is calculated between two points in the linear section of the transfer function. Gain Error A measure of the output error with all 1s loaded to the DAC, and the difference between the ideal and actual analog output range. Ideally, the output should be 50 × REF_IN. It is expressed as a percentage of full-scale range. DC Power Supply Rejection Ratio (PSRR) A measure of the change in analog output for a change in VPP supply voltage. It is expressed in dB, and VPP is varied ±5%. Analog Crosstalk The area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-sec. Digital Feedthrough A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to (SYNC is high). It is specified in nV-sec and measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s and vice versa. Output Noise Spectral Density A measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in μV/√Hz. Rev. A | Page 11 of 16 AD5535B Data Sheet FUNCTIONAL DESCRIPTION At power-on, all the DAC registers are loaded with 0s. DAC SECTION The architecture of each DAC channel consists of a resistor string DAC, followed by an output buffer amplifier operating with a nominal gain of 50. The voltage at the REF_IN pin provides the reference voltage for the corresponding DAC. The input coding to the DAC is straight binary, and the ideal DAC output voltage is given by The A4 to A0 bits can address any one of the 32 channels. A4 is the MSB of the address, while A0 is the LSB. DB13 to DB0 Bits The DB13 to DB0 bits are used to write a 14-bit data-word into the addressed DAC register. Figure 2 is the timing diagram for a serial write to the AD5535B. The serial interface works with both a continuous and a discontinuous serial clock. The first falling edge of SYNC resets the serial clock counter to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC are ignored until the correct number of bits are shifted in. After 19 bits are shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. The user must allow 200 ns (minimum) between successive writes. LSB MSB A4 A3 A2 A1 DB13 TO DB0 A0 Figure 15. Serial Data Format 50 × V REF _ IN × D MICROPROCESSOR INTERFACING 214 where D is the decimal equivalent (0 to 16,383) of the binary code, which is loaded to the DAC register. The output buffer amplifier is specified to drive a load of 1 MΩ and 200 pF. The linear output voltage range for the output amplifier is from 7 V to VPP − 1 V. The amplifier output bandwidth is typically 30 kHz, and is capable of sourcing 550 µA and sinking 2.8 mA. Settling time for a ¼ to ¾ full-scale step change is typically 60 µs with a load of up to 200 pF. AD5535B-to-ADSP-BF527 Interface The Blackfin® DSP is easily interfaced to the AD5535B without the need for extra logic. A data transfer is initiated by writing a word to the TX register after SPORT is enabled. In a write sequence, data is clocked out on each rising edge of the serial clock of the DSP and clocked into the AD5535B on the falling edge of its SCLK. The SPORT can be configured to transmit 19 SCLKs while TFS is low. Figure 16 shows the connection diagram. RESET FUNCTION AD5535B The reset function on the AD5535B can be used to reset all nodes on the device to their power-on reset condition. All the DACs are loaded with 0s, and all registers are cleared. Take the RESET pin low to implement the reset function. SERIAL INTERFACE ADSP-BF527 SPORT_TFS SPORT_TSCK SPORT_DTO GPIO0 SYNC SCLK SDIN RESET The serial interface is controlled by the three following pins: • SYNC, which is the frame synchronization pin for the serial interface. • SCLK, which is the serial clock input that operates at clock speeds of up to 30 MHz. • DIN, which is the serial data input and data must be valid upon the falling edge of SCLK. To update a single DAC channel, a 19-bit data-word is written to the AD5535B input register. Rev. A | Page 12 of 16 Figure 16. AD5535B-to-ADSP-BF527 Interface 10852-011 VOUT = A4 to A0 Bits 10852-010 The AD5535B consists of a 32-channel, 14-bit DAC with 200 V high voltage amplifiers in a single 15 mm × 15 mm CSP_BGA package. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to the device is through a serial interface operating at clock rates of up to 30 MHz, which is compatible with DSP and microcontroller interface standards. A 5-bit address and a 14-bit data-word are loaded into the AD5535B input register via the serial interface. The channel address is decoded, and the data-word is converted into an analog output voltage for this channel. Data Sheet AD5535B Data appearing on the MOSI output is valid on the falling edge of SCK. The MC68HC11 transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. PC7 is then taken high and pulled low again before any further write cycles can take place. Figure 17 shows the connection diagram. AD5535B* MC68HC11* DIN SYNC SCK MOSI PC7 *ADDITIONAL PINS OMITTED FOR CLARITY. 10852-012 SCLK AD5535B* PIC16C6x/7x* SCLK DIN SYNC SCK/RC3 SDI/RC4 RA1 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 18. AD5535B-to-PIC16C6x/7x Interface AD5535B-to-8051 Interface The AD5535B requires a clock synchronized to the serial data. Therefore, the 8051 serial interface must operate in Mode 0. In this mode, serial data exits the 8051 through RxD, and a shift clock is output on TxD. The SYNC signal is derived from a port line (P1.1). Figure 19 shows how the 8051 is connected to the AD5535B. Because the AD5535B shifts data out upon the rising edge of the shift clock and latches data in upon the falling edge, the shift clock must be inverted. Note that the AD5535B also requires its data to be MSB first. Because the 8051 outputs LSB first, the transmit routine must take this into account. Figure 17. AD5535B-to-MC68HC11 Interface AD5535B* AD5535B-to-PIC16C6x/7x Interface The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). In this example, I/O port RA1 is being used to pulse SYNC and to enable the serial port of the AD5535B. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are 10852-013 The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR). SCK of the MC68HC11 drives the SCLK of the AD5535B and the MOSI output drives the serial data line (DIN) of the AD5535B. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5535B, the SYNC pin is taken low (PC7). necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. RA1 must be pulled low to start a transfer. RA1 must then be brought high and pulled low again before any further write cycles can take place. Figure 18 shows the connection diagram. 8051* SCLK TxD DIN RxD SYNC P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY. Rev. A | Page 13 of 16 Figure 19. AD5535B-to-8051 Interface 10852-014 AD5535B-to-MC68HC11 Interface AD5535B Data Sheet APPLICATIONS INFORMATION MEMS MIRROR CONTROL APPLICATION REF198 +5V +210V (4.096V) OUTPUT RANGE 0V TO 200V VPP REF_IN V+ The AD5535B is targeted to all optical switching control systems based on MEMS technology. The AD5535B is a 32-channel, 14-bit DAC with integrated high voltage amplifiers. The output amplifiers are capable of generating an output range of 0 V to 200 V when using a 4 V reference. The full-scale output voltage is programmable from 50 V to 200 V using reference voltages from 1 V to 4 V. Each amplifier can output 550 µA and directly drives the control actuators, which determine the position of MEMS mirrors in optical switch applications. 14-BIT DAC VOUT0 ACTUATORS FOR MEMS MIRROR VOUT31 ARRAY 14-BIT DAC SENSOR + 4-TO-1 MUX (ADG739) OR 32-TO-1 MUX (ADG732) OR SINGLECHANNEL ADC (AD7671) 10852-015 AD5535B 8-CHANNEL ADC (AD7856) ADSP-21065L The AD5535B is generally used in a closed-loop feedback system, as shown in Figure 20, with a high resolution ADC and DSP. The exact position of each mirror is measured using capacitive sensors. The sensor outputs are multiplexed using an ADG739 4-to-1 multiplexer to an 8-channel, 14-bit ADC (AD7856). An alternative solution is to multiplex using a 32-to-1 multiplexer (ADG732) into a single-channel ADC (AD7671). The control loop is driven by an ADSP-21065L, a 32-bit SHARC® DSP with an SPI-compatible SPORT interface. With 14-bit monotonic behavior and a 0 V to 200 V output range, coupled with its fast serial interface, the AD5535B is ideally suited for controlling a cluster of MEMS-based mirrors. Figure 20. AD5535B in a MEMS-Based Optical Switch IPC-221-COMPLIANT BOARD LAYOUT The diagram in Figure 21 is a typical 2-layer printed circuit board (PCB) layout for the AD5535B that complies with the specifications outlined in IPC-221. Do not connect to the four corner balls labeled as original no connects. Connect balls labeled as additional no connects to AGND. The routing shown in Figure 21 shows the feasibility of connecting to the high voltage balls while complying with the spacing requirements of IPC-221. Figure 21 also shows the physical distances that are available. A1 BALL PAD CORNER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C D ORIGINAL NO CONNECTS E F G ADDITIONAL NO CONNECTS J H 1.414mm m µm 5µ 05 D 40 AD 4 A = = R R E E m C µm C A A 0 0µ 25 SP µm SP 25 0 10 A B DETAIL A 250µm RAD SPACE = 433µm 100µm K 1 1 2mm SPACE = 433µm L 100µm M N SPACE = 433µm P 250µm RAD 1 Figure 21. Layout Guidelines to Comply with IPC-221 Rev. A | Page 14 of 16 10852-016 1 Data Sheet AD5535B POWER SUPPLY DECOUPLING RECOMMENDATIONS On the AD5535B, it is recommended to tie all grounds together as close to the device as possible. If the number of supplies must be reduced, bring all supplies back separately and make a provision on the board via a link option to drive the AVCC and V+ pins from the same supply. Decouple all power supplies adequately with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors. GUIDELINES FOR PCB LAYOUT Design printed circuit boards such that the analog and digital sections are separated and confined to the designated analog and digital sections of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally the best for ground planes because it optimizes shielding of sensitive signal lines. Join digital and analog ground planes in one place only, at the AGND and DGND pins of the high resolution converter. To isolate the high frequency bus of the processor from the bus of the high resolution converters, buffer or latch data and address buses on the board. These act as a Faraday shield and increase the signal-to-noise performance of the converters by reducing the amount of high frequency digital coupling. Avoid running digital lines under the device because they couple noise onto the die. Allow the ground plane to run under the IC to avoid noise coupling. Use as large a trace as possible for the supply lines of the device to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield components, such as clocks with fast-switching signals, with digital ground to avoid radiating noise to other sections of the board. Never run clock signals near the analog inputs of the device. Avoid crossovers of digital and analog signals. Keep traces for analog inputs as wide and short as possible and shield with analog ground if possible. Run traces on opposite sides of the 2-layer PCB at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible to use with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Multilayer printed circuit boards with dedicated ground, power, and tracking layers offer the optimum solution in terms of obtaining analog performance, but at increased manufacturing costs. Good decoupling is vitally important when using high resolution converters. Decouple all analog supplies with 10 µF tantalum capacitors in parallel with 0.1 µF ceramic capacitors to analog ground. To achieve the best results from the decoupling components, place them as close to the device as possible, ideally right up against the IC or the IC socket. The main aim of a bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thereby reducing the possibility of power supply spikes. Decouple digital supplies of high resolution converters with 10 µF tantalum capacitors and 0.1 µF ceramic capacitors to the digital ground plane. Decouple the V+ supply with a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor to AGND. Decouple all logic chips with 0.1 µF ceramic capacitors to digital ground to decouple high frequency effects associated with digital circuitry. Rev. A | Page 15 of 16 AD5535B Data Sheet OUTLINE DIMENSIONS 15.10 15.00 SQ 14.90 A1 BALL CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P BALL A1 PAD CORNER 13.00 REF TOP VIEW 1.00 BSC BOTTOM VIEW DETAIL A *1.25 MAX 0.85 MIN DETAIL A 1.70 MAX *0.41 0.36 0.31 COPLANARITY 0.12 *0.46 NOM BALL DIAMETER *COMPLIANT WITH JEDEC STANDARDS MO-192-AAE-1 WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK. NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm. 12-19-2012-A SEATING PLANE Figure 22. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-124-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5535BKBC AD5535BKBCZ EVAL-AD5535BEBZ 1 Function 32 DACs 32 DACs Output Voltage Span 0 V to 200 V maximum 0 V to 200 V maximum Temperature Range −10°C to +85°C −10°C to +85°C Z = RoHS Compliant Part. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10852-0-4/13(A) Rev. A | Page 16 of 16 Package Description 124-Lead CSP_BGA 124-Lead CSP_BGA Evaluation Board Package Option BC-124-2 BC-124-2