1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 AD7476/AD7477/AD7478 FUNCTIONAL BLOCK DIAGRAM FEATURES Fast throughput rate: 1 MSPS Specified for VDD of 2.35 V to 5.25 V Low power 3.6 mW at 1 MSPS with 3 V supplies 15 mW at 1 MSPS with 5 V supplies Wide input bandwidth 70 dB SNR at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Standby mode: 1 μA maximum 6-lead SOT-23 package VDD VIN 12-/10-/8-BIT SUCCESSIVEAPPROXIMATION ADC SCLK CONTROL LOGIC SDATA CS GND 01024-001 AD7476/AD7477/AD7478 Figure 1. APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7476/AD7477/AD74781 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 6 MHz. 1. First 12-/10-/8-Bit ADCs in SOT-23 Packages. 2. High Throughput with Low Power Consumption. 3. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. Current consumption is 1 μA maximum when in shutdown mode. 4. Reference Derived from the Power Supply. 5. No Pipeline Delay. The parts feature a standard successiveapproximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts. The AD7476/AD7477/AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the parts are 0 V to VDD. The conversion rate is determined by the SCLK. 1 Protected by U.S. Patent No. 6,681,332. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved. AD7476/AD7477/AD7478 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Terminology .................................................................................... 12 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 13 General Description ......................................................................... 1 Circuit Information.................................................................... 13 Product Highlights ........................................................................... 1 Converter Operation.................................................................. 13 Revision History ............................................................................... 2 ADC Transfer Function ............................................................. 13 Specifications..................................................................................... 3 Typical Connection Diagram ................................................... 14 AD7476 Specifications ................................................................. 3 Modes of Operation ................................................................... 15 AD7477 Specifications ................................................................. 5 Power vs. Throughput Rate ....................................................... 17 AD7478 Specifications ................................................................. 7 Serial Interface ............................................................................ 18 Timing Specifications .................................................................. 8 Microprocessor Interfacing ....................................................... 19 Absolute Maximum Ratings............................................................ 9 Outline Dimensions ....................................................................... 21 ESD Caution .................................................................................. 9 Ordering Guide .......................................................................... 22 Pin Configuration and Function Descriptions ........................... 10 REVISION HISTORY 1/09—Rev. E to Rev. F Changes to Features.......................................................................... 1 Changes to Ordering Guide .......................................................... 22 4/06—Rev. D to Rev. E Updated Format .................................................................. Universal Changes to Table 1 Endnotes .......................................................... 3 Changes to Table 2 Endnotes .......................................................... 5 Changes to Table 3 Endnotes .......................................................... 7 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 3/04—Rev. C to Rev. D Added U.S. Patent Number ..............................................................1 Changes to Specifications .................................................................2 Changes to Absolute Maximum Ratings ........................................6 Changes to AD7476/AD7477/AD7478 to ADSP-21xx Interface section.............................................................................. 16 2/03—Rev. B to Rev. C Changes to General Description .....................................................1 Changes to Specifications .................................................................2 Changes to Absolute Maximum Ratings ........................................6 Changes to Ordering Guide .............................................................6 Changes to Typical Connection Diagram section ..................... 10 Changes to Figure 8 caption.......................................................... 11 Changes to Figure 19...................................................................... 16 Changes to Figure 20...................................................................... 17 Updated Outline Dimensions ....................................................... 18 Rev. F | Page 2 of 24 AD7476/AD7477/AD7478 SPECIFICATIONS AD7476 SPECIFICATIONS A version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise noted; S and B versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 3 Signal-to-Noise Ratio (SNR)3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 A Version 1,2 B Version1,2 S Version1,2 Unit 69 70 70 69 70 −78 −80 dB min dB min dB typ dB min dB typ dB typ dB typ −80 −82 71.5 71 72.5 −78 −80 −78 −78 10 30 6.5 −78 −78 10 30 6.5 −78 −78 10 30 6.5 dB typ dB typ ns typ ps typ MHz typ 12 12 ±1.5 ±0.6 −0.9/+1.5 ±0.75 ±1.5 12 ±1.5 ±0.6 −0.9/+1.5 ±0.75 ±2 ±1.5 ±2 Bits LSB max LSB typ LSB max LSB typ LSB max LSB typ LSB max LSB typ 0 to VDD ±1 30 0 to VDD ±1 30 0 to VDD ±1 30 V μA max pF typ 2.4 1.8 0.4 0.8 ±1 ±1 10 2.4 1.8 0.4 0.8 ±1 ±1 10 2.4 1.8 0.4 0.8 ±1 ±1 10 V min V min V max V max μA max μA typ pF max 70 ±1 Differential Nonlinearity3 ±0.75 Offset Error3 70 ±0.5 Gain Error3 ±0.5 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUT Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 5 LOGIC OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding VDD − 0.2 0.4 ±10 10 VDD − 0.2 VDD − 0.2 0.4 0.4 ±10 ±10 10 10 Straight (Natural) Binary Rev. F | Page 3 of 24 V min V max μA max pF max Test Conditions/Comments fIN = 100 kHz sine wave B version, VDD = 2.4 V to 5.25 V TA = 25°C B version, VDD = 2.4 V to 5.25 V fa = 103.5 kHz, fb = 113.5 kHz fa = 103.5 kHz, fb = 113.5 kHz @ 3 dB S, B versions, VDD = (2.35 V to 3.6 V) 4 ; A version, VDD = (2.7 V to 3.6 V) Guaranteed no missed codes to 12 bits VDD = 2.35 V VDD = 3 V VDD = 5 V Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 μA; VDD = 2.35 V to 5.25 V ISINK = 200 μA AD7476/AD7477/AD7478 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation 7 Normal Mode (Operational) Full Power-Down A Version 1,2 B Version1,2 S Version1,2 Unit Test Conditions/Comments 0.8 500 350 1000 1.33 500 400 600 1.33 500 400 600 μs max ns max ns max kSPS max 16 SCLK cycles Full-scale step input Sine wave input ≤ 100 kHz See Serial Interface section 2.35/5.25 2.35/5.25 2.35/5.25 V min/max 2 1 3.5 2 1 3 2 1 3 mA typ mA typ mA max 1.6 1.4 1.4 mA max 1 80 1 80 1 80 μA max μA max Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.35 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = fSAMPLEMAX 6 VDD = 2.35 V to 3.6 V, fSAMPLE = fSAMPLEMAX6 SCLK off SCLK on 17.5 4.8 5 3 15 4.2 5 3 15 4.2 5 3 mW max mW max μW max μW max VDD = 5 V, fSAMPLE = fSAMPLEMAX6 VDD = 3 V, fSAMPLE = fSAMPLEMAX6 VDD = 5 V, SCLK off VDD = 3 V, SCLK off 1 Temperature range for A and B versions is −40°C to +85°C; temperature range for S version is −55°C to +125°C. Operational from VDD = 2.0 V. See the Terminology section. 4 Maximum B and S version specifications apply as typical figures when VDD = 5.25 V. 5 Guaranteed by characterization. 6 For A version: fSAMPLEMAX = 1 MSPS; B and S versions: fSAMPLEMAX = 600 kSPS. 7 See the Power vs. Throughput Rate section. 2 3 Rev. F | Page 4 of 24 AD7476/AD7477/AD7478 AD7477 SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE A Version 1,2 S Version1,2 Unit Signal-to-(Noise + Distortion) (SINAD) Total Harmonic Distortion (THD) 3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Gain Error3 ANALOG INPUT 61 −73 −74 61 −73 −74 dB min dB max dB max −78 −78 10 30 6.5 −78 −78 10 30 6.5 dB typ dB typ ns typ ps typ MHz typ 10 ±1 ±0.9 ±1 ±1 10 ±1 ±0.9 ±1 ±1 Bits LSB max LSB max LSB max LSB max 0 to VDD ±1 30 0 to VDD ±1 30 V μA max pF typ 2.4 0.8 0.4 ±1 ±1 10 2.4 0.8 0.4 ±1 ±1 10 V min V max V max μA max μA typ pF max Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate Test Conditions/Comments fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS fa = 103.5 kHz, fb = 113.5 kHz fa = 103.5 kHz, fb = 113.5 kHz @ 3 dB Guaranteed no missed codes to 10 bits VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD VDD – 0.2 VDD – 0.2 0.4 0.4 ±10 ±10 10 10 Straight (Natural) Binary V min V max μA max pF max ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V ISINK = 200 μA 800 400 1 ns max ns max MSPS max 16 SCLK cycles with SCLK at 20 MHz 800 400 1 Rev. F | Page 5 of 24 See Serial Interface section AD7476/AD7477/AD7478 Parameter POWER REQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode A Version 1,2 S Version1,2 Unit 2.7/5.25 2.7/5.25 V min/max 2 1 3.5 1.6 1 80 2 1 3.5 1.6 1 80 mA typ mA typ mA max mA max μA max μA max Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V; SCLK on or off VDD = 2.7 V to 3.6 V; SCLK on or off VDD = 4.75 V to 5.25 V; fSAMPLE = 1 MSPS VDD = 2.7 V to 3.6 V; fSAMPLE = 1 MSPS SCLK off SCLK on 17.5 4.8 5 17.5 4.8 5 mW max mW max μW max VDD = 5 V; fSAMPLE = 1 MSPS VDD = 3 V; fSAMPLE = 1 MSPS VDD = 5 V; SCLK off Test Conditions/Comments Power Dissipation 5 Normal Mode (Operational) Full Power-Down 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 3 Rev. F | Page 6 of 24 AD7476/AD7477/AD7478 AD7478 SPECIFICATIONS VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE A Version 1,2 S Version1,2 Unit Signal-to-(Noise + Distortion) (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD)3 Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth DC ACCURACY 49 −65 −65 49 −65 −65 dB min dB max dB max −68 −68 10 30 6.5 −68 −68 10 30 6.5 dB typ dB typ ns typ ps typ MHz typ Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error Gain Error Total Unadjusted Error (TUE) ANALOG INPUT 8 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 8 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 Bits LSB max LSB max LSB max LSB max LSB max Input Voltage Ranges DC Leakage Current Input Capacitance LOGIC INPUTS 0 to VDD ±1 30 0 to VDD ±1 30 V μA max pF typ 2.4 0.8 0.4 ±1 ±1 10 2.4 0.8 0.4 ±1 ±1 10 V min V max V max μA max μA typ pF max Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN, SCLK Pin Input Current, IIN, CS Pin Input Capacitance, CIN 4 LOGIC OUTPUTS Test Conditions/Comments fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS fa = 498.7 kHz, fb = 508.7 kHz fa = 498.7 kHz, fb = 508.7 kHz @ 3 dB Guaranteed no missed codes to eight bits VDD = 5 V VDD = 3 V Typically 10 nA, VIN = 0 V or VDD Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE VDD − 0.2 VDD − 0.2 0.4 0.4 ±10 ±10 10 10 Straight (Natural) Binary V min V max μA max pF max ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V ISINK = 200 μA Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS 800 400 1 800 400 1 ns max ns max MSPS max 16 SCLK cycles with SCLK at 20 MHz 2.7/5.25 2.7/5.25 V min/max 2 1 3.5 1.6 1 80 2 1 3.5 1.6 1 80 mA typ mA typ mA max mA max μA max μA max VDD IDD Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Rev. F | Page 7 of 24 See Serial Interface section Digital I/Ps = 0 V or VDD VDD = 4.75 V to 5.25 V, SCLK on or off VDD = 2.7 V to 3.6 V, SCLK on or off VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS SCLK off SCLK on AD7476/AD7477/AD7478 Parameter Power Dissipation 5 Normal Mode (Operational) Full Power-Down A Version 1,2 S Version1,2 Unit Test Conditions/Comments 17.5 4.8 5 17.5 4.8 5 mW max mW max μW max VDD = 5 V, fSAMPLE = 1 MSPS VDD = 3 V, fSAMPLE = 1 MSPS VDD = 5 V, SCLK off 1 Temperature range for A version is −40°C to +85°C; temperature range for S version is −55°C to +125°C. Operational from VDD = 2.0 V, with input high voltage, VINH = 1.8 V minimum. See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 3 TIMING SPECIFICATIONS VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 4. Parameter fSCLK 4 tCONVERT tQUIET t1 t2 t3 5 t45 t5 t6 t7 t8 6 tPOWER-UP 7 2,3 Limit at TMIN, TMAX 1 3V 5V 10 10 20 20 12 12 16 × tSCLK 50 10 10 20 40 70 0.4 × tSCLK 0.4 × tSCLK 10 10 25 1 16 × tSCLK 50 10 10 20 20 20 0.4 × tSCLK 0.4 × tSCLK 10 10 25 1 Unit kHz min MHz max MHz max Description A version ns min ns min ns min ns max ns max ns max ns min Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulsewidth CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge, A version Data access time after SCLK falling edge, B version SCLK low pulsewidth ns min SCLK high pulsewidth ns min ns min ns max μs typ SCLK to data valid hold time SCLK falling edge to SDATA high impedance SCLK falling edge to SDATA high impedance Power-up time from full power-down B version 1 3 V specifications apply from VDD = 2.7 V to 3.6 V for A version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B version; 5 V specifications apply from VDD = 4.75 V to 5.25 V. Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Version A timing specifications apply to the AD7477 and AD7478 S version; B version timing specifications apply to the AD7476 S version. 4 Mark/space ratio for the SCLK input is 40/60 to 60/40. 5 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 6 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading. 7 See Power-Up Time section. 2 200µA 1.6V CL 50pF 200µA IOH 01024-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specifications Rev. F | Page 8 of 24 AD7476/AD7477/AD7478 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Analog Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND Input Current to Any Pin Except Supplies1 Operating Temperature Range Commercial Range (A, B Versions) Military Range (S Version) Storage Temperature Range Junction Temperature SOT-23 Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow (10 sec to 30 sec) Pb-free Temperature Soldering Reflow ESD Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. –40°C to +85°C −55°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 235 (0/+5)°C 255 (0/+5)°C 3.5 kV 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 9 of 24 AD7476/AD7477/AD7478 VDD 1 GND 2 VIN 3 AD7476/ AD7477/ AD7478 6 CS 5 SDATA TOP VIEW 4 (Not to Scale) SCLK 01024-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD GND 3 4 VIN SCLK 5 SDATA 6 CS Description Power Supply Input. The VDD range for the AD7476/AD7477/AD7478 is from 2.35 V to 5.25 V. Analog Ground. Ground reference point for all circuitry on the part. All analog input signals should be referred to this GND voltage. Analog Input. Single-ended analog input channel. The input range is 0 V to VDD. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7476/AD7477/AD7478 conversion process. Data Out. Logic output. The conversion result is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7476 consists of four leading zeros followed by the 12 bits of conversion data; this is provided MSB first. The data stream from the AD7477 consists of four leading zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first. The data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion data, followed by four trailing zeros, which is provided MSB first. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7476/AD7477/AD7478 and framing the serial data transfer. Rev. F | Page 10 of 24 AD7476/AD7477/AD7478 TYPICAL PERFORMANCE CHARACTERISTICS 0 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 71.67dB THD = –81.00dB SFDR = –81.63dB –15 –20 –30 SNR (dB) SNR (dB) –35 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 49.82dB THD = –75.22dB SFDR = –67.78dB –10 –55 –75 –40 –50 –60 –70 –115 0 50 100 150 200 250 300 350 400 450 01024-007 01024-004 –95 –80 –90 500 0 50 100 FREQUENCY (kHz) 150 200 250 300 350 400 450 500 FREQUENCY (kHz) Figure 4. AD7476 Dynamic Performance at 1 MSPS Figure 7. AD7478 Dynamic Performance at 1 MSPS –66 8192 POINT FFT fSAMPLE = 600kSPS fIN = 100kHz SINAD = 71.71dB THD = –80.88dB SFDR = –83.23dB –15 VDD = 2.35V –68 SINAD (dB) SNR (dB) –35 SCLK = 20MHz –67 –55 –69 VDD = 2.7V –70 –75 VDD = 5.25V –71 01024-005 –115 0 50 100 150 200 250 VDD = 4.75V –72 VDD = 3.6V –73 10k 300 FREQUENCY (kHz) 1M INPUT FREQUENCY (kHz) Figure 5. AD7476 Dynamic Performance at 600 kSPS Figure 8. AD7476 SINAD vs. Input Frequency at 993 kSPS 0 –69.0 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 61.66dB THD = –80.64dB SFDR = –85.75dB –10 –20 –30 SCLK = 12MHz VDD = 2.35V –69.5 –70.0 SINAD (dB) –40 –50 –60 VDD = 2.7V –70.5 –71.0 VDD = 5.25V –70 –71.5 VDD = 4.75V –90 –100 0 50 100 150 200 250 300 350 400 450 VDD = 3.6V –72.0 –72.5 10k 500 FREQUENCY (kHz) 100k INPUT FREQUENCY (kHz) Figure 6. AD7477 Dynamic Performance at 1 MSPS Figure 9. AD7476 SINAD vs. Input Frequency at 605 kSPS Rev. F | Page 11 of 24 01024-009 –80 01024-006 SNR (dB) 100k 01024-008 –95 1M AD7476/AD7477/AD7478 TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7476/AD7477, the endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition, and full scale, a point ½ LSB above the last code transition. For the AD7478, the endpoints of the transfer function are zero scale, a point 1 LSB below the first code transition, and full scale, a point 1 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (such as AGND + 0.5 LSB). For the AD7478, this is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal (such as AGND + 1 LSB). Gain Error For the AD7476/AD7477, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as VREF – 1.5 LSB) after the offset error has been adjusted out. For the AD7478, this is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (such as VREF – 1 LSB) after the offset error has been adjusted. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after the end of conversion. See the Serial Interface section for more details. Signal-to-(Noise + Distortion) Ratio This is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Total Unadjusted Error This is a comprehensive specification that includes gain error, linearity error, and offset error. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7476/ AD7477/AD7478, it is defined as: THD(dB ) = 20 log V22 + V32 + V4 2 + V52 + V62 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), while the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7476/AD7477/AD7478 are tested using the CCIF standard where two input frequencies are used (fa = 498.7 kHz and fb = 508.7 kHz). In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB; for a 10-bit converter it is 62 dB; and for an 8-bit converter it is 50 dB. Rev. F | Page 12 of 24 AD7476/AD7477/AD7478 THEORY OF OPERATION CIRCUIT INFORMATION CHARGE REDISTRIBUTION DAC The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, fast, micropower, single-supply ADCs. The parts can be operated from a 2.35 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7476/AD7477/ AD7478 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. VIN A SAMPLING CAPACITOR COMPARATOR SW1 CONTROL LOGIC B SW2 01024-011 AGND CONVERSION PHASE VDD/2 Each AD7476/AD7477/AD7478 provides an on-chip, trackand-hold ADC and a serial interface housed in a tiny 6-lead SOT-23 package, which offers considerable space-saving advantages. The serial clock input accesses data from the part and provides the clock source for the successive-approximation ADC. The analog input range is 0 V to VDD. An external reference is not required for the ADC, nor is there a reference on-chip. The reference for the AD7476/AD7477/AD7478 is derived from the power supply and thus provides the widest dynamic input range. The AD7476/AD7477/AD7478 also feature a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. Figure 11. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7476/AD7477/AD7478 is straight binary. For the AD7476/AD7477, designed code transitions occur midway between successive integer LSB values, such as ½ LSB, 1½ LSB, and so on. The LSB size for the AD7476 is VDD/4096, and the LSB size for the AD7477 is VDD/1024. The ideal transfer characteristic for the AD7476/AD7477 is shown in Figure 12. For the AD7478, designed code transitions occur midway between successive integer LSB values, such as 1 LSB, 2 LSB, and so on. The LSB size for the AD7478 is VDD/256. The ideal transfer characteristic for the AD7478 is shown in Figure 13. CONVERTER OPERATION 111 ... 111 111 ... 110 ADC CODE The AD7476/AD7477/AD7478 are successive-approximation analog-to-digital converters based around a charge redistribution DAC. Figure 1 and Figure 11 show simplified schematics of the ADC. Figure 10 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. 111 ... 000 1LSB = VDD/4096 (AD7476) 1LSB = VDD/1024 (AD7477) 011 ... 111 CHARGE REDISTRIBUTION DAC 000 ... 010 000 ... 001 SAMPLING CAPACITOR COMPARATOR SW1 B AGND 0V CONTROL LOGIC ACQUISITION PHASE 0.5LSB +VDD – 1.5LSB ANALOG INPUT Figure 12. Transfer Characteristic for the AD7476/AD7477 SW2 VDD/2 01024-010 A 01024-012 000 ... 000 VIN 111 ... 111 Figure 10. ADC Acquisition Phase 111 ... 000 1LSB = VDD/256 (AD7478) 011 ... 111 000 ... 010 000 ... 001 000 ... 000 0V +VDD – 1LSB 1LSB ANALOG INPUT Figure 13. Transfer Characteristic for AD7478 Rev. F | Page 13 of 24 01024-013 ADC CODE 111 ... 110 When the ADC starts a conversion (see Figure 11), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 12 and Figure 13 show the ADC transfer function. AD7476/AD7477/AD7478 TYPICAL CONNECTION DIAGRAM Table 7. Figure 14 shows a typical connection diagram for the AD7476/AD7477/AD7478. VREF is taken internally from VDD and as such, VDD should be well decoupled. This provides an analog input range of 0 V to VDD. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477 is followed by two trailing zeros. The 8-bit result from the AD7478 is followed by four trailing zeros. Reference Tied to VDD AD780 @ 3 V REF193 AD780 @ 2.5 V REF192 AD1582 AD7476 SNR Performance 1 kHz Input (dB) 71.17 70.4 71.35 70.93 70.05 Analog Input Figure 15 shows an equivalent circuit of the analog input structure of the AD7476/AD7477/AD7478. The two diodes, D1 and D2, provide ESD protection for the analog input. Take care to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. This causes these diodes to become forward-biased and start conducting current into the substrate. These diodes can conduct a maximum of 10 mA without causing irreversible damage to the part. Alternatively, because the supply current required by the AD7476/AD7477/AD7478 is so low, a precision reference can be used as the supply source to the part. A REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) can be used to supply the required voltage to the ADC (see Figure 14). This configuration is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V, such as 15 V. The REF19x outputs a steady voltage to the AD7476/ AD7477/AD7478. If the low dropout REF193 is used, the current it typically needs to supply to the AD7476/AD7477/ AD7478 is 1 mA. When the ADC is converting at a rate of 1 MSPS, the REF193 needs to supply a maximum of 1.6 mA to the AD7476/AD7477/AD7478. The load regulation of the REF193 is typically 10 ppm/mA (REF193, VS = 5 V), which results in an error of 16 ppm (48 μV) for the 1.6 mA drawn from it. This corresponds to a 0.065 LSB error for the AD7476 with VDD = 3 V from the REF193, a 0.016 LSB error for the AD7477, and a 0.004 LSB error for the AD7478. For applications where power consumption is of concern, the power-down mode of the ADC and the sleep mode of the REF19x reference should be used to improve power performance. See the Modes of Operation section. The Capacitor C1 in Figure 15 is typically about 4 pF and can primarily be attributed to pin capacitance. The Resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 100 Ω. The Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 30 pF. For ac applications, removing high frequency components from the analog input signal is recommended by use of a band-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate using an input buffer amplifier. The choice of the op amp is a function of the particular application. VDD D1 1µF TANT VDD 0V TO VDD INPUT VIN GND AD7476/ AD7477/ AD7478 REF193 0.1µF 10µF VIN 10µF C1 4pF SDATA R1 C2 30pF D2 CONVERSAION PHASE—SWITCH OPEN TRACK PHASE—SWITCH CLOSED SCLK Figure 15. Equivalent Analog Input Circuit µC/µP CS 01024-014 1mA 690nF 5V SUPPLY 01024-015 3V SERIAL INTERFACE Figure 14. REF193 as Power Supply Table 7 provides some typical performance data with various references used as a VDD source with a low frequency analog input. Under the same setup conditions, the references are compared and the AD780 proved the optimum reference. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 16 shows a graph of the total harmonic distortion versus source impedance for different analog input frequencies when using a supply voltage of 2.7 V and sampling at a rate of 605 kSPS. Figure 17 and Figure 18 each show a graph of the total harmonic distortion vs. analog input signal frequency for various supply voltages while sampling at 993 kSPS with an SCLK frequency of 20 MHz and 605 kSPS with an SCLK frequency of 12 MHz, respectively. Rev. F | Page 14 of 24 AD7476/AD7477/AD7478 0 Digital Input VDD = 2.7V fS = 605kSPS –10 The digital input applied to the AD7476/AD7477/AD7478 is not limited by the maximum ratings that limit the analog input. Instead, the digital input applied can go to 7 V and is not restricted by the VDD + 0.3 V limit as on the analog input. For example, if the AD7476/AD7477/AD7478 are operated with a VDD of 3 V, then 5 V logic levels can be used on the digital input. However, note that the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS or SCLK is applied before VDD, there is no risk of latch-up as there is on the analog input when a signal greater than 0.3 V is applied prior to VDD. –20 –30 THD (dB) fIN = 200kHz –40 –50 fIN = 300kHz –60 –70 –80 01024-016 fIN = 100kHz –90 fIN = 10kHz –100 1 10 100 1k 10k SOURCE IMPEDANCE (Ω) Figure 16. THD vs. Source Impedance for Various Analog Input Frequencies –50 –55 –60 THD (dB) –65 –70 VDD = 2.35V VDD = 5.25V VDD = 2.7V –75 VDD = 4.75V –85 VDD = 3.6V –90 10k 100k 01024-017 –80 1M INPUT FREQUENCY (Hz) Figure 17. THD vs. Analog Input Frequency, fs = 993 kSPS –72 VDD = 2.35V –74 –78 VDD = 2.7V –80 VDD = 4.75V VDD = 5.25V –82 VDD = 3.6V –84 10k 100k INPUT FREQUENCY (Hz) Figure 18. THD vs. Analog Input Frequency, fs = 605 kSPS 01024-018 THD (dB) –76 1M MODES OF OPERATION Select the mode of operation of the AD7476/AD7477/AD7478 by controlling the (logic) state of the CS signal during a conversion. The two possible modes of operation are normal mode and power-down mode. The point at which CS is pulled high after the conversion has been initiated determines whether or not the AD7476/AD7477/AD7478 enters power-down mode. Similarly, if already in power-down, CS can control whether the device returns to normal operation or remains in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. Normal Mode This mode is intended for fastest throughput rate performance. Users do not have to worry about power-up times with the AD7476/AD7477/AD7478 remaining fully powered at all times. Figure 19 shows the general diagram of the AD7476/AD7477/ AD7478 in normal mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the tenth SCLK falling edge, but before the sixteenth SCLK falling edge, the part remains powered up, but the conversion terminates and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until CS returns high sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete, (SDATA has returned to threestate), another conversion can be initiated after the quiet time, tQUIET, has elapsed by again bringing CS low. Rev. F | Page 15 of 24 AD7476/AD7477/AD7478 Power-Down Mode This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered between each conversion, or a series of conversions can be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AD7476/AD7477/ AD7478 is in power-down mode, all analog circuitry is powered down. To enter power-down, the conversion process must be interrupted by bringing CS high any time after the second falling edge of SCLK and before the tenth falling edge of SCLK, as shown in Figure 20. Once CS is brought high in this window of SCLKs, the part enters power-down and the conversion initiated by the falling edge of CS is terminated and SDATA goes back into three-state. To exit this mode of operation and power up the AD7476/ AD7477/AD7478 again, perform a dummy conversion. On the falling edge of CS, the device begins to power up, and continues to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device is fully powered up once 16 SCLKs have elapsed and, as shown in Figure 21, valid data results from the next conversion. If CS is brought high before the tenth falling edge of SCLK, the AD7476/AD7477/AD7478 again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. Although the device may begin to power up on the falling edge of CS, it powers down again on the rising edge of CS as long as it occurs before the tenth SCLK falling edge. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. CS 1 10 16 SDATA 01024-019 SCLK 4 LEADING ZEROS + CONVERSION RESULT Figure 19. Normal Mode Operation CS 1 2 10 16 01024-020 SCLK THREE-STATE SDATA Figure 20. Entering Power-Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED CS A1 10 16 1 16 SDATA INVALID DATA VALID DATA Figure 21. Exiting Power-Down Mode Rev. F | Page 16 of 24 01024-021 SCLK AD7476/AD7477/AD7478 When powering up from the power-down mode with a dummy cycle, as shown in Figure 21, the track-and-hold, that was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 21. Although at any SCLK frequency, one dummy cycle is sufficient to power up the device and acquire VIN, this does not necessarily mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and fully acquire VIN; 1 μs is sufficient to power up the device and acquire the input signal. If, for example, a 5 MHz SCLK frequency is applied to the ADC, the cycle time is 3.2 μs. In one dummy cycle, 3.2 μs, the part is powered up and VIN is fully acquired. However, after 1 μs with a 5 MHz SCLK, only five SCLK cycles elapse. At this stage, the ADC is fully powered up and the signal acquired. In this case, the CS can be brought high after the tenth SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. When power supplies are first applied to the AD7476/AD7477/ AD7478, the ADC may power up in either power-down mode or normal mode. Allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, to keep the part in the power-down mode while not in use and then to power up the part in power-down mode, use the dummy cycle to ensure the device is in power-down by executing a cycle such as that shown in Figure 20. Once supplies are applied to the AD7476/AD7477/AD7478, the power-up time is the same when powering up from the power-down mode. It takes approximately 1 μs to fully power up if the part powers up in normal mode. It is not necessary to wait 1 μs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, ensure that adequate acquisition time has been allowed. POWER VS. THROUGHPUT RATE By using the power-down mode on the AD7476/AD7477/ AD7478 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 22 shows that as the throughput rate reduces, the device remains in its power-down state longer, and the average power consumption over time drops accordingly. For example, if the AD7476/AD7477/AD7478 operates in continuous sampling mode with a throughput rate of 100 kSPS and a SCLK of 20 MHz (VDD = 5 V), and the device is placed in the power-down mode between conversions, then the power consumption is calculated as follows. The power dissipation during normal operation is 17.5 mW (VDD = 5 V). If the powerup time is one dummy cycle, such as 1 μs, and the remaining conversion time is another cycle, such as 1 μs, then the part is said to dissipate 17.5 mW for 2 μs during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is (2/10) × (17.5 mW) = 3.5 mW. If VDD = 3 V, SCLK = 20 MHz, and the device is again in power-down mode between conversions, the power dissipation during normal operation is 4.8 mW. The AD7476/AD7477/AD7478 can now be said to dissipate 4.8 mW for 2 μs during each conversion cycle. With a throughput rate of 100 kSPS, the average power dissipated during each cycle is (2/10) × (4.8 mW) = 0.96 mW. Figure 22 shows the power vs. throughput rate when using the power-down mode between conversions with both 5 V and 3 V supplies. 100 VDD = 5V, SCLK = 20MHz 10 VDD = 3V, SCLK = 20MHz 1 0.1 01024-022 The power-up time of the AD7476/AD7477/AD7478 is typically 1 μs, which means that with any frequency of SCLK up to 20 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time (tQUIET) must still be allowed from the point at which the bus goes back into three-state (after the dummy conversion), to the next falling edge of CS. When running at 1 MSPS throughput rate, the AD7476/AD7477/ AD7478 powers up and acquires a signal within ±0.5 LSB in one dummy cycle, such as 1 μs. This means that if the ADC powers up in the desired mode of operation, and a dummy cycle is not required to change mode, then a dummy cycle is not required to place the track-and-hold into track. POWER (mW) Power-Up Time 0.01 0 50 100 150 200 250 300 350 THROUGHPUT RATE (kSPS) When powering up from power-down mode, the part returns to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track. Figure 22. Power vs. Throughput Rate Power-down mode is intended for use with throughput rates of approximately 333 kSPS and under. At higher sampling rates, power is not saved by using power-down mode. Rev. F | Page 17 of 24 AD7476/AD7477/AD7478 SERIAL INTERFACE Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7476/ AD7477/AD7478. Figure 23, Figure 24, and Figure 25 show the detailed timing diagrams for serial interfacing to the AD7476, AD7477, and AD7478, respectively. The serial clock provides the conversion clock and controls the transfer of information from the part during conversion. CS going low provides the first leading zero to be read by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Thus, the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge, although the first leading zero has to be read on the first SCLK falling edge after the CS falling edge. Therefore, the first rising edge of SCLK after the CS falling edge provides the second leading zero. The 15th rising SCLK edge has DB0 provided or the final zero for the AD7477 and AD7478. This may not work with most microcontrollers/DSPs, but could possibly be used with FPGAs and ASICs. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input at this point. The conversion initiates and requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold goes back into track on the next SCLK rising edge as shown at Point B in Figure 23, Figure 24, and Figure 25. On the sixteenth SCLK falling edge, the SDATA line will go back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion terminates and the SDATA line goes back into three-state; otherwise, SDATA returns to three-state on the 16th SCLK falling edge as shown in Figure 23, Figure 24, and Figure 25. t1 CS tCONVERT t6 1 SCLK 2 3 4 t3 SDATA THREESTATE Z B 5 13 ZERO ZERO DB11 15 t5 t7 t4 ZERO 14 16 t8 tQUIET DB10 DB2 DB1 THREE-STATE DB0 01024-023 t2 4 LEADING ZEROS Figure 23. AD7476 Serial Interface Timing Diagram t1 CS tCONVERT t6 1 SCLK 2 3 4 t3 THREESTATE SDATA Z B 5 13 ZERO ZERO DB9 15 t5 t7 t4 ZERO 14 16 t8 tQUIET DB8 DB0 4 LEADING ZEROS ZERO ZERO THREE-STATE 01024-024 t2 2 TRAILING ZEROS Figure 24. AD7477 Serial Interface Timing Diagram t1 CS tCONVERT t6 1 SCLK 2 3 4 t4 t3 SDATA THREESTATE Z ZERO ZERO 4 LEADING ZEROS ZERO B 12 DB7 13 14 15 t5 t7 16 t8 tQUIET ZERO 8 BITS OF DATA ZERO ZERO ZERO 4 TRAILING ZEROS Figure 25. AD7478 Serial Interface Timing Diagram Rev. F | Page 18 of 24 THREE-STATE 01024-025 t2 AD7476/AD7477/AD7478 MICROPROCESSOR INTERFACING The serial interface on the AD7476/AD7477/AD7478 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7476/AD7477/AD7478 with some of the more common microcontroller and DSP serial interface protocols. AD7476/AD7477/AD7478 to TMS320C5x/C54x Interface The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7476/ AD7477/AD7478. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7476/AD7477/AD7478 without any glue logic required. In addition, the serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format bit, FO, can be set to 1 to set the word length to eight bits, in order to implement the power-down mode on the AD7476/ AD7477/AD7478. The connection diagram is shown in Figure 26. Note that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provides equidistant sampling. SCLK TMS320C5x/ TMS320C54x1 The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS controls the RFS and, therefore, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, such as, TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data could be transmitted, or it could wait until the next clock edge. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, a SCLK of 2 MHz is obtained, and eight master clock periods elapse for every one SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and, subsequently, between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on an SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP. CLKX CLKR SDATA CS AD7476/ AD7477/ AD74781 DR FSX SCLK FSR SDATA 01024-026 1ADDITIONAL PINS OMITTED FOR CLARITY CS Figure 26. Interfacing to the TMS320C5x/C54x ADSP-21xx1 SCLK DR RFS TFS AD7476/AD7477/AD7478 to ADSP-21xx Interface The ADSP-21xx family of DSPs are interfaced directly to the AD7476/AD7477/AD7478 without any glue logic required. The SPORT control register is set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data-Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0 ITFS = 1 1ADDITIONAL PINS OMITTED FOR CLARITY 01024-027 AD7476/ AD7477/ AD74781 The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However, in this example, the timer interrupt controls the sampling rate of the ADC and, under certain conditions, equidistant sampling may not be achieved. Figure 27. Interfacing to the ADSP-21xx AD7476/AD7477/AD7478 to DSP56xxx Interface The connection diagram in Figure 28 shows how the AD7476/ AD7477/AD7478 can be connected to the synchronous serial interface (SSI) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB =1) with internally generated word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To implement the power-down mode, SLEN is set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 27. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. To implement the power-down mode on the AD7476/AD7477/ AD7478, the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. Note that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provides equidistant sampling. Rev. F | Page 19 of 24 AD7476/AD7477/AD7478 DSP56xxx1 AD7476/ AD7477/ AD74781 MC68HC161 SCK SCLK SCLK/PMC2 SDATA SRD SDATA MISO/PMC0 CS SC2 CS 1ADDITIONAL PINS OMITTED FOR CLARITY 01024-028 SCLK 1ADDITIONAL Figure 28. Interfacing to the DSP56xxx SS/PMC9 PINS OMITTED FOR CLARITY 01024-029 AD7476/ AD7477/ AD74781 Figure 29. Interfacing to the MC68HC16 AD7476/AD7477/AD7478 to MC68HC16 Interface The serial peripheral interface (SPI) on the MC68HC16 is configured for master mode (MSTR = 1), the clock polarity bit (CPOL) = 1, and the clock phase bit (CPHA) = 0. The SPI is configured by writing to the SPI Control Register (SPCR). For more information on the MC68HC16, check with Motorola for the related documentation. The serial transfer takes place as a 16-bit operation when the SIZE bit in the SPCR register is set to SIZE = 1. To implement the power-down mode with an 8-bit transfer, set SIZE = 0. A connection diagram is shown in Figure 29. Rev. F | Page 20 of 24 AD7476/AD7477/AD7478 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1 2 3 2.80 BSC 1.60 BSC PIN 1 INDICATOR 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.15 MAX 0.50 0.30 0.22 0.08 SEATING PLANE 10° 4° 0° 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 30. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev. F | Page 21 of 24 AD7476/AD7477/AD7478 ORDERING GUIDE Model AD7476ARTZ-500RL7 3 AD7476ARTZ-REEL3 AD7476ARTZ-REEL73 AD7476BRTZ-R23 AD7476BRTZ-REEL3 AD7476BRTZ-REEL73 AD7476SRTZ-500RL73 AD7476SRTZ-R23 AD7476SRTZ-REEL3 AD7476SRTZ-REEL73 AD7476WARJZ-RL73, 4 AD7477ARTZ-500RL73 AD7477ARTZ-REEL3 AD7477ARTZ-REEL73 AD7477SRTZ-REEL3 AD7478ARTZ-500RL73 AD7478ARTZ-REEL3 AD7478ARTZ-REEL73 AD7478SRTZ-REEL73 AD7478WARTZ-RL73, 4 EVAL-AD7476CBZ3, 6 EVAL-AD7477CBZ3, 6 EVAL-CONTROL BRD2 7 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −40°C to +85°C Linearity Error (LSB) 1 ±1 typical ±1 typical ±1 typical ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1.5 maximum ±1 typical ±1 maximum ±1 maximum ±1 maximum ±1 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum ±0.5 maximum 1 Package Option 2 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 RJ-6 Evaluation Board Evaluation Board Control Board Branding CEA# CEA# CEA# CEB# CEB# CEB# CES# CES# CES# CES# CEA# C46 5 C465 C465 C3F C3Z C3Z C3Z C3Y C3Z Linearity error refers to integral linearity error. RJ = 6-Lead SOT-23. Z = RoHS Compliant Part, # denotes RoHS compliant part maybe top or bottom marked. 4 Qualified for automotive. 5 Prior to 0523 date code, parts are marked with CFA#. 6 This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 7 This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, users need to order the particular ADC evaluation board, such as the EVAL-AD7476CB, the EVAL-CONTROL BRD2, and a 12 V ac transformer. See relevant evaluation board application note for more information. 2 3 Rev. F | Page 22 of 24 AD7476/AD7477/AD7478 NOTES Rev. F | Page 23 of 24 AD7476/AD7477/AD7478 NOTES ©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01024-0-1/09(F) Rev. F | Page 24 of 24