Data Sheet 250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-/14-/12-Bit ADC AD7656/AD7657/AD7658 FEATURES 6 independent ADCs True bipolar analog inputs Pin-/software-selectable ranges: ±10 V, ±5 V Fast throughput rate: 250 kSPS iCMOS process technology Low power 140 mW at 250 kSPS with 5 V supplies Wide input bandwidth 86.5 dB SNR at 50 kHz input frequency On-chip reference and reference buffers Parallel, serial, and daisy-chain interface modes High speed serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible Standby mode: 100 µW maximum 64-lead LQFP FUNCTIONAL BLOCK DIAGRAM VDD CONVST A CLK OSC REF CONVST B CONVST C AVCC DVCC CS SER/PAR VDRIVE CONTROL LOGIC STBY BUF V1 T/H 16-/14-/12-BIT SAR V2 T/H 16-/14-/12-BIT SAR OUTPUT DRIVERS DOUT A SCLK OUTPUT DRIVERS BUF V3 T/H 16-/14-/12-BIT SAR V4 T/H 16-/14-/12-BIT SAR BUF V5 T/H 16-/14-/12-BIT SAR V6 T/H 16-/14-/12-BIT SAR DOUT B OUTPUT DRIVERS DOUT C OUTPUT DRIVERS DATA/ CONTROL LINES RD APPLICATIONS AD7656/AD7657/AD7658 Power line monitoring systems Instrumentation and control systems Multi-axis positioning systems VSS AGND DGND 05020-001 WR Figure 1. GENERAL DESCRIPTION The AD7656/AD7657/AD76581 contain six 16-/14-/12-bit, fast, low power, successive approximation ADCs all in the one package that is designed on the iCMOS™ process (industrial CMOS). iCMOS is a process combining high voltage silicon with submicron CMOS and complementary bipolar technologies. It enables the development of a wide range of high performance analog ICs, capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, which dramatically reduces power consumption and package size. The AD7656/AD7657/AD7658 feature throughput rates up to 250 kSPS. The parts contain low noise, wide bandwidth, track-and-hold amplifiers that can handle input frequencies up to 12 MHz. 1 The conversion process and data acquisition are controlled using CONVST signals and an internal oscillator. Three CONVST pins allow independent, simultaneous sampling of the three ADC pairs. The AD7656/AD7657/AD7658 all have a high speed parallel and serial interface, allowing the devices to interface with microprocessors or DSPs. In serial interface mode, the parts have a daisy-chain feature that allows multiple ADCs to connect to a single serial interface. The AD7656/ AD7657/AD7658 can accommodate true bipolar input signals in the ±4 × VREF range and ±2 × VREF range. The AD7656/ AD7657/AD7658 also contain an on-chip 2.5 V reference. PRODUCT HIGHLIGHTS 1. 2. 3. Six 16-/14-/12-bit, 250 kSPS ADCs on board. Six true bipolar, high impedance analog inputs. Parallel and high speed serial interfaces. Protected by U.S. Patent No. 6,731,232. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved. AD7656/AD7657/AD7658 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 14 Applications ....................................................................................... 1 Terminology .................................................................................... 18 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 20 General Description ......................................................................... 1 Converter Details ....................................................................... 20 Product Highlights ........................................................................... 1 ADC Transfer Function ............................................................. 21 Revision History ............................................................................... 2 Reference Section ....................................................................... 21 Specifications..................................................................................... 3 Typical Connection Diagram ................................................... 21 AD7656 .......................................................................................... 3 Driving the Analog Inputs ........................................................ 22 AD7657 .......................................................................................... 5 Interface Section ......................................................................... 22 AD7658 .......................................................................................... 7 Application Hints ........................................................................... 29 Timing Specifications .................................................................. 9 Layout .......................................................................................... 29 Absolute Maximum Ratings .......................................................... 10 Power Supply Configuration..................................................... 29 Thermal Resistance .................................................................... 10 Outline Dimensions ....................................................................... 30 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 30 Pin Configuration and Function Descriptions ........................... 11 REVISION HISTORY 3/12—Rev. C to Rev D Changes to Figure 26 ...................................................................... 22 8/10—Rev. B to Rev. C Changes to t1 Unit in Table 4 ........................................................... 9 Changes to VDD to AVCC Rating in Table 5 .................................. 10 Added Power Supply Configuration Section .............................. 29 Added Figure 36.............................................................................. 29 VDD to AVCC 1/10—Rev. A to Rev. B Changes to Unit of DC Accuracy Parameter, Table 1 .................. 3 Changes to DC Accuracy Parameter, Table 2 ............................... 5 Changes to DC Accuracy Parameter, Table 3 ............................... 7 Changes to Terminology Section.................................................. 18 Updated Outline Dimensions ....................................................... 30 Changes to Ordering Guide .......................................................... 30 4/06—Rev. 0 to Rev. A Added AD7657/AD7658 parts ......................................... Universal Changes to Table 1.............................................................................3 Changes to Table 5.......................................................................... 10 3/06—Revision 0: Initial Version Rev. D | Page 2 of 32 Data Sheet AD7656/AD7657/AD7658 SPECIFICATIONS AD7656 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; For ±4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution No Missing Codes Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient B Version1 Y Version1 Unit 84 85.5 85 86.5 −90 −92 −100 −100 84 85.5 85 86.5 −90 −92 −100 −100 dB min dB typ dB min dB typ dB max dB typ dB typ dB typ −112 −107 10 4 35 −100 12 2 −112 −107 10 4 35 −100 12 2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 16 15 16 ±3 ±1 ±0.75 ±0.35 ±0.023 ±0.038 ±0.75 ±0.35 16 14 16 ±4.5 ±1 ±0.75 ±0.35 ±0.023 ±0.038 ±0.75 ±0.35 Bits Bits min Bits min LSB max LSB typ % FSR max % FSR max % FSR max % FSR max % FSR max % FSR max ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V µA max pF typ pF typ 2.5/3 ±1 18.5 2.49/2.51 150 25 6 2.5/3 ±1 18.5 2.49/2.51 150 25 6 V min/max µA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ Test Conditions/Comments fIN = 50 kHz sine wave VDD/VSS = ±5 V to ±10 V VDD/VSS = ±12 V to ±16.5 V fa = 50 kHz, fb = 49 kHz Rev. D | Page 3 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB @ 25°C ±0.22% FSR typical ±0.004% FSR typical ±0.22% FSR typical See Table 8 for min VDD/VSS for each range RNG bit/RANGE pin = 0 RNG bit/RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1,000 hours AD7656/AD7657/AD7658 Parameter LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL Normal Mode (Static) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) Normal Mode (Operational) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Data Sheet B Version1 Y Version1 Unit 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±1 ±1 10 10 Twos complement V min V max µA max pF max 3.1 550 250 3.1 550 250 µs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 28 28 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 80 80 µA max 143 140 35 100 143 140 35 100 mW max mW max mW max µW max Power Dissipation Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C. See the Terminology section. 3 Sample tested during initial release to ensure compliance. 1 2 Rev. D | Page 4 of 32 Test Conditions/Comments Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 µA ISINK = 200 µA Parallel interface mode only For 4 × VREF range, VDD = 10 V to 16.5 V For 4 × VREF range, VDD = −10 V to −16.5 V Digital I/PS = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS Data Sheet AD7656/AD7657/AD7658 AD7657 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; For ±4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution No Missing Codes Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 B Version1 Y Version1 Unit 81.5 82.5 83.5 −90 −92 −100 81.5 82.5 83.5 −89 −92 −100 dB min dB min dB typ dB max dB typ dB typ −109 −104 10 4 35 −100 12 2 −109 −104 10 4 35 −100 12 2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 14 14 ±1.5 ±1 ±0.75 ±0.3 ±0.0305 ±0.0427 ±0.75 ±0.3 14 14 ±1.5 ±1 ±0.75 ±0.3 ±0.0305 ±0.0427 ±0.75 ±0.3 Bits Bits min LSB max LSB typ % FSR max % FSR max % FSR max % FSR max % FSR max % FSR max ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V µA max pF typ pF typ 2.5/3 ±1 18.5 2.49/2.51 150 25 6 2.5/3 ±1 18.5 2.49/2.51 150 25 6 V min/max µA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max Test Conditions/Comments fIN = 50 kHz sine wave fa = 50 kHz, fb = 49 kHz Rev. D | Page 5 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB ±0.183% FSR typical ±0.015 % FSR typical ±0.183% FSR typical See Table 8 for min VDD/VSS for each range RNG bit/RANGE pin = 0 RNG bit/RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1,000 hours Typically 10 nA, VIN = 0 V or VDRIVE AD7656/AD7657/AD7658 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL Normal Mode (Static) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) Normal Mode (Operational) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Data Sheet B Version1 Y Version1 Unit Test Conditions/Comments VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±1 ±1 10 10 Twos complement V min V max µA max pF max ISOURCE = 200 µA ISINK = 200 µA 3.1 550 250 3.1 550 250 µs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 28 28 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 80 80 µA max 143 140 35 100 143 140 35 100 mW max mW max mW max µW max Power Dissipation Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C. See the Terminology section. 3 Sample tested during initial release to ensure compliance. 1 2 Rev. D | Page 6 of 32 Parallel interface mode only For 4 × VREF range, VDD = 10 V to 16.5 V For 4 × VREF range, VDD = −10 V to −16.5 V Digital I/PS = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS Data Sheet AD7656/AD7657/AD7658 AD7658 VREF = 2.5 V internal/external, AVCC = 4.75 V to 5.25 V, DVCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V; For ±4 × VREF range: VDD = 10 V to 16.5 V, VSS = −10 V to −16.5 V; For ±2 × VREF range: VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V; fSAMPLE = 250 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay Aperture Delay Matching Aperture Jitter Channel-to-Channel Isolation2 Full Power Bandwidth DC ACCURACY Resolution No Missing Codes Differential Nonlinearity Integral Nonlinearity2 Positive Full-Scale Error2 Positive Full-Scale Error Matching2 Bipolar Zero-Scale Error2 Bipolar Zero-Scale Error Matching2 Negative Full-Scale Error2 Negative Full-Scale Error Matching2 ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance 3 REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance3 Reference Output Voltage Long-Term Stability Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)3 B Version1 Y Version1 Unit 73 73.5 −88 −92 −97 73 73.5 −88 −92 −97 dB min dB typ dB max dB typ dB typ −106 −101 10 4 35 −100 12 2 −106 −101 10 4 35 −100 12 2 dB typ dB typ ns max ns max ps typ dB typ MHz typ MHz typ 12 12 ±0.7 ±1 ±0.75 ±0.366 ±3 ±3 ±0.75 ±0.366 12 12 ±0.7 ±1 ±0.75 ±0.366 ±3 ±3 ±0.75 ±0.366 Bits Bits min LSB max LSB max % FSR max % FSR max LSB max LSB max % FSR max % FSR max Test Conditions/Comments fIN = 50 kHz sine wave fa = 50 kHz, fb = 49 kHz ±4 × VREF ±2 × VREF ±1 10 14 ±4 × VREF ±2 × VREF ±1 10 14 V V µA max pF typ pF typ 2.5/3 ±1 18.5 2.49/2.51 150 25 6 2.5/3 ±1 18.5 2.49/2.51 150 25 6 V min/max µA max pF typ V min/max ppm typ ppm/°C max ppm/°C typ 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max Rev. D | Page 7 of 32 fIN on unselected channels up to 100 kHz @ −3 dB @ −0.1 dB ±0.244% FSR typical ±0.0488% FSR typical ±0.244% FSR typical See Table 8 for min VDD/VSS for each range RNG bit/RANGE pin = 0 RNG bit/RANGE pin = 1 ±4 × VREF range when in track ±2 × VREF range when in track REFEN/DIS = 1 1,000 hours Typically 10 nA, VIN = 0 V or VDRIVE AD7656/AD7657/AD7658 Parameter LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS AVCC DVCC VDRIVE ITOTAL Normal Mode (Static) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) Normal Mode (Operational) (Includes IAVCC, IVDD, IVSS, IVDRIVE, IDVCC) ISS (Operational) IDD (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Data Sheet B Version1 Y Version1 Unit Test Conditions/Comments VDRIVE − 0.2 VDRIVE − 0.2 0.2 0.2 ±1 ±1 10 10 Twos complement V min V max µA max pF max ISOURCE = 200 µA ISINK = 200 µA 3.1 550 250 3.1 550 250 µs max ns max kSPS 5/15 −5/−15 5 5 3/5 5/15 −5/−15 5 5 3/5 V nom min/max V nom min/max V nom V nom V nom min/max 28 28 mA max 26 26 mA max 0.25 0.25 7 0.25 0.25 7 mA max mA max mA max 80 80 µA max 143 140 35 100 143 140 35 100 mW max mW max mW max µW max Power Dissipation Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Full Power-Down Mode (STBY Pin) Temperature ranges are as follows: B version is −40°C to +85°C and Y version is −40°C to +125°C See the Terminology section. 3 Sample tested during initial release to ensure compliance. 1 2 Rev. D | Page 8 of 32 Parallel interface mode only For 4 × VREF range, VDD = 10 V to 16.5 V For 4 × VREF range, VDD = −10 V to −16.5 V Digital I/PS = 0 V or VDRIVE AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V VSS = −16.5 V, fSAMPLE = 250 kSPS VDD = 16.5 V, fSAMPLE = 250 kSPS AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V fSAMPLE = 250 kSPS Data Sheet AD7656/AD7657/AD7658 TIMING SPECIFICATIONS AVCC/DVCC = 4.75 V to 5.25 V, VDD = 5 V to 16.5 V, VSS = −5 V to −16.5 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMIN to TMAX, unless otherwise noted. 1 Table 4. Parameter PARALLEL MODE tCONVERT tQUIET Limit at TMIN, TMAX VDRIVE < 4.75 V VDRIVE = 4.75 V to 5.25 V Unit Description 3 150 3 150 µs typ ns min 550 25 60 2 25 ns min ns min ns max ms max µs max Conversion time, internal clock Minimum quiet time required between bus relinquish and start of next conversion Acquisition time Minimum CONVST low pulse CONVST high to BUSY high STBY rising edge to CONVST rising edge Partial power-down mode 15 0 5 5 5 ns min ns min ns min ns min ns min WR pulse width CS to WR setup time CS to WR hold time Data setup time before WR rising edge Data hold after WR rising edge 0 0 0 36 36 10 12 6 ns min ns min ns min ns min ns max ns min ns max ns min BUSY to RD delay CS to RD setup time CS to RD hold time RD pulse width Data access time after RD falling edge Data hold time after RD rising edge Bus relinquish time after RD rising edge Minimum time between reads 18 12 22 0.4 tSCLK 0.4 tSCLK 10 18 MHz max ns max ns max ns min ns min ns min ns max Frequency of serial read clock Delay from CS until SDATA three-state disabled Data access time after SCLK rising edge/CS falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time after SCLK falling edge CS rising edge to SDATA high impedance tACQ t10 t1 tWAKE-UP 550 25 60 2 25 PARALLEL WRITE OPERATION t11 15 t12 0 t13 5 t14 5 t15 5 PARALLEL READ OPERATION t2 0 t3 0 t4 0 t5 45 t6 45 t7 10 t8 12 t9 6 SERIAL INTERFACE fSCLK 18 t16 12 2 t17 22 t18 0.4 tSCLK t19 0.4 tSCLK t20 10 t21 18 2 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. A buffer is used on the data output pins for this measurement. 200µA TO OUTPUT PIN IOL 1.6V CL 25pF 200µA IOH 05020-002 1 Figure 2. Load Circuit for Digital Output Timing Specification Rev. D | Page 9 of 32 AD7656/AD7657/AD7658 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to AGND, DGND VSS to AGND, DGND VDD to AVCC AVCC to AGND, DGND DVCC to AVCC DVCC to DGND, AGND AGND to DGND VDRIVE to DGND Analog Input Voltage to AGND1 Digital Input Voltage to DGND Digital Output Voltage to GND REFIN to AGND Input Current to Any Pin Except Supplies2 Operating Temperature Range B Version Y Version Storage Temperature Range Junction Temperature Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow Rating −0.3 V to +16.5 V +0.3 V to −16.5 V AVCC − 0.3 V to 16.5 V −0.3 V to +7 V −0.3 V to AVCC + 0.3 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to DVCC + 0.3 V VSS − 0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVCC + 0.3 V ±10 mA −40°C to +85°C −40°C to +125°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a four-layer board. Table 6. Thermal Resistance Package Type 64-Lead LQFP ESD CAUTION 240(+0)°C 260(+0)°C If the analog inputs are being driven from alternative VDD and VSS supply circuitry, a 240 Ω series resistor should be placed on the analog inputs. 2 Transient currents of up to 100 mA do not cause SCR latch-up. 1 Rev. D | Page 10 of 32 θJA 45 θJC 11 Unit °C/W Data Sheet AD7656/AD7657/AD7658 AVCC AGND AGND REFIN/REFOUT REFCAPA AGND REFCAPB AGND REFCAPC 64 63 62 61 60 59 58 AGND AVCC AGND H/S SEL SER/PAR/SEL DB15 WR/REFEN/DIS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 48 V6 47 AVCC 3 46 AVCC DB11 4 45 V5 DB10/DOUT C 5 44 AGND DB9/DOUT B 6 43 AGND DB8/DOUT A 7 DGND 8 VDRIVE 9 DB14/REFBUF EN/DIS 1 DB13 2 DB12 PIN 1 AD7656/AD7657/AD7658 TOP VIEW (Not to Scale) 42 V4 41 AVCC 40 AVCC DB7/HBEN/DCEN 10 39 V3 DB6/SCLK 11 38 AGND DB5/DCIN A 12 37 AGND DB4/DCIN B 13 36 V2 DB3/DCIN C 14 35 AVCC DB2/SEL C 15 34 AVCC DB1/SEL B 16 33 V1 05020-003 VDD AGND VSS W/B RESET RANGE DVCC DGND STBY CONVST A CONVST B CONVST C CS RD BUSY DB0/SEL A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 54, 56, 58 33, 36, 39, 42, 45, 48 Mnemonic REFCAPA, REFCAPB, REFCAPC V1 to V6 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 AGND 26 DVCC 9 VDRIVE 8, 25 DGND 34, 35, 40, 41, 46, 47, 50, 60 AVCC 23, 22, 21 CONVST A, CONVST B, CONVST C Description Decoupling capacitors are connected to these pins. This decouples the reference buffer for each ADC pair. Each REFCAP pin should be decoupled to AGND using 10 µF and 100 nF capacitors. Analog Input 1 to 6. These are six single-ended analog inputs. In hardware mode, the analog input range on these channels is determined by the RANGE pin. In software mode, it is determined by Bit RNGC to Bit RNGA of the control register (see Table 10). Analog Ground. Ground reference point for all analog circuitry on the AD7656/AD7657/AD7658. All analog input signals and any external reference signal should be referred to this AGND voltage. All 11 of these AGND pins should be connected to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Digital Power, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to DGND, and 10 µF and 100 nF decoupling capacitors should be placed on the DVCC pin. Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the interface. Nominally at the same supply as the supply of the host interface. This pin should be decoupled to DGND, and 10 µF and 100 nF decoupling capacitors should be placed on the VDRIVE pin. Digital Ground. This is the ground reference point for all digital circuitry on the AD7656/AD7657/AD7658. Both DGND pins should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. These supply pins should be decoupled to AGND, and 10 µF and 100 nF decoupling capacitors should be placed on the AVCC pins. Conversion Start Input A, B, C. These logic inputs are used to initiate conversions on the ADC pairs. CONVST A is used to initiate simultaneous conversions on V1 and V2. CONVST B is used to initiate simultaneous conversions on V3 and V4. CONVST C is used to initiate simultaneous conversions on V5 and V6. When CONVSTx switches from low to high, the track-and-hold switch on the selected ADC pair switches from track to hold and the conversion is initiated. These inputs can also be used to place the ADC pairs into partial power-down mode. Rev. D | Page 11 of 32 AD7656/AD7657/AD7658 Pin No. 19 Mnemonic CS 20 RD 63 WR/REFEN/DIS 18 BUSY 51 REFIN/REFOUT 61 SER/PAR/SEL 17 DB0/SEL A 16 DB1/SEL B 15 DB2/SEL C 14 DB3/DCIN C 13 DB4/DCIN B 12 DB5/DCIN A 11 DB6/SCLK 10 DB7/HBEN/DCEN Data Sheet Description Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the output bus is enabled and the conversion result is output on the parallel data bus lines. When both CS and WR are logic low in parallel mode, DB[15:8] are used to write data to the on-chip control register. In serial mode, the CS is used to frame the serial read transfer and clock out the MSB of the serial output data. Read Data. When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, the RD line should be held low. Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low, DB[15:8] are used to write data to the internal control register. When the H/S SEL pin is low, this pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal reference is disabled and an external reference should be applied to the REFIN/REFOUT pin. When H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin should be decoupled. See the Reference Section. BUSY Output. This pin transitions high when a conversion is started and remains high until the conversion is complete and the conversion data is latched into the output data registers. A new conversion should not be initiated on the AD7656/AD7657/AD7658 when the BUSY signal is high. Reference Input/Output. The on-chip reference is available on this pin for use external to the AD7656/AD7657/AD7658. Alternatively, the internal reference can be disabled and an external reference can be applied to this input. See the Reference Section. When the internal reference is enabled, this pin should be decoupled using at least a 10 µF decoupling capacitor. Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is high, the serial interface mode is selected. In serial mode, DB[10:8] take on their DOUT[C:A] function, DB[0:2] take on their DOUT select function, DB7 takes on its DCEN function. In serial mode, DB15 and DB[13:11] should be tied to DGND. Data Bit 0/Select DOUT A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SEL A function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with one/two/three DOUT output pins and enables DOUT A as a serial output. When operating in serial mode, this pin should always be = 1. Data Bit 1/Select DOUT B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SEL B function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with two/three DOUT output pins and enables DOUT B as a serial output. If this pin is 0, the DOUT B is not enabled to operate as a serial data output pin and only one DOUT output pin, DOUT A, is used. Unused serial DOUT pins should be left unconnected. Data Bit 2/Select DOUT C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SEL C function; it is used to configure the serial interface. If this pin is 1, the serial interface operates with three DOUT output pins and enables DOUT C as a serial output. If this pin is 0, the DOUT C is not enabled to operate as a serial data output pin. Unused serial DOUT pins should be left unconnected. Data Bit 3/Daisy-Chain Input C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input C. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. Data Bit 4/Daisy-Chain Input B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input B. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. Data Bit 5/Daisy-Chain Input A. When SER/PAR is low, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and DCEN = 1, this pin acts as Daisy-Chain Input A. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. Data Bit 6/Serial Clock. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin takes on its SCLK input function; it is the read serial clock for the serial transfer. Data Bit 7/High Byte Enable/Daisy-Chain Enable. When operating in parallel word mode (SER/PAR = 0 and W/B = 0), this pin takes on its Data Bit 7 function. When operating in parallel byte mode (SER/PAR = 0 and W/B = 1), this pin takes on its HBEN function. When in this mode and the HBEN pin is logic high, the data is output MSB byte first on DB[15:8]. When the HBEN pin is logic low, the data is output LSB byte first on DB[15:8]. When operating in serial mode (SER/PAR = 1), this pin takes on its DCEN function. When the DCEN pin is logic high, the parts operate in daisychain mode with DB[5:3] taking on their DCIN[A:C] function. When operating in serial mode but not in daisy-chain mode, this pin should be tied to DGND. Rev. D | Page 12 of 32 Data Sheet Pin No. 7 Mnemonic DB8/DOUT A 6 DB9/DOUT B 5 DB10/DOUT C 4 DB11 3, 2, 64 DB12, DB13, DB15 1 DB14/REFBUFEN/DIS 28 RESET 27 RANGE 31 VDD 30 VSS 24 STBY 62 H/S SEL 29 W/B AD7656/AD7657/AD7658 Description Data Bit 8/Serial Data Output A. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL A = 1, this pin takes on its DOUT A function and outputs serial conversion data. Data Bit 9/Serial Data Output B. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL B = 1, this pin takes on its DOUT B function and outputs serial conversion data. This configures the serial interface to have two DOUT output lines. Data Bit 10/Serial Data Output C. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1 and SEL C = 1, this pin takes on its DOUT C function and outputs serial conversion data. This configures the serial interface to have three DOUT output lines. Data Bit 11/Digital Ground. When SER/PAR = 0, this pin acts as a three-state parallel digital output pin. When SER/PAR = 1, this pin should be tied to DGND. Data Bit 12, Data Bit 13, Data Bit 15. When SER/PAR = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output the conversion result. When CS and WR are low, these pins are used to write to the control register. When SER/PAR = 1, these pins should be tied to DGND. For the AD7657, DB15 contains a leading zero. For the AD7658, DB15, DB13, and DB12 contain leading zeros. Data Bit 14/REFBUF Enable/Disable. When SER/PAR = 0, this pin acts as a three-state digital input/ output pin. For the AD7657/AD7658, DB14 contains a leading zero. When SER/PAR = 1, this pin can be used to enable or disable the internal reference buffers. Reset Input. When set to logic high, this pin resets the AD7656/AD7657/AD7658. The current conversion, if any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656/AD7657/AD7658 are configured depending on the logic levels on the hardware select pins. In all modes, the parts should receive a RESET pulse after power-up. The reset high pulse should be typically 100 ns wide. After the RESET pulse, the AD7656/AD7657/AD7658 needs to see a valid CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse. Analog Input Range Selection. Logic input. The logic level on this pin determines the input range of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND and the input range is determined by the RNGA, RNGB, and RNGC bits in the control register. Positive Power Supply Voltage. This is the positive supply voltage for the analog input section, and 10 µF and 100 nF decoupling capacitors should be placed on the VDD pin. Negative Power Supply Voltage. This is the negative supply voltage for the analog input section, and 10 µF and 100 nF decoupling capacitors should be placed on the VSS pin. Standby Mode Input. This pin is used to put all six on-chip ADCs into standby mode. The STBY pin is high for normal operation and low for standby operation. Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656/AD7657/AD7658 operate in hardware select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST pins. When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the control register. In serial mode, CONVST A is used to initiate conversions on the selected ADC pairs. Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656/AD7657/ AD7658 using the parallel data lines DB[15:0]. When this pin is logic high, byte mode is enabled. In this mode, data is transferred using data lines DB[15:8] and DB[7] takes on its HBEN function. To obtain the 16-bit conversion result, 2-byte reads are required. In serial mode, this pin should be tied to DGND. Rev. D | Page 13 of 32 AD7656/AD7657/AD7658 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 0 VDD/VSS = ±15V AVCC/DVCC/VDRIVE = +5V INTERNAL REFERENCE ±10V RANGE TA = 25°C fS = 250kSPS fIN = 50kHz SNR = +87.33dB SINAD = +87.251dB THD = –104.32dB SFDR = –104.13dB –40 –80 1.0 0.5 0 –0.5 –100 AVCC/DVCC/VDRIVE = +5V –1.0 V /V = ±12V DD SS fSAMPLE = 250kSPS 2 × VREF RANGE –1.5 DNL WCP = 0.81LSB DNL WCN = –0.57LSB –2.0 0 10k 20k 30k –120 05020-030 –140 –160 0 25 50 75 100 125 40k 50k 60k 65535 CODE FREQUENCY (kHz) Figure 7. AD7656 Typical DNL Figure 4. AD7656 FFT for ±10 V Range 2.0 0 VDD/VSS = ±12V AVCC/DVCC/VDRIVE = +5V INTERNAL REFERENCE ±5V RANGE TA = 25°C fS = 250kSPS fIN = 50kHz SNR = +86.252dB SINAD = +86.196dB THD = –105.11dB SFDR = –98.189dB –40 –60 –80 AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V 1.6 fSAMPLE = 250kSPS 2 × VREF RANGE 1.2 0.8 INL (LSB) –20 (dB) 05020-016 (dB) –60 1.5 DNL (LSB) –20 –100 0.4 0 –0.4 –0.8 –120 05020-031 –160 0 25 50 75 100 05020-035 –1.2 –140 –1.6 –2.0 125 0 2000 4000 6000 10000 12000 14000 16383 12000 14000 16383 Figure 8. AD7657 Typical INL Figure 5. AD7656 FFT for ±5 V Range 2.0 2.0 AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V 1.5 fSAMPLE = 250kSPS 2 × VREF RANGE 1.0 INL WCP = 0.64LSB INL WCN = –0.76LSB AVCC/DVCC/VDRIVE = +5V 1.6 VDD/VSS = ±12V 1.2 0.8 DNL (LSB) 0.5 0 –0.5 0.4 0 –0.4 –0.8 –1.0 –2.0 0 10k 20k 30k 40k 50k 60k 65535 05020-034 –1.2 –1.5 05020-017 INL (LSB) 8000 CODE FREQUENCY (kHz) –1.6 –2.0 0 2000 4000 6000 8000 10000 CODE CODE Figure 9. AD7657 Typical DNL Figure 6. AD7656 Typical INL Rev. D | Page 14 of 32 Data Sheet AD7656/AD7657/AD7658 –60 1.0 AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V fSAMPLE = 250kSPS 2 × VREF RANGE 0.8 0.6 –70 0 –0.2 AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±5.25V ±5V RANGE AVCC/DVCC/ VDRIVE = +4.75V VDD/VSS = ±10V ±10V RANGE –80 0.2 THD (dB) –90 AVCC/DVCC/ VDRIVE = +5V VDD/VSS = ±12V ±5V RANGE –100 –0.4 –0.6 AVCC/DVCC/ VDRIVE = +5.25V VDD/VSS = ±16.5V ±10V RANGE 05020-033 –110 –0.8 0 500 1000 1500 2000 2500 3000 3500 –120 10 4095 CODE 05020-022 INL (LSB) 0.4 –1.0 fSAMPLE = 250kSPS INTERNAL REFERENCE TA = 25°C 1000 100 ANALOG INPUT FREQUENCY (kHz) Figure 10. AD7658 Typical INL Figure 13. AD7656 THD vs. Input Frequency 1.0 –60 VDD/VSS = ±16.5V AVCC/DVCC/VDRIVE = +5.25V TA = 25°C –70 INTERNAL REFERENCE ±4 × VREF RANGE AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V fSAMPLE = 250kSPS 2 × VREF RANGE 0.8 0.6 0.4 THD (dB) DNL (LSB) –80 0.2 0 –0.2 RSOURCE = 1000Ω –90 RSOURCE = 220Ω –100 –0.4 RSOURCE = 100Ω –0.6 500 1000 1500 2000 2500 3000 3500 –120 10 4095 CODE –40 AVCC/DVCC/ VDRIVE = +5V VDD/VSS = ±12V ±5V RANGE –60 75 AVCC/DVCC/ VDRIVE = +5V VDD/VSS = ±5.25V ±5V RANGE 70 65 f SAMPLE = 250kSPS INTERNAL REFERENCE TA = 25°C 60 10 100 RSOURCE = 1000Ω –80 –90 –100 RSOURCE = 100Ω –110 RSOURCE = 10Ω RSOURCE = 220Ω RSOURCE = 50Ω –120 10 1000 ANALOG INPUT FREQUENCY (kHz) Figure 12. AD7656 SINAD vs. Input Frequency VDD/VSS = ±12V AVCC/DVCC/VDRIVE = +5V TA = 25°C INTERNAL REFERENCE ±2 × VREF RANGE –70 THD (dB) AVCC/DVCC/ VDRIVE = +4.75 V VDD/VSS = ±10V ±10V RANGE –50 05020-023 SINAD (dB) 80 Figure 14. AD7656 THD vs. Input Frequency for Various Source Impedances, ±4 × VREF Range AVCC/DVCC/VDRIVE = +5.25V VDD/VSS = ±16.5V ±10V RANGE 85 100 ANALOG INPUT FREQUENCY (kHz) Figure 11. AD7658 Typical DNL 90 05020-026 0 RSOURCE = 10Ω RSOURCE = 50Ω 05020-027 –1.0 –110 05020-032 –0.8 100 ANALOG INPUT FREQUENCY (kHz) Figure 15. AD7656 THD vs. Input Frequency for Various Source Impedances, ±2 × VREF Range Rev. D | Page 15 of 32 AD7656/AD7657/AD7658 Data Sheet 2.510 2.508 100 fSAMPLE = 250kSPS ±2 × VREF RANGE INTERNAL REFERENCE TA = 25°C fIN = 10kHz 100nF ON VDD AND VSS AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V 80 2.504 PSRR (dB) REFERENCE VOLTAGE (V) 90 2.506 2.502 2.500 70 VSS 60 2.498 VDD 2.496 2.492 –55 –35 –15 5 25 45 65 85 105 05020-021 05020-018 50 2.494 40 30 125 80 TEMPERATURE (°C) 130 180 230 280 330 380 430 480 530 SUPPLY RIPPLE FREQUENCY (kHz) Figure 16. Reference Voltage vs. Temperature Figure 19. PSRR vs. Supply Ripple Frequency 3.20 87.0 AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V 3.15 86.5 86.0 3.05 85.5 3.00 SNR (dB) CONVERSION TIME (µs) 3.10 2.95 2.90 ±5V RANGE, AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V ±10V RANGE, AVCC/DVCC/VDRIVE = +5.25V VDD/VSS = ±16.5V 85.0 84.5 2.85 84.0 2.70 –55 83.5 fSAMPLE = 250kSPS fIN = 50kHz INTERNAL REFERENCE 83.0 –40 –20 0 20 40 05020-019 2.75 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 80 100 120 140 Figure 20. AD7656 SNR vs. Temperature –100 3500 3212 3000 VDD/VSS = ±15V AVCC/DVCC/VDRIVE = +5V INTERNAL REFERENCE 8192 SAMPLES 2806 –101 fSAMPLE = 250kSPS fIN = 50kHz INTERNAL REFERENCE –102 THD (dB) 2500 2000 1532 1500 ±10V RANGE, AVCC/DVCC/VDRIVE = +5.25V VDD/VSS = ±16.5V –103 –104 ±5V RANGE, AVCC/DVCC/VDRIVE = +5V VDD/VSS = ±12V –105 500 392 168 57 –4 –3 –2 –1 0 1 25 0 2 3 –106 –107 –40 05020-024 1000 05020-029 NUMBER OF OCCURRENCES 60 TEMPERATURE (°C) Figure 17. Conversion Time vs. Temperature 0 0 –5 05020-025 2.80 –20 0 20 40 60 80 100 TEMPERATURE (°C) CODE Figure 21. AD7656 THD vs. Temperature Figure 18. AD7656 Histogram of Codes Rev. D | Page 16 of 32 120 140 AD7656/AD7657/AD7658 120 30 110 25 100 90 80 AVCC/DVCC/VDRIVE = 5V VDD/VSS = ±12V TA = 25°C INTERNAL REFERENCE ±2 × VREF RANGE 30kHz ON SELECTED CHANNEL 70 20 40 60 80 ±5V RANGE 15 10 AVCC/DVCC/VDRIVE = +5V fSAMPLE = 250kSPS FOR ±5V RANGE VDD/VSS = ±12V FOR ±10V RANGE VDD/VSS = ±16.5V 5 60 0 20 100 120 140 0 –40 –20 0 20 40 60 TEMPERATURE (°C) FREQUENCY OF INPUT NOISE (kHz) Figure 22. Channel-to-Channel Isolation Figure 23. Dynamic Current vs. Temperature Rev. D | Page 17 of 32 80 05020-020 DYNAMIC CURRENT (mA) ±10V RANGE 05020-028 CHANNEL-TO-CHANNEL ISOLATION (dB) Data Sheet 100 AD7656/AD7657/AD7658 Data Sheet TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a ½ LSB below the first code transition and full scale at ½ LSB above the last code transition. The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Thus, this is 98 dB for a 16-bit converter, 86.04 dB for a 14-bit converter, and 74 dB for a 12-bit converter. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, that is, AGND − 1 LSB. Bipolar Zero Code Error Matching The difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the last code transition (011…110) to (011…111) from the ideal (+4 × VREF − 1 LSB, +2 × VREF − 1 LSB) after adjusting for the bipolar zero code error. Positive Full-Scale Error Matching The difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition (10…000) to (10…001) from the ideal (−4 × VREF + 1 LSB, −2 × VREF + 1 LSB) after adjusting for the bipolar zero code error. Negative Full-Scale Error Matching The difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of the conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of the conversion. See the Track-and-Hold Section for more details. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7656/AD7657/AD7658, it is defined as THD (dB) = 20 log V2 2 + V3 2 + V 4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7656/AD7657/AD7658 are tested using the CCIF standard in which two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Power Supply Rejection (PSR) Variations in power supply affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. See the Typical Performance Characteristics section. Rev. D | Page 18 of 32 Data Sheet AD7656/AD7657/AD7658 Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 30 kHz signal. Figure 19 shows the power supply rejection ratio vs. supply ripple frequency for the AD7656/AD7657/AD7658. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC’s VDD and VSS supplies of frequency fS PSRR (dB) = 10 log (Pf/PfS) where: Pf is equal to the power at frequency f in the ADC output. PfS is equal to the power at frequency fS coupled onto the VDD and VSS supplies. % FSR %FSR is calculated using the full theoretical span of the ADC. Rev. D | Page 19 of 32 AD7656/AD7657/AD7658 Data Sheet THEORY OF OPERATION CONVERTER DETAILS Analog Input Section The AD7656/AD7657/AD7658 are high speed, low power converters that allow the simultaneous sampling of six on-chip ADCs. The analog inputs on the AD7656/AD7657/AD7658 can accept true bipolar input signals. The RANGE pin/RNG bits are used to select either ±4 × VREF or ±2 × VREF as the input range for the next conversion. The AD7656/AD7657/AD7658 can handle true bipolar input voltages. The logic level on the RANGE pin or the value written to the RNGx bits in the control register determines the analog input range on the AD7656/AD7657/AD7658 for the next conversion. When the RANGE pin/RNGx bit is 1, the analog input range for the next conversion is ±2 × VREF. When the RANGE pin/RNGx bit is 0, the analog input range for the next conversion is ±4 × VREF. A conversion is initiated on the AD7656/AD7657/AD7658 by pulsing the CONVST x input. On the rising edge of CONVST x, the track-and-hold of the selected ADC pair is placed into hold mode and the conversions are started. After the rising edge of CONVST x, the BUSY signal goes high to indicate that the conversion is taking place. The conversion clock for the AD7656/AD7657/AD7658 is internally generated, and the conversion time for the parts is 3 µs. The BUSY signal returns low to indicate the end of conversion. On the falling edge of BUSY, the track-and-hold returns to track mode. Data can be read from the output register via the parallel or serial interface. Track-and-Hold Section The track-and-hold amplifiers on the AD7656/AD7657/AD7658 allow the ADCs to accurately convert an input sine wave of fullscale amplitude to 16-/14-/12-bit resolution, respectively. The input bandwidth of the track-and-hold amplifiers is greater than the Nyquist rate of the ADC, even when the AD7656/ AD7657/AD7658 are operating at its maximum throughput rate. The parts can handle input frequencies of up to 12 MHz. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVSTx. The aperture time for the track-and-hold (that is, the delay time between the external CONVSTx signal actually going into hold) is 10 ns. This is well matched across all six track-and-holds on one device and from device to device. This allows more than six ADCs to be sampled simultaneously. The end of the conversion is signaled by the falling edge of BUSY, and it is at this point that the track-and-holds return to track mode and the acquisition time begins. VDD D1 R1 C2 V1 C1 D2 05020-004 Each AD7656/AD7657/AD7658 contains six SAR ADCs, six track-and-hold amplifiers, an on-chip 2.5 V reference, reference buffers, and high speed parallel and serial interfaces. The parts allow the simultaneous sampling of all six ADCs when all three CONVST signals are tied together. Alternatively, the six ADCs can be grouped into three pairs. Each pair has an associated CONVST signal used to initiate simultaneous sampling on each ADC pair, on four ADCs, or on all six ADCs. CONVST A is used to initiate simultaneous sampling on V1 and V2, CONVST B is used to initiate simultaneous sampling on V3 and V4, and CONVST C is used to initiate simultaneous sampling on V5 and V6. VSS Figure 24. Equivalent Analog Input Structure Figure 24 shows an equivalent circuit of the analog input structure of the AD7656/AD7657/AD7658. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the VDD and VSS supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward-biased and to start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the parts is 10 mA. Capacitor C1 in Figure 24 is typically about 4 pF and can be attributed primarily to pin capacitance. Resistor R1 is a lumped component made up of the on resistance of a switch (track-and-hold switch). This resistor is typically about 25 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 10 pF typically. The AD7656/AD7657/AD7658 require VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than the analog input range (see Table 8 for the requirements on these supplies for each analog input range). The AD7656/AD7657/AD7658 require a low voltage AVCC supply of 4.75 V to 5.25 V to power the ADC core, a DVCC supply of 4.75 V to 5.25 V for the digital power, and a VDRIVE supply of 2.7 V to 5.25 V for the interface power. To meet the specified performance when using the minimum supply voltage for the selected analog input range, it can be necessary to reduce the throughput rate from the maximum throughput rate. Table 8. Minimum VDD/VSS Supply Voltage Requirements Analog Input Range (V) ±4 × VREF ±4 × VREF ±2 × VREF ±2 × VREF Rev. D | Page 20 of 32 Reference Voltage (V) +2.5 +3.0 +2.5 +3.0 Full-Scale Input (V) ±10 ±12 ±5 ±6 Minimum VDD/VSS (V) ±10 ±12 ±5 ±6 Data Sheet AD7656/AD7657/AD7658 ADC TRANSFER FUNCTION The output coding of the AD7656/AD7657/AD7658 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/65536 for the AD7656, FSR/16384 for the AD7657, and FSR/4096 for the AD7658. The ideal transfer characteristic is shown in Figure 25. ADC CODE 011...111 011...110 000...001 000...000 111...111 –FSR/2 + 1/2LSB AGND – 1LSB +FSR/2 – 3/2LSB ANALOG INPUT 05020-005 100...010 100...001 100...000 Figure 25. AD7656/AD7657/AD7658 Transfer Characteristic The LSB size is dependent on the analog input range selected (see Table 9). REFERENCE SECTION The RFIN/REFOUT pin either allows access to the AD7656/ AD7657/AD7658’s 2.5 V reference or it allows an external reference to be connected, providing the reference source for each part’s conversions. The AD7656/AD7657/AD7658 can accommodate a 2.5 V to 3 V external reference range. When using an external reference, the internal reference needs to be disabled. After a reset, the AD7656/AD7657/AD7658 default to operating in external reference mode with the internal reference buffers enabled. The internal reference can be enabled in either hardware or software mode. To enable the internal reference in hardware mode, the H/S SEL pin = 0 and the REFEN/DIS pin = 1. To enable the internal reference in software mode, H/S SEL = 1 and a write to the control register is necessary to make DB9 of the register = 1. For the internal reference mode, the REFIN/REFOUT pin should be decoupled using 10 µF and 100 nF capacitors. The AD7656/AD7657/AD7658 contain three on-chip reference buffers. Each of the three ADC pairs has an associated reference buffer. These reference buffers require external decoupling capacitors on REFCAPA, REFCAPB, and REFCAPC pins, and 10 µF and 100 nF decoupling capacitors should be placed on these REFCAP pins. The internal reference buffers can be disabled in software mode by writing to Bit DB8 in the internal control register. If operating the devices in serial mode, the internal reference buffers can be disabled in hardware mode by setting the DB14/REFBUFEN/DIS pin high. If the internal reference and its buffers are disabled, an external buffered reference should be applied to the REFCAP pins. TYPICAL CONNECTION DIAGRAM Figure 26 shows the typical connection diagram for the AD7656/AD7657/AD7658. There are eight AVCC supply pins on the parts. The AVCC supply is the supply that is used for the AD7656/AD7657/AD7658 conversion process; therefore, it should be well decoupled. Each AVCC supply pin should be individually decoupled with a 10 µF tantalum capacitor and a 100 nF ceramic capacitor. The AD7656/AD7657/AD7658 can operate with the internal reference or an externally applied reference. In this configuration, the parts are configured to operate with the external reference. The REFIN/REFOUT pin is decoupled with a 10 µF and 100 nF capacitor pair. The three internal reference buffers are enabled. Each of the REFCAP pins are decoupled with the 10 µF and 100 nF capacitor pair. Six of the AVCC supply pins are used as the supply to the six ADC cores on the AD7656/AD7657/AD7658 and, as a result, are used for the conversion process. Each analog input pin is surrounded by an AVCC supply pin and an AGND pin. These AVCC and AGND pins are the supply and ground for the individual ADC cores. For example, Pin 33 is V1, Pin 34 is the AVCC supply for ADC Core 1, and Pin 32 is the AGND for ADC Core 1. An alternative reduced decoupling solution is to group these six AVCC supply pins into three pairs, Pin 34 and Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. For the AD7656, a 100 µF decoupling capacitor can be placed on each of the pin pairs. All of the other supply and reference pins should be decoupled with a 10 µF decoupling capacitor. When the AD7657 is configured in this reduced decoupling configuration, each of the three AVCC pin pairs should be decoupled with a 33 µF capacitor. When the AD7658 is configured in this same configuration, each of the three AVCC pin pairs should be decoupled with a 22 µF capacitor. If the same supply is being used for the AVCC supply and DVCC supply, a ferrite or small RC filter should be placed between the supply pins. The AGND pins are connected to the AGND plane of the system. The DGND pins are connected to the digital ground plane in the system. The AGND and DGND planes should be connected together at one place in the system. This connection should be made as close as possible to the AD7656/AD7657/AD7658 in the system. Table 9. LSB Size for Each Analog Input Range Range Input Range LSB Size FS Range ±10 V 0.305 mV 20 V/65536 AD7656 ±5 V 0.152 mV 10 V/65536 ±10 V 1.22 mV 20 V/16384 AD7657 ±5 V 0.610 mV 10 V/16384 Rev. D | Page 21 of 32 ±10 V 4.88 mV 20 V/4096 AD7658 ±5 V 2.44mV 10 V/4096 AD7656/AD7657/AD7658 Data Sheet DVCC A N A L OG SUPPLY VOLTAGE 5V1 + 10µF +9.5V TO +16.5V2 SUPPLY 10µF + 100nF AGND AVCC DVCC VDD 100nF DGND 100nF 10µF + 10µF 100nF + 10µF VDRIVE DGND D0 TO D15 AGND + DIGITAL SUPPLY VOLTAGE +3V OR +5V PARALLEL INTERFACE µP/µC/DSP CONVST A, B, C CS RD BUSY REFCAPA, B, C 100nF AGND AD7656/AD7657/AD7658 10µF + RESET REFIN/OUT 100nF SER/PAR H/S W/B RANGE AGND SIX ANALOG INPUTS –9.5V TO –16.5V2 SUPPLY VS S 10µF + STBY 100nF VDRIVE AGND 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN. 2SEE POWER SUPPLY CONFIGURATION SECTION. 05020-006 2.5V REF Figure 26. Typical Connection Diagram Parallel Interface (SER/PAR = 0) The VDRIVE supply is connected to the same supply as the processor. The voltage on VDRIVE controls the voltage value of the output logic signals. The VDD and VSS signals should be decoupled with a minimum 10 µF decoupling capacitor. These supplies are used for the high voltage analog input structures on the AD7656/AD7657/AD7658 analog inputs. DRIVING THE ANALOG INPUTS Together, the driver amplifier and the analog input circuit used for the AD7656 must settle for a full-scale step input to a 16-bit level (0.0015%), which is within the specified 550 ns acquisition time of the AD7656. The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7656. The driver also needs to have a THD performance suitable to that of the AD7656. The AD8021 meets all these requirements. The AD8021 needs an external compensation capacitor of 10 pF. If a dual version of the AD8021 is required, the AD8022 can be used. The AD8610 and the AD797 can also be used to drive the AD7656/AD7657/AD7658. INTERFACE SECTION The AD7656/AD7657/AD7658 provide two interface options, a parallel interface and a high speed serial interface. The required interface mode is selected via the SER/PAR pin. The parallel interface can operate in word (W/B = 0) or byte (W/B = 1) mode. The interface modes are discussed in the following sections. The AD7656/AD7657/AD7658 consist of six 16-/14-/12-bit ADCs, respectively. A simultaneous sample of all six ADCs can be performed by connecting all three CONVST pins together, CONVST A, CONVST B, and CONVST C. The AD7656/AD7657/ AD7658 need to see a CONVST pulse to initiate a conversion; this should consist of a falling CONVST edge followed by a rising CONVST edge. The rising edge of CONVSTx initiates simultaneous conversions on the selected ADCs. The AD7656/ AD7657/AD7658 contain an on-chip oscillator that is used to perform the conversions. The conversion time, tCONV, is 3 µs. The BUSY signal goes low to indicate the end of conversion. The falling edge of the BUSY signal is used to place the trackand-hold into track mode. The AD7656/AD7657/AD7658 also allow the six ADCs to be converted simultaneously in pairs by pulsing the three CONVST pins independently. CONVST A is used to initiate simultaneous conversions on V1 and V2, CONVST B is used to initiate simultaneous conversions on V3 and V4, and CONVST C is used to initiate simultaneous conversions on V5 and V6. The conversion results from the simultaneously sampled ADCs are stored in the output data registers. Data can be read from the AD7656/AD7657/AD7658 via the parallel data bus with standard CS and RD signals (W/B = 0). To read the data over the parallel bus, SER/PAR should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines DB0 to DB15 leave their high impedance state when both CS and RD are logic low. Rev. D | Page 22 of 32 Data Sheet AD7656/AD7657/AD7658 can affect the performance of the conversion. For the specified performance, it is recommended to perform the read after the conversion. For unused input channel pairs, the associated CONVSTx pin should be tied to VDRIVE. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results. A read operation can take place after the BUSY signal goes low. The number of required read operations depends on the number of ADCs that are simultaneously sampled (see Figure 27). If CONVST A and CONVST B are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V3, and V4. If CONVST A and CONVST C are simultaneously brought low, four read operations are required to obtain the conversion results from V1, V2, V5, and V6. The conversion results are output in ascending order. For the AD7657, DB15 and DB14 contain two leading zeros and DB[13:0] output the 14-bit conversion result. For the AD7658, DB[15:12] contain four leading zeros, and DB[11:0] output the 12-bit conversion result. If there is only an 8-bit bus available, the AD7656/AD7657/ AD7658 interface can be configured to operate in byte mode (W/B = 1). In this configuration, the DB7/HBEN/DCEN pin takes on its HBEN function. Each channel conversion result from the AD7656/AD7657/AD7658 can be accessed in two read operations, with 8 bits of data provided on DB15 to DB8 for each of the read operations (see Figure 28). The HBEN pin determines whether the read operation first accesses the high byte or the low byte of the 16-bit conversion result. To always access the low byte first on DB15 to DB8, the HBEN pin should be tied low. To always access the high byte first on DB15 to DB8, the HBEN pin should be tied high. In byte mode when all three CONVST pins are pulsed together to initiate simultaneous conversions on all six ADCs, 12 read operations are necessary to read back the six 16-/14-/12-bit conversion results. DB[6:0] should be left unconnected in byte mode. When using the three CONVST signals to independently initiate conversions on the three ADC pairs, care should be taken to ensure that a conversion is not initiated on a channel pair when the BUSY signal is high. It is also recommended not to initiate a conversion during a read sequence because doing so t10 CONVST A, CONVST B, CONVST C tCONVERT tACQ BUSY t4 CS t3 t5 t9 t2 DB0 TO DB15 t7 t6 V1 V2 V3 V4 t8 V5 tQUIET 05020-007 RD V6 Figure 27. Parallel Interface Timing Diagram (W/B = 0) CS t4 t3 t5 t6 DB15 TO DB8 t8 t7 LOW BYTE HIGH BYTE Figure 28. Parallel Interface—Read Cycle for Byte Mode of Operation (W/B = 1, HBEN = 0) Rev. D | Page 23 of 32 05020-008 RD t9 AD7656/AD7657/AD7658 Data Sheet Software Selection of ADCs Table 11. The H/S SEL pin determines the source of the combination of ADCs that are to be simultaneously sampled. When the H/S SEL pin is logic low, the combination of channels to be simultaneously sampled is determined by the CONVST A, CONVST B, and CONVST C pins. When the H/S SEL pin is logic high, the combination of channels selected for simultaneous sampling is determined by the contents of the Control Register DB15 to Control Register DB13. In this mode, a write to the control register is necessary. The control register is an 8-bit write-only register. Data is written to this register using the CS and WR pins and the DB[15:8] data pins (see Figure 29). The control register is shown in Table 10. To select an ADC pair to be simultaneously sampled, set the corresponding data line high during the write operation. Bit DB15 Mnemonic VC DB14 VB DB13 VA DB12 RNGC DB11 RNGB DB10 RNGA DB9 REFEN DB8 REFBUF The AD7656/AD7657/AD7658 control register allows individual ranges to be programmed on each ADC pair. DB12 to DB10 in the control register are used to program the range on each ADC pair. After a reset occurs on the AD7656/AD7657/AD7658, the control register contains all zeros. The CONVST A signal is used to initiate a simultaneous conversion on the combination of channels selected via the control register. The CONVST B and CONVST C signals can be tied low when operating in software mode (H/S SEL = 1). The number of read pulses required depends on the number of ADCs selected in the control register and on whether the devices are operating in word or byte mode. The conversion results are output in ascending order. During the write operation, Data Bus Bit DB15 to Bit DB8 are bidirectional and become inputs to the control register when RD is logic high and CS and WR are logic low. The logic state on DB15 through DB8 is latched into the control register when WR goes logic high. Table 10. Control Register Bit Function Descriptions (Default All 0s) DB14 VB DB13 VA DB12 RNGC DB11 RNGB DB10 RNGA DB9 REFEN DB8 REFBUF CS WR t12 t13 t11 t15 t14 DB15 TO DB8 DATA Figure 29. Parallel Interface—Write Cycle for Word Mode (W/B= 0) Rev. D | Page 24 of 32 05020-009 DB15 VC Comment This bit is used to select Analog Inputs V5 and V6 for the next conversion. When this bit = 1, V5 and V6 are simultaneously converted on the next CONVST A rising edge. This bit is used to select Analog Inputs V3 and V4 for the next conversion. When this bit = 1, V3 and V4 are simultaneously converted on the next CONVST A rising edge. This bit is used to select Analog Inputs V1 and V2 for the next conversion. When this bit = 1, V1 and V2 are simultaneously converted on the next CONVST A rising edge. This bit is used to select the analog input range for Analog Inputs V5 and V6. When this bit = 1, the ±2 × VREF mode is selected for the next conversion. When this bit = 0, the ±4 × VREF mode is selected for the next conversion. This bit is used to select the analog input range for Analog Inputs V3 and V4. When this bit = 1, the ±2 × VREF mode is selected for the next conversion. When this bit = 0, the ±4 × VREF mode is selected for the next conversion. This bit is used to select the analog input range for Analog Inputs V1 and V2. When this bit = 1, the ±2 × VREF mode is selected for the next conversion. When this bit = 0, the ±4 × VREF mode is selected for the next conversion. This bit is used to select the internal reference or an external reference. When this bit = 0, the external reference mode is selected. When this bit = 1, the internal reference is selected. This bit is used to select between using the internal reference buffers and choosing to bypass these reference buffers. When this bit = 0, the internal reference buffers are enabled and decoupling is required on the REFCAP pins. When this bit = 1, the internal reference buffers are disabled and a buffered reference should be applied to the REFCAP pins. Data Sheet AD7656/AD7657/AD7658 Changing the Analog Input Range (H/S SEL = 0) The AD7656/AD7657/AD7658 RANGE pin allows the user to select either ±2 × VREF or ±4 × VREF as the analog input range for the six analog inputs. When the H/S SEL pin is low, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion. When the RANGE pin is logic high at the falling edge of the BUSY signal, the range for the next conversion is ±2 × VREF. When the RANGE pin is logic low at the falling edge of the BUSY signal, the range for the next conversion is ±4 × VREF. After a RESET pulse, the range is updated on the first falling BUSY edge after the RESET pulse. Changing the Analog Input Range (H/S SEL = 1) When the H/S SEL pin is high, the range can be changed by writing to the control register. DB[12:10] in the control register are used to select the analog input ranges for the next conversion. Each analog input pair has an associated range bit, allowing independent ranges to be programmed on each ADC pair. When the RNGx bit = 1, the range for the next conversion is ±2 × VREF. When the RNGx bit = 0, the range for the next conversion is ±4 × VREF. Serial Interface (SER/PAR = 1) By pulsing one, two, or all three CONVST x signals, the AD7656/AD7657/AD7658 use their on-chip trimmed oscillator to simultaneously convert the selected channel pairs on the rising edge of CONVST x. After the rising edge of CONVST x, the BUSY signal goes high to indicate that the conversion has started. It returns low when the conversion is complete 3 µs later. The output register is loaded with the new conversion results, and data can be read from the AD7656/AD7657/AD7658. To read the data back from the parts over the serial interface, SER/PAR should be tied high. The CS and SCLK signals are used to transfer data from the AD7656/AD7657/AD7658. The parts have three DOUT pins, DOUT A, DOUT B, and DOUT C. Data can be read back from each part using one, two, or all three DOUT lines. Figure 30 shows six simultaneous conversions and the read sequence using three DOUT lines. Also in Figure 30, 32 SCLK transfers are used to access data from the AD7656/AD7657/ AD7658; however, two 16 SCLK individually framed transfers with the CS signal can also be used to access the data on the three DOUT lines. When operating the AD7656/AD7657/AD7658 in serial mode with conversion data clocking out on all three DOUT lines, DB0/SEL A, DB1/SEL B, and DB2/SEL C should be tied to VDRIVE. These pins are used to enable the DOUT A to DOUT C lines, respectively. If it is required to clock conversion data out on two data out lines, DOUT A and DOUT B should be used. To enable DOUT A and DOUT B, DB0/SEL A and DB1/SEL B should be tied to VDRIVE and DB2/SEL C should be tied low. When six simultaneous conversions are performed and only two DOUT lines are used, a 48 SCLK transfer can be used to access the data from the AD7656/AD7657/AD7658. The read sequence is shown in Figure 31 for a simultaneous conversion on all six ADCs using two DOUT lines. If a simultaneous conversion occurred on all six ADCs, and only two DOUT lines are used to read the results from the AD7656/AD7657/AD7658. DOUT A clocks out the result from V1, V2, and V5, while DOUT B clocks out the results from V3, V4, and V6. Data can also be clocked out using just one DOUT line, in which case, DOUT A should be used to access the conversion data. To configure the AD7656/AD7657/AD7658 to operate in this mode, DB0/SEL A should be tied to VDRIVE and DB1/SEL B and DB2/SEL C should be tied low. The disadvantage of using just one DOUT line is that the throughput rate is reduced. Data can be accessed from the AD7656/AD7657/AD7658 using one 96 SCLK transfer, three 32 SCLK individually framed transfers, or six 16 SCLK individually framed transfers. In serial mode, the RD signal should be tied low. The unused DOUT line(s) should be left unconnected in serial mode. Serial Read Operation Figure 32 shows the timing diagram for reading data from the AD7656/AD7657/AD7658 in serial mode. The SCLK input signal provides the clock source for the serial interface. The CS signal goes low to access data from the AD7656/AD7657/AD7658. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 16-bit conversion result. The ADCs output 16 bits for each conversion result; the data stream of the AD7656 consists of 16 bits of conversion data provided MSB first. The data stream for the AD7657 consists of two leading zeros followed by 14 bits of conversion data MSB first. The data stream for the AD7658 consists of four leading zeros and 12 bits of conversion data provided MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 15 data bits are clocked out on the rising edge of the SCLK signal. Data is valid on the SCLK falling edge. To access each conversion result, 16 clock pulses must be provided to the AD7656/AD7657/ AD7658. Figure 32 shows how a 16 SCLK read is used to access the conversion results. Rev. D | Page 25 of 32 AD7656/AD7657/AD7658 CONVST A, CONVST B, CONVST C Data Sheet tCONVERT tACQ BUSY CS 32 16 SCLK V1 V2 DOUT B V3 V4 DOUT C V5 V6 05020-010 tQUIET DOUT A Figure 30. Serial Interface with Three DOUT Lines CS 48 DOUT A V1 V2 V5 DOUT B V3 V4 V6 05020-011 SCLK Figure 31. Serial Interface with Two DOUT Lines t1 t2 BUSY ACQUISITION t10 tACQ tCONVERT CONVERSION ACQUISITION tQUIET CS SCLK t19 t16 t18 t17 t20 t21 DOUT A, DOUT B, DOUT C DB15 DB14 DB13 Figure 32. Serial Read Operation Rev. D | Page 26 of 32 DB1 DB0 05020-012 CONVST A, CONVST B, CONVST C Data Sheet AD7656/AD7657/AD7658 Daisy-Chain Mode (DCEN = 1, SER/PAR = 1) When reading conversion data back from the AD7656/AD7657/ AD7658 using their three/two/one DOUT pins, it is possible to configure the parts to operate in daisy-chain mode, using the DCEN pin. This daisy-chain feature allows multiple AD7656/ AD7657/AD7658 devices to be cascaded together and is useful for reducing component count and wiring connections. An example connection of two devices is shown in Figure 33. This configuration shows two DOUT lines being used. Simultaneous sampling of the 12 analog inputs is possible by using a common CONVSTx signal. The DB5, DB4, and DB3 data pins are used as data input pins DCIN [A:C] for the daisy-chain mode. The rising edge of CONVST is used to initiate a conversion on the AD7656/AD7657/AD7658. After the BUSY signal has gone low to indicate that the conversion is complete, the user can begin to read the data from the two devices. Figure 34 shows the serial timing diagram when operating two AD7656/AD7657/ D7658 devices in daisy-chain mode. The CS falling edge is used to frame the serial transfer from the AD7656/AD7657/AD7658 devices, to take the bus out of threestate, and to clock out the MSB of the first conversion result. In the example shown in Figure 34, all 12 ADC channels are simultaneously sampled. Two DOUT lines are used to read the conversion results in this example. CS frames a 96 SCLK transfer. During the first 48 SCLKs, the conversion data is transferred from Device 2 to Device 1. DOUT A on Device 2 transfers conversion data from V1, V2, and V5 into DCIN A in Device 1. DOUT B on Device 2 transfers conversion results from V3, V4, and V6 to DCIN B in Device 1. During the first 48 SCLKs, Device 1 transfers data into the digital host. DOUT A on Device 1 transfers conversion data from V1, V2, and V5. DOUT B on Device 1 transfers conversion data from V3, V4, and V6. During the last 48 SCLKs, Device 2 clocks out zeros and Device 1 shifts the data clocked in from Device 2 during the first 48 SCLKs into the digital host. This example can also be implemented using six 16 SCLK individually framed transfers if DCEN remains high during the transfers. Figure 35 shows the timing if two AD7656/AD7657/AD7658 devices are configured in daisy-chain mode and are operating with three DOUT lines. Assuming a simultaneous sampling of all 12 inputs occurs, the CS frames a 64 SCLK transfer during the read operation. During the first 32 SCLKs of this transfer, the conversion results from Device 1 are clocked into the digital host and the conversion results from Device 2 are clocked into Device 1. During the last 32 SCLKs of the transfer, the conversion results from Device 2 are clocked out of Device 1 and into the digital host. Device 2 clocks out zeros. Standby/Partial Power-Down Modes of Operation Each ADC pair can be individually placed into partial powerdown mode by bringing the CONVST x signal low before the falling edge of BUSY. To power the ADC pair back up, the CONVST x signal should be brought high to tell the ADC pair to power up and place the track-and-hold into track mode. After the power-up time from partial power-down has elapsed, the CONVST x signal should receive a rising edge to initiate a valid conversion. In partial power-down mode, the reference buffers remain powered up. While an ADC pair is in partial powerdown mode, conversions can still occur on the other ADCs. The AD7656/AD7657/AD7658 have a standby mode whereby the devices can be placed into a low power consumption mode (100 µW maximum). The AD7656/AD7657/AD7658 are placed into standby mode by bringing the logic input STBY low and can be powered up again for normal operation by bringing STBY logic high. The output data buffers are still operational when the AD7656/AD7657/AD7658 are in standby mode, meaning the user can continue to access the conversion results of the parts. This standby feature can be used to reduce the average power consumed by the AD7656/AD7657/AD7658 when operating at lower throughput rates. The parts can be placed into standby at the end of each conversion when BUSY goes low and taken out of standby again prior to the next conversion. The time for the AD7656/AD7657/AD7658 to come out of standby is called the wake-up time. The wakeup time limits the maximum throughput rate at which the AD7656/AD7657/AD7658 can operate when powering down between conversions. See the Specifications section. Rev. D | Page 27 of 32 AD7656/AD7657/AD7658 Data Sheet CONVERT DIGITAL HOST CONVST CONVST DOUT A DCIN A DOUT A DATA IN1 DOUT B DCIN B DOUT B DATA IN2 AD7656/AD7657/AD7658 SCLK AD7656/AD7657/AD7658 SCLK CS CS CS 05020-013 SCLK DCEN = 0 DEVICE 2 DCEN = 1 DEVICE 1 Figure 33. Daisy-Chain Configuration CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 65 94 95 96 SCLK MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 MSB V1 LSB V1 MSB V2 LSB V5 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 MSB V3 LSB V3 MSB V4 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V5 LSB V5 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V6 LSB V6 05020-014 DEVICE 1, DOUT A Figure 34. Daisy-Chain Serial Interface Timing with Two DOUT Lines CONVST A, CONVST B, CONVST C BUSY CS 1 2 3 15 16 17 31 32 33 47 48 49 63 64 DEVICE 1, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 1, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 1, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 MSB V5 LSB V5 MSB V6 LSB V6 DEVICE 2, DOUT A MSB V1 LSB V1 MSB V2 LSB V2 DEVICE 2, DOUT B MSB V3 LSB V3 MSB V4 LSB V4 DEVICE 2, DOUT C MSB V5 LSB V5 MSB V6 LSB V6 Figure 35. Daisy-Chain Serial Interface Timing with Three DOUT Lines Rev. D | Page 28 of 32 05020-015 SCLK Data Sheet AD7656/AD7657/AD7658 APPLICATION HINTS The printed circuit board that houses the AD7656/AD7657/ AD7658 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. At least one ground plane should be used. It could be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably underneath the AD7656/ AD7657/AD7658, or at least as close as possible to each part. If the AD7656/AD7657/AD7658 are in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point, a star ground point, which should be established as close as possible to the AD7656/AD7657/AD7658. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Individual vias or multiple vias to the ground plane should be used for each ground pin. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7656/AD7657/AD7658 to avoid noise coupling. Fast-switching signals like CONVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other to reduce the effect of feedthrough through the board. The power supply lines to the AVCC, DVCC, VDRIVE, VDD, and VSS pins on the AD7656/AD7657/AD7658 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good connections should be made between the AD7656/AD7657/AD7658 supply pins and the power tracks on the board; this should involve the use of a single via or multiple vias for each supply pin. parasitic inductances. Recommended decoupling capacitors are 100 nF, low ESR, ceramic capacitors (Farnell 335-1816) and 10 μF, low ESR, tantalum capacitors (Farnell 197-130) for the AVCC decoupling. A large tantalum decoupling capacitor should be placed where the AVCC supply enters the board. An alternative reduced decoupling arrangement is outlined in the Typical Connection Diagram section. This decoupling arrangement groups the AVCC supply pins into pairs and allows the decoupling capacitors to be shared between the supply pairs. Group the six AVCC core supply pins into three pairs, Pin 34 and Pin 35, Pin 40 and Pin 41, and Pin 46 and Pin 47. Connect the supply pins in each pair together; their location on the AD7656/ AD7657/AD7658 pin configuration easily facilitates this. For the AD7656, decouple each pair with a 100 µF capacitor; for the AD7657, decouple each pair with a 33 µF capacitor; for the AD7658, decouple each pair with a 22 µF capacitor. For this minimum decoupling configuration, all other supply and reference pins should be decoupled with a 10 µF decoupling capacitor. POWER SUPPLY CONFIGURATION As outlined in the Absolute Maximum Ratings section, the analog inputs should not be applied to the AD7656/AD7657/ AD7658 until after the AD7656/AD7657/AD7658 power supplies have been applied to the device. However, if a condition exists where the system analog signal conditioning circuitry supplies are different to the VDD and VSS supplies of the AD7656/AD7657/AD7658, or if the analog inputs may be applied prior to the AD7656/AD7657/AD7658 supplies being established, then an analog input series resister and Schottky diodes in series with the VDD and VSS supplies are recommended, see Figure 36. This configuration should also be used if AVCC is applied to the AD7656/AD7657/AD7658 prior to VDD and VSS. Good decoupling is also important to lower the supply impedance presented to the AD7656/AD7657/AD7658 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on all of the power supply pins, VDD, VSS, AVCC, DVCC, and VDRIVE. These decoupling capacitors should be placed close to, ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be placed on each of the supply pins. Avoid sharing these capacitors between pins. Use big vias to connect the capacitors to the power and ground planes. Use wide, short traces between the via and the capacitor pad, or place the via adjacent to the capacitor pad to minimize Rev. D | Page 29 of 32 VDD 240Ω ANALOG INPUTS V1 V2 V3 V4 V5 V6 VDD AD7656/ AD7657/ AD7658 VSS VSS Figure 36. Power Supply Configuration 05020-036 LAYOUT AD7656/AD7657/AD7658 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 37. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 AD7656BSTZ AD7656BSTZ-REEL AD7656YSTZ AD7656YSTZ-REEL AD7657BSTZ AD7657BSTZ-REEL AD7657YSTZ AD7657YSTZ-REEL AD7658BSTZ AD7658BSTZ-REEL AD7658YSTZ AD7658YSTZ-REEL EVAL-AD7656CBZ EVAL-AD7657CBZ EVAL-AD7658CBZ EVAL-CONTROL BRD2Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +125°C −40°C to +125°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Evaluation Board Evaluation Board Controller Board Package Option ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 ST-64-2 Z = RoHS Compliant Part. The EVAL-CONTROL BRD2Z is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete evaluation kit, the particular ADC evaluation board, for example, EVAL-AD7656/AD7657/AD7658CBZ, the EVAL-CONTROL BRD2Z and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information. Rev. D | Page 30 of 32 Data Sheet AD7656/AD7657/AD7658 NOTES Rev. D | Page 31 of 32 AD7656/AD7657/AD7658 Data Sheet NOTES ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05020-0-3/12(D) Rev. D | Page 32 of 32