AD AD8332ARU-REEL Ultralow noise vgas with preamplifier and programmable rin Datasheet

Ultralow Noise VGAs with
Preamplifier and Programmable RIN
AD8331/AD8332/AD8334
FEATURES
Ultrasound and sonar time-gain controls
High performance AGC systems
I/Q signal processing
High speed, dual ADC drivers
VIN
VCM
LMD
3.5dB/15.5dB
VMID
LNA
INH
HILO
+
19dB
–
–
LNA VCM
BIAS
VGA BIAS AND
INTERPOLATOR
48dB
ATTENUATOR
+
VOH
21dB
PA
VOL
GAIN
CONTROL
INTERFACE
CLAMP
RCLMP
ENB
03199-001
AD8331/AD8332/AD8334
GAIN
Figure 1. Signal Path Block Diagram
60
VGAIN = 1V
50
HIGH GAIN
MODE
VGAIN = 0.8V
40
VGAIN = 0.6V
30
VGAIN = 0.4V
20
VGAIN = 0.2V
VGAIN = 0V
10
0
–10
100k
03199-002
APPLICATIONS
LON LOP VIP
GAIN (dB)
Ultralow noise preamplifier
Voltage noise = 0.74 nV/√Hz
Current noise = 2.5 pA/√Hz
3 dB bandwidth
AD8331: 120 MHz
AD8332, AD8334: 100 MHz
Low power
AD8331: 125 mW/channel
AD8332, AD8334: 145 mW/channel
Wide gain range with programmable postamp
−4.5 dB to +43.5 dB
+7.5 dB to +55.5 dB
Low output-referred noise: 48 nV/√Hz typical
Active input impedance matching
Optimized for 10-bit/12-bit ADCs
Selectable output clamping level
Single 5 V supply operation
AD8332 and AD8334 available in lead frame chip scale package
FUNCTIONAL BLOCK DIAGRAM
1M
10M
100M
1G
FREQUENCY (Hz)
GENERAL DESCRIPTION
The AD8331/AD8332/AD8334 are single-, dual-, and quadchannel ultralow noise, linear-in-dB, variable gain amplifiers
(VGAs). Optimized for ultrasound systems, they are usable as a
low noise variable gain element at frequencies up to 120 MHz.
Included in each channel are an ultralow noise preamplifier
(LNA), an X-AMP® VGA with 48 dB of gain range, and a
selectable gain postamplifier with adjustable output limiting.
The LNA gain is 19 dB with a single-ended input and
differential outputs. Using a single resistor, the LNA input
impedance can be adjusted to match a signal source without
compromising noise performance.
The 48 dB gain range of the VGA makes these devices suitable
for a variety of applications. Excellent bandwidth uniformity is
maintained across the entire range. The gain control interface
provides precise linear-in-dB scaling of 50 dB/V for control
voltages between 40 mV and 1 V. Factory trim ensures excellent
part-to-part and channel-to-channel gain matching.
Figure 2. Frequency Response vs. Gain
Differential signal paths result in superb second- and thirdorder distortion performance and low crosstalk.
The VGA’s low output-referred noise is advantageous in driving
high speed differential ADCs. The gain of the postamplifier can
be pin selected to 3.5 dB or 15.5 dB to optimize gain range and
output noise for 12-bit or 10-bit converter applications. The
output can be limited to a user-selected clamping level,
preventing input overload to a subsequent ADC. An external
resistor adjusts the clamping level.
The operating temperature range is −40°C to +85°C. The
AD8331 is available in a 20-lead QSOP package, the AD8332 is
available in 28-lead TSSOP and 32-lead LFCSP packages, and
the AD8334 is available in a 64-lead LFCSP package.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8331/AD8332/AD8334
TABLE OF CONTENTS
Features .............................................................................................. 1
Variable Gain Amplifier ............................................................ 27
Applications....................................................................................... 1
Postamplifier ............................................................................... 28
General Description ......................................................................... 1
Applications..................................................................................... 30
Functional Block Diagram .............................................................. 1
LNA—External Components.................................................... 30
Revision History ............................................................................... 3
Driving ADCs ............................................................................. 32
Specifications..................................................................................... 4
Overload ...................................................................................... 32
Absolute Maximum Ratings............................................................ 7
Optional Input Overload Protection. ...................................... 33
ESD Caution.................................................................................. 7
Layout, Grounding, and Bypassing.......................................... 33
Pin Configurations and Function Descriptions ........................... 8
Multiple Input Matching ........................................................... 33
Typical Performance Characteristics ........................................... 12
Disabling the LNA...................................................................... 33
Test Circuits..................................................................................... 20
Ultrasound TGC Application ................................................... 34
Measurement Considerations................................................... 20
High Density Quad Layout ....................................................... 34
Theory of Operation ...................................................................... 24
Outline Dimensions ....................................................................... 39
Overview...................................................................................... 24
Ordering Guide .......................................................................... 40
Low Noise Amplifier (LNA) ..................................................... 25
Rev. E | Page 2 of 40
AD8331/AD8332/AD8334
REVISION HISTORY
4/06—Rev. D to Rev. E
Added AD8334 ................................................................... Universal
Changes to Figure 1 and Figure 2....................................................1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................7
Changes to Figure 7 through Figure 9 and Figure 12.................12
Changes to Figure 13, Figure 14, Figure 16, and Figure 18 .......13
Changes to Figure 23 and Figure 24 .............................................14
Changes to Figure 25 through Figure 27......................................15
Changes to Figure 31 and Figure 33 through Figure 36.............16
Changes to Figure 37 through Figure 42......................................17
Changes to Figure 43, Figure 44, and Figure 48..........................18
Changes to Figure 49, Figure 50, and Figure 54..........................19
Inserted Figure 56 and Figure 57 ..................................................20
Inserted Figure 58, Figure 59, and Figure 61 ...............................21
Changes to Figure 60 ......................................................................21
Inserted Figure 63 and Figure 65 ..................................................22
Changes to Figure 64 ......................................................................22
Moved Measurement Considerations Section ............................20
Inserted Figure 67 and Figure 68 ..................................................23
Inserted Figure 70 and Figure 71 ..................................................24
Change to Figure 72 ........................................................................24
Changes to Figure 73 and Low Noise Amplifier Section ...........25
Changes to Postamplifier Section .................................................28
Changes to Figure 80 ......................................................................29
Changes to LNA—External Components Section......................30
Changes to Logic Inputs—ENB, MODE, and HILO Section....31
Changes to Output Decoupling and Overload Sections ............32
Changes to Layout, Grounding, and Bypassing Section ............33
Changes to Ultrasound TGC Application Section......................34
Added High Density Quad Layout Section .................................34
Inserted Figure 94............................................................................38
Updated Outline Dimensions........................................................39
Changes to Ordering Guide...........................................................40
3/06—Rev. C to Rev. D
Updated Format ................................................................. Universal
Changes to Features and General Description..............................1
Changes to Table 1 ............................................................................3
Changes to Table 2 ............................................................................6
Changes to Ordering Guide...........................................................34
11/03—Rev. B to Rev. C
Addition of New Part......................................................... Universal
Changes to Figures............................................................. Universal
Updated Outline Dimensions........................................................32
5/03—Rev. A to Rev. B
Edits to Ordering Guide.................................................................32
Edits to Ultrasound TGC Application Section ...........................25
Added Figure 71, Figure 72, and Figure 73..................................26
Updated Outline Dimensions........................................................31
2/03—Rev. 0 to Rev. A
Edits to Ordering Guide.................................................................32
Rev. E | Page 3 of 40
AD8331/AD8332/AD8334
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating,
−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
Table 1.
Parameter
LNA CHARACTERISTICS
Gain
Input Voltage Range
Input Resistance
Input Capacitance
Output Impedance
−3 dB Small Signal Bandwidth
Slew Rate
Input Voltage Noise
Input Current Noise
Noise Figure
Active Termination Match
Unterminated
Harmonic Distortion @ LOP1 or LOP2
HD2
HD3
Output Short-Circuit Current
LNA + VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth
AD8331
AD8332, AD8334
−3 dB Large Signal Bandwidth
AD8331
AD8332, AD8334
Slew Rate
AD8331
AD8332, AD8334
Input Voltage Noise
Noise Figure
Active Termination Match
Unterminated
Output-Referred Noise
AD8331
AD8332, AD8334
Output Impedance, Postamplifier
Conditions
Single-ended input to differential output
Input to output (single ended)
AC-coupled
RFB = 280 Ω
RFB = 412 Ω
RFB = 562 Ω
RFB = 1.13 kΩ
RFB = ∞
Min
Typ
Max
Unit
19
13
±275
50
75
100
200
6
13
5
130
650
0.74
2.5
dB
dB
mV
Ω
Ω
Ω
Ω
kΩ
pF
Ω
MHz
V/μs
nV/√Hz
pA/√Hz
3.7
2.5
dB
dB
−56
−70
165
dBc
dBc
mA
120
100
MHz
MHz
110
90
MHz
MHz
LO gain
HI gain
LO gain
HI gain
RS = 0 Ω, HI or LO gain, RFB = ∞, f = 5 MHz
VGAIN = 1.0 V
RS = RIN = 50 Ω, f = 10 MHz, measured
RS = RIN = 200 Ω, f = 5 MHz, simulated
RS = 50 Ω, RFB = ∞, f = 10 MHz, measured
RS = 200 Ω, RFB = ∞, f = 5 MHz, simulated
300
1200
275
1100
0.82
V/μs
V/μs
V/μs
V/μs
nV/√Hz
4.15
2.0
2.5
1.0
dB
dB
dB
dB
VGAIN = 0.5 V, LO gain
VGAIN = 0.5 V, HI gain
VGAIN = 0.5 V, LO gain
VGAIN = 0.5 V, HI gain
DC to 1 MHz
48
178
40
150
1
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Ω
Single-ended, either output
VOUT = 0.2 V p-p
RS = 0 Ω, HI or LO gain, RFB = ∞, f = 5 MHz
RFB = ∞, HI or LO gain, f = 5 MHz
f = 10 MHz, LOP output
RS = RIN = 50 Ω
RS = 50 Ω, RFB = ∞
VOUT = 0.5 V p-p, single-ended, f = 10 MHz
Pin LON, Pin LOP
VOUT = 0.2 V p-p
VOUT = 2 V p-p
Rev. E | Page 4 of 40
AD8331/AD8332/AD8334
Parameter
Output Signal Range, Postamplifier
Differential
Output Offset Voltage
AD8331
AD8332, AD8334
Output Short-Circuit Current
Harmonic Distortion
AD8331
HD2
HD3
HD2
HD3
AD8332, AD8334
HD2
HD3
HD2
HD3
Input 1 dB Compression Point
Two-Tone Intermodulation Distortion (IMD3)
AD8331
AD8332, AD8334
Output Third-Order Intercept
AD8331
AD8332, AD8334
Channel-to-Channel Crosstalk (AD8332, AD8334)
Overload Recovery
Group Delay Variation
ACCURACY
Absolute Gain Error 2
Gain Law Conformance 3
Channel-to-Channel Gain Matching
GAIN CONTROL INTERFACE (Pin GAIN)
Gain Scaling Factor
Gain Range
Input Voltage (VGAIN) Range
Input Impedance
Response Time
COMMON-MODE INTERFACE (PIN VCMn)
Input Resistance 4
Output CM Offset Voltage
Voltage Range
Conditions
RL ≥ 500 Ω, unclamped, either pin
VGAIN = 0.5 V
Differential
Common mode
Differential
Common mode
Min
Typ
VCM ± 1.125
4.5
Max
Unit
V
V p-p
−50
−125
−20
−125
±5
−25
±5
–25
45
+50
+100
+20
+100
mV
mV
mV
mV
mA
VGAIN = 0.5 V, VOUT = 1 V p-p, HI gain
f = 1 MHz
−88
−85
−68
−65
dBc
dBc
dBc
dBc
VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz to 10 MHz
−82
−85
−62
−66
1
dBc
dBc
dBc
dBc
dBm 1
VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz
−80
−72
−78
−74
dBc
dBc
dBc
dBc
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz
VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz
VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz
5 MHz < f < 50 MHz, full gain range
38
33
35
32
−98
5
±2
dBm
dBm
dBm
dBm
dB
ns
ns
f = 10 MHz
f = 1 MHz
f = 10 MHz
0.05 V < VGAIN < 0.10 V
0.10 V < VGAIN < 0.95 V
0.95 V < VGAIN < 1.0 V
0.1 V < VGAIN < 0.95 V
0.1 V < VGAIN < 0.95 V
−1
−1
−2
+0.5
±0.3
−1
±0.2
±0.1
+2
+1
+1
dB
dB
dB
dB
dB
0.10 V < VGAIN < 0.95 V
LO gain
HI gain
48.5
50
−4.5 to +43.5
7.5 to 55.5
0 to 1.0
10
500
51.5
dB/V
dB
dB
V
MΩ
ns
48 dB gain change to 90% full scale
Current limited to ±1 mA
VCM = 2.5 V
VOUT = 2.0 V p-p
Rev. E | Page 5 of 40
−125
30
−25
1.5 to 3.5
+100
Ω
mV
V
AD8331/AD8332/AD8334
Parameter
ENABLE INTERFACE
(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power
Logic Level to Disable Power
Input Resistance
Power-Up Response Time
HILO GAIN RANGE INTERFACE (PIN HILO)
Logic Level to Select HI Gain Range
Logic Level to Select LO Gain Range
Input Resistance
OUTPUT CLAMP INTERFACE
(PIN RCLMP; HI OR LO GAIN)
Accuracy
HILO = LO
HILO = HI
MODE INTERFACE (PIN MODE)
Logic Level for Positive Gain Slope
Logic Level for Negative Gain Slope
Input Resistance
POWER SUPPLY (PIN VPS1, PIN VPS2,
PIN VPSV, PIN VPSL, PIN VPOS)
Supply Voltage
Quiescent Current per Channel
AD8331
AD8332, AD8334
Power Dissipation per channel
AD8331
AD8332, AD8334
Power-Down Current
AD8332 (VGA and LNA Disabled)
AD8331 (VGA and LNA Disabled)
LNA Current
AD8331 (ENBL)
AD8332, AD8334 (ENBL)
VGA Current
AD8331 (ENBV)
AD8332, AD8334 (ENBV)
PSRR
Conditions
Min
Typ
Max
Unit
5
1.0
V
V
kΩ
kΩ
kΩ
μs
ms
5
1.0
50
V
V
kΩ
±50
±75
mV
mV
2.25
0
Pin ENB
Pin ENBL
Pin ENBV
VINH = 30 mV p-p
VINH = 150 mV p-p
25
40
70
300
4
2.25
0
RCLMP = 2.74 kΩ, VOUT = 1 V p-p (clamped)
RCLMP = 2.21 kΩ, VOUT = 1 V p-p (clamped)
0
2.25
1.0
5
V
V
kΩ
5.5
V
200
4.5
5.0
20
20
25
29
mA
mA
125
145
mW
mW
No signal
Each channel
Each channel
VGAIN = 0 V, f = 100 kHz
1
All dBm values are referred to 50 Ω.
The absolute gain refers to the theoretical gain expression in Equation 1.
3
Best-fit to linear-in-dB curve.
4
The current is limited to ±1 mA typical.
2
Rev. E | Page 6 of 40
50
50
300
240
600
400
μA
μA
7.5
7.5
11
12
15
15
mA
mA
7.5
7.5
14
17
−68
20
20
mA
mA
dB
AD8331/AD8332/AD8334
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Voltage
Supply Voltage (VPSn, VPSV, VPSL, VPOS)
Input Voltage (INHn)
ENB, ENBL, ENBV, HILO Voltage
GAIN Voltage
Power Dissipation
AR Package 1
CP-20 Package (AD8331)
CP-32 Package (AD8332)
RQ Package1
CP-64 Package (AD8334)
Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
θJA
AR Package1
CP-20 Package 2
CP-32 Package2
RQ Package1
CP-64 Package 3
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
VS + 200 mV
VS + 200 mV
2.5 V
0.96 W
1.63 W
1.97 W
0.78 W
0.91 W
−40°C to +85°C
−65°C to +150°C
300°C
68°C/W
40°C/W
33°C/W
83°C/W
24.2°C/W
1
Four-layer JEDEC board (2S2P).
Exposed pad soldered to board, nine thermal vias in pad—JEDEC, 4-layer
board J-STD-51-9.
3
Exposed pad soldered to board, 25 thermal vias in pad—JEDEC, 4-layer
board J-STD-51-9.
2
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 7 of 40
AD8331/AD8332/AD8334
20
COMM
19
ENBL
3
18
ENBV
LON
4
17
COMM
LOP
5
16
VOL
COML
6
15
VOH
VIP
7
14
VPOS
VIN
8
13
HILO
MODE
9
12
RCLMP
GAIN 10
11
VCM
LMD
1
INH
2
VPSL
PIN 1
INDICATOR
AD8331
TOP VIEW
(Not to Scale)
03199-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 20-Lead QSOP Pin Configuration (AD8331)
Table 3. 20-Lead QSOP Pin Function Description (AD8331)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
LMD
INH
VPSL
LON
LOP
COML
VIP
VIN
MODE
GAIN
VCM
RCLMP
HILO
VPOS
VOH
VOL
COMM
ENBV
ENBL
COMM
Description
LNA Signal Ground
LNA Input
LNA 5 V Supply
LNA Inverting Output
LNA Noninverting Output
LNA Ground
VGA Noninverting Input
VGA Inverting Input
Gain Slope Logic Input
Gain Control Voltage
Common Mode Voltage
Output Clamping Level
Gain Range Select (HI or LO)
VGA 5 V Supply
Noninverting VGA Output
Inverting VGA Output
VGA Ground
VGA Enable
LNA Enable
VGA Ground
Rev. E | Page 8 of 40
25 LON1
29
28
27
26
25
19 HILO
6
18 ENB
VPS2
7
LON2
8
21 VIN1
VCM2
9
20 VCM1
17 VOH1
VOL2 13
16 VOL1
COMM 14
15 VPSV
03199-004
VOH2 12
VPSV
TOP VIEW
(Not to Scale)
20
NC
19
VOL2
18
VOH2
17
COMM
9
10
11
NC = NO CONNECT
Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)
AD8332
12
13
14
15
16
03199-005
5
INH2
8
VOL1
21
GAIN
LMD2
VIN2
22 VIP1
RCLMP
4
7
VOH1
22
MODE
LMD1
VIP2
23
VIN2
3
VCM2
2
INH1
COMM
VIP2
VPS1
23 COM1
24
LOP2
24 LOP1
6
GAIN 10
30
PIN 1
INDICATOR
COM2
1
5
RCLMP 11
32
LON1
LOP2
TOP VIEW
(Not to Scale)
31
27 INH1
COM2
AD8332
ENBV
4
ENBL
26 VPS1
LON2
HILO
3
VCM1
VPS2
VIN1
2
VIP1
1
INH2
COM1
28 LMD1
LMD2
PIN 1
INDICATOR
LOP1
AD8331/AD8332/AD8334
Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)
Table 4. 28-Lead TSSOP Pin Function Description (AD8332)
Table 5. 32-Lead LFCSP Pin Function Description (AD8332)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
LMD2
INH2
VPS2
LON2
LOP2
COM2
VIP2
VIN2
VCM2
GAIN
RCLMP
VOH2
VOL2
COMM
VPSV
VOL1
VOH1
ENB
HILO
VCM1
VIN1
VIP1
COM1
LOP1
LON1
VPS1
INH1
LMD1
Description
CH2 LNA Signal Ground
CH2 LNA Input
CH2 Supply LNA 5 V
CH2 LNA Inverting Output
CH2 LNA Noninverting Output
CH2 LNA Ground
CH2 VGA Noninverting Input
CH2 VGA Inverting Input
CH2 Common-Mode Voltage
Gain Control Voltage
Output Clamping Resistor
CH2 Noninverting VGA Output
CH2 Inverting VGA Output
VGA Ground (Both Channels)
VGA Supply 5 V (Both Channels)
CH1 Inverting VGA Output
CH1 Noninverting VGA Output
Enable—VGA/LNA
VGA Gain Range Select (HI or LO)
CH1 Common-Mode Voltage
CH1 VGA Inverting Input
CH1 VGA Noninverting Input
CH1 LNA Ground
CH1 LNA Noninverting Output
CH1 LNA Inverting Output
CH1 LNA Supply 5 V
CH1 LNA Input
CH1 LNA Signal Ground
Rev. E | Page 9 of 40
Mnemonic
LON1
VPS1
INH1
LMD1
LMD2
INH2
VPS2
LON2
LOP2
COM2
VIP2
VIN2
VCM2
MODE
GAIN
RCLMP
COMM
VOH2
VOL2
NC
VPSV
VOL1
VOH1
COMM
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
Description
CH1 LNA Inverting Output
CH1 LNA Supply 5 V
CH1 LNA Input
CH1 LNA Signal Ground
CH2 LNA Signal Ground
CH2 LNA Input
CH2 LNA Supply 5 V
CH2 LNA Inverting Output
CH2 LNA Noninverting Output
CH2 LNA Ground
CH2 VGA Noninverting Input
CH2 VGA Inverting Input
CH2 Common-Mode Voltage
Gain Slope Logic Input
Gain Control Voltage
Output Clamping Level Input
VGA Ground
CH2 Noninverting VGA Output
CH2 Inverting VGA Output
No Connect
VGA Supply 5 V
CH1 Inverting VGA Output
CH1 Noninverting VGA Output
VGA Ground
VGA Enable
LNA Enable
VGA Gain Range Select (HI or LO)
CH1 Common-Mode Voltage
CH1 VGA Inverting Input
CH1 VGA Noninverting Input
CH1 LNA Ground
CH1 LNA Noninverting Output
VCM2
VCM1
EN34
EN12
CLMP12
GAIN12
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
COM2
AD8331/AD8332/AD8334
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INH2
1
LMD2
2
COM2X
48
COM12
47
VOH1
3
46
VOL1
LON2
4
45
VPS12
LOP2
5
44
VOL2
VIP2
6
43
VOH2
VIN2
7
42
COM12
VPS2
8
41
MODE
VPS3
9
40
NC
VIN3
10
39
COM34
VIP3
11
38
VOH3
LOP3
12
37
VOL3
LON3
13
36
VPS34
COM3X
14
35
VOL4
LMD3
15
34
VOH4
INH3
16
33
COM34
PIN 1
INDICATOR
AD8334
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)
Table 6. 64-Lead LFCSP Pin Function Description (AD8334)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Mnemonic
INH2
LMD2
COM2X
LON2
LOP2
VIP2
VIN2
VPS2
VPS3
VIN3
VIP3
LOP3
LON3
COM3X
LMD3
INH3
COM3
COM4
INH4
LMD4
COM4X
LON4
LOP4
VIP4
VIN4
VPS4
GAIN34
CLMP34
Description
CH2 LNA Input
CH2 LNA VMID Bypass (AC-Coupled to GND)
CH2 LNA Ground Shield
CH2 LNA Feedback Output (for RFBK)
CH2 LNA Output
CH2 VGA Positive Input
CH2VGA Negative Input
CH2 LNA Supply 5 V
CH3 LNA Supply 5 V
CH3VGA Negative Input
CH3 VGA Positive Input
CH3 LNA Positive Output
CH3 LNA Feedback Output (for RFBK)
CH3 LNA Ground Shield
CH3 LNA VMID Bypass (AC-Coupled to GND)
CH3 LNA Input
CH3 LNA Ground
CH4 LNA Ground
CH4 LNA Input
CH4 LNA VMID Bypass (AC-Coupled to GND)
CH4 LNA Ground Shield
CH4 LNA Feedback Output (for RFBK)
CH4 LNA Positive Output
CH4 VGA Positive Input
CH4VGA Negative Input
CH4 LNA Supply 5 V
Gain Control Voltage for CH3 and CH4
Output Clamping Level Input for CH3 and CH4
Rev. E | Page 10 of 40
03199-006
NC
VCM3
VCM4
HILO
CLMP34
GAIN34
VPS4
VIN4
VIP4
LOP4
LON4
COM4X
LMD4
INH4
COM4
COM3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD8331/AD8332/AD8334
Pin No.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
HILO
VCM4
VCM3
NC
COM34
VOH4
VOL4
VPS34
VOL3
VOH3
COM34
NC
MODE
COM12
VOH2
VOL2
VPS12
VOL1
VOH1
COM12
VCM2
VCM1
EN34
EN12
CLMP12
GAIN12
VPS1
VIN1
VIP1
LOP1
LON1
COM1X
LMD1
INH1
COM1
COM2
Description
Gain Select for Postamp 0 dB or 12 dB
CH4 Common-Mode Voltage—AC Bypass
CH3 Common-Mode Voltage—AC Bypass
No Connect
VGA Ground, CH3 and CH4
CH4 Positive VGA Output
CH4 Negative VGA Output
VGA Supply 5V CH3 and CH4
CH3 Negative VGA Output
CH3 Positive VGA Output
VGA ground CH3 and CH4
No Connect
Gain Control SLOPE, Logic Input, 0 = Positive
VGA Ground CH1 and CH2
CH2 Positive VGA Output
CH2 Negative VGA Output
CH2 VGA Supply 5 V CH1 and CH2
CH1 Negative VGA Output
CH1 Positive VGA Output
VGA Ground CH1 and CH2
CH2 Common-Mode Voltage—AC Bypass
CH1 Common-Mode Voltage—AC Bypass
Shared LNA/VGA Enable, CH3 and CH4
Shared LNA/VGA Enable, CH1 and CH2
Output Clamping Level Input, CH1 and CH2
Gain Control Voltage CH1 and CH2
CH1 LNA Supply 5 V
CH1 VGA Negative Input
CH1 VGA Positive Input
CH1 LNA Positive Output
CH1 LNA Feedback Output (for RFBK)
CH1 LNA Ground Shield
CH1 LNA VMID Bypass (AC-Coupled to GND)
CH1 LNA Input
CH1 LNA Ground
CH2 LNA Ground
Rev. E | Page 11 of 40
AD8331/AD8332/AD8334
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL = 500 Ω, RS = RIN = 50 Ω, RFB = 280 Ω, CSH = 22 pF, f = 10 MHz, RCLMP = ∞, CL = 1 pF, VCM pin floating,
−4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
50
60
50
40
HILO = HI
PERCENT OF UNITS (%)
30
20
10
HILO = LO
0
0.2
0.4
0.6
20
10
ASCENDING GAIN MODE
DESCENDING GAIN MODE
(WHERE AVAILABLE)
03199-007
–10
30
0.8
1.0
0
–0.5
1.1
03199-010
GAIN (dB)
40
0
SAMPLE SIZE = 80 UNITS
VGAIN = 0.5V
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
GAIN ERROR (dB)
VGAIN (V)
Figure 10. Gain Error Histogram
Figure 7. Gain vs. VGAIN and MODE (MODE Available on AC Package)
25
2.0
20
1.5
SAMPLE SIZE = 50 UNITS
VGAIN = 0.2V
GAIN ERROR (dB)
–40°C
PERCENT OF UNITS (%)
15
1.0
+25°C
0.5
0
–0.5
+85°C
–1.0
10
5
0
25
20
VGAIN = 0.7V
15
03199-008
0.2
0.4
0.6
0.8
1.0
0
1.1
VGAIN (V)
CHANNEL TO CHANNEL GAIN MATCH (dB)
Figure 8. Absolute Gain Error vs. VGAIN at Three Temperatures
Figure 11. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
2.0
50
1.5
40
VGAIN = 1V
VGAIN = 0.8V
30
VGAIN = 0.6V
GAIN (dB)
0.5
1MHz
0
10MHz
30MHz
VGAIN = 0.4V
10
VGAIN = 0.2V
50MHz
70MHz
0
0.2
0.4
0.6
0.8
1.0
VGAIN = 0V
–10
–20
100k
1.1
03199-012
–1.5
–2.0
20
0
–1.0
03199-009
GAIN ERROR (dB)
1.0
–0.5
0.19
0.21
0
5
–0.17
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0.11
0.13
0.15
0.17
–2.0
03199-011
10
–1.5
1M
10M
100M
FREQUENCY (Hz)
VGAIN (V)
Figure 12. Frequency Response for Various Values of VGAIN
Figure 9. Absolute Gain Error vs. VGAIN at Various Frequencies
Rev. E | Page 12 of 40
500M
AD8331/AD8332/AD8334
0
VGAIN = 1V
50
VGAIN = 0.8V
40
VGAIN = 0.6V
30
VGAIN = 0.4V
20
VGAIN = 0.2V
VOUT = 1V p-p
–20
VGAIN = 1.0V
CROSSTALK (dB)
GAIN (dB)
60
AD8332
VGAIN = 0.7V
–40
AD8334
VGAIN = 0.4V
–60
–80
10
VGAIN = 0V
03199-013
–10
100k
1M
10M
100M
03199-016
–100
0
–120
100k
500M
1M
FREQUENCY (Hz)
Figure 13. Frequency Response for Various Values of VGAIN, HILO = HI
50
VGAIN = 0.5V
RIN = RS = 75Ω
20
45
RIN = RS = 50Ω
GROUP DELAY (ns)
40
RIN = RS = 100Ω
RIN = RS = 200Ω
0
RIN = RS = 500Ω
–10
RIN = RS = 1kΩ
03199-014
1M
10M
100M
30
1µF
COUPLING
25
20
15
10
–20
–30
100k
0.1µF
COUPLING
35
03199-017
10
5
0
100k
500M
1M
FREQUENCY (Hz)
10M
100M
FREQUENCY (Hz)
Figure 14. Frequency Response for Various Matched Source Impedances
Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling
20
30
VGAIN = 0.5V
RFB = ∞
T = +85°C
T = +25°C
T = –40°C
HI GAIN
10
OFFSET VOLTAGE (mV)
20
10
0
–10
0
–10
–20
20
LO GAIN
10
0
–20
1M
10M
100M
–20
500M
FREQUENCY (Hz)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
03199-018
–30
100k
T = +85°C
T = +25°C
T = –40°C
–10
03199-015
GAIN (dB)
100M
Figure 16. Channel-to-Channel Crosstalk vs.
Frequency for Various Values of VGAIN
30
GAIN (dB)
10M
FREQUENCY (Hz)
0.9
1.0
1.1
VGAIN (V)
Figure 15. Frequency Response, Unterminated LNA, RS = 50 Ω
Figure 18. Representative Differential Output Offset Voltage vs.
VGAIN at Three Temperatures
Rev. E | Page 13 of 40
AD8331/AD8332/AD8334
50j
30
SAMPLE SIZE = 100
0.2V < VGAIN < 0.7V
RIN = 50Ω,
RFB = 270Ω
25
% TOTAL
100j
25j
35
RIN = 6kΩ,
RFB = ∞
f = 100kHz
20
0Ω
17Ω
15
10
RIN = 75Ω,
RFB = 412Ω
0
03199-019
5
49.6
49.7
49.8
49.9
50.0
50.1
50.2
50.3
50.4
RIN = 100Ω,
RFB = 549Ω
50.5
RIN = 200Ω,
RFB = 1.1kΩ
–25j
–100j
03199-022
GAIN SCALING FACTOR
–50j
Figure 19. Gain Scaling Factor Histogram
100
Figure 22. Smith Chart, S11 vs. Frequency,
0.1 MHz to 200 MHz for Various Values of RFB
20
SINGLE ENDED, PIN VOH OR VOL
RL = ∞
VIN = 10mV p-p
RIN = 50Ω
GAIN (dB)
RIN = 200Ω
5
RIN = 500Ω
0
RIN = 1kΩ
1
–10
1M
10M
RIN = 75Ω
–15
100k
100M
1M
FREQUENCY (Hz)
10M
100M
03199-023
–5
0.1
100k
500M
FREQUENCY (Hz)
Figure 20. Output Impedance vs. Frequency
Figure 23. LNA Frequency Response, Single Ended, for Various Values of RIN
10k
20
RFB = ∞, CSH = 0pF
15
RFB = 6.65kΩ, CSH = 0pF
RFB = 3.01kΩ, CSH = 0pF
GAIN (dB)
1k
RFB = 1.1kΩ, CSH = 1.2pF
100
RFB = ∞
10
RFB = 549Ω, CSH = 8.2pF
5
0
–5
10
100k
1M
RFB = 270Ω, CSH = 22pF
10M
100M
FREQUENCY (Hz)
–10
–15
100k
03199-024
RFB = 412Ω, CSH = 12pF
03199-021
INPUT IMPEDANCE (Ω)
RIN = 100Ω
10
10
03199-020
OUTPUT IMPEDANCE (Ω)
15
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 21. LNA Input Impedance vs.
Frequency for Various Values of RFB and CSH
Figure 24. Frequency Response for Unterminated LNA, Single Ended
Rev. E | Page 14 of 40
AD8331/AD8332/AD8334
500
1.00
RS = 0, RFB = ∞,
0.95 VGAIN = 1V, f = 10MHz
0.90
300
LO GAIN
AD8332
AD8334
HI GAIN
AD8331
200
INPUT NOISE (nV/ Hz)
400
0.85
0.80
0.75
0.70
0.65
0.60
0
0
0.2
0.4
0.6
0.8
03199-028
100
03199-025
OUTPUT REFERRED NOISE (nV/ Hz)
f = 10MHz
0.55
0.50
–50
1.0
–30
–10
VGAIN (V)
Figure 25. Output-Referred Noise vs. VGAIN
2.5
10
30
50
70
90
TEMPERATURE (°C)
Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature
RS = 0, RFB = ∞, VGAIN = 1V,
HILO = LO OR HI
10
f = 5MHz, RFB = ∞,
VGAIN = 1V
INPUT NOISE (nV/ Hz)
1.5
RS THERMAL NOISE
ALONE
03199-026
1.0
1
0.5
100k
1M
10M
100M
0.1
FREQUENCY (Hz)
03199-029
INPUT NOISE (nV/ Hz)
2.0
1
10
100
1k
SOURCE RESISTANCE (Ω)
Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency
Figure 29. Input-Referred Noise vs. RS
100
7
RS = 0, RFB = ∞,
HILO = LO OR HI, f = 10MHz
INCLUDES NOISE OF VGA
NOISE FIGURE (dB)
10
1
5
RIN = 50Ω
4
3
2
RIN = 75Ω
RIN = 100Ω
RIN = 200Ω
RFB = ∞
0
0.2
0.4
0.6
0.8
03199-030
0.1
1
03199-027
INPUT NOISE (nV/ Hz)
6
SIMULATION
0
50
100
1.0
VGAIN (V)
1k
SOURCE RESISTANCE (Ω)
Figure 30. Noise Figure vs. RS for Various Values of RIN
Figure 27. Short-Circuit, Input-Referred Noise vs. VGAIN
Rev. E | Page 15 of 40
AD8331/AD8332/AD8334
PREAMP LIMITED
–30
f = 10MHz, RS = 50Ω
f = 10MHz,
VOUT = 1V p-p
30
–40
HARMONIC DISTORTION (dBc)
NOISE FIGURE (dB)
HILO = LO, RIN = 50Ω
25
HILO = HI, RIN = 50Ω
20
15
HILO = LO, RFB = ∞
10
HILO = HI, RIN = ∞
0
03199-031
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
–50
–60
–70
HILO = HI, HD3
0
200
400
600
800
VGAIN (V)
1000 1200 1400 1600 1800 2000
RLOAD (Ω)
Figure 31. Noise Figure vs. VGAIN
Figure 34. Harmonic Distortion vs. RLOAD
30
–40
f = 10MHz,
VOUT = 1V p-p
f = 10MHz, RS = 50Ω
HILO = HI, RIN = 50Ω
HILO = HI, RFB = ∞
20
15
10
HILO = LO, RIN = 50Ω
0
10
HILO = LO, RFB = ∞
15
20
25
30
03199-032
5
35
40
45
50
55
–50
HILO = LO, HD2
HILO = LO, HD3
–60
HILO = HI, HD3
–80
–90
60
HILO = HI, HD2
–70
03199-035
HARMONIC DISTORTION (dBc)
25
NOISE FIGURE (dB)
HILO = LO, HD3
–80
–90
1.1
HILO = LO, HD2
HILO = HI, HD2
03199-034
35
0
10
20
GAIN (dB)
30
40
50
CLOAD (pF)
Figure 35. Harmonic Distortion vs. CLOAD
Figure 32. Noise Figure vs. Gain
–20
–20
–30
HILO = LO, HD2
HILO = LO, HD3
–50
–60
HILO = HI, HD2
–70
HILO = LO, HD3
HILO = LO, HD2
–60
HILO = HI, HD2
HILO = HI, HD3
–80
HILO = HI, HD3
–80
–90
1M
–40
10M
–100
100
03199-036
–40
03199-033
HARMONIC DISTORTION (dBc)
–10
f = 10MHz,
GAIN = 30dB
G = 30dB,
VOUT = 1V p-p
HARMONIC DISTORTION (dBc)
0
0
1
2
3
4
VOUT (V p-p)
FREQUENCY (Hz)
Figure 36. Harmonic Distortion vs. Differential Output Voltage
Figure 33. Harmonic Distortion vs. Frequency
Rev. E | Page 16 of 40
AD8331/AD8332/AD8334
0
0
VOUT = 1V p-p
VOUT = 1V p-p COMPOSITE (f1 + f2)
G = 30dB
–10
–20
–30
HILO = LO, HD3
IMD3 (dBc)
–40
HILO = LO, HD2
–60
–80
–50
–70
HILO = HI, HD3
HILO = HI, HD2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–80
HILO = HI
–90
1M
1.0
10M
VGAIN (V)
Figure 40. IMD3 vs. Frequency
0
40
10MHz HILO = HI
VOUT = 1V p-p
35
–20
1MHz HILO = LO
HILO = LO, HD3
–60
–80
HILO = HI, HD3
10MHz HILO = LO
25
1MHz HILO = HI
20
15
10
HILO = HI, HD2
–100
03199-038
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
03199-041
–40
30
HILO = LO, HD2
INPUT RANGE
LIMITED WHEN
HILO = LO
OUTPUT IP3 (dBm)
DISTORTION (dBc)
100M
FREQUENCY (Hz)
Figure 37. Harmonic Distortion vs. VGAIN, f = 1 MHz
–120
03199-040
–100
–120
HILO = LO
–40
–60
03199-037
DISTORTION (dBc)
–20
INPUT RANGE
LIMITED WHEN
HILO = LO
VOUT = 1V p-p COMPOSITE (f1 + f2)
0
1.0
0
0.1
VGAIN (V)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGAIN (V)
Figure 41. Output Third-Order Intercept vs. VGAIN
Figure 38. Harmonic Distortion vs. VGAIN, f = 10 MHz
10
2mV
f = 10MHz
100
90
0
–10
HILO = HI
–20
10
–40
50mV
10ns
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VGAIN (V)
Figure 42. Small Signal Pulse Response, G = 30 dB,
Top: Input, Bottom: Output Voltage, HILO = HI or LO
Figure 39. Input 1 dB Compression vs. VGAIN
Rev. E | Page 17 of 40
03199-042
0
–30
03199-039
INPUT POWER (dBm)
HILO = LO
AD8331/AD8332/AD8334
5.0
20mV
4.5
100
4.0
90
HILO = HI
VOUT (V p-p)
3.5
HILO = LO
3.0
2.5
2.0
1.5
10
0
10ns
03199-046
03199-043
1.0
500mV
0.5
0
0
5
10
15
20
25
30
35
40
45
50
70
80
RCLMP (kΩ)
Figure 46. Clamp Level vs. RCLMP
Figure 43. Large Signal Pulse Response, G = 30 dB,
HILO = HI or LO, Top: Input, Bottom: Output Voltage
4
2
G = 30dB
1
G = 40dB
CL = 0pF
CL = 10pF
CL = 22pF
CL = 47pF
INPUT
RCLMP = 48.1kΩ
RCLMP = 16.5kΩ
3
2
INPUT
VOUT (V)
VOUT (V)
1
0
0
RCLMP = 7.15kΩ
RCLMP = 2.67kΩ
–1
–2
–1
0
10
20
30
40
–4
–30
03199-047
INPUT IS NOT TO SCALE
–2
–50 –40 –30 –20 –10
03199-044
–3
–20
50
–10
0
10
20
30
40
50
60
TIME (ns)
TIME (ns)
Figure 47. Clamp Level Pulse Response for 4 Values of RCLMP
Figure 44. Large Signal Pulse Response for Various Capacitive Loads,
CL = 0 pF, 10 pF, 20 pF, 50 pF
200mV
500mV
100
90
10
200mV
400ns
03199-045
100ns
03199-048
0
Figure 48. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst,
VGAIN = 0.27 V VGA Output Shown
Figure 45. Pin GAIN Transient Response,
Top: VGAIN, Bottom: Output Voltage
Rev. E | Page 18 of 40
AD8331/AD8332/AD8334
1V
2V
100
90
10
1V
1ms
03199-052
100ns
03199-049
0
Figure 52. Enable Response, Large Signal,
Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
Figure 49. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst,
VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
B
0
VPS1, VGAIN = 0.5V
1V
–10
100
–20
90
PSRR (dB)
VPSV, VGAIN = 0.5V
–30
–40
–50
VPS1, VGAIN = 0V
10
–60
0
03199-053
–70
03199-050
100ns
–80
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 50. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst,
VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
Figure 53. PSRR vs. Frequency (No Bypass Capacitor)
140
QUIESCENT SUPPLY CURRENT (mA)
1ms
03199-051
200mV
130
VGAIN = 0.5V
AD8334
120
110
100
90
80
70
AD8332
60
50
40
AD8331
30
20
–40
–20
0
20
40
03199-054
2V
60
80
TEMPERATURE (°C)
Figure 51. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
B
Rev. E | Page 19 of 40
Figure 54. Quiescent Supply Current vs. Temperature
100
AD8331/AD8332/AD8334
TEST CIRCUITS
MEASUREMENT CONSIDERATIONS
Short-circuit input noise measurements are made using Figure 62.
The input-referred noise level is determined by dividing the
output noise by the numerical gain between Point A and Point B
and accounting for the noise floor of the spectrum analyzer.
The gain should be measured at each frequency of interest and
with low signal levels because a 50 Ω load is driven directly. The
generator is removed when noise measurements are made.
Figure 55 through Figure 68 show typical measurement
configurations and proper interface values for measurements
with 50 Ω conditions.
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
18nF 270Ω
0.1µF
0.1µF
INH
22pF
LMD
237Ω
28Ω
DUT
1:1
237Ω
0.1µF
0.1µF
28Ω
03199-055
FERRITE
BEAD
120nH
Figure 55. Gain and Bandwidth Measurements
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
18nF 10kΩ
FERRITE
BEAD
10kΩ 120nH
0.1µF
22pF
LMD
237Ω
0.1µF
INH
28Ω
DUT
1:1
237Ω
0.1µF
0.1µF
03199-056
28Ω
Figure 56. Frequency Response for Various Matched Source Impedances
NETWORK ANALYZER
FERRITE
BEAD
120nH
50Ω
0.1µF
22pF
INH
LMD
0.1µF
50Ω
0.1µF
IN
237Ω
28Ω
DUT
1:1
237Ω
0.1µF
28Ω
03199-057
OUT
Figure 57. Frequency Response for Unterminated LNA, RS = 50 Ω
Rev. E | Page 20 of 40
AD8331/AD8332/AD8334
NETWORK ANALYZER
50Ω
OUT
50Ω
IN
18nF 10kΩ
0.1µF
AND
10µF
0.1µF
AND
10µF
237Ω
INH
22pF
28Ω
LNA
LMD
VGA
1:1
237Ω
0.1µF
0.1µF
AND
10µF
28Ω
03199-058
FERRITE
BEAD
120nH
Figure 58. Group Delay vs. Frequency for Two Values of AC Coupling
NETWORK
ANALYZER
18nF 270Ω
OUT
0.1µF
22pF
237Ω
0.1µF
INH
28Ω
DUT
LMD
1:1
50Ω
237Ω
0.1µF
0.1µF
03199-059
50Ω
FERRITE
BEAD
120nH
28Ω
Figure 59. LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats
NETWORK ANALYZER
OUT
50Ω
50Ω
IN
0.1µF
0.1µF
0.1µF
0.1µF
237Ω
INH
22pF
LMD
28Ω
LNA
1:1
VGA
237Ω
0.1µF
0.1µF
0.1µF
28Ω
03199-060
FERRITE
BEAD
120nH
Figure 60. Frequency Response for Unterminated LNA, Single Ended
NETWORK
ANALYZER
18nF 270Ω
0.1µF
22pF
INH
LMD
0.1µF
0.1µF
237Ω
1:1
IN
50Ω
28Ω
DUT
237Ω
0.1µF
28Ω
Figure 61. Short-Circuit, Input-Referred Noise
Rev. E | Page 21 of 40
03199-061
FERRITE
BEAD
120nH
AD8331/AD8332/AD8334
SPECTRUM
ANALYZER
A
B
49.9Ω
50Ω
GAIN
FERRITE
BEAD
0.1µF 120nH
22pF
1Ω
0.1µF
INH
1:1
LMD
0.1µF
0.1µF
03199-062
SIGNAL GENERATOR
TO MEASURE GAIN
DISCONNECT FOR
NOISE MEASUREMENT
50Ω
IN
Figure 62. Noise Figure
18nF
270Ω
AD8332
0.1µF
INH
–6dB
LPF
SPECTRUM
ANALYZER
22pF
50Ω
1kΩ
LMD
0.1µF
0.1µF
–6dB
28Ω
IN
50Ω
1:1
28Ω
03199-063
SIGNAL
GENERATOR
0.1µF 1kΩ
Figure 63. Harmonic Distortion vs. Load Resistance
SPECTRUM
ANALYZER
18nF
AD8332
0.1µF
INH
–6dB
50Ω
SIGNAL
GENERATOR
22pF
0.1µF
–6dB
237Ω
28Ω
237Ω
LMD
0.1µF
0.1µF
IN
50Ω
1:1
28Ω
03199-064
LPF
270Ω
Figure 64. Harmonic Distortion vs. Load Capacitance
+22dB –6dB
SPECTRUM
ANALYZER
FERRITE
BEAD
120nH
50Ω
+22dB –6dB
COMBINER
–6dB
18nF 270Ω
0.1µF
22pF
0.1µF 237Ω
INH
LMD
28Ω
237Ω
DUT
0.1µF
0.1µF
–6dB
INPUT
50Ω
1:1
28Ω
50Ω
03199-065
SIGNAL
GENERATORS
Figure 65. IMD3 vs. Frequency
Rev. E | Page 22 of 40
AD8331/AD8332/AD8334
OSCILLOSCOPE
18nF 270Ω
50Ω
22pF
50Ω
0.1µF 237Ω
INH
28Ω
237Ω
DUT
LMD
0.1µF
IN
0.1µF
1:1
28Ω
03199-066
FERRITE
BEAD
120nH 0.1µF
Figure 66. Pulse Response Measurements
OSCILLOSCOPE
FERRITE
BEAD
120nH 0.1µF
18nF 270Ω
0.1µF
INH
22pF
LMD
50Ω
RF
0.1µF
SIGNAL
GENERATOR
DIFF
PROBE
CH1 CH2
255Ω
DUT
0.1µF 255Ω
9.5dB
TO PIN GAIN
OR ENxx
03199-067
50Ω
PULSE
GENERATOR
Figure 67. GAIN and Enable Transient Response
NETWORK
ANALYZER
OUT 50Ω
22pF
50Ω
RF
SIGNAL
GENERATOR
18nF 270Ω
TO POWER
PIN(S)
0.1µF
INH
LMD
0.1µF
IN
DUT
DIFF PROBE
PROBE POWER
255Ω
0.1µF 255Ω
03199-068
FERRITE
BEAD
120nH 0.1µF
50Ω
Figure 68. PSRR vs. Frequency
Rev. E | Page 23 of 40
AD8331/AD8332/AD8334
THEORY OF OPERATION
LON1 LOP1 VIP1 VIN1 EN12
OVERVIEW
The following discussion applies to all part numbers. Figure 69,
Figure 70, and Figure 71 are functional block diagrams of the
AD8331, AD8332, and AD8334, respectively.
LON LOP VIP
VIN
VCM
VMID
INH
LMD
–
+
LNA
–
+
LNA
BIAS
ATTENUATOR
–48dB
VMID1
LNA 1
LMD1
– ATTENUATOR
–48dB
+
LNA
BIAS
21dB
GAIN
INT
+ ATTENUATOR
–48dB
–
LON2
GAIN12
VOL2
21dB
PA2
VOH2
LOP2
VOL
VIP2
CLAMP
RCLMP
MODE
03199-069
ENBV
VOL1
HILO
INH2
PA
GAIN
INT
VOH1
PA1
LNA 2
VIN2
VGA BIAS AND
INTERPOLATOR
CLMP12
CLAMP
21dB
VGA BIAS AND
INTERPOLATOR
LMD2
VOH
AD8331
ENBL
INH1
HILO
3.5dB/
15.5dB
VCM1
GAIN
Figure 69. AD8331 Functional Block Diagram
GAIN UP/
DOWN
MODE
VMID2
VCM2
VMID3
VCM3
VIN3
VIP3
– ATTENUATOR
–48dB
+
LOP3
LON3
INH3
PA3
VOL3
VGA BIAS AND
INTERPOLATOR
LNA 3
VOH3
21dB
GAIN
INT
GAIN34
LMD3
VCM1
BIAS
(VMID)
LMD2
LNA 2
21dB
LNA 4
+ ATTENUATOR
–48dB
–
LON2 LOP2 VIP2 VIN2
AD8334
INH4
VOH1
VOH4
CLAMP34
CLMP34
VMID4
PA1
VOL1
LON4
VGA BIAS AND
INTERPOLATOR
PA4
03199-071
LMD1
– ATTENUATOR
–48dB
+
VOL4
21dB
LMD4
GAIN
INT
21dB
VMID
ENB
VCM2
VCM4
VOL2
Each channel contains an LNA that provides user-adjustable
input impedance termination, a differential X-AMP VGA, and a
programmable gain postamplifier with adjustable output voltage
limiting. Figure 72 shows a simplified block diagram with
external components.
PA2
CLAMP
EN34
Figure 71. AD8334 Functional Block Diagram
VOH2
AD8332
LOP4 VIP4 VIN4
GAIN
RCLMP
03199-070
LNA 1
INH2
3.5dB/
15.5dB
VMID
+19dB
INH1
+ ATTENUATOR
–48dB
–
LNA
BIAS
HILO
Figure 70. AD8332 Functional Block Diagram
HILO
LON
VIN
SIGNAL PATH
INH
LMD
PRE-AMPLIFIER
19dB
+
LNA
–
3.5dB/15.5dB
VOH
48dB
ATTENUATOR
21dB
POSTAMP
VOL
VMID
LOP
BIAS
(VMID)
VIP
BIAS AND
INTERPOLATOR
VCM
GAIN
INTERFACE
GAIN
Figure 72. Simplified Block Diagram
Rev. E | Page 24 of 40
CLAMP
RCLMP
03199-072
LON1 LOP1 VIP1 VIN1
AD8331/AD8332/AD8334
The linear-in-dB gain-control interface is trimmed for slope
and absolute accuracy. The gain range is 48 dB, extending from
−4.5 dB to +43.5 dB in HI gain and +7.5 dB to +55.5 dB in LO
gain mode. The slope of the gain control interface is 50 dB/V,
and the gain control range is 40 mV to 1 V. Equation 1 and
Equation 2 are the expressions for gain.
LOW NOISE AMPLIFIER (LNA)
GAIN (dB) = 50 (dB/V) × VGAIN − 6.5 dB, (HILO = LO)
A simplified schematic of the LNA is shown in Figure 74. INH
is capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of 3.25 V and centers the
output common-mode levels at 2.5 V. A Capacitor CLMD of the
same value as the Input Coupling Capacitor CINH is connected
from the LMD pin to ground.
(1)
or
GAIN (dB) = 50 (dB/V) × VGAIN + 5.5 dB, (HILO = LO)
(2)
The ideal gain characteristics are shown in Figure 73.
60
Good noise performance relies on a proprietary ultralow noise
preamplifier at the beginning of the signal chain, which minimizes
the noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input matching.
CFB
RFB
50
LOP
GAIN (dB)
VPOS
I0
30
20
CINH
10
HILO = LO
RS
0
0.2
0.4
0.6
INH
Q1
I0
LMD
Q2
CLMD
CSH
I0
I0
0.8
1.0
03199-074
03199-073
ASCENDING GAIN MODE
DESCENDING GAIN MODE
(WHERE AVAILABLE)
0
–10
LON
HILO = HI
40
1.1
Figure 74. Simplified LNA Schematic
VGAIN (V)
Figure 73. Ideal Gain Control Characteristics
The gain slope is negative with the MODE pulled high (where
available):
GAIN (dB) = −50 (dB/V) × VGAIN + 45.5 dB, (HILO = LO)
(3)
or
GAIN (dB) = −50 (dB/V) × VGAIN + 57.5 dB, (HILO = HI)
(4)
The LNA converts a single-ended input to a differential output
with a voltage gain of 19 dB. If only one output is used, the gain
is 13 dB. The inverting output is used for active input impedance
termination. Each of the LNA outputs is capacitively coupled to
a VGA input. The VGA consists of an attenuator with a range of
48 dB followed by an amplifier with 21 dB of gain for a net gain
range of −27 dB to +21 dB. The X-AMP gain-interpolation
technique results in low gain error and uniform bandwidth, and
differential signal paths minimize distortion.
The final stage is a logic programmable amplifier with gains of
3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for
12-bit and 10-bit ADC applications, in terms of output-referred
noise and absolute gain range. Output voltage limiting can be
programmed by the user.
The LNA supports differential output voltages as high as 5 V p-p
with positive and negative excursions of ±1.25 V, about a
common-mode voltage of 2.5 V. Because the differential gain
magnitude is 9, the maximum input signal before saturation is
±275 mV or +550 mV p-p. Overload protection ensures quick
recovery time from large input voltages. Because the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
voltage noise of 0.74 nV/√Hz. This is achieved with a current
consumption of only 11 mA per channel (55 mW). On-chip
resistor matching results in precise single-ended gains of 4.5×
(9× differential), critical for accurate impedance control. The
use of a fully differential topology and negative feedback
minimizes distortion. Low HD2 is particularly important in
second harmonic ultrasound imaging applications. Differential
signaling enables smaller swings at each output, further
reducing third-order distortion.
Rev. E | Page 25 of 40
AD8331/AD8332/AD8334
Active Impedance Matching
RS
The LNA supports active impedance matching through an external
shunt feedback resistor from Pin LON to Pin INH. The input
resistance, RIN, is given by Equation 5, where A is the singleended gain of 4.5, and 6 kΩ is the unterminated input impedance.
+
RESISTIVE TERMINATION
(5)
RS
VIN
CFB is needed in series with RFB because the dc levels at Pin LON
and Pin INH are unequal. Expressions for choosing RFB in terms
of RIN and for choosing CFB are found in the Applications section.
CSH and the ferrite bead enhance stability at higher frequencies
where the loop gain is diminished and prevent peaking. Frequency
response plots of the LNA are shown in Figure 23 and Figure 24.
The bandwidth is approximately 130 MHz for matched input
impedances of 50 Ω to 200 Ω and declines at higher source
impedances. The unterminated bandwidth (when RFB = ∞) is
approximately 80 MHz.
RIN
+
RS
VOUT
–
ACTIVE IMPEDANCE MATCH
RFB
R
IN
RS
VIN
+
VOUT
–
RIN =
RFB
1 + 4.5
Figure 75. Input Configurations
7
INCLUDES NOISE OF VGA
6
NOISE FIGURE (dB)
Each output can drive external loads as low as 100 Ω in addition
to the 100 Ω input impedance of the VGA (200 Ω differential).
Capacitive loading up to 10 pF is permissible. All loads should
be ac-coupled. Typically, Pin LOP output is used as a singleended driver for auxiliary circuits, such as those used for
Doppler ultrasound imaging, and Pin LON drives RFB.
Alternatively, a differential external circuit can be driven from
the two outputs in addition to the active feedback termination.
In both cases, important stability considerations discussed in
the Applications section should be carefully observed.
VOUT
–
03199-075
RIN
6 kΩ × RFB
R
= FB 6 kΩ =
1+ A
33 kΩ + RFB
VIN
UNTERMINATED
RIN
RESISTIVE TERMINATION
(RS = RIN)
5
4
3
ACTIVE IMPEDANCE MATCH
2
SIMULATION
0
50
100
03199-076
1
The impedance at each LNA output is 5 Ω. A 0.4 dB reduction
in open-circuit gain results when driving the VGA, and 0.8 dB
with an additional 100 Ω load at the output. The differential
gain of the LNA is 6 dB higher. If the load is less than 200 Ω on
either side, a compensating load is recommended on the
opposite output.
UNTERMINATED
1k
RS (Ω)
Figure 76. Noise Figure vs. RS for Resistive,
Active Matched and Unterminated Inputs
7
INCLUDES NOISE OF VGA
LNA Noise
5
RIN = 50Ω
4
3
2
RIN = 75Ω
RIN = 100Ω
RIN = 200Ω
RFB = ∞
1
03199-077
The input-referred voltage noise sets an important limit on
system performance. The short-circuit input voltage noise of
the LNA is 0.74 nV/√Hz or 0.82 nV/√Hz (at maximum gain),
including the VGA noise. The open-circuit current noise is
2.5 pA/√Hz. These measurements, taken without a feedback
resistor, provide the basis for calculating the input noise and
noise figure performance of the configurations in Figure 75.
Figure 76 and Figure 77 are simulations extracted from these
results, and the 4.1 dB NF measurement with the input actively
matched to a 50 Ω source. Unterminated (RFB = ∞) operation
exhibits the lowest equivalent input noise and noise figure.
Figure 76 shows the noise figure vs. source resistance, rising at
low RS, where the LNA voltage noise is large compared to the
source noise, and again at high RS due to current noise. The
VGA’s input-referred voltage noise of 2.7 nV/√Hz is included in
all of the curves.
NOISE FIGURE (dB)
6
SIMULATION
0
50
100
1k
RS (Ω)
Figure 77. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
Rev. E | Page 26 of 40
AD8331/AD8332/AD8334
The primary purpose of input impedance matching is to
improve the system transient response. With resistive termination,
the input noise increases due to the thermal noise of the
matching resistor and the increased contribution of the LNA’s
input voltage noise generator. With active impedance matching,
however, the contributions of both are smaller than they would
be for resistive termination by a factor of 1/(1 + LNA Gain).
Figure 76 shows their relative noise figure (NF) performance. In
this graph, the input impedance was swept with RS to preserve
the match at each point. The noise figures for a source impedance
of 50 Ω are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the
resistive, active, and unterminated configurations. The noise
figures for 200 Ω are 4.6 dB, 2.0 dB, and 1.0 dB, respectively.
Figure 77 is a plot of the NF vs. RS for various values of RIN,
which is helpful for design purposes. The plateau in the NF for
actively matched inputs mitigates source impedance variations.
For comparison purposes, a preamp with a gain of 19 dB and
noise spectral density of 1.0 nV/√Hz, combined with a VGA
with 3.75 nV/√Hz, yields a noise figure degradation of
approximately 1.5 dB (for most input impedances), significantly
worse than the AD8332 performance.
The equivalent input noise of the LNA is the same for singleended and differential output applications. The LNA noise figure
improves to 3.5 dB at 50 Ω without VGA noise, but this is
exclusive of noise contributions from other external circuits
connected to LOP. A series output resistor is usually
recommended for stability purposes when driving external
circuits on a separate board (see the Applications section). In
low noise applications, a ferrite bead is even more desirable.
VARIABLE GAIN AMPLIFIER
The differential X-AMP VGA provides precise input
attenuation and interpolation. It has a low input-referred noise
of 2.7 nV/√Hz and excellent gain linearity. A simplified block
diagram is shown in Figure 78.
GAIN
GAIN INTERPOLATOR
(BOTH CHANNELS)
+
POSTAMP
6dB
R
48dB
2R
POSTAMP
The signal level at successive stages in the input attenuator
falls from 0 dB to −48 dB in 6 dB steps. The input stages of the
X-AMP are distributed along the ladder, and a biasing interpolator,
controlled by the gain interface, determines the input tap point.
With overlapping bias currents, signals from successive taps
merge to provide a smooth attenuation range from 0 dB to
−48 dB. This circuit technique results in excellent, linear-in-dB
gain law conformance and low distortion levels and deviates
±0.2 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.
The X-AMP inputs are part of a gain-of-12 feedback amplifier
that completes the VGA. Its bandwidth is 150 MHz. The input
stage is designed to reduce feedthrough to the output and to
ensure excellent frequency response uniformity across gain
setting (see Figure 12 and Figure 13).
Gain Control
Position along the VGA attenuator is controlled by a singleended analog control voltage, VGAIN, with an input range of
40 mV to 1.0 V. The gain control scaling is trimmed to a slope
of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control
range saturate to minimum or maximum gain values. Both
channels of the AD8332 are controlled from a single gain
interface to preserve matching. Gain can be calculated using
Equation 1 and Equation 2.
03199-078
VIN
–
The input of the VGA is a differential R-2R ladder attenuator
network with 6 dB steps per stage and a net input impedance of
200 Ω differential. The ladder is driven by a fully differential
input signal from the LNA and is not intended for single-ended
operation. LNA outputs are ac-coupled to reduce offset and
isolate their common-mode voltage. The VGA inputs are biased
through the ladder’s center tap connection to VCM, which is
typically set to 2.5 V and is bypassed externally to provide a
clean ac ground.
Gain accuracy is very good because both the scaling factor and
absolute gain are factory trimmed. The overall accuracy relative
to the theoretical gain expression is ±1 dB for variations in
temperature, process, supply voltage, interpolator gain ripple,
trim errors, and tester limits. The gain error relative to a best-fit
line for a given set of conditions is typically ±0.2 dB. Gain
matching between channels is better than 0.1 dB (Figure 11
shows gain errors in the center of the control range). When
VGAIN < 0.1 or > 0.95, gain errors are slightly greater.
gm
VIP
X-AMP VGA
Figure 78. Simplified VGA Schematic
Rev. E | Page 27 of 40
AD8331/AD8332/AD8334
The gain slope can be inverted, as shown in Figure 73 (available
in most versions). The gain drops with a slope of −50 dB/V
across the gain control range from maximum to minimum gain.
This slope is useful in applications, such as automatic gain
control, where the control voltage is proportional to the
measured output signal amplitude. The inverse gain mode is
selected by setting the MODE pin HI.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. While
the input-referred noise of the LNA limits the minimum
resolvable input signal, the output-referred noise, which
depends primarily on the VGA, limits the maximum
instantaneous dynamic range that can be processed at any one
particular gain control voltage. This limit is set in accordance
with the quantization noise floor of the ADC.
Output and input-referred noise as a function of VGAIN are
plotted in Figure 25 and Figure 27 for the short-circuited input
conditions. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.
The output-referred noise is flat over most of the gain range,
because it is dominated by the fixed output-referred noise of the
VGA. Values are 48 nV/√Hz in LO gain mode and 178 nV/√Hz
in HI gain mode. At the high end of the gain control range, the
noise of the LNA and source prevail. The input-referred noise
reaches its minimum value near the maximum gain control
voltage, where the input-referred contribution of the VGA
becomes very small.
signal. A transformer can be used with single-ended applications
when low noise is desired.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and usually only evident when a large signal is
present. Its effect is observable only in LO gain mode, where the
noise floor is substantially lower. The gain interface includes an
on-chip noise filter, which reduces this effect significantly at
frequencies above 5 MHz. Care should be taken to minimize
noise impinging at the GAIN input. An external RC filter can be
used to remove VGAIN source noise. The filter bandwidth should be
sufficient to accommodate the desired control bandwidth.
Common-Mode Biasing
An internal bias network connected to a midsupply voltage
establishes common-mode voltages in the VGA and postamp.
An externally bypassed buffer maintains the voltage. The bypass
capacitors form an important ac ground connection, because
the VCM network makes a number of important connections
internally, including the center tap of the VGA’s differential
input attenuator, the feedback network of the VGA’s fixed gain
amplifier, and the feedback network of the postamplifier in both
gain settings. For best results, use a 1 nF and a 0.1 μF capacitor
in parallel, with the 1 nF nearest to the VCM pin. Separate
VCM pins are provided for each channel. For dc-coupling to a
3 V ADC, the output common-mode voltage is adjusted to
1.5 V by biasing the VCM pin.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB (×1.5) or 15.5 dB
(×6), set by the logic pin, HILO. Figure 79 is a simplified block
diagram.
+
At lower gains, the input-referred noise, and thus noise figure,
increases as the gain decreases. The instantaneous dynamic
range of the system is not lost, however, because the input
capacity increases with it. The contribution of the ADC noise
floor has the same dependence as well. The important
relationship is the magnitude of the VGA output noise floor
relative to that of the ADC.
Gm2
VOH
Gm1
F2
F1
VCM
The preceding noise performance discussion applies to a
differential VGA output signal. Although the LNA noise
performance is the same in single-ended and differential
applications, the VGA performance is not. The noise of the
VGA is significantly higher in single-ended usage, because the
contribution of its bias noise is designed to cancel in the differential
VOL
–
Gm1
03199-079
Gm2
With its low output-referred noise levels, these devices ideally
drive low voltage ADCs. The converter noise floor drops 12 dB
for every 2 bits of resolution and drops at lower input full-scale
voltages and higher sampling rates. ADC quantization noise is
discussed in the Applications section.
Figure 79. Postamplifier Block Diagram
Separate feedback attenuators implement the two gain settings.
These are selected in conjunction with an appropriately scaled
input stage to maintain a constant 3 dB bandwidth between the
two gain modes (~150 MHz). The slew rate is 1200 V/μs in HI
gain mode and 300 V/μs in LO gain mode. The feedback
networks for HI and LO gain modes are factory trimmed to
adjust the absolute gains of each channel.
Rev. E | Page 28 of 40
AD8331/AD8332/AD8334
Although the quantization noise floor of an ADC depends on a
number of factors, the 48 nV/√Hz and 178 nV/√Hz levels are
well suited to the average requirements of most 12-bit and 10-bit
converters, respectively. An additional technique, described in
the Applications section, can extend the noise floor even lower
for possible use with 14-bit ADCs.
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential
when operating at a 2.5 V common-mode voltage. The postamp
implements an optional output clamp engaged through a
resistor from RCLMP to ground. Table 8 shows a list of
recommended resistor values.
Output clamping can be used for ADC input overload
protection, if needed, or postamp overload protection when
operating from a lower common-mode level, such as 1.5 V. The
user should be aware that distortion products increase as output
levels approach the clamping levels, and the user should adjust
the clamp resistor accordingly. For additional information, see
the Applications section.
The accuracy of the clamping levels is approximately ±5% in LO
or HI mode. Figure 80 illustrates the output characteristics for a
few values of RCLMP.
5.0
4.5
RCLMP = ∞
4.0
8.8kΩ
3.5
3.5kΩ
3.0
2.5
RCLMP = 1.86kΩ
2.0
3.5kΩ
1.5
8.8kΩ
1.0
0.5
0
–3
RCLMP = ∞
–2
–1
03199-080
The topology of the postamplifier provides constant inputreferred noise with the two gain settings and variable
output-referred noise. The output-referred noise in HI gain
mode increases (with gain) by four. This setting is recommended
when driving converters with higher noise floors. The extra gain
boosts the output signal levels and noise floor appropriately. When
driving circuits with lower input noise floors, the LO gain mode
optimizes the output dynamic range.
VOH, VOL (V)
Noise
0
1
2
VINH (V)
Figure 80. Output Clamping Characteristics
Rev. E | Page 29 of 40
3
AD8331/AD8332/AD8334
APPLICATIONS
CLMD
0.1µF
The LMD pin (connected to the bias circuitry) must be bypassed to
ground and signal sourced to the INH pin capacitively coupled
using 2.2 nF to 0.1 μF capacitors (see Figure 81).
1
2
5V
The unterminated input impedance of the LNA is 6 kΩ. The
user can synthesize any LNA input resistance between 50 Ω and
6 kΩ. RFB is calculated according to Equation 6 or selected from
Table 7.
RFB =
33 kΩ × (RIN )
RFB (Nearest STD 1% Value, Ω)
280
412
562
1.13 k
3.01 k
∞
5
6
7
0.1µF
Table 7. LNA External Component Values for Common
Source Impedances
RIN (Ω)
50
75
100
200
500
6k
4
(6)
6 kΩ – (RIN )
1nF
8
9
VGAIN
CSH (pF)
22
12
8
1.2
None
None
3
1nF
10
11
0.1µF
1nF
12
13
14
LMD2
LMD1
INH2
INH1
VPS2
VPS1
LON2
LON1
LOP2
LOP1
COM2
COM1
VIP2
VIP1
VIN2
VIN1
VCM2
VCM1
GAIN
HILO
RCLMP
ENB
VOH2
VOL2
COMM
LNA
SOURCE
FB
VOH1
VOL1
VPSV
28
0.1µF
CSH*
27
5V
CFB*
26
RFB* 1nF
25
0.1µF
LNA OUT
24
23
22
0.1µF
21
20
1nF
19
0.1µF
5V
18
5V
17
*
16
*
VGA OUT
VGA OUT
15
5V
1nF
03199-081
LNA—EXTERNAL COMPONENTS
0.1µF
*SEE TEXT
When active input termination is used, a decoupling capacitor
(CFB) is required to isolate the input and output bias voltages of
the LNA.
Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)
RFB
The shunt input capacitor, CSH, reduces gain peaking at higher
frequencies where the active termination match is lost due to
the gain roll-off of the LNA at high frequencies. The value of
CSH diminishes as RIN increases to 500 Ω, at which point no
capacitor is required. Suggested values for CSH for 50 Ω ≤ RIN ≤
200 Ω are shown in Table 7.
LNA
DECOUPLING
RESISTOR
VIP
5Ω
TO EXT
CIRCUIT
50Ω
LON
100Ω
VCM
LNA
CSH
5Ω
100Ω
LOP
50Ω
Figure 82 shows the interconnection details of the LNA output.
Capacitive coupling between the LNA outputs and the VGA
inputs is required because of the differences in their dc levels
and the need to eliminate the offset of the LNA. Capacitor
values of 0.1 μF are recommended. There is 0.4 dB loss in gain
between the LNA output and the VGA input due to the 5 Ω
output resistance. Additional loading at the LOP and LON
outputs affect LNA gain.
LNA
DECOUPLING
RESISTOR
TO EXT
CIRCUIT
03199-082
VIN
When a long trace to Pin INH is unavoidable, or if both LNA
outputs drive external circuits, a small ferrite bead (FB) in series
with Pin INH preserves circuit stability with negligible effect on
noise. The bead shown is 75 Ω at 100 MHz (Murata BLM21 or
equivalent). Other values can prove useful.
Figure 82. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits.
Pin LOP should be used in those instances when a single-ended
LNA output is required. The user should be aware of stray
capacitance loading of the LNA outputs, in particular LON. The
LNA can drive 100 Ω in parallel with 10 pF. If an LNA output is
routed to a remote PC board, it tolerates a load capacitance up
to 100 pF with the addition of a 49.9 Ω series resistor or ferrite
75 Ω/100 MHz bead.
Gain Input
The GAIN pin is common to both channels of the AD8332. The
input impedance is nominally 10 MΩ and a bypass capacitor
from 100 pF to1 nF is recommended.
Rev. E | Page 30 of 40
AD8331/AD8332/AD8334
VCM Input
The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH
defaults to 2.5 V dc. With output ac-coupled applications, the
VCM pin is unterminated; however, it must still be bypassed in
close proximity for ac grounding of internal circuitry. The VGA
outputs can be dc connected to a differential load, such as an
ADC. Common-mode output voltage levels between 1.5 V and
3.5 V can be realized at Pin VOH and Pin VOL by applying the
desired voltage at Pin VCM. DC-coupled operation is not
recommended when driving loads on a separate PC board.
The voltage on the VCM pin is sourced by an internal buffer
with an output impedance of 30 Ω and a ±2 mA default output
current (see Figure 83). If the VCM pin is driven from an
external source, its output impedance should be <<30 Ω and its
current drive capability should be >>2 mA. If the VCM pins of
several devices are connected in parallel, the external buffer
should be capable of overcoming their collective output currents.
When a common-mode voltage other than 2.5 V is used, a
voltage-limiting resistor, RCLMP, is needed to protect against
overload.
30Ω
VCM
100pF
Note that third harmonic distortion increases as waveform
amplitudes approach clipping. For lowest distortion, the clamp
level should be set higher than the converter input span. A
clamp level of 1.5 V p-p is recommended for a 1 V p-p linear
output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for
a 0.5 V p-p operation. The best solution is determined
experimentally. Figure 84 shows third harmonic distortion
as a function of the limiting level for a 2 V p-p output signal.
A wider limiting level is desirable in HI gain mode.
–20
VGAIN = 0.75V
–30
–40
–50
HILO = LO
–60
HILO = HI
–70
–80
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
CLAMP LIMIT LEVEL (V p-p)
Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input
INTERNAL
CIRCUITRY
RO << 30Ω
NEW VCM
0.1µF
AC GROUNDING FOR
INTERNAL CIRCUITRY
03199-083
2mA MAX
The RCLMP pin provides the user with a means to limit the
output voltage swing when used with loads that have no
provisions for prevention of input overdrive. The peak-to-peak
limited voltage is adjusted by a resistor to ground, and Table 8
lists several voltage levels and the corresponding resistor value.
Unconnected, the default limiting level is 4.5 V p-p.
03199-084
If gain control noise in LO gain mode becomes a factor,
maintaining ≤15 nV/√Hz noise at the GAIN pin ensures
satisfactory noise performance. Internal noise prevails below
15 nV/√Hz at the GAIN pin. Gain control noise is negligible in
HI gain mode.
Optional Output Voltage Limiting
HD3 (dBc)
Parallel connected devices can be driven by a common voltage
source or DAC. Decoupling should take into account any
bandwidth considerations of the drive waveform, using the total
distributed capacitance.
Figure 83. VCM Interface
Logic Inputs—ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 kΩ and
can be pulled up to 5 V (a pull-up resistor is recommended) or
driven by any 3 V or 5 V logic families. The enable pin, ENB,
powers down the VGA—when pulled low, the VGA output
voltages are near ground. Multiple devices can be driven from a
common source. Consult Table 3, Table 4, Table 5, and Table 6
for circuit functions controlled by the enable pins.
Table 8. Clamp Resistor Values
Clamp Level (V p-p)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.4
Pin HILO is compatible with 3 V or 5 V CMOS logic families. It
is either connected to ground or pulled up to 5 V, depending on
the desired gain range and output noise.
Rev. E | Page 31 of 40
Clamp Resistor Value (kΩ)
HILO = LO
HILO = HI
1.21
2.74
2.21
4.75
4.02
7.5
6.49
11
9.53
16.9
14.7
26.7
23.2
49.9
39.2
100
73.2
AD8331/AD8332/AD8334
4V p-p DIFF,
48nV/ Hz
0.1µF
1.5µH
158Ω
1.5µH
158Ω
18pF
ADC
Figure 85. 20 MHz Second-Order, Low-Pass Filter
OVERLOAD
These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.
Signals larger than ±275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 48
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.
Both stages of the VGA are susceptible to overload. Postamp
limiting is more common and results in the clean-limited
output characteristics found in Figure 49. Recovery is fast in all
cases. The graph in Figure 87 summarizes the combinations of
input signal and gain that lead to the different types of overload.
POSTAMP
OVERLOAD
DRIVING ADCs
43.5
The output drive accommodates a wide range of ADCs. The
noise floor requirements of the VGA depend on a number of
application factors, including bit resolution, sampling rate, fullscale voltage, and the bandwidth of the noise/antialias filter. The
output noise floor and gain range can be adjusted by selecting
HI or LO gain mode.
The relative noise and distortion performance of the two gain
modes can be compared in Figure 25 and Figure 31 through
Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC fullscale voltages as high as 4 V p-p. Because distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 36), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 86 has an output full-scale range of
2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.
187Ω
X-AMP
OVERLOAD
15mV
POSTAMP
OVERLOAD
25mV
56.5
4mV
X-AMP
OVERLOAD
25mV
41dB
29dB
–4.5
1m
24.5dB
LO GAIN
MODE
24.5dB
HI GAIN
MODE
7.5
10m
0.1 0.275
INPUT AMPLITUDE (V)
1
1m
10m
0.1 0.275
INPUT AMPLITUDE (V)
1
03199-087
84.5Ω
0.1µF
AD6644
Figure 86. Adjusting the Noise Floor for 14-Bit ADCs
GAIN (dB)
84.5Ω
03199-085
OPTIONAL
BACKPLANE
ADC
LPF
LNA OVERLOAD
When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and to mitigate charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 85
shows a second-order, low-pass filter with a bandwidth of
20 MHz. The capacitor is chosen in conjunction with the 10 pF
input capacitance of the ADC.
374Ω
2:1
VOL
GAIN (dB)
An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.
187Ω
VOH
LNA OVERLOAD
When driving capacitive loads greater than about 10 pF, or long
circuit connections on other boards, an output network of
resistors and/or ferrite beads can be useful to ensure stability.
These components can be incorporated into a Nyquist filter
such as the one shown in Figure 81. In Figure 81, the resistor
value is 84.5 Ω. The AD8332-EVAL incorporates 100 Ω in
parallel with a 120 nH bead. Lower value resistors are permissible
for applications with nearby loads or with gains less than 40 dB.
The exact values of these components can be selected empirically.
2V p-p DIFF,
24nV/ Hz
03199-086
Output Decoupling
Figure 87. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the
maximum output swing of the postamp and its overload
response. When the clamp feature is not used, the output level
defaults to approximately 4.5 V p-p differential centered at
2.5 V common mode. When other common-mode levels are set
through the VCM pin, the value of RCLMP should be selected for
graceful overload. A value of 8.3 kΩ or less is recommended for
1.5 V or 3.5 V common-mode levels (7.2 kΩ for HI gain mode).
This limits the output swing to just above 2 V p-p differential.
Rev. E | Page 32 of 40
AD8331/AD8332/AD8334
OPTIONAL INPUT OVERLOAD PROTECTION
MULTIPLE INPUT MATCHING
Applications in which high transients are applied to the LNA
input can benefit from the use of clamp diodes. A pair of backto-back Schottky diodes can reduce these transients to manageable
levels. Figure 88 illustrates how such a diode-protection scheme
can be connected.
Matching of multiple sources with dissimilar impedances can be
accomplished as shown in Figure 90. A relay and low supply
voltage analog switch can be used to select between multiple
sources and their associated feedback resistors. An ADG736
dual SPDT switch is shown in this example; however, multiple
switches are also available and users are referred to the Analog
Devices Selection Guide for switches and multiplexers.
COMM 20
0.1µF
RSH
3
CSH
2
CFB
RFB
INH
DISABLING THE LNA
ENBL 19
Where accessible, connection of the LNA enable pin to ground
powers down the LNA, resulting in a current reduction of about
half. In this mode, the LNA input and output pins can be left
unconnected; however, the power must be connected to all the
supply pins for the disabling circuit to function. Figure 89
illustrates the connections using an AD8331 as an example.
3 VPSL
1
BAS40-04
03199-088
4 LON
2
Figure 88. Input Overload Clamping
When selecting overload protection, the important parameters
are forward and reverse voltages and trr (or τrr). The Infineon
BAS40-04 series shown in Figure 88 has a τrr of 100 ps and VF of
310 mV at 1 mA. Many variations of these specifications can be
found in vendor catalogs.
NC
1
LMD
COMM
20
AD8331
NC
2
INH
ENBL
VPSL
ENBV
LON
COMM
LOP
VOL
19
CFB
0.018µF
LAYOUT, GROUNDING, AND BYPASSING
5V
Due to their excellent high frequency characteristics, these
devices are sensitive to their PCB environment. Realizing
expected performance requires attention to detail critical to
good high speed board design.
3
NC
A multilayer board with power and ground planes is
recommended with blank areas in the signal layers filled with
ground plane. Be certain that the power and ground pins
provided for robust power distribution to the device are
connected. Decouple the power supply pins with surface-mount
capacitors as close as possible to each pin to minimize impedance
paths to ground. Decouple the LNA power pins from the VGA
supply using ferrite beads. Together with the capacitors, ferrite
beads eliminate undesired high frequencies without reducing
the headroom. Use a larger value capacitor for every 10 chips to
20 chips to decouple residual low frequency noise. To minimize
voltage drops, use a 5 V regulator for the VGA array.
Several critical LNA areas require special care. The LON and
LOP output traces must be as short as possible before connecting to
the coupling capacitors connected to Pin VIN and Pin VIP. RFB
must be placed near the LON pin as well. Resistors must be
placed as close as possible to the VGA output pins, VOL and
VOH, to mitigate loading effects of connecting traces. Values
are discussed in the Output Decoupling section.
Signal traces must be short and direct to avoid parasitic effects.
Wherever there are complementary signals, symmetrical layout
should be employed to maintain waveform balance. PCB traces
should be kept adjacent when running differential signals over a
long distance.
Rev. E | Page 33 of 40
NC
4
5
18
5V
17
16
VOUT
6
0.1µF
VIN
0.1µF
MODE
7
8
9
COML
VOH
VIP
VPOS
VIN
HILO
MODE
RCLMP
15
14
13
5V
HILO
12
RCLMP
GAIN
10
GAIN
VCM
11
VCM
03199-089
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP FB
Figure 89. Disabling the LNA
AD8331/AD8332/AD8334
ADG736
Using the EVAL-AD8332/AD9238 evaluation board and a high
speed ADC FIFO evaluation kit connected to a laptop, an FFT
can be performed on the AD8332. With the on-board clock of
20 MHz, minimal low-pass filtering, and both channels driven
with a 1 MHz filtered sine wave, the THD is −75 dB, noise floor
is −93 dB, and HD2 is −83 dB.
1.13kΩ
SELECT RFB
280Ω
LON
18nF
200Ω
5Ω
INH
50Ω
HIGH DENSITY QUAD LAYOUT
LNA
LOP
5Ω
0.1µF
AD8332
The AD8334 is the ideal solution for applications with limited
board space. Figure 94 represents four channels routed to and
away from this very compact quad VGA. Note that none of the
signal paths crosses and that all four channels are spaced apart
to eliminate crosstalk.
03199-090
LMD
Figure 90. Accommodating Multiple Sources
ULTRASOUND TGC APPLICATION
The AD8332 ideally meets the requirements of medical and
industrial ultrasound applications. The TGC amplifier is a key
subsystem in such applications, because it provides the means
for echolocation of reflected ultrasound energy.
Figure 91 through Figure 93 are schematics of a dual, fully
differential system using the AD8332 and the AD9238, 12-bit
high speed ADC with conversion speeds as high as 65 MSPS.
In this example, all of the components shown are 0402 size;
however, the same layout is executable at the expense of slightly
more board area. The sketch also assumes that both sides of the
printed circuit board are available for components, and that the
bypass and power supply decoupling circuitry is located on the
wiring side of the board.
Rev. E | Page 34 of 40
AD8331/AD8332/AD8334
S3
EIN2
TP5
AD8332ARU
C50
0.1µF
LMD2
LMD1
28
2
+5V
CFB2
18nF
+
C80
22pF
RFB2
274Ω
C41
0.1µF
3
C74
1nF
L6
120nH FB +5VLNA
5
6
7
VCM1
VPS1
26
8
LON2
LON1
LOP2
LOP1
COM2
COM1
VIP2
VIP1
VIN2
VIN1
C48
0.1µF
TP2 GAIN
TP7 GND
R3
(RCLMP)
C78
1nF
9
10
VCM2
VCM1
VIN–B
JP8
DC2H
CFB1
18nF
RFB1
274Ω
24
C42
0.1µF
23
C59
0.1µF
22
21
20
HILO
11
C69
0.1µF
C43
0.1µF
+5VGA
19
HI GAIN
JP10
LO GAIN
+5VGA
C68
1nF
R27
100Ω
L19
SAT
L17
SAT
C54
0.1µF
L11
120nH FB
13
C67
L20 SAT
SAT
L18 JP12
SAT
C55
0.1µF
L10
120nH FB
14
JP7
DC2L
GAIN
C83
1nF
12
C66
SAT
S1
EIN1
25
C77
1nF
VIN+B
C60
0.1µF
VCM1
JP13
OPTIONAL 4-POLE LOW-PASS
FILTER
C79
22pF
+5VLNA
4
C53
0.1µF
VPS2
L13
120nH FB
27
JP6
IN1
L7
120nH FB +5VGA
C51
0.1µF
INH1
JP5
IN2
+5VLNA
C46
1µF
INH2
TP6
C70
0.1µF
L12
120nH FB
TB1
+5V
TP4
(BLACK)
TB2
GND
C49
0.1µF
RCLMP
VOH2
ENB
VOH1
VOL2
VOL1
COM
VPSV
18
ENABLE
JP16
DISABLE
17
R24
100Ω
16
15
JP9
OPTIONAL 4-POLE LOW-PASS
FILTER
L9
120nH FB
C58
0.1µF
L1
SAT
L15
SAT
L8
120nF FB
JP17
C56
0.1µF
L14
SAT
C64
SAT L16
SAT
VIN+A
C65
SAT
VIN–A
R26
100Ω
+5VGA
C45
0.1µF
R25
100Ω
C85
1nF
JP10
Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238
Rev. E | Page 35 of 40
03199-091
TP3
(RED)
1
AD8331/AD8332/AD8334
3
+
2
C22
0.1µF
C31
0.1µF
1
L4
120nH FB
IN OUT GND
C30
0.1µF
OUT
TAB
L3
120nH FB
R5
33Ω
VIN+_A
L2
120nH FB
1
2
3
R6
33Ω
R4
C18
1.5kΩ C17
1nF
C33 0.1µF
10µF
6.3V
+
C40
0.1µF
R12
1.5kΩ
C35
0.1µF
C1
0.1µF
C36
0.1µF
4
5
6
C52
10nF
TP9
C32 +
0.1µF
VREF
C34
10µF
6.3V
C38
0.1µF
C12
10µF
6.3V
9
C57
10nF
C39
10µF
C37
0.1µF
VIN–B
S2
EXT CLOCK
VIN+B
13
14
15
R7
33Ω
16
17
C20
0.1µF
R16
5kΩ
R17
49.9Ω
C15
1nF
C62
18pF
R18
499Ω
C63
0.1µF
C19
1nF
18
19
R19
499Ω
JP3
JP11
R20
4.7kΩ
R41
4.7kΩ
20
21
22
+3.3VCLK
ADCLK
+
C86
0.1µF
4
1
VDD OE
20MHz
3
OUT
GND
2
U6
SG-636PCE
11
12
1.5kΩ
+3.3VCLK
7
8
10
C16
1.5kΩ
0.1µF
R8
33Ω
C47
10µF
6.3V
ADCLK
JP4
2
1
INT
3
4
U5
74VHC04
5
6
DNC
TP 12
1
R9
0Ω
2
U5
74VHC04
9
8
TP 13
DATA
CLK
U5
74VHC04
13
12
11
10
U5
74VHC04
D0_B
D1_B
D2_B
2
23
24
25
26
27
28
3
1
JP1
SPARES
DNC
U5
74VHC04
U5
74VHC04
EXT
3
ADCLK
+
C61
18pF
VIN–_A
C29
0.1µF
C2
10µF
6.3V
C21
1nF
29
D3_B
30
D4_B
31
D5_B
32
AGND
AVDD
VIN+_A
CLK_A
63
VIN–_A
SHARED_REF
AGND
MUX_SELECT
61
R14
4.7kΩ
AVDD
PDWN_A
60
R15 +3.3VADDIG
0Ω
59
OEB_A
REFB_A
OTR_A
58
OTR_A
D11_A (MSB)
57
D11_A
56
D10_A
55
D9_A
54
D8_A
VREF
D10_A
SENSE
D9_A
REFB_B
REFT_B
AVDD
AGND
VIN–_B
VIN+_B
AGND
AVDD
CLK_B
D8_A
DRGND
D7_A
D6_A
D5_A
D4_A
D3_A
D1_A
DFS
D0_A
PDWN_B
OEB_B
DNC
DNC
DNC
DNC
DRVDD
D0_B
DRGND
D1_B
OTR_B
D2_B
D11_B (MSB)
DRGND
D10_B
DRVDD
D9_B
D3_B
D4_B
D5_B
C24
1nF
D8_B
D7_B
D6_B
+3.3VADDIG
53
DRVDD 52
D2_A
DCS
Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238
Rev. E | Page 36 of 40
62
REFT_A
+3.3VADDIG
C26
0.1µF
R11
100Ω
R10
JP2
0Ω SHARED
REF
Y
N
64
51
50
49
48
47
46
45
44
43
42
C23
0.1µF
C25
1nF
D7_A
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
41
40
39
38
37
36
35
34
33
C13
1nF
C14 +
0.1µF
C11
10µF
6.3V
OTR_B
D11_B
D10_B
D9_B
D8_B
D7_B
D6_B
03199-092
+5V
+3.3VAVDD
L5
120nH FB
U1 A/D CONVERTER AD9238
VR1
ADP3339AKC-3.3
C44
1µF
AD8331/AD8332/AD8334
DATACLKA
1
OTR_A
D11_A
D10_A
D9_A
D7_A
D6_A
RP 9
8
7
20
U10 VCC
74VHC541
19
10
G2
GND
2
18
A1
Y1
3
17
Y2
A2
16
4
Y3
A3
3
6
4
5
5
8
6
7
7
3
6
8
4
5
9
1
2
22 × 4
RP 10
G1
A4
Y4
A5
Y5
A6
Y6
A7
A8
Y7
Y8
+
C3
0.1µF
C28
10µF
6.3V
1
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DNC
DNC
1
2
22 × 4
RP 11
6
3
4
4
5
1
22 × 4
2
RP 12
5
8
6
7
7
3
6
8
4
5
9
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
3
6
5
8
7
15
4
5
10
9
14
1
22 × 4
8
12
11
13
2
RP2
7
14
13
12
3
6
16
11
4
5
18
G1
A3
1
4
6
U7 VCC 20
74VHC541
10
G2
GND
2
18
A1
Y1
3
17
A2
Y2
7
RP 1
2
8
7
C10 +
0.1µF
C8
0.1µF
19
8
22 × 4
3
2
+3.3VDVDD
1
R40
22Ω
+3.3VDVDD
C76
10µF
6.3V
16
1
22 × 4
8
20
2
RP 3
7
22
3
6
24
4
5
26
HEADER UP MALE NO SHROUD
D8_A
2
22 × 4
1
15
17
19
21
23
25
1
22 × 4
8
28
2
RP 4
7
30
29
3
6
32
31
4
5
34
33
36
35
15
14
13
27
38
37
40
39
12
SAM080UPM
11
+3.3VDVDD
OTR_B
D11_B
D10_B
D9_B
D7_B
D6_B
D5_B
RP 13
22 × 4
RP 14
3
8
7
6
4
1
7
5
4
2
20
U2
G1
VCC
74VHC541
10
GND
G2
2
18
A1
Y1
3
17
A2
Y2
16
4
A3
Y3
5
15
A4
Y4
6
14
A5
Y5
7
13
A6
Y6
8
12
A7
Y7
9
11
A8
Y8
5
22 × 4
+
C7
0.1µF
19
6
3
1
8
8
+
C9
0.1µF
C27
10µF
6.3V
+3.3VDVDD
1
RP 15
20
U3 VCC
74VHC541
10
GND
G2
2
18
Y1
A1
G1
19
D4_B
D3_B
D2_B
D1_B
D0_B
DNC
DNC
2
7
3
6
4
1
2
5
22 × 4
RP 16
8
7
3
4
5
6
3
6
7
4
5
8
9
A2
Y2
A3
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
C4
0.1µF
C5
0.1µF
C6 +
0.1µF
C75
10µF
6.3V
17
16
15
41
44
43
1
22 × 4
8
46
45
2
RP 5
7
48
47
3
6
50
49
4
5
52
51
53
1
22 × 4
8
54
2
RP 6
7
56
3
6
58
4
5
60
1
22 × 4
8
62
2
RP 7
7
64
3
6
66
4
5
68
55
57
59
61
63
65
67
1
22 × 4
8
70
69
2
RP 8
7
72
71
3
6
74
73
4
5
76
75
14
13
12
R39
22Ω
11
DATACLK
Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238
Rev. E | Page 37 of 40
42
HEADER UP MALE NO SHROUD
D8_B
2
22 × 4
78
77
80
79
SAM080UPM
03199-093
1
1
AD8331/AD8332/AD8334
CH 1 LNA INPUT
VCM2
EN34
VCM1
EN12
GAIN12
CLMP12
VIN1
VPS1
VIP1
LOP1
LON1
COM1X
INH1
LMD1
COM2
49
COM12
LMD2
VOH1
COM2X
VOL1
LON2
VPS12
LOP2
VOL2
VIP2
VOH2
VIN2
COM12
AD8334
VPS2
MODE
POWER SUPPLY DECOUPLING
LOCATED ON WIRING SIDE
NC
VPS3
VIN3
COM34
VIP3
VOH3
LOP3
VOL3
LON3
VPS34
COM3X
VOL4
LMD3
VOH4
COM34
48
47
46
CH 1 DIFFERENTIAL
OUTPUT
45
44
43
CH 2 DIFFERENTIAL
OUTPUT
42
41
40
39
38
CH 3 DIFFERENTIAL
OUTPUT
37
36
35
34
CH 4 DIFFERENTIAL
OUTPUT
33
NC
INH3
VCM3
16
50
VCM4
15
51
HILO
14
52
CLMP34
13
53
GAIN34
12
54
VPS4
11
55
VIN4
9
10
56
VIP4
8
57
LOP4
7
58
LON4
6
59
COM4X
5
60
LMD4
4
61
INH4
3
INH2
COM4
2
COM3
1
62
COM1
63
64
CH 2 LNA INPUT
CH 3 LNA INPUT
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
03199-094
CH 4 LNA INPUT
Figure 94. Signal Path and Board Layout for AD8334
Rev. E | Page 38 of 40
AD8331/AD8332/AD8334
OUTLINE DIMENSIONS
0.345
0.341
0.337
9.80
9.70
9.60
20
28
11
15
4.50
4.40
4.30
1
1
6.40 BSC
0.158
0.154
0.150
10
0.244
0.236
0.228
PIN 1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.065
0.049
1.20 MAX
8°
0°
0.20
0.09
SEATING
PLANE
0.010
0.004
0.75
0.60
0.45
0.069
0.053
0.025
BSC
0.012
0.008
COPLANARITY
0.004
SEATING
PLANE
0.010
0.006
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AE
COMPLIANT TO JEDEC STANDARDS MO-137-AD
Figure 95. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
Figure 96. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in Inches
0.60 MAX
5.00
BSC SQ
0.60 MAX
25
24
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
0.80 MAX
0.65 TYP
9
8
0.25 MIN
3.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
THE EXPOSE PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO
THE GROUND PLANE.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 97. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
Rev. E | Page 39 of 40
041806-A
TOP
VIEW
32
0.050
0.016
AD8331/AD8332/AD8334
9.00
BSC SQ
0.60 MAX
8.75
BSC SQ
SEATING
PLANE
*4.85
4.70 SQ
4.55
EXPOSED PAD
(BOTTOM VIEW)
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
PIN 1
INDICATOR
1
THE EXPOSE PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO
THE GROUND PLANE.
0.20 REF
031706-A
TOP
VIEW
12° MAX
64
49
48
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.25
0.18
0.60 MAX
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 98. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8331ARQ
AD8331ARQ-REEL
AD8331ARQ-REEL7
AD8331ARQZ 1
AD8331ARQZ-RL1
AD8331ARQZ-R71
AD8331-EVAL
AD8332ACP-R2
AD8332ACP-REEL
AD8332ACP-REEL7
AD8332ACPZ-R71
AD8332ACPZ-RL1
AD8332ARU
AD8332ARU-REEL
AD8332ARU-REEL7
AD8332ARUZ1
AD8332ARUZ-R71
AD8332ARUZ-RL1
AD8332-EVAL
EVAL-AD8332/AD9238
AD8334ACPZ-WP1
AD8334ACPZ-REEL1
AD8334ACPZ-REEL71
AD8334-EVAL
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
20-Lead Shrink Small Outline Package (QSOP)
20-Lead Shrink Small Outline Package (QSOP)
20-Lead Shrink Small Outline Package (QSOP)
20-Lead Shrink Small Outline Package (QSOP)
20-Lead Shrink Small Outline Package (QSOP)
20-Lead Shrink Small Outline Package (QSOP)
Evaluation Board with AD8331ARQ
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
Evaluation Board with AD8332ARU
Evaluation Board with AD8332ARU and AD9238 ADC
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board with AD8334ACP
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03199-0-4/06(E)
Rev. E | Page 40 of 40
Package Option
RQ-20
RQ-20
RQ-20
RQ-20
RQ-20
RQ-20
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
RU-28
RU-28
RU-28
RU-28
RU-28
RU-28
CP-64-1
CP-64-1
CP-64-1
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