a High Speed, Low Power Monolithic Op Amp AD848/AD849 The AD848 and AD849 are high speed, low power monolithic operational amplifiers. The AD848 is internally compensated so that it is stable for closed loop gains of 5 or greater. The AD849 is fully decompensated and is stable at gains greater than 24. The AD848 and AD849 achieve their combination of fast ac and good dc performance by utilizing Analog Devices’ junction isolated complementary bipolar (CB) process. This process enables these op amps to achieve their high speed while only requiring 4.8 mA of current from the power supplies. The AD848 and AD849 are members of Analog Devices’ family of high speed op amps. This family includes, among others, the AD847 which is unity gain stable, with a gain bandwidth of 50 MHz. For more demanding applications, the AD840, AD841 and AD842 offer even greater precision and greater output current drive. The AD848 and AD849 have good dc performance. When operating with ± 5 V supplies, they offer open loop gains of 13 V/mV (AD848 with a 500 Ω load) and low input offset voltage of 1 mV maximum. Common-mode rejection is a minimum of 92 dB. Output voltage swing is ± 3 V even into loads as low as 150 Ω. AD848/49 6 OUTPUT +IN 3 –VS 4 8 NULL 7 +VS –IN 2 TOP VIEW 5 NC (Not to Scale) NC = NO CONNECT OUTPUT NC NC NC V+ 20-Terminal LCC Pinout 18 17 16 15 14 NC 19 13 NC OFFSET 20 NULL NC 1 AD848SE/883B 12 NC TOP VIEW (Not to Scale) 11 NC 2 10 V– 3 9 4 5 6 7 8 NC OFFSET NULL NC NC PRODUCT DESCRIPTION NULL 1 +IN APPLICATIONS Cable Drivers 8- and 10-Bit Data Acquisition Systems Video and RF Amplification Signal Generators Plastic (N), Small Outline (R) and Cerdip (Q) Packages NC DC PERFORMANCE 3 nV/√Hz Input Voltage Noise – AD849 85 V/mV Open Loop Gain into a 1 kV Load – AD849 1 mV max Input Offset Voltage Performance Specified for 65 V and 615 V Operation Available in Plastic, Hermetic Cerdip and Small Outline Packages. Chips and MIL-STD-883B Parts Available. Available in Tape and Reel in Accordance with EIA-481A Standard CONNECTION DIAGRAMS –IN FEATURES 725 MHz Gain Bandwidth – AD849 175 MHz Gain Bandwidth – AD848 4.8 mA Supply Current 300 V/ms Slew Rate 80 ns Settling Time to 0.1% for a 10 V Step – AD849 Differential Gain: AD848 = 0.07%, AD849 = 0.08% Differential Phase: AD848 = 0.088, AD849 = 0.048 Drives Capacitive Loads NC NC = NO CONNECT APPLICATIONS HIGHLIGHTS 1. The high slew rate and fast settling time of the AD848 and AD849 make them ideal for video instrumentation circuitry, low noise pre-amps and line drivers. 2. In order to meet the needs of both video and data acquisition applications, the AD848 and AD849 are optimized and tested for ± 5 V and ± 15 V power supply operation. 3. Both amplifiers offer full power bandwidth greater than 20 MHz (for 2 V p-p with ± 5 V supplies). 4. The AD848 and AD849 remain stable when driving any capacitive load. 5. Laser wafer trimming reduces the input offset voltage to 1 mV maximum on all grades, thus eliminating the need for external offset nulling in many applications. 6. The AD848 is an enhanced replacement for the LM6164 series and can function as a pin-for-pin replacement for many high speed amplifiers such as the HA2520/2/5 and EL2020 in applications where the gain is 5 or greater. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD848/AD849–SPECIFICATIONS (@ T = +258C, unless otherwise noted) A Model Conditions VS TMIN to TMAX ±5 V ± 15 V ±5 V ± 15 V ± 5 V, ± 15 V INPUT OFFSET VOLTAGE1 Offset Drift INPUT BIAS CURRENT TMIN to TMAX INPUT OFFSET CURRENT TMIN to TMAX Offset Current Drift OPEN LOOP GAIN DYNAMIC PERFORMANCE Gain Bandwidth Full Power Bandwidth2 VO = ± 2.5 V RLOAD = 500 Ω TMIN to TMAX RLOAD = 150 Ω VOUT = ± 10 V RLOAD = 1 kΩ TMIN to TMAX AVCL ≥ 5 VO = 2 V p-p, RL = 500 Ω VO = 20 V p-p, RL = 1 kΩ Slew Rate Settling Time to 0.1% Phase Margin RLOAD = 1 kΩ –2.5 V to +2.5 V 10 V Step, AV = –4 CLOAD = 10 pF RLOAD = 1 kΩ Min ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V AD848J Typ Max 0.2 1 0.5 2.3 1.5 3.0 7 3.3 6.6 7.2 50 300 400 0.3 Min AD848A/S Typ Max 0.2 1 0.5 2.3 2 3.5 7 3.3 6.6/5 7.5 50 300 400 0.3 Units mV mV mV mV µV/°C µA µA nA nA nA/°C ±5 V 9 7 13 9 7/5 8 ± 15 V 12 8 13 V/mV V/mV V/mV 8 20 12 8/6 20 V/mV V/mV ±5 V ± 15 V 125 175 125 175 MHz MHz ±5 V 24 24 MHz ± 15 V ±5 V ± 15 V ±5 V ± 15 V ± 15 V 4.7 200 300 65 100 4.7 200 300 65 100 MHz V/µs V/µs ns ns 225 225 60 60 Degrees DIFFERENTIAL GAIN f = 4.4 MHz ± 15 V 0.07 0.07 % DIFFERENTIAL PHASE f = 4.4 MHz ± 15 V 0.08 0.08 Degree COMMON-MODE REJECTION VCM = ± 2.5 V VCM = ± 12 V TMIN to TMAX ±5 V ± 15 V POWER SUPPLY REJECTION VS = ± 4.5 V to ± 18 V TMIN to TMAX INPUT VOLTAGE NOISE f = 10 kHz ± 15 V INPUT CURRENT NOISE f = 10 kHz ± 15 V ±5 V +4.3 –3.4 +14.3 –13.4 INPUT COMMON-MODE VOLTAGE RANGE 92 92 88 105 105 92 92 88 105 105 dB dB dB 85 80 98 85 80 98 dB dB 5 5 nV/√Hz 1.5 1.5 pA/√Hz +4.3 –3.4 +14.3 –13.4 V V V V 3.6 3 1.4 ±V ±V ±V ±V ±V ± 15 V OUTPUT VOLTAGE SWING RLOAD = 500 Ω RLOAD = 150 Ω RLOAD = 50 Ω RLOAD = 1 kΩ RLOAD = 500 Ω ±5 V ±5 V ±5 V ± 15 V ± 15 V 3.0 2.5 3.0 2.5 12 10 ± 15 V SHORT CIRCUIT CURRENT 3.6 3 1.4 12 10 32 32 mA INPUT RESISTANCE 70 70 kΩ INPUT CAPACITANCE 1.5 1.5 pF 15 15 Ω OUTPUT RESISTANCE Open Loop POWER SUPPLY Operating Range Quiescent Current ±5 V TMIN to TMAX ± 15 V TMIN to TMAX 64.5 4.8 5.1 618 6.0 7.4 6.8 8.0 64.5 4.8 5.1 618 6.0 7.4/8.3 6.8 8.0/9.0 V mA mA mA mA NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes at T A = +25°C. 2 Full power bandwidth = slew rate/2 π VPEAK. Refer to Figure 1. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested. Specifications subject to change without notice. –2– REV. B AD848/AD849 Model Conditions VS TMIN to TMAX ±5 V ± 15 V ±5 V ± 15 V ± 5 V, ± 15 V INPUT OFFSET VOLTAGE1 Offset Drift INPUT BIAS CURRENT TMIN to TMAX INPUT OFFSET CURRENT TMIN to TMAX Offset Current Drift OPEN LOOP GAIN DYNAMIC PERFORMANCE Gain Bandwidth Full Power Bandwidth2 VO = ± 2.5 V RLOAD = 500 Ω TMIN to TMAX RLOAD = 150 Ω VOUT = ± 10 V RLOAD = 1 kΩ TMIN to TMAX AVCL ≥ 25 VO = 2 V p-p, RL = 500 Ω VO = 20 V p-p, RL = 1 kΩ Slew Rate Settling Time to 0.1% Phase Margin RLOAD = 1 kΩ –2.5 V to +2.5 V 10 V Step, AV = –24 CLOAD = 10 pF RLOAD = 1 kΩ Min ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V ± 5 V, ± 15 V AD849J Typ Max 0.3 1 0.3 1 1.3 1.3 2 3.3 6.6 7.2 50 300 400 0.3 Min AD849A/S Typ Max 0.1 0.75 0.1 0.75 1.0 1.0 2 3.3 6.6/5 7.5 50 300 400 0.3 Units mV mV mV mV µV/°C µA µA nA nA nA/°C ±5 V 30 20 50 32 ± 15 V 45 30 85 30 50 20/15 32 V/mV V/mV V/mV 45 85 30/25 V/mV V/mV ±5 V ± 15 V 520 725 520 725 MHz MHz ±5 V 20 20 MHz ± 15 V ±5 V ± 15 V ±5 V ± 15 V ± 15 V 4.7 200 300 65 80 4.7 200 300 65 80 MHz V/µs V/µs ns ns 225 225 60 60 Degrees DIFFERENTIAL GAIN f = 4.4 MHz ± 15 V 0.08 0.08 % DIFFERENTIAL PHASE f = 4.4 MHz ± 15 V 0.04 0.04 Degrees COMMON-MODE REJECTION VCM = ± 2.5 V VCM = ± 12 V TMIN to TMAX ±5 V ± 15 V POWER SUPPLY REJECTION VS = ± 4.5 V to ± 18 V TMIN to TMAX INPUT VOLTAGE NOISE f = 10 kHz ± 15 V INPUT CURRENT NOISE f = 10 kHz ± 15 V ±5 V +4.3 –3.4 +14.3 –13.4 INPUT COMMON-MODE VOLTAGE RANGE 100 100 96 115 115 100 100 96 115 115 dB dB dB 98 94 120 98 94 120 dB dB 3 3 nV/√Hz 1.5 1.5 pA/√Hz +4.3 –3.4 +14.3 –13.4 V V V V 3.6 3 1.4 ±V ±V ±V ±V ±V ± 15 V OUTPUT VOLTAGE SWING RLOAD = 500 Ω RLOAD = 150 Ω RLOAD = 50 Ω RLOAD = 1 kΩ RLOAD = 500 Ω ±5 V ±5 V ±5 V ± 15 V ± 15 V 3.0 2.5 INPUT RESISTANCE INPUT CAPACITANCE OUTPUT RESISTANCE Open Loop POWER SUPPLY Operating Range Quiescent Current ±5 V TMIN to TMAX ± 15 V TMIN to TMAX 3.0 2.5 12 10 ± 15 V SHORT CIRCUIT CURRENT 3.6 3 1.4 12 10 32 32 mA 25 25 kΩ 1.5 1.5 pF 15 15 Ω 64.5 4.8 5.1 618 6.0 7.4 6.8 8.0 64.5 4.8 5.1 618 6.0 7.4/8.3 6.8 8.0/9.0 V mA mA mA mA NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes at T A = +25°C. 2 Full power bandwidth = slew rate/2 π VPEAK. Refer to Figure 1. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. All others are guaranteed but not necessarily tested. Specifications subject to change without notice. REV. B –3– AD848/AD849 ABSOLUTE MAXIMUM RATINGS 1 METALIZATION PHOTOGRAPH Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 Watts Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 6 V Storage Temperature Range (Q) . . . . . . . . –65°C to +150°C (N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175°C Lead Temperature Range (Soldering 60 sec) . . . . . . . +300°C Contact factory for latest dimensions. (AD848 and AD849 are identical except for the part number in the upper right.) Dimensions shown in inches and (mm). NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 LCC: θJA = 150°C/Watt Mini-DIP Package: θJA = 110°C/Watt Cerdip Package: θJA = 110°C/Watt Small Outline Package: θJA = 155°C/Watt. ORDERING GUIDE Model Gain Bandwidth MHz Min Stable Gain Max Offset Voltage mV Temperature Range – 8C Package Option1 AD848JN AD848JR2 AD848JCHIPS AD848AQ AD848SQ AD848SQ/883B AD848SE/883B 175 175 175 175 175 175 175 5 5 5 5 5 5 5 1 1 1 1 1 1 1 0 to +70 0 to +70 0 to +70 –40 to +85 –55 to +125 –55 to +125 –55 to +125 N-8 R-8 Die Form Q-8 Q-8 Q-8 E-20A AD849JN AD849JR2 AD849AQ AD849SQ AD849SQ/883B 725 725 725 725 725 25 25 25 25 25 1 1 0.75 0.75 0.75 0 to +70 0 to +70 –40 to +85 –55 to +125 –55 to +125 N-8 R-8 Q-8 Q-8 Q-8 AD847J/A/S 50 1 1 See AD847 Data Sheet NOTES 1 E = LCC; N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC). 2 Plastic SOIC (R) available in tape and reel. AD848 available in S grade chips. AD849 available in J and S grade chips. –4– REV. B AD848/AD849 Figure 1. AD848 Inverting Amplifier Configuration Figure 2. AD849 Inverting Amplifier Configuration Figure 1a. AD848 Large Signal Pulse Response Figure 2a. AD849 Large Signal Pulse Response Figure 1b. AD848 Small Signal Pulse Response Figure 2b. AD849 Small Signal Pulse Response OFFSET NULLING The input voltage of the AD848 and AD849 are very low for high speed op amps, but if additional nulling is required, the circuit shown in Figure 3 can be used. For high performance circuits it is recommended that a resistor (RB in Figures 1 and 2) be used to reduce bias current errors by matching the impedance at each input. The offset voltage error caused by the input currents is decreased by more than an order of magnitude. Figure 3. Offset Nulling REV. B –5– AD848/AD849–Typical Characteristics Figure 4. Quiescent Current vs. Supply Voltage (AD848 and AD849) (@ TA = +258C and VS = 615 V, unless otherwise noted) Figure 5. Large Signal Frequency Response (AD848 and AD849) Figure 6. Output Voltage Swing vs. Load Resistance (AD848 and AD849) Figure 7. Open Loop Gain vs. Load Resistance (AD848) Figure 8. Open Loop Gain vs. Load Resistance (AD849) Figure 9. Output Swing and Error vs. Settling Time (AD848) Figure 10. Quiescent Current vs. Temperature (AD848 and AD849) Figure 11. Short Circuit Current Limit vs. Temperature (AD848 and AD849) Figure 12. Input Bias Current vs. Temperature (AD848 and AD849) –6– REV. B AD848/AD849 Figure 13. Open Loop Gain and Phase Margin vs. Frequency (AD848) Figure 14. Open Loop Gain and Phase Margin vs. Frequency (AD849) Figure 16. Harmonic Distortion vs. Frequency (AD848) Figure 17. Harmonic Distortion vs. Frequency (AD849) Figure 19. Power Supply Rejection vs. Frequency (AD848) Figure 20. Power Supply Rejection vs. Frequency (AD849) REV. B –7– Figure 15. Normalized Gain Bandwidth Product vs. Temperature (AD848 and AD849) Figure 18. Slew Rate vs. Temperature (AD848 and AD849) Figure 21. Common-Mode Rejection vs. Frequency GROUNDING AND BYPASSING In designing practical circuits with the AD848 or AD849, the user must remember that whenever high frequencies are involved, some special precautions are in order. Circuits must be built with short interconnect leads. A large ground plane should be used whenever possible to provide a low resistance, low inductance circuit path, as well as minimizing the effects of high frequency coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth. Feedback resistors should be of low enough value to assure that the time constant formed with the capacitances at the amplifier summing junction will not limit the amplifier performance. Resistor values of less than 5 kΩ are recommended. If a larger resistor must be used, a small (< 10 pF) feedback capacitor in parallel with the feedback resistor, RF, may be used to compensate for the input capacitances and optimize the dynamic performance of the amplifier. Often termination is not used, either because signal integrity requirements are low or because too many high frequency signals returned to ground contaminate the ground plane. Unterminated cables appear as capacitive loads. Since the AD848 and AD849 are stable into any capacitive load, the op amp will not oscillate if the cable is not terminated; however pulse integrity will be degraded. Figure 23 shows the AD848 driving both 100 pF and 1000 pF loads. LOW NOISE PRE-AMP The input voltage noise spectral densities of the AD848 and the AD849 are shown in Figure 24. The low wideband noise and high gain bandwidths of these devices makes them well suited as pre-amps for high frequency systems. C1261b–5–9/90 AD848/AD849–Applications AD848/AD849 Power supply leads should be bypassed to ground as close as possible to the amplifier pins. 0.1 µF ceramic disc capacitors are recommended. VIDEO LINE DRIVER The AD848 functions very well as a low cost, high speed line driver of either terminated or unterminated cables. Figure 22 shows the AD848 driving a doubly terminated cable. A back-termination resistor (RBT, also equal to the characteristic impedance of the cable) may be placed between the AD848 output and the cable in order to damp any reflected signals caused by a mismatch between RT and the cable’s characteristic impedance. This will result in a “cleaner” signal, although it requires that the op amp supply ± 2 V to the output in order to achieve a ± 1 V swing at the line. Figure 24. Input Voltage Noise Spectral Density Input voltage noise will be the dominant source of noise at the output in most applications. Other noise sources can be minimized by keeping resistor values as small as possible. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP (N) Package Cerdip (Q) Package PRINTED IN U.S.A. The termination resistor, RT, (when equal to the characteristic impedance of the cable) minimizes reflections from the far end of the cable. While operating off ± 5 V supplies, the AD848 maintains a typical slew rate of 200 V/µs, which means it can drive a ± 1 V, 24 MHz signal on the terminated cable. Figure 22. Video Line Driver 100pF LOAD Small Outline (R) Package 1000pF LOAD Figure 23. AD848 Driving a Capacitive Load –8– REV. B