AD AD9066JR Dual 6-bit, 60 msps monolithic a/d converter Datasheet

a
FEATURES
Two Matched ADCs on Single Chip
CMOS-Compatible I/O
Low-Power (400 mW) Dissipation
Single +5 V Supply
On-Chip Voltage Reference
Self-Biased for AC-Coupled Inputs
28-Lead SOIC and SSOP Packages
APPLICATIONS
Direct Broadcast Satellite (DBS) Receivers
QAM Demodulators
Wireless LANs
VSAT Receivers
PRODUCT DESCRIPTION
The AD9066 is a dual 6-bit ADC that has been optimized for
low-cost in-phase and quadrature (I and Q) demodulators.
Primary applications include digital direct broadcast satellite
applications where broadband quadrature phase shift keying
(QPSK) modulation is used. In these receivers the recovered signal
is separated into I and Q vector components and digitized.
To reduce total system cost and power dissipation, the AD9066
provides an internal voltage reference and operates from a
single +5 volt power supply. Digital outputs are CMOS compatible and rated to 60 MSPS conversion rates. The digital
input (ENCODE) utilizes a CMOS input stage with a TTL
compatible (1.4 V) threshold.
The AD9066 is housed in a 28-lead SOIC and a 28-lead SSOP
package and is available in two temperature grades. The
AD9066JR is rated for operation over the 0°C to 70°C commercial temperature range. The AD9066AR/ARS is rated for the
–40°C to +85°C industrial temperature range.
The internal voltage reference insures that the analog input is
biased to midscale with low offset when driven from an accoupled source. In dc-coupled applications, the midscale voltage
reference can be used to control external biasing amplifiers to
minimize offsets due to variations in temperature or supply voltage.
Dual 6-Bit, 60 MSPS
Monolithic A/D Converter
AD9066
FUNCTIONAL BLOCK DIAGRAM
+VS
AD9066
VT
INA
6-BIT
DAC
D0A-D5A
6-BIT
DAC
D0B-D5B
REF A
ENCODE
INB
REF B
VB
PIN CONFIGURATIONS
ENCODE 1
28 D5A (MSB)
+VS 2
27 D4A
GND 3
26 D3A
GND 4
25 D2A
+VS 5
INA 6
24 D1A
AD9066
(JR/AR)
23 D0A (LSB)
GND 7
TOP VIEW 22 GND
+VS 8 (Not to Scale) 21 +VS
VT 9
20 D5B (MSB)
REF A 10
19 D4B
INB 11
18 D3B
REF B 12
17 D2B
VB 13
16 D1B
NC 14
15 D0B (LSB)
NC = NO CONNECT
+VS 1
28
GND
VT 2
27
INA
REF A 3
26
+VS
INB 4
25
GND
24
GND
REF B 5
AD9066
+VS
(ARS)
TOP VIEW 22 ENCODE
(LSB) D0B 8 (Not to Scale) 21 D5A (MSB)
VB 6
23
NC 7
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
D1B 9
20
D4A
D2B 10
19
D3A
D3B 11
18
D2A
D4B 12
17
D1A
(MSB) D5B 13
16
D0A (LSB)
+VS 14
15
GND
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9066–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, T
S
Parameter
Test
Level
Temp
Min
ANALOG INPUT
Full-Scale Input Range
Gain Matching (FS Range)
DC Input (Midscale)1
Input Offset1
Input Capacitance
Input Resistance (DC)
Input Bandwidth (3 dB)
Gain Flatness (to 15 MHz)
Integral Linearity
Differential Linearity
Monotonicity
VI
IV
V
VI
IV
VI
V
V
VI
VI
VI
Full
Full
+25°C
Full
Full
Full
+25°C
+25°C
Full
Full
Full
475
SWITCHING PERFORMANCE
Max Conversion Rate
Output Delay (tV)2
Output Delay (tPD)2
Aperture Uncertainty (Jitter)
Aperture Time (tA)
VI
IV
IV
V
V
Full
Full
Full
+25°C
+25°C
60
4
DYNAMIC PERFORMANCE3
Effective Number of Bits
SINAD
Harmonic Distortion (THD)
Crosstalk Rejection
VI
VI
VI
IV
+25°C
+25°C
+25°C
+25°C
5.3
34
40
40
ENCODE INPUT
Logic High Voltage
Logic Low Voltage
Input High Current
Input Low Current
Pulsewidth High
Pulsewidth Low
VI
VI
VI
VI
IV
IV
Full
Full
Full
Full
Full
Full
2.0
DIGITAL OUTPUTS
Output Coding
Logic High Voltage (IOH = 1 mA)
Logic Low Voltage (IOL = 1 mA)
VI
VI
Full
Full
Full
POWER SUPPLY
+VS Supply Voltage
Power Supply Rejection Ratio1
+VS Supply Current
Power Dissipation4
VI
IV
VI
VI
Full
Full
Full
Full
AD9066JR
Typ
500
Max
Min
525
16
450
+1.0
15
55
–1.0
+1.0
+0.5
–1.0
–0.5
+VS – 1.1
–1.0
25
10
45
100
0.25
–1.0
–0.5
C
= T A)
AD9066AR/ARS
Typ
Max
500
530
16
+VS – 1.1
22
Guaranteed
10
45
100
0.25
+1.0
15
57
+1.0
+0.5
10
1.0
MSPS
ns
ns
ps rms
ns
5.7
36
50
50
Bits
dB
dB
dBc
11
12
10
1.0
5.7
36
50
50
5.2
33
40
40
2.0
0.8
500
500
7.0
7.0
0.8
500
500
7.0
7.0
Offset Binary
V
V
µA
µA
ns
ns
Offset Binary
3.8
3.8
0.4
110
80
400
mV
mV
V
LSBs
pF
kΩ
MHz
dB
LSBs
LSBs
Guaranteed
60
4
4.75
Unit
5.25
130
120
600
4.75
110
80
400
0.4
V
V
5.25
130
120
600
V
mV/V
mA
mW
NOTES
1
For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.
2
tV and tPD are measured from the 1.4 V level of the Clock and the 50% level between VOH and VOL. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed ± 40 µA.
3
Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.
4
Typical thermal impedance for the “R” style (SOIC) 28-lead package is: θJC = 4°C/W, θCA = 41°C/W, θJA = 45°C/W, and the “RS” style (SSOP) 28-lead package is:
θJC = 26.97°C/W, θCA = 51.61°C/W, θJA = 78.58°C/W.
Specifications subject to change without notice.
–2–
REV. A
AD9066
PIN DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS
Pin
Min
Max
Unit
ENCODE
+VS
INA, INB
VT
REF A, REF B
VB
D0–D5 Current OUT
–0.5
+VS
7.0
+VS
+VS
+VS
+VS
20
V
V
V
V
V
V
mA
–0.5
2.5
–0.5
0.0
AR:JR ARS
Pin
Pin
No.
No. Name
EXPLANATION OF TEST LEVELS
Test Level
Description
I
II
100% Production Tested
100% Production Tested at +25°C, and
Sample Tested at Specified Temperatures
Sample Tested Only
Parameter Is Guaranteed by Design
Parameter Is Typical Value Only
100% Tested at +25°C
III
IV
V
VI
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . . 132 × 68 × 21 (± 1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,810
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
ORDERING GUIDE
Model
Temperature Range
Package Option*
AD9066AR
AD9066JR
AD9066ARS
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
R-28
R-28
RS-28
*R = “SO” Small Outline Package; RS = SSOP.
1
22
ENCODE
2
3
4
5
6
7
8
9
23
24
25
26
27
28
1
2
+VS
GND
GND
+VS
INA
GND
+VS
VT
10
3
REF A
11
12
4
5
INB
REF B
13
6
VB
14
15
7
8
NC
D0B (LSB)
16
17
18
19
20
21
22
23
9
10
11
12
13
14
15
16
24
25
26
27
28
17
18
19
20
21
D1B
D2B
D3B
D4B
D5B (MSB)
+VS
+5 V Supply for Digital Outputs.
GND
Ground.
D0A (LSB) Digital Outputs Channel A,
CMOS Compatible.
D1A
D2A
D3A
D4A
D5A (MSB)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9066 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
Function
TTL Compatible CMOS Clock,
Samples on Rising Edge.
+5 V Supply for Digital Input.
Ground.
Ground.
+5 V Supply (Analog).
Channel A Analog Input.
Ground.
+5 V Supply (Analog).
Top of Voltage Reference, Bypass
to GND.
Mid Reference to ADC A, Bypass
to GND.
Channel B Analog Input.
Mid Reference to ADC B, Bypass
to GND.
Bottom of Reference Ladder, Bypass to GND.
No Connect.
Digital Outputs Channel B,
CMOS Compatible.
WARNING!
ESD SENSITIVE DEVICE
AD9066
Gain Variation
5.8
The full-scale input range is established by the current through
the two matched resistor ladders (620 ohms each nominal). Therefore the gain of the ADC may be modified by forcing different
voltages across the top and bottom voltage taps (VT and VB).
ENCODE = 60MSPS
5.7
ENOB – Bits
5.6
The easiest way to increase the input range will be to force VB
to a lower voltage. Using an external amplifier, the voltage at VB
may be forced as low as 3.0 V (3.58 nominal). Using the previously described relationship for full scale and the internal
resistor ladder values, 3.0 V at VB will result in a nominal fullscale input range of 705 mV.
5.5
5.4
5.3
A larger input range can be established by taking the VT voltage
all the way to the supply voltage level while pulling VB to 3.0 V.
This would force a 2 V potential across the ladder and create a
full-scale input range of 1.6 V.
5.2
1
10
MHz
100
Figure 1. ENOB vs. Analog Input Frequency
Greater flexibility and improved power supply rejection can be
achieved by forcing external voltage references at both the top
and bottom of the resistor ladder.
5.8
ANALOG INPUT = 10.1MHz
111111
5.7
2n –2 = 62
ENOB – Bits
5.6
100000
5.5
011111
5.4
5.3
000001
000000
5.2
10
100
–FULL-SCALE
MHz
MIDSCALE
+FULL-SCALE
Figure 3.
Figure 2. ENOB vs. Encode Rate
USING THE AD9066
Analog Input and Voltage References
+VS = 5V
400⍀
The AD9066 is optimized to allow ac coupled inputs with a fullscale input range of 500 mV ± 5%. An LSB weight is approximately 8 mV. The full-scale input range is defined as the voltage
range that accommodates 2n – 2 codes of equally weighted LSBs
(between the first and last code transitions). For the AD9066
there are 32 codes above and below the midscale voltage of the
A see Figure 3).
VS
VT
40k⍀
310⍀ 310⍀
40k⍀
REF B
REF A
INPUT
310⍀ 310⍀
VB
2mA
The full-scale input range of the AD9066 is equal to 500/620 ×
(VT – VB), or nominally 500 mV. For dc coupled applications,
the REF A and REF B voltages can be used to feed back offset
compensation signals. This will allow the midscale transition
voltage of the ADCs to track supply and temperature variations.
a. Reference Circuit
1.4V THRESHOLD
b. Encode Input
VS
VS
In the event that offset correction signals are generated digitally,
the REF pins would not be required. Figure 4a shows the
equivalent circuit for the internal references. All component
tolerances are ± 25%.
OUTPUTS
40k⍀
REF
c. Output Bits
d. Analog Input
Figure 4. Equivalent Circuits
–4–
REV. A
AD9066
Timing
ENCODE
866⍀
The duty cycle of the encode clock for the AD9066 is critical in
obtaining rated performance of the ADC. Rated maximum and
minimum pulse widths should be maintained, especially for
sample rates greater than 40 MSPS.
6 BITS
866⍀
The AD9066 provides latched data outputs with three pipeline
delays. The length and load on the output data lines should be
minimized to reduce power supply transients inside the AD9066
which might diminish dynamic performance.
2k⍀
866⍀
N
6 BITS
tA
N+1
+15V
866⍀
INB
1/2
AD812
+
ENCODE
–15V
tV
VALID DATA
FOR N–3
tPD
VALID DATA
FOR N–2
Figure 6. Bipolar Input Using AD812 Drive for AD9066
VALID DATA
FOR N–1
Layout should follow high frequency/high speed design guidelines. In addition the capacitance around the inverting input to
the AD812 should be minimized through a tight layout and the
use of low capacitance chip resistors for gain setting.
DATA
CHANGING
Figure 5. Timing Diagram
Quadrature Receiver Using the AD9066
The data is invalid during the period between tV and tPD. This
period refers to the time required for the AD9066 to fully switch
between valid CMOS logic levels. When latching the output
data, be careful to observe latch setup and hold time restrictions
as well as this data invalid period when designing the system
timing.
Although any type of input signal may be applied, the AD9066
has been optimized for low cost in-phase and quadrature (I and
Q) demodulators. Primary applications include digital direct
broadcast satellite applications where broadband quadrature
phase shift keying (QPSK) modulation is used. In these receivers
the recovered signal is separated into I and Q vector components
and digitized.
Layout and Signal Care
To insure optimum performance, a single low impedance
ground plane is recommended. Analog and digital grounds
should be connected together at the AD9066. Analog and digital power supplies should be bypassed, at the device, to ground
through 0.1 µF ceramic capacitors.
AD9066
IF IN
Driving the AD9066 with a Bipolar Input
VCO
The analog input range of the AD9066 is between 3.7 V and
4.2 V. Because the input is offset, the normal method of driving
the analog input is to use a blocking capacitor between the analog source and the AD9066 analog input pins. In applications
where DC coupling must be employed, the simple circuit shown
in Figure 6 will take a bipolar input and offset it to the operating
range of the AD9066.
LPF
ADC
LPF
ADC
90ⴗ
The use of sockets may limit the dynamic performance of the
part and is not recommended except for prototype or evaluation
purposes.
VCO
Figure 7. Simplified Block Diagram
For data symbol rates less than 10 Mbaud, the AD607 IF/RF
receiver subsystem provides an ideal solution for the second
conversion stage of a complete receiver system. Figure 8 shows
the AD9066 and AD607 used together.
The AD607 accepts inputs as high as 500 MHz which may be
the output of the first IF stage or RF signals directly. The IF/RF
signal is mixed with the local oscillator to provide an IF frequency of 400 kHz to 22 MHz. This signal is filtered externally
and then amplified with an on-chip AGC before being synchronously demodulated with an on-chip PLL carrier recovery
circuit. The outputs are digitized with the AD9066. The digital
outputs may be processed with a DSP chip such as the ADSP2171, ADSP-21062, general purpose DSP or ASIC.
To offset the input, the midpoint voltage of the AD9066 is buffered off chip and then inverted with an AD712, a low input bias
current dual op amp. This inverted midpoint is then fed to a
summation amplifier that combines the bipolar input with the
inverted offset voltage. The summation amplifier is an AD812, a
wideband current feedback amplifier that provides good bandwidth and low distortion.
REV. A
REF A
OR REF B
+
1/2
AD712
N+2
D0–D5
AD9066
1/2
AD712
2k⍀
866⍀
866⍀
ANALOG
INPUT
1/2
AD812
+
+
INA
–5–
AD9066
CLOCK
LOCAL
OSCILLATOR
1
CLKIN
–16dBM
6
10⍀
VMID
VINA
0ⴗ
+
BANDPASS
FILTER
RF INPUT
(ANTENNA)
+
OPTIONAL
BPF
OR LPF
330⍀
330⍀
100nF
10⍀
4.7␮F
MIDPOINT
BIAS
GENERATOR
90ⴗ
VINB
20
19
18
17
16
15
B OUTPUTS
(QUADRATURE)
AGC
DETECTOR
AGC VOLTAGE
AD607
A OUTPUTS
(INPHASE)
AD9066
PLL
11
100nF
28
27
26
25
24
23
BIAS
CIRCUIT
RECEIVED SIGNAL
STRENGTH INDICATOR
PTAT
VOLTAGE
Figure 8. Digitizer with AD607 Receiver Circuit
The outputs of the comparators are converted to a 6-bit word
and converted to CMOS levels. The digital signals are latched at
six stages (two pipeline delays) in the signal path. The digital
outputs are CMOS with approximately equal rise and fall times.
Theory of Operation
The AD9066 dual ADC employs a patented interpolated flash
architecture. This architecture enables 64 possible quantization
levels with only 32 comparator preamplifiers. This keeps input
capacitance to a minimum. The midpoint of the reference ladder is fed back to the analog input, allowing easy biasing of the
ADC to midscale for ac coupled applications.
The encode clock utilizes a CMOS input stage with TTLcompatible (1.4 V) thresholds. Internal clock buffers minimize
external clock drive requirements.
As shown in Figure 4d, a simple resistor is used to provide the
reference ladder midpoint to the analog input. The high impedance MOS inputs of the comparators insure no static voltage
drop across the resistor. This eliminates the need for an active
buffer (and its inherent offsets) to set the reference midpoint at
the analog input.
–6–
REV. A
AD9066
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
1
0.4193 (10.65)
0.3937 (10.00)
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
8ⴗ
0ⴗ
0.0192 (0.49) SEATING
0.0125 (0.32)
PLANE
0.0138 (0.35)
0.0091 (0.23)
0.0291 (0.74)
ⴛ 45ⴗ
0.0098 (0.25)
C2019–0–6/00 (rev. A) 00566
28-Lead Small Outline Package
(R-28)
0.0500 (1.27)
0.0157 (0.40)
28-Lead SSOP
(RS-28)
0.407 (10.34)
0.397 (10.08)
15
1
14
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
28
0.078 (1.98) PIN 1
0.068 (1.73)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25)
PLANE
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
PRINTED IN U.S.A.
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
0.07 (1.79)
0.066 (1.67)
REV. A
–7–