16-Bit, 200 MSPS/500 MSPS TxDAC+® with 2×/4×/8× Interpolation and Signal Processing AD9786 FEATURES PRODUCT HIGHLIGHTS 16-bit resolution, 200 MSPS input data rate IMD 90 dBc @10 MHz Noise spectral density (NSD): −164 dBm/Hz @ 10 MHz WCDMA ACLR = 80 dBc @ 40 MHz IF DNL = ±0.3 LSB INL = ±0.6 LSB Selectable 2×/4×/8× interpolation filters Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes Single- or dual-channel signal processing Selectable image rejection Hilbert transform Flexible calibration engine Direct IF transmission features Serial control interface Versatile clock and data interface 3.3 V-compatible digital interface On-chip 1.2 V reference 80-lead, thermally enhanced, TQFP_EP package 1. 16-bit, high speed, interpolating TxDAC+. 2. 2×/4×/8× user-selectable interpolating filter. The filter eases data rate and output signal reconstruction filter requirements. 3. 200 MSPS input data rate. 4. Ultra high speed, 500 MSPS DAC conversion rate. 5. Flexible clock with single-ended or differential input. CMOS, 1 V p-p sine wave, and LVPECL capability. 6. Complete CMOS DAC function. It operates from a 3.1 V to 3.5 V single analog (AVDD) supply, 2.5 V digital supply, and a 3.3 V digital (DRVDD) supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 7. On-chip voltage reference. The AD9786 includes a 1.20 V temperature-compensated band gap voltage reference. 8. Multichip synchronization. Multiple AD9786 DACs can be synchronized to a single master AD9786 to ease timing design requirements and optimize image reject transmit performance. APPLICATIONS Base stations: multicarrier WCDMA, GSM/EDGE, TD-SCDMA, IS136, TETRA Instrumentation RF signal generators, arbitrary waveform generators HDTV transmitters Broadband wireless systems Digital radio links Satellite systems 2× 2× 2× 0 fDAC/2 fDAC/4 fDAC/8 0 90 CLK– DATA PORT SYNCHRONIZER 16-BIT DAC REFIO IOUTA IOUTB 90 Q 2× 2× CSB SCLK ×1 LATCH SDO HILBERT RESET 2× CLOCK DISTRIBUTION AND CONTROL 03152-001 CLK+ ZERO STUFF FSADJ SDIO 0 DATACLK Δt SPI P2B[15:0] DATA ASSEMBLER P1B[15:0] 90 Re()/Im() I REFERENCE CIRCUITS LATCH CALIBRATION FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9786 TABLE OF CONTENTS Features .............................................................................................. 1 General Operation of the Serial Interface............................... 20 Applications....................................................................................... 1 Serial Interface Port Pin Descriptions ..................................... 20 Product Highlights ........................................................................... 1 MSB/LSB Transfers .................................................................... 21 Functional Block Diagram .............................................................. 1 Notes on Serial Port Operation ................................................ 21 Revision History ............................................................................... 3 Mode Control (via Serial Port) ..................................................... 22 General Description ......................................................................... 4 Digital Filter Specifications ........................................................... 26 Specifications..................................................................................... 5 Digital Interpolation Filter Coefficients.................................. 26 DC Specifications ......................................................................... 5 Clock/Data Timing .................................................................... 27 Dynamic Specifications ............................................................... 6 Real and Complex Signals......................................................... 32 Digital Specifications ................................................................... 7 Modulation Modes..................................................................... 33 Absolute Maximum Ratings............................................................ 8 Power Dissipation....................................................................... 38 Thermal Resistance ...................................................................... 8 Hilbert Transform Implementation......................................... 40 ESD Caution.................................................................................. 8 Operating the AD9786 Rev. F Evaluation Board ....................... 44 Pin Configuration and Function Descriptions............................. 9 Power Supplies ............................................................................ 44 Clock .............................................................................................. 9 PECL Clock Driver .................................................................... 44 Analog.......................................................................................... 10 Data Inputs.................................................................................. 45 Data .............................................................................................. 10 Serial Port .................................................................................... 45 Serial Interface ............................................................................ 11 Analog Output ............................................................................ 45 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 55 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 55 Serial Control Interface.................................................................. 20 Rev. B | Page 2 of 56 AD9786 REVISION HISTORY 10/05—Rev. A to Rev. B Updated Format.................................................................. Universal Changes to Figure 1...........................................................................1 Changes to Table 2 ............................................................................6 Changes to Table 3 ............................................................................7 Changes to External Sync Mode Section .....................................31 Updated Outline Dimensions........................................................58 Changes to Ordering Guide...........................................................58 2/05—Rev. 0 to Rev. A Changed DRVDD Supply Range...................................... Universal Changes to DC Specifications .........................................................4 Changes to Dynamic Specifications ...............................................5 Changes to Digital Specifications....................................................6 Changes to Absolute Maximum Ratings........................................7 Change to Figure 2 ............................................................................8 Replaced Figure 13 ..........................................................................14 Replaced Figure 14 ..........................................................................14 Replaced Figure 16 ..........................................................................15 Replaced Figure 21 ..........................................................................16 Replaced Figure 22 ..........................................................................16 Replaced Figure 26..........................................................................16 Replaced Figure 27..........................................................................17 Changes to Table 15 ........................................................................22 Change to Figure 44........................................................................26 Replaced Figure 45..........................................................................26 Change to Figure 47........................................................................27 Change to Figure 48........................................................................27 Change to Figure 51........................................................................29 Change to Figure 52........................................................................29 Change to Figure 53........................................................................30 Change to DATAADJUST Synchronization Section..................31 Changes to Power Dissipation Section.........................................40 Changes to Table 37 ........................................................................42 Changes to Data Inputs Section ....................................................46 Change to Figure 88........................................................................49 Replaced Figure 95..........................................................................55 Updated Outline Dimensions........................................................60 Changes to Ordering Guide...........................................................60 7/04—Revision 0: Initial Version Rev. B | Page 3 of 56 AD9786 GENERAL DESCRIPTION The AD9786 is a 16-bit, high speed, CMOS DAC with 2×/4×/8× interpolation and signal processing features tuned for communications applications. It offers state-of-the-art distortion and noise performance. The AD9786 was developed to meet the demanding performance requirements of multicarrier and third-generation base stations. The selectable interpolation filters simplify interfacing to a variety of input data rates while also taking advantage of oversampling performance gains. The modulation modes allow convenient bandwidth placement and selectable sideband suppression. The flexible clock interface accepts a variety of input types such as 1 V p-p sine wave, CMOS, and LVPECL in single-ended or differential mode. Internal dividers generate the required data rate interface clocks. The AD9786 provides a differential current output, supporting single-ended or differential applications; it provides a nominal full-scale current from 10 mA to 20 mA. The AD9786 is manufactured on an advanced, low cost, 0.25 μm CMOS process. Rev. B | Page 4 of 56 AD9786 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION DC Accuracy1 Integral Nonlinearity Differential Nonlinearity ANALOG OUTPUT Offset Error Gain Error (with Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (External Reference Mode) Small Signal Bandwith TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (with Internal Reference) Reference Voltage Drift POWER SUPPLY AVDD1, AVDD2 Voltage Range Analog Supply Current (IAVDD1 + IAVDD2) IAVDD1 + IAVDD2 in Sleep Mode ACVDD, ADVDD Voltage Range Analog Supply Current (IACVDD + IADVDD) CLKVDD Voltage Range Clock Supply Current (ICLKVDD) DVDD Voltage Range Digital Supply Current (IDVDD) DRVDD Voltage Range Digital Supply Current (IDRVDD) Nominal Power Dissipation4 OPERATING RANGE Min Typ 16 Max ±0.6 ±0.3 ±0.015 ±1.5 10 –1.0 LSB LSB ±0.0175 20 +1.0 10 1.15 1.23 1 V μA 1.25 10 200 V MΩ kHz 0 ±4 ±30 ppm of FSR/°C ppm of FSR/°C ppm/°C 3.1 3.3 50 18 3.5 V mA mA 2.35 2.5 2.5 2.65 V mA 2.35 2.5 12 2.65 V mA 2.35 2.5 52.5 2.65 V mA 3.1 3.3 5.3 1.25 3.5 V μA W °C –40 Measured at IOUTA driving a virtual ground. Nominal full-scale current, IOUTFS, is 32× the IREF current. 3 Use an external amplifier to drive any external load. 4 Measured under the following conditions: fDATA = 125 MSPS, fDAC = 500 MSPS, 4× interpolation, fDAC/4 modulation, Hilbert off. 2 Rev. B | Page 5 of 56 % of FSR % of FSR mA V MΩ 1.30 0.1 1 Unit Bits +85 AD9786 DYNAMIC SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Minimum DAC Output Update Rate Maximum DAC Output Update Rate (fDAC) AC LINEARITY/BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 100 MSPS; fOUT = 5 MHz, 4×, 2× Interpolation fDATA = 200 MSPS; fOUT = 10 MHz fDATA = 200 MSPS; fOUT = 25 MHz fDATA = 200 MSPS; fOUT = 50 MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = –6 dBFS) fDATA = 200 MSPS; fOUT1 = 5 MHz; fOUT2 = 6 MHz fDATA = 200 MSPS; fOUT1 = 15 MHz; fOUT2 = 16 MHz fDATA = 200 MSPS; fOUT1 = 25 MHz; fOUT2 = 26 MHz fDATA = 200 MSPS; fOUT1 = 45 MHz; fOUT2 = 46 MHz fDATA = 200 MSPS; fOUT1 = 65 MHz; fOUT2 = 66 MHz fDATA = 200 MSPS; fOUT1 = 85 MHz; fOUT2 = 86 MHz Noise Power Spectral Density (NPSD) fDATA = 156 MSPS; fOUT = 10 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz fDATA = 156 MSPS; fOUT = 50 MHz; 0 dBFS, 8 Tones, Separation = 500 kHz Adjacent Channel Power Ratio (ACLR) WCDMA ACLR with 3.84 MHz BW, Single Carrier IF = 21 MHz, fDATA = 122.88 MSPS, 4× Interpolation IF = 224.76 MHz, fDATA = 122.88 MSPS, 4× Interpolation, High-Pass Interpolation Filter Mode Rev. B | Page 6 of 56 Min Typ 500 Max Unit 20 MHz MSPS 93 85 78 78 dBc dBc dBc dBc 85 85 84 80 78 75 dBc dBc dBc dBc dBc dBc −164 −161 dBm/Hz dBm/Hz 80 72 dB dB AD9786 DIGITAL SPECIFICATIONS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Input Capacitance CLOCK INPUTS1 Input Voltage Range Common-Mode Voltage Differential Voltage Latch Pulse Width (tLPW) Data Setup Time to DACCLK Out in Master Mode (tS) Data Hold Time to DACCLK Out in Master Mode (tH) 1 Min Typ Max Unit 0 0.9 +10 +10 V V μA μA pF 1.6 –10 –10 5 0 0.75 0.5 5 −0.5 2.9 See the Clock/Data Timing section for setup and hold times in various timing modes. Rev. B | Page 7 of 56 1.5 1.5 2.65 2.25 V V V ns ns ns AD9786 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD1, AVDD2, DRVDD ACVDD, ADVDD, CLKVDD, DVDD AGND1, AGND2, ACGND, ADGND, CLKGND, DGND REFIO, FSADJ IOUTA, IOUTB P1B15 to P1B0, P2B15 to P2B0, RESET DATACLK CLK+, CLK− CSB, SCLK, SDIO, SDO Junction Temperature Range Storage Temperature Lead Temperature (10 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. With Respect to AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1, AGND2, ACGND, ADGND, CLKGND, DGND AGND1 AGND1 DGND Rating −0.3 V to +3.6 V −0.3 to AVDD1 + 0.3 −1.0 to AVDD1 +0.3 −0.3 to DRVDD + 0.3 DGND CLKGND DGND −0.3 to DRVDD + 0.3 −0.3 to CLKVDD + 0.3 −0.3 to DRVDD + 0.3 −0.3 V to +2.8 V −0.3 V to +0.3 V THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type1 80-lead TQFP_EP (Thermally Enhanced) ` 1 With thermal pad soldered to PCB. −65°C to +125°C 150°C 300°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 8 of 56 θJA 23.5 Unit °C/W AD9786 DNC ADVDD ADGND ACVDD ACGND AVDD2 AVDD1 AGND2 AGND1 IOUTA IOUTB AGND1 AVDD1 AGND2 AVDD2 ACGND ADGND ACVDD ADVDD DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 CLKVDD 1 DNC 2 60 FSADJ PIN 1 IDENTIFIER 59 REFIO CLKVDD 3 58 RESET CLKGND 4 57 CSB CLK+ 5 56 SCLK CLK– 6 55 SDIO 54 SDO CLKGND 7 53 DGND DGND 8 DVDD 9 52 DVDD AD9786 P1B15 10 51 P2B0 TOP VIEW (Not to Scale) P1B14 11 50 P2B1 P1B13 12 49 P2B2 P1B12 13 48 P2B3 P1B11 14 47 P2B4 P1B10 15 46 P2B5 DGND 16 45 DGND DVDD 17 44 DVDD P1B9 18 P1B8 19 43 P2B6 42 P2B7 P1B7 20 41 P2B8 03152-002 P2B10 P2B9 P2B11 P2B12 DGND DVDD IQSEL/P2B15 ONEPORTCLOCK/P2B14 P2B13 DRVDD DATACLK P1B0 P1B2 P1B1 DVDD DGND P1B3 P1B4 P1B5 DNC = DO NOT CONNECT P1B6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 2. Pin Configuration CLOCK Table 6. Clock Pin Function Descriptions Pin No. 5, 6 2 31 Mnemonic CLK+, CLK– DNC DATACLK 1, 3 4, 7 CLKVDD CLKGND Direction I I/O Description Differential Clock Input. Do Not Connect. DCLKEXT 0x02[3] Mode 0 Pin configured for input of channel data rate or synchronizer clock. Internal clock synchronizer can be turned on or off with DCLKCRC (0x02[2]). 1 Pin configured for output of channel data rate or synchronizer clock. Clock Domain 2.5 V. Clock Domain 0 V. Rev. B | Page 9 of 56 AD9786 ANALOG Table 7. Analog Pin Function Descriptions Pin No. 59 60 70, 71 61 62, 79 63, 78 64, 77 65, 76 66, 75 67, 74 68, 73 69, 72 80 Mnemonic REFIO FSADJ IOUTB, IOUTA DNC ADVDD ADGND ACVDD ACGND AVDD2 AGND2 AVDD1 AGND1 DNC Direction A A A Description Reference. Full-Scale Adjust. Differential DAC Output Currents. Do Not Connect. Analog Domain Digital Content 2.5 V. Analog Domain Digital Content 0 V. Analog Domain Clock Content 2.5 V. Analog Domain Clock Content 0 V. Analog Domain Clock Switching 3.3 V. Analog Domain Switching 0 V. Analog Domain Quiet 3.3 V. Analog Domain Quiet 0 V. Do Not Connect. DATA Table 8. Data Pin Function Descriptions Pin No. 10 to 15, 18 to 24, 27 to 29 Mnemonic P1B15 to P1B0 Direction I 32 IQSEL/P2B15 I 33 ONEPORTCLOCK/P2B14 I/O 34, 37 to 43, 46 to 51 30 9, 17, 26, 36, 44, 52 8, 16, 25, 35, 45, 53 P2B13 to P2B0 I Description Input Data Port 1. ONEPORT 0x02[6] Mode 0 Latched data routed for I channel processing. 1 Latched data demultiplexed by IQSEL and routed for interleaved I/Q processing. ONEPORT IQPOL IQSEL/ 0x02[6] 0x02[1] P2B15 Mode (IQPOL = 0) 0 X X Latched data routed to Q channel Bit 15 (MSB) processing. 1 0 0 Latched data on Data Port 1 routed to Q channel processing. 1 0 1 Latched data on Data Port 1 routed to I channel processing. 1 1 0 Latched data on Data Port 1 routed to I channel processing. 1 1 1 Latched data on Data Port 1 routed to Q channel processing. ONEPORT 0x02[6] 0 Latched data routed for Q channel Bit 14 processing. 1 Pin configured for output of clock at twice the channel data route. Input Data Port 2, Bit 13 to Bit 0. DRVDD DVDD Digital Output Pin Supply, 3.3 V. Digital Domain, 2.5 V. DGND Digital Domain, 0 V. Rev. B | Page 10 of 56 AD9786 SERIAL INTERFACE Table 9. Serial Interface Pin Function Descriptions Pin No. 54 Mnemonic SDO Direction O 55 SDIO I/O 56 57 58 SCLK CSB RESET I I I Description SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 High impedance. SDIODIR CSB 0x00[7] Mode 1 X High impedance. 0 0 Serial data output. 0 1 Serial data input/output depending on Bit 7 of the serial instruction byte. Serial Interface Clock. Serial Interface Chip Select. Resets entire chip to default state. Rev. B | Page 11 of 56 AD9786 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-sec. Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Spurious-Free Dynamic Range (SFDR) The difference between the rms amplitude of the output signal and the amplitude of the peak spurious signal over the specified bandwidth. The units are often in dBc (dB with respect to the carrier). Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1, minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that would typically appear around fDAC (output data rate) can be greatly suppressed. Pass Band Frequency band in which any input applied therein passes unattenuated to the DAC output. Stop-Band Rejection The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band. Rev. B | Page 12 of 56 AD9786 Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. A half-band FIR filter has constant group delay over its entire frequency range Impulse Response Response of the device to an impulse applied to the input. Adjacent Channel Leakage Ratio (ACLR) A ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Modulation The process of passing the real and imaginary components of a signal through a complex modulator (transfer function = ejwt = coswt + jsinwt) and realizing real and imaginary components on the modulator output. Hilbert Transform A function with unity gain over all frequencies, but with a phase shift of 90° for negative frequencies and a phase shift of –90° for positive frequencies. Although this function cannot be implemented ideally, it can be approximated with a short FIR filter with enough accuracy to be very useful in single sideband radio architectures. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images are redundant and have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. B | Page 13 of 56 AD9786 TYPICAL PERFORMANCE CHARACTERISTICS TMIN to TMAX; AVDD1, AVDD2, DRVDD = 3.3 V; ACVDD, ADVDD, CLKVDD, DVDD = 2.5 V; IOUTFS = 20 mA; differential transformer coupled output; 50 Ω doubly terminated, unless otherwise noted. 120 120 100 100 –6dBFS –6dBFS 0dBFS 40 40 20 20 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 0dBFS 60 0 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 Figure 3. SFDR vs. Frequency, fDATA = 200 MSPS, 1× Interpolation Figure 6. SFDR vs. Frequency, fDATA = 200 MSPS, 2× Interpolation 120 120 –3dBFS 100 03152-006 60 SFDR (dBc) 80 03152-003 100 –3dBFS –6dBFS 80 SFDR (dBc) 80 –6dBFS 0dBFS 60 60 40 40 20 20 0 5 10 15 20 25 30 FREQUENCY (MHz) 35 40 45 0 03152-004 0 0dBFS 0 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 4. SFDR vs. Frequency, fDATA = 100 MSPS, 4× Interpolation Figure 7. SFDR vs. Frequency, fDATA = 125 MSPS, 4× Interpolation 120 120 –6dBFS 03152-007 SFDR (dBc) 80 SFDR (dBc) –3dBFS –3dBFS –6dBFS 100 100 –3dBFS 80 60 0dBFS 60 –3dBFS 40 40 20 20 0 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 5. SFDR vs. Frequency, fDATA = 50 MSPS, 8× Interpolation 0 0 5 10 15 20 FREQUENCY (MHz) 25 30 Figure 8. SFDR vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation Rev. B | Page 14 of 56 03152-008 SFDR (dBc) 0dBFS 03152-005 SFDR (dBc) 80 AD9786 90 85 85 80 OUT OF BAND SFDR (dBc) 90 –3dBFS –6dBFS 70 0dBFS 65 60 0dBFS –3dBFS 75 70 –6dBFS 65 60 55 55 0 10 20 30 40 50 FOUT (MHz) 60 70 80 50 03152-009 50 0 10 20 30 ANALOG OUTPUT FREQUENCY (MHz) 03152-012 SFDR (dBc) 75 80 40 Figure 12. Out-of-Band SFDR, fDATA = 100 MSPS, 4× Interpolation Figure 9. Out-of-Band SFDR, fDATA = 200 MSPS, 2× Interpolation 100 90 95 0dBFS 85 90 OUT OF BAND SFDR (dBc) 85 –6dBFS 75 70 65 –3dBFS 60 55 –6dBFS 75 –3dBFS 70 65 60 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) 03152-010 55 50 50 0 5 10 15 20 ANALOG OUTPUT FREQUENCY (MHz) 25 Figure 10. Out-of-Band SFDR, fDATA = 125 MSPS, 4× Interpolation Figure 13. Out-of-Band SFDR, fDATA = 50 MSPS, 8× Interpolation 100 100 95 –3dBFS 95 –3dBFS 03152-013 IMD (dBc) 80 0dBFS 80 90 90 85 85 –6dBFS 80 IMD (dBc) 75 70 0dBFS –6dBFS 75 70 65 65 60 60 55 55 50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) Figure 11. Out-of-Band SFDR, fDATA = 62.5 MSPS, 8× Interpolation 50 0 20 40 FOUT (MHz) 60 80 03152-014 0dBFS 03152-011 IMD (dBc) 80 Figure 14. Third-Order IMD vs. Frequency, fDATA = 160 MSPS, 1× Interpolation Rev. B | Page 15 of 56 AD9786 100 100 95 95 –3dBFS –3dBFS 90 80 80 IMD (dBc) 85 75 0dBFS 70 65 60 55 55 20 40 60 80 100 FOUT (MHz) 120 140 160 Figure 15. Third-Order IMD vs. Frequency, fDATA = 160 MSPS, 2× Interpolation 0dBFS 70 60 0 50 0 20 40 60 FOUT (MHz) 80 100 Figure 18. Third-Order IMD vs. Frequency, fDATA = 200 MSPS,1x Interpolation 100 100 –3dBFS 95 –3dBFS 95 90 90 –6dBFS 85 –6dBFS 85 80 IMD (dBc) 80 75 70 70 65 60 60 55 55 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 Figure 16. Third-Order IMD vs. Frequency, fDATA = 200 MSPS, 2× Interpolation 50 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 03152-019 65 75 0dBFS 0dBFS 03152-016 IMD (dBc) 75 65 50 –6dBFS 03152-018 –6dBFS 85 03152-015 IMD (dBc) 90 Figure 19. Third-Order IMD vs. Frequency, fDATA = 100 MSPS, 4× Interpolation 100 100 95 95 –3dBFS 0dBFS 90 90 85 85 –6dBFS –6dBFS 80 IMD (dBc) IMD (dBc) 80 75 70 75 70 0dBFS 65 –3dBFS 60 60 55 55 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) 50 03152-017 50 Figure 17. Third-Order IMD vs. Frequency, fDATA = 125 MSPS, 4× Interpolation 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 03152-020 65 Figure 20. Third-Order IMD vs. Frequency, fDATA = 50 MSPS, 8× Interpolation Rev. B | Page 16 of 56 AD9786 100 0.3 95 –3dBFS 0.2 90 0.1 85 –6dBFS DNL (LSBs) IMD (dBc) 80 75 70 0dBFS 65 0 –0.1 –0.2 60 –0.3 0 20 40 60 80 100 120 140 160 180 200 220 240 260 FOUT (MHz) –0.4 03152-021 50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE Figure 24. Typical DNL Figure 21. Third-Order IMD vs. Frequency, fDATA = 62.5 MSPS, 8× Interpolation 1.25 –140 1.00 0.25 0 –0.50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE 03152-022 –0.25 FDATA = 78MSPS, 1× INTERPOLATION –155 –160 –165 FDATA = 78MSPS, 2× INTERPOLATION –170 –175 –180 0 10 20 30 40 50 60 ANALOG OUTPUT FREQUENCY (MHz) 70 80 Figure 25. Noise Spectral Density vs. Analog Input Frequency, fDATA = 78 MSPS Figure 22. Typical INL –150 –140 –152 NOISE SPECTRAL DENSITY (dBm/Hz) –145 –150 FDATA = 156MSPS, 1× INTERPOLATION –155 –160 –165 FDATA = 156MSPS, 2× INTERPOLATION –170 –180 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 03152-023 –175 –154 –156 –158 AIN = –3DBFS –160 AIN = 0DBFS –162 –164 –166 AIN = –6DBFS –168 –170 0 10 20 30 40 50 60 ANALOG OUTPUT FREQUENCY (MHz) 70 80 Figure 26. Noise Spectral Density vs. Analog Input Frequency, fDATA = 78 MSPS, 2x Interpolation Figure 23. Noise Spectral Density vs. Analog Input Frequency, fDATA = 156 MSPS Rev. B | Page 17 of 56 03152-026 INL (LSBs) 0.50 –150 03152-025 NOISE SPECTRAL DENSITY (dBm/Hz) –145 0.75 NOISE SPECTRAL DENSITY (dBm/Hz) 03152-024 55 AD9786 –150 –154 10 AIN = –3dBFS –156 Ref Lv1 10 dBm Marker 1 [T1] RBW 10 kHz RF Att 20 dB –87.73 dBm VBW 10 kHz 9.71442886 MHz SWT 5s Unit dBm A 0 –10 –158 –20 AIN = 0dBFS –160 1MA –30 1AVG –40 –162 –50 AIN = –6dBFS –164 –60 –70 –166 –80 –168 1 –90 –170 0 20 40 60 80 100 120 ANALOG OUTPUT FREQUENCY (MHz) 140 160 –100 03152-027 NOISE SPECTRAL DENSITY (dBm/Hz) –152 –110 START 100 kHz 19.9 MHz/ STOP 200 MHz Figure 30. Two Tones Around 23 MHz, fDATA = 200 MSPS, 2× Interpolation, Low-Pass Digital Filter Mode Figure 27. Noise Spectral Density vs. Analog Input Frequency, fDATA = 156 MSPS, 2x Interpolation –60 –65 10 Marker 1 [T1] –87.95 dBm 11.71743487 MHz RBW 10 kHz RF Att 20 dB VBW 10 kHz SWT 5s Unit dBm A 0 –70 ACLR (dBc) Ref Lv1 10 dBm 0dBFS –10 –3dBFS –20 –75 1MA –30 1AVG –40 –80 –50 –6dBFS –60 –70 –85 –80 1 0 25 50 75 FOUT (MHz) 100 125 150 –100 –110 START 100 kHz 19.9 MHz/ STOP 200 MHz 03152-031 –90 03152-028 –90 Figure 31. Two Tones Around 177 MHz, fDATA = 200 MSPS, 2× Interpolation, High-Pass Digital Filter Mode Figure 28. ACLR for First Adjacent Band vs. Frequency, fDATA = 61.44 MSPS, 4× Interpolation REF –29.82dBm *AVG Log 10dB/ *ATTEN 6dB –60 –65 –6dBFS AVERAGE 103 0dBFS –75 –3dBFS PAVG 22 W1 S2 –85 CENTER 51.44MHz *RES BW 30kHz VBW 300kHz RMS RESULTS FREQ OFFSET REF BW –90 0 20 40 60 80 100 120 FOUT (MHz) 140 160 180 200 CARRIER POWER 5.000MHz –17.41dBm/ 10.000MHz 3.84MHz 15.000MHz 20.000MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz SPAN 43.84MHz SWEEP 142.2ms (601 pts) LOWER dBc dBm 0.15 –17.26 –74.24 –91.65 –75.73 –93.14 –75.67 –93.08 UPPER dBc dBm –74.63 –92.05 –75.67 –93.08 –76.38 –93.79 –75.75 –93.17 Figure 32. ACLR for Two WCDMA Carriers @ 51.44 MHz, fDATA = 61.44 MSPS, 4× Interpolation Figure 29. ACLR for First Adjacent Band vs. Frequency, fDATA = 76.8 MSPS, 4× Interpolation Rev. B | Page 18 of 56 03152-032 –80 03152-029 ACLR (dBc) –70 AD9786 REF –22.76dBm *AVG Log 10dB/ REF –33.3dBm *AVG Log 10dB/ *ATTEN 8dB *ATTEN 6dB AC-COUPLED AC-COUPLED AVERAGE 104 AVERAGE 22 PAVG 104 W1 S2 CENTER 46.40MHz *RES BW 30kHz VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –10.38dBm/ 10.000MHz 3.84 MHz 15.000MHz 3.840MHz 3.840MHz 3.840MHz SPAN 33.84MHz SWEEP 109.8ms (601 pts) LOWER dBc dBm –79.00 –89.38 –80.78 –91.16 –79.71 –90.09 UPPER dBc dBm –79.63 –90.01 –81.77 –92.15 –81.45 –91.83 CARRIER POWER 5.000MHz –20.32dBm/ 10.000MHz 3.84MHz 15.000MHz 20.000MHz 25.000MHz *ATTEN 6dB AVERAGE 22 PAVG 22 W1 S2 VBW 300kHz RMS RESULTS FREQ OFFSET REF BW CARRIER POWER 5.000MHz –15.30dBm/ 10.000MHz 3.84MHz 15.000MHz 3.840MHz 3.840MHz 3.840MHz SPAN 33.84MHz SWEEP 109.8ms (601 pts) LOWER dBc dBm –72.33 –87.64 –72.41 –87.71 –72.67 –87.97 UPPER dBc dBm –72.13 –87.43 –73.02 –88.32 –73.50 –88.88 03152-034 CENTER 142.88MHz *RES BW 30kHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz 3.840MHz SPAN 53.84MHz SWEEP 174.6ms (601 pts) LOWER dBc dBm 0.22 –20.11 –0.60 –20.92 –72.68 –93.00 –72.74 –93.06 –73.05 –93.37 UPPER dBc dBm –0.16 –20.48 –72.05 –92.37 –72.85 –93.18 –72.55 –92.88 –72.02 –92.35 Figure 35. ACLR for Four WCDMA Carriers Near 50 MHz, fDATA = 61.44 MSPS, 4× Interpolation Figure 33. ACLR for Single WCDMA Carrier @ 20 MHz, fDATA = 61.44 MSPS, 4× Interpolation REF –28.2dBm *AVG Log 10dB/ VBW 300kHz RMS RESULTS FREQ OFFSET REF BW 03152-033 CENTER 20.00MHz *RES BW 30kHz Figure 34. ACLR for Single WCDMA Carrier @ 142.88 MHz, fDATA = 61.44 MSPS, 4× Interpolation Rev. B | Page 19 of 56 03152-035 PAVG 22 W1 S2 AD9786 SERIAL CONTROL INTERFACE Instruction Byte SDIO (PIN 55) SCLK (PIN 56) AD9786 SPI PORT INTERFACE CSB (PIN 57) 03152-036 SDO (PIN 54) Figure 36. AD9786 SPI Port Interface The AD9786 serial port is a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9786. Singleor multiple-byte transfers are supported, as well as MSB-first or LSB-first transfer formats. The AD9786 serial interface port can be configured as a single pin I/O (SDIO), or as two unidirectional pins for input/output (SDIO/SDO). GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9786. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9786, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9786 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9786. A logic high on the CSB pin, followed by a logic low, resets the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle, none of the present data is written. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9786 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes, as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single-byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic high indicates a read operation; Logic 0 indicates a write operation. N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle (see Table 10). Table 10. Bytes Transferred During Data Transfer Cycle N1 0 0 1 1 N2 0 1 0 1 Description Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes The bit decodes are shown as follows: MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0) of the instruction byte determine which register is accessed during the data transfer portion of the communication cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9786. SERIAL INTERFACE PORT PIN DESCRIPTIONS SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9786 and to run the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input to the AD9786 is registered on the rising edge of SCLK. All data is driven out of the AD9786 on the falling edge of SCLK. CSB—Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. The SDO and SDIO pins go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO—Serial Data I/O. Data is always written into the AD9786 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register Address 0x00. The default is Logic 0, which configures the SDIO pin as unidirectional. SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9786 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. B | Page 20 of 56 AD9786 MSB/LSB TRANSFERS INSTRUCTION CYCLE A4 A3 The same considerations apply to setting the software reset SWRST (0x00[5]) bit. All other registers are set to their default values, but the software reset does not affect the bits in Register Address 0x00 and Register Address 0x04. A0 D7 D6N D5N D30 D20 D10 D00 D7 D6N D5N D30 D20 D10 D00 Figure 37. Serial Register Interface Timing MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N D00 D10 D20 D4N D5N D6N D7N SDO 03152-038 SCLK Figure 38. Serial Register Interface Timing LSB First tDS The AD9786 serial port configuration bits reside in Bit 6 and Bit 7 of Register Address 0x00. Note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register might occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. A2 A1 SDO NOTES ON SERIAL PORT OPERATION It is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset. R/W N1 N0 03152-037 SDIO tSCLK CSB tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 03152-039 The AD9786 serial port controller address increments from 0x1F to 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address decrements from 0x00 to 0x1F for multibyte I/O operations if the LSB-first mode is active. SCLK Figure 39. Timing Diagram for Register Write CSB SCLK tDV SDIO SDO DATA BIT n DATA BIT n–1 Figure 40. Timing Diagram for Register Read Rev. B | Page 21 of 56 03152-040 The AD9786 serial port can support both MSB-first or LSB-first data formats. This functionality is controlled by register address DATADIR (0x00[6]). The default is MSB first. When this bit is set active high, the AD9786 serial port is in LSB-first format. That is, if the AD9786 is in LSB-first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB-first format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB-first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB-first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB-first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. DATA TRANSFER CYCLE CSB AD9786 MODE CONTROL (VIA SERIAL PORT) Table 11. Address COMMS FILTER DATA MODULATE RESERVED DCLKCRC CALMEMCK MEMRDWR MEMADDR MEMDATA DCRCSTAT 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 Bit 7 SDIODIR INTERP[1] DATAFMT CHANNEL Reserved DATAADJ[3] Bit 6 DATADIR INTERP[0] ONEPORT HILBERT Reserved DATAADJ[2] CALSTAT MEMADDR[7] CALEN MEMADDR[6] Bit 5 SWRST Bit 4 SLEEP DCLKSTR MODDUAL Reserved DATAADJ[1] CALMEM[1] XFERSTAT MEMADDR[5] MEMDATA[5] Bit 3 PDN ZSTUFF DCLKPOL DCLKEXT SIDEBAND MOD[1] Reserved Reserved DATAADJ[0] MODSYNC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CALMEN[0] XFEREN SMEMWR MEMADDR[4] MEMADDR[3] MEMDATA[4] MEMDATA[3] Bit 2 Bit 1 HPFX8 DCLKCRC MOD[0] Reserved MODADJ[2] HPFX4 IQPOL Bit 0 EXREF HPFX2 CRAYDIN Reserved MODADJ[1] Reserved MODADJ[0] CALCKDIV[2] SMEMRD MEMADDR[2] MEMDATA[2] DCRCSTAT[2] CALCKDIV[2] FMEMRD MEMADDR[1] MEMDATA[1] DCRCSTAT[1] CALCKDIV[2] UNCAL MEMADDR[0] MEMDATA[0] DCRCSTAT[0] Table 12. COMMS(00) SDIODIR Bit 7 Direction I Default 0 DATADIR 6 I 0 SWRST SLEEP PDN EXREF 5 4 3 0 I I I I 0 0 0 0 FILTER(01) INTERP[1:0] Bit [7:6] Direction I Default 00 ZSTUFF HPFX8 3 2 I I 0 0 HPFX4 1 I 0 HPFX2 0 I 0 Description 0: SDIO pin configured for input only during data transfer 1: SDIO configured for input or output during data transfer 0: Serial data uses MSB-first format 1: Serial data uses LSB-first format 1: Default all serial register bits, except Address 0x00 and Address 0x04 1: DAC output current off 1: All analog and digital circuitry, except serial interface, off 0: Internal band gap reference 1: External reference Table 13. Description 00: No interpolation 01: Interpolation 2× 10: Interpolation 4× 11: Interpolation 8× 1: Zero stuffing on 0: ×8 interpolation filter configured for low-pass 1: ×8 interpolation filter configured for high-pass 0: ×4 interpolation filter configured for low-pass 1: ×4 interpolation filter configured for high-pass 0: ×2 interpolation filter configured for low-pass 1: ×2 interpolation filter configured for high-pass Rev. B | Page 22 of 56 AD9786 Table 14. DATA(02) DATAFMT Bit 7 Direction I Default 0 ONEPORT 6 I 0 DCLKSTR 5 I 0 DCLKPOL 4 I 0 DCLKEXT 3 I 0 DCLKCRC 2 I 0 IQPOL 1 I 0 GRAYDIN 0 I 0 Description 0: Twos complement data format 1: Unsigned binary input data format 0: I and Q input data onto Port 1 and Port 2, respectively 1: I and Q input data interleaved onto Port 1 0: DATACLK pin, 12 mA drive strength 1: DATACLK pin, 24 mA drive strength 0: Input data latched on DATACLK/DACCLK rising edge (dependent on mode) 1: Input data latched on DATACLK/DACCLK falling edge (dependent on mode) 0: DATACLK pin inputs channel data rate or modulator synchronizer clock 1: DATACLK pin outputs channel data rate or modulator synchronizer clock 0: With DATACLK pin as input, DATACLK clock recovery off 1: With DATACLK pin as input, DATACLK clock recovery on 0: In one-port mode, IQSEL = 1 latches data into I channel, IQSEL = 0 latches data into Q channel 1: In one-port mode, IQSEL = 0 latches data into I channel, IQSEL = 1 latches data into Q channel 0: Gray decoder off 1: Gray decoder on Table 15. MODULATE(03) CHANNEL Bit 7 Direction I Default 0 HILBERT MODDUAL 6 5 I I 0 0 SIDEBAND 4 I 0 MOD[1:0] [3:2] I 00 Description MODDUAL CHANNEL 0x03[5] 0x03[7] 0 0 I channel processing routed to DAC 0 1 Q channel processing routed to DAC 1 0 Modulator real output routed to DAC 1 1 Modulator imaginary output routed to DAC 1: With MODDUAL on, Hilbert transform on 0: Modulator uses a single channel 1: Modulator uses both I and Q channels 0: With MODDUAL on, upper sideband rejected 1: With MODDUAL on, lower sideband rejected 00: No modulation 01: fS/2 modulation 10: fS/4 modulation 11: fS/8 modulation Rev. B | Page 23 of 56 AD9786 Table 16. DCLKCRC(05) DATAADJ[3:0] Bit [7:4] Direction I Default 0000 Description DATACLK offset (twos complement representation) 0111: +7 : 0000: 0 : 1000: −8 0: Channel data rate clock synchronizer mode 1: State machine clock synchronizer mode Modulator coefficient offset fS/8 fS/4 fS/2 000 1 1 1 001 +1/√2 0 –1 010 0 –1 1 011 –1/√2 0 –1 100 –1 +1 +1 101 –1/√2 0 –1 110 0 –1 +1 111 +1/√2 0 –1 MODSYNC 3 I 00 MODADJ[2:0] [2:0] I 000 Bit [3:0] Direction O Default Description Hardware version identifier CALMEMCK(OE) CALMEM Bit [5:4] Direction O Default 00 CALCKDIV[2:0] [2:0] I 00 Description Calibration memory 00: Uncalibrated 01: Self-calibration 10: Factory calibration 11: User input Calibration clock divide ratio from channel data rate 000: /32 001: /64 : 110: /2048 111: /4096 MEMRDWR(OF) CALSTAT Bit 7 Direction O Default 0 CALEN XFERSTAT 6 5 I O 0 0 XFEREN SMEMWR SMEMRD FMEMRD UNCAL 4 3 2 1 0 I I I I I 0 0 0 0 0 Table 17. VERSION(0D) VERSION[3:0] Table 18. Table 19. Description 0: Self-calibration cycle not complete 1: Self-calibration cycle complete 1: Self-calibration in progress 0: Factory memory transfer not complete 1: Factory memory transfer complete 1: Factory memory transfer in progress 1: Write static memory data from external port 1: Read static memory to external port 1: Read factory memory data to external port 1: Use uncalibrated Rev. B | Page 24 of 56 AD9786 Table 20. MEMADDR(10) MEMADDR [7:0] Bit [7:0] Direction I/O Default 00000000 Description Address of factory or static memory to be accessed Bit [5:0] Direction I/O Default 000000 Description Data or factory or static memory access DCRCSTAT(12) DCRCSTAT (2) Bit 2 Direction O Default 0 DCRCSTAT(1) 1 O 0 DCRCSTAT(0) 0 O 0 Description 0: With DATACLK CRC on, lock has never been achieved 1: With DATACLK CRC on, lock has been achieved at least once 0: With DATACLK CRC on, system is currently not locked 1: With DATACLK CRC on, system is currently locked 0: With DATACLK CRC on, system is currently locked 1: With DATACLK CRC on, system lost lock due to jitter Table 21. MEMDATA(11) MEMDATA [5:0] Table 22. Rev. B | Page 25 of 56 AD9786 DIGITAL FILTER SPECIFICATIONS DIGITAL INTERPOLATION FILTER COEFFICIENTS 0 Table 23. Stage 1 Interpolation Filter Coefficients Upper Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) Integer Value 9 0 –27 0 65 0 –131 0 239 0 –407 0 665 0 –1070 0 1764 0 –3273 0 10358 16384 –20 –40 –60 –80 –100 –120 –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 03152-041 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) Figure 41. 2× Interpolation Filter Response 0 –20 –40 –60 –80 –100 Upper Coefficient H(19) H(18) H(17) H(16) H(15) H(14) H(13) H(12) H(11) Integer Value 19 0 –120 0 436 0 –1284 0 5045 8192 –140 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 03152-042 Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) 0.5 03152-043 –120 Table 24. Stage 2 Interpolation Filter Coefficients Figure 42. 4× Interpolation Filter Response 0 –20 –40 –60 –80 Table 25. Stage 3 Interpolation Filter Coefficients Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) Upper Coefficient H(11) H(10) H(9) H(8) H(7) Integer Value 7 0 –53 0 302 512 –100 –120 –140 –0.5 Rev. B | Page 26 of 56 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 Figure 43. 8× Interpolation Filter Response AD9786 CLOCK/DATA TIMING Table 26. Data Port Synchronization DCLKEXT 0x02, Bit 3 1 1 MODSYNC 0x05, Bit 3 0 1 DCLKCRC 0x02, Bit 2 X X Mode DATACLK Master Modulator Master 0 0 0 External Sync Mode 0 0 1 DATACLK Slave 0 1 0 Low Setup/Hold 0 1 1 Modulator Slave Two-Port Data Input Mode (DATACLK Master) With the interpolation set to 1×, the DATACLK output is a delayed and inverted version of DACCLK at the same frequency. Note that DACCLK refers to the differential clock inputs applied at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a constant delay between the edges of DACCLK and DATACLK. The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be latched into the AD9786 upon either the rising or falling edge of DACCLK. With DCLKPOL = 0, the data is latched in upon the falling edge of DACCLK, as shown in Figure 44. With DCLKPOL = 1, as shown in Figure 45, data is latched in upon the rising edge of DACCLK. The setup and hold times are always with respect to the latching edge of DACCLK. With the interpolation set to 4× or 8×, the DACCLK input runs at 4× or 8× the speed of the DATACLK output. The data is latched in upon a rising edge of DACCLK, similar to the 2× interpolation mode. DATACLKOUT t12 tH = 2.9ns MIN 03152-044 tS = –0.5ns MIN DATA With the interpolation set to 2×, the DACCLK input runs at twice the speed of the DATACLK. Data is latched into the digital inputs of the AD9786 upon every other rising edge of DACCLK, as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as shown in Figure 47, the latching edge of DACCLK is the rising edge that occurs just before the falling edge of DATACLK. With DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is the rising edge of DACCLK that occurs just before the rising edge of DATACLK. The setup and hold time values are identical to those in Figure 44 and Figure 45. Note that there is a slight difference in the delay from the rising edge of DACCLK to the falling edge of DATACLK, and the delay from the rising edge of DACCLK to the rising edge of DATACLK. As Figure 46 shows, the DATACLK duty cycle is slightly less than 50%. This is true in all modes. DACCLKIN tD = 6ns TYP Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0 DACCLKIN However, the latching edge is every fourth edge in 4× interpolation mode and every eighth edge in the 8× interpolation mode. Similar to operation in the 2× interpolation mode, with DCLKPOL = 0, the latching edge of DACCLK is the rising edge that occurs just before the falling edge of DATACLK. With DCLKPOL = 1, the latching edge of DACCLK is the rising edge that occurs just before the rising edge of DATACLK. The setup and hold time values are identical to those in 1× and 2× interpolation. DATACLKOUT tH = 2.9ns MIN DATA 03152-045 tD = 5.5ns TYP tS = –0.5ns MIN Function Channel data rate clock output Modulator synchronization DATACLK output DATACLK inactive, DACCLK synchronous with external data DATACLK input, data rate clock, data recovery on DATACLK input, input data synchronous with DATACLK Input modulator synchronizer DATACLK input Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1 Rev. B | Page 27 of 56 AD9786 Note that DCLKPOL (Register 0x02, Bit 4) can be used to select the edge of DACCLK upon which the input data is latched. DATACLKOUT There are three status bits available for a read that allow the user to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in Register 0x12. 03152-046 DACCLKIN There is a defined setup-and-hold window with respect to input data and the latching edge of DACCLK. There is also a required timing relationship between DATACLK and DACCLK. This is referred to in Figure 49 and Figure 50 as tST and tHT (setup and hold for transition). For example, with DCLKPOL set to Logic 0, the input data latches upon the first rising edge of DACCLK that occurs more than 1.5 ns before the falling edge of DATACLK. DACCLK should not be given a rising edge in the window of 500 ps to 1.5 ns before the latching edge (falling edge when DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK. Failure to account for this timing relationship could result in corrupt data. Figure 46. DATACLK Duty Cycle tS = –0.5ns MIN tH = 2.9ns MIN DACCLKIN 03152-047 tD = 6ns TYP DATA Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0 DATACLKIN tHT = 1.5ns MIN tST = –500ps MIN tS = 0.0ns MIN tH = 3.2ns MIN 03152-049 DACCLKIN DATA Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0 DATACLKOUT DACCLKIN tH = 2.9ns MIN Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1 DATACLKIN tST = –1.0ns MIN DATACLK Slave Mode (Data Recovery On) tHT = 2.0ns MIN tS = 0.0ns MIN DATACLK (Pin 31) can be used as an input to synchronize multiple AD9786s. A clock generated by an AD9786 operating in master mode, or a clock from an external source, can be used to drive DATACLK. In this mode, two clocks are required to be applied to the AD9786. A clock running at the DAC sample rate, referred to as DACCLK, must be applied to the differential inputs (Pin 5 and Pin 6) of the AD9786. As described previously, a clock at the input sample rate must also be applied to Pin 31 (DATACLK). An internal DLL synchronizes the two applied clocks. The timing relationships between the input data, DATACLK, and DACCLK are given in Figure 49 and Figure 50. Rev. B | Page 28 of 56 tH = 3.2ns MIN DATA Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1 03152-050 DATA 03152-048 tD = 5ns TYP tS = –0.5ns MIN AD9786 Low Setup/Hold Mode (DATACLK Input, Data Recovery Off) DACCLKIN Some applications might require that digital input data be synchronized with the DATACLK input, rather than DACCLK. For these applications, the AD9786 can be programmed for low setup/hold mode by entering the values in Table 26 into the SPI registers. With data recovery off and the MODSYNC bit set to Logic 1, the AD9786 latches data in upon the rising or falling edge of DATACLK input, depending on the state of DCLKPOL. tS = –300ps MIN 03152-053 DATA DACCLKIN Figure 53. External Sync Mode with 2× Interpolation DATACLKIN tHT = 0.0ns MIN tS = –1.1ns MIN tH = 2.8ns MIN DATA 03152-051 tST = 3.0ns MIN Figure 51. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 0 DACCLKIN DATACLKIN tHT = 1.0ns MIN tS = –1.8ns MIN tH = 3.1ns MIN DATA 03152-052 tST = 2.0ns MIN tH = 2.9ns MIN Figure 52. Low Setup and Hold Mode Timing, 1× Interpolation, DCLKPOL = 1 External Sync Mode In the external sync mode, the DATACLK is programmed as an input but is not used. Applying a DATACLK input while in this mode has no effect. The digital input data is synchronized solely to the DACCLK input. With 1× interpolation, the data input is latched upon every rising edge of DACCLK. The challenge is that the user has no way of knowing exactly which edge is the latching edge when the interpolating filters are in use. In 2×, 4×, and 8× interpolation modes, the latching edge of DACCLK is every 2nd, 4th, or 8th edge, respectively. With the 2 ns keep-out window, shown in Figure 53, there is a strong possibility of violating setup and hold times, especially at high speeds. It is recommended that users sense the DAC output noise floor for setup and hold violations. If setup and hold is violated, DCLKPOL can be switched. The effect of switching the state of DCLKPOL is that the latching edge is moved by one, two, or four DACCLK cycles if the AD9786 is in 2×, 4×, or 8× interpolation modes, respectively. Note that in this mode, the DATAADJ bits have no effect. Note that when using the AD9786 in external sync mode with 1× interpolation, that functionality is identical to master mode, except that DATACLK out is not available. That is, with DATACLKPOL = 0, data is latched on the falling edge of DACCLK, and with DATACLKPOL = 1, data is latched on the rising edge of DACCLK. DATAADJUST Synchronization When designing the digital interface for high speed DACs, care must be taken to ensure that the DAC input data meets setup and hold requirements. Often, compensation must be used in the clock delay path to the digital engine driving the DAC. The AD9786 has the on-chip capability to vary the latching edge of DACCLK. With the interpolation function enabled, this allows the user the choice of multiple edges upon which to latch the data. For instance, if the AD9786 is using 8× interpolation, the user can latch from one of eight edges before the rising edge of DATACLK, or seven edges after this rising edge. The specific edge upon which data is latched is controlled by SPI Register 0x05, Bits 7:4. Table 27 shows the relationship of the latching edge of DACCLK and DATACLK with the various settings of the DATAADJ bits. Table 27. DATAADJ Values for Latching Edge Sync SPI Register 0x05 Bit 7 Bit 6 Bit 5 Bit 4 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Rev. B | Page 29 of 56 Latching Edge Write DATACLK 0 +1 +2 +3 +4 +5 +6 +7 –8 –7 –6 –5 –4 –3 –2 –1 AD9786 Figure 54, Figure 55, and Figure 56 show the alignment for the latching edge of DACCLK with 4× interpolation and different settings for DATAADJ. In Figure 54, the AD9786 is in DATACLK master mode. DATAADJ is set to 0000, with DCLKPOL set to 0 so that the latching edge of DACCLK is immediately before the rising edge of DATACLK. The data transitions shown in Figure 54 are synchronous with the DACCLK, so that DACCLK and input data are constant with respect to each other. The only visible change when DATAADJ is altered is that DATACLK moves, indicating the latching edge has moved as well. Note that in DATACLK master mode, when DATAADJ is altered, the latching edge with respect to DATACLK remains the same. Figure 55 shows the same conditions, but with DATAADJ set to 1111. This moves DATACLK to the left in the plot, indicating that it occurs one DACCLK cycle before it did in Figure 54; therefore, the latching edge of DACCLK also occurs one cycle earlier. RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK DACCLK LATCHING EDGE DATA TRANSITION 03152-055 Note that the data in Figure 44 to Figure 53 was taken with the DATAADJ default of 0000. Changing the DATAADJ values allows the user to select the specific edge of DACCLK upon which the input data is latched. This can be done in master mode, but it is most useful in slave mode. For more information on using DATAADJ and MODADJ to synchronize multiple AD9786s, see Analog Devices Application Note 747. Table 27 lists the values available for 8× interpolation, which, in turn, provides a choice of 16 edges to sync data. With 4× interpolation, there is a choice of eight edges, and the relevant values from Table 27 are 0000, 0010, 0100, 0110, 1000, 1010, 1100, and 1110. These options allow latching edge placement from +3 cycles to −4 cycles. In 2× interpolation, four edges are available, and the relevant values from Table 27 are 0000, 0100, 1000, and 1100. The choices for DATAADJ are diminished to +1 cycle to –2 cycles. Figure 55. DATAADJ = 1111 Figure 56 shows the same conditions, with DATAADJ set to 0001; therefore, DATACLK moves to the right in the plot. This indicates that it occurs one DACCLK cycle after it did in Figure 54; therefore, the latching edge of DACCLK also occurs one cycle later. RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK RISING EDGE OF DATACLK CONCURRENT WITH LATCHING EDGE OF DACCLK DACCLK LATCHING EDGE DATA TRANSITION 03152-054 Figure 56. DATAADJ = 0001 DATA TRANSITION Figure 54. DATAADJ = 0000 Rev. B | Page 30 of 56 03152-056 DACCLK LATCHING EDGE AD9786 data images falling in the interpolation filter pass band are passed. In band-limited applications, the images at the output |of the DAC must be limited by an analog reconstruction filter. The complexity of the analog reconstruction filter is determined by the proximity of the closest image to the required signal band. Higher interpolation rates yield larger stop-band regions, suppressing more input images and resulting in a much relaxed analog reconstruction filter. Interpolation Modes Table 28. Interpolation Modes INTERP[0] 0 1 0 1 Mode No interpolation ×2 interpolation ×4 interpolation ×8 interpolation Interpolation is the process of increasing the number of points in a time domain waveform by approximating points between the input data points on a uniform time grid. This produces a higher output data rate. Applied to an interpolation DAC, a digital interpolation filter is used to approximate the interpolated points, having an output data rate increased by the interpolation factor. Interpolation filter responses are achieved by cascading individual digital filter banks, whose filter coefficients are given in Table 23, Table 24, and Table 25. Filter responses are shown in Figure 57, which shows the interpolation filters of the AD9786 under different interpolation rates, normalized to the input data rate, fSIN. The digital filter’s frequency domain response exhibits symmetry about half the output data rate and dc. It causes images of the input data to be shaped by the interpolation filter’s frequency response. This has the advantage of causing input data images that fall in the stop band of the digital filter to be rejected by the stop-band attenuation of the interpolation filter, while input A DAC shapes its output with a sinc function, having a null at the sampling frequency of the DAC. The higher the DAC sampling rate compared to the input signal bandwidth, the less the DAC sinc function shapes the output. The higher the interpolation rate, the more input data images fall in the interpolation filter stop band and are rejected; the bandwidth between passed images is larger with higher interpolation factors. The sinc function shaping is also reduced with a higher interpolation factor. Table 29. Sinc Shaping at Band Edge of Interpolation Filters Mode No interpolation ×2 interpolation ×4 interpolation ×8 interpolation Sinc Shaping @ 0.43 fSIN (dB) –2.8241 –0.6708 –0.1657 –0.0413 Bandwidth to First Image fSIN 2 fSIN 4 fSIN 8 fSIN SINC RESPONSE NO INTERPOLATION 0 –50 INTERP[1] = 0 INTERP[0] = 0 –100 –150 –8 –6 –4 –2 –0 2 4 6 8 fSIN ×2 INTERPOLATION 0 –50 INTERP[1] = 0 INTERP[0] = 1 –100 –150 –8 –6 –4 –2 0 2 4 6 8 fSIN ×4 INTERPOLATION 0 –50 INTERP[1] = 1 INTERP[0] = 0 –100 –150 –8 –6 –4 –2 0 2 4 6 8 fSIN ×8 INTERPOLATION 0 –50 INTERP[1] = 1 INTERP[0] = 1 –100 –150 –8 –6 –4 –2 0 2 Figure 57. Interpolation Modes Rev. B | Page 31 of 56 4 6 8 fSIN 03152-057 INTERP[1] 0 0 1 1 AD9786 REAL AND COMPLEX SIGNALS A complex signal contains both magnitude and phase information. Given two signals at the same frequency, if the leading signal in phase is cosinusoidal and the lagging signal is sinusoidal, information pertaining to the magnitude and phase of a combination of the two signals can be derived; the combination of the two signals can be considered a complex signal. The cosine and sine can be represented as a series of exponentials, recalling that a multiplication by j is a counterclockwise rotation about the Re/Im plane. The phasor representation of a complex signal with Frequency f is shown in Figure 58. Im Im Re C A/2 A/2 2πft Re A/2 A –f 0 +f FREQUENCY A/2 C = Ae2πft = Acos(2πft) + jAsin(2πft) Asin(2πft) = A e+j2πft + e–j2πft 2 e+j2πft + e–j2πft 2j = = A 2 A 2 [e+j2πft + e–j2πft] [ je+j2πft + e–j2πft] The AD9786 has two channels of interpolation filters, allowing both I and Q components to be shaped by the same filter transfer function. The interpolation filter’s frequency response is a real transfer function. Two DACs are required to represent a complex signal. A single DAC can only synthesize a real signal. When a DAC synthesizes a real signal, negative frequency components fold onto the positive frequency axis. If the input to the DAC is mirrored symmetrically about dc, the negative frequency components fold directly onto the positive frequency components in phase-producing, constructive signal summation. If the input to the DAC is not mirrored symmetrically about dc, negative frequency components might not be in phase with positive frequency components, causing destructive signal summation. Different applications might benefit from either type of signal summation. 03152-058 Acos(2πft) = A The cosine term—referred to as the real in-phase, or I component, of a complex signal—represents a signal on the real plane with mirror symmetry about dc. The sine term—referred to as the imaginary quadrature, or Q complex signal component— represents a signal on the imaginary plane with mirror asymmetry about dc. Figure 58. Complex Phasor Representation Rev. B | Page 32 of 56 AD9786 MODULATION MODES Table 30. Single-Channel Modulation MODDUAL 0 0 0 0 0 0 0 0 CHANNEL 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode I channel, no modulation I channel, modulation by fDAC/2 I channel, modulation by fDAC/4 I channel, modulation by fDAC/8 Q channel, no modulation Q channel, modulation by fDAC/2 Q channel, modulation by fDAC/4 Q channel, modulation by fDAC/8 Either channel of the AD9786 interpolation filter channels can be routed to the DAC and modulated. In single-channel operation, the input data can be modulated by a real sinusoid; the input data and the modulating sinusoid contain both positive and negative frequency components. A double sideband output results when modulating two real signals. At the DAC output, the positive and negative frequency components add in phase, resulting in constructive signal summation. Table 31. Synthesis Bandwidth vs. Interpolation Modes As the modulating sinusoidal frequency becomes a larger fraction of the DAC update rate, fDAC, the sinc function of the DAC shapes the modulated signal bandwidth more, and the first image moves closer. Table 32. Modulated Pass-Band Edges Sinc Shaping (Lower/Upper) Because the AD9786 interpolation filter pass band represents a large portion of the input data Nyquist band, it is possible for modulated signal bands to touch or overlap images if sufficient interpolation is not used under certain modulation and interpolation modes. Figure 59 shows the effects of fDAC/8 modulation when using 8× interpolation. Figure 60 to Figure 62 show the effects of real modulation under all interpolation modes. The sinc shaping at the corners of the modulated signal band and the bandwidth to the first image for those cases whose pass bands do not touch or overlap are tabulated. Modulation None fDAC/2 fDAC/4 fDAC/8 Modulation None None fSIN fSIN Overlap Overlap fDAC/4 None 0 –2.8241 –0.0701 –22.5378 Overlap fDAC/8 Overlap fDAC/2 Rev. B | Page 33 of 56 Interpolation ×2 ×4 2 fSIN 4 fSIN 2 fSIN 4 fSIN Touching 2 fSIN Overlap Touching Interpolation ×2 ×4 0 0 –0.6708 –0.1657 –1.1932 –2.3248 –9.1824 –6.1190 Touching –0.2921 –1.9096 Overlap Touching ×8 8 fSIN 8 fSIN 4 fSIN 6 fSIN ×8 0 –0.0413 –3.0590 –4.9337 –0.5974 –1.3607 –0.0727 –0.4614 AD9786 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC/4 3fDAC/8 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC fDAC/8 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 –fDAC FILTERED INTERPOLATION IMAGES fDAC 03152-059 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 Figure 59. Double Sideband Modulation NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 MOD[1] = 0 MOD[0] = 1 –50 –100 –150 –8 –6 –4 –2 0 2 4 6 8 fSIN ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 –50 –100 –150 –8 –6 –4 –2 0 2 4 6 8 fSIN ×4 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 0 MOD[1] = 0 MOD[0] = 1 –50 –100 –150 –8 –6 –4 –2 0 2 4 6 INTERP[1] = 1 INTERP[0] = 1 MOD[1] = 0 MOD[0] = 1 –50 –100 –150 –8 8 fSIN ×8 INTERPOLATION 0 –6 –4 –2 0 2 4 Figure 60. Real Modulation by fDAC/2 Under All Interpolation Modes Rev. B | Page 34 of 56 6 8 fSIN 03152-060 –fDAC fS/8 MODULATION AD9786 NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×2 INTERPOLATION 0 INTERP[1] = 0 –50 INTERP[0] = 1 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×4 INTERPOLATION 0 INTERP[1] = 1 –50 INTERP[0] = 0 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×8 INTERPOLATION 0 INTERP[1] = 1 INTERP[0] = 1 –50 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN 03215-061 MOD[1] = 1 –100 Figure 61. Real Modulation by fDAC/4 Under All Interpolation Modes NO INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 6 8 fSIN ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 0 8 fSIN 6 ×4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 0 8 fSIN 6 ×8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 –50 –150 8– MOD[0] = 0 –6 –4 –2 0 2 4 Figure 62. Real Modulation by fDAC/8 Under All Interpolation Modes Rev. B | Page 35 of 56 6 8 fSIN 03152-062 MOD[1] = 1 –100 AD9786 Table 33. Dual-Channel Complex Modulation MODDUAL 0 0 0 0 0 0 0 0 CHANNEL 0 0 0 0 1 1 1 1 MOD[1] 0 0 1 1 0 0 1 1 MOD[0] 0 1 0 1 0 1 0 1 Mode Real output, no modulation Real output, modulation by fDAC/2 Real output, modulation fDAC/4 Real output, modulation fDAC/8 Image output, no modulation Image output, modulation by fDAC/2 Image output, modulation by fDAC/4 Image output, modulation by fDAC/8 Table 34. Complex Modulated Pass-Band Edges Sinc Shaping (Lower/Upper) In dual-channel mode, the two channels can be modulated by a complex signal, with either the real or imaginary modulation result directed to the DAC. Assume initially, as in Figure 63, that the complex modulating signal is defined for a positive frequency only. This causes the output spectrum to be translated in frequency by the modulation factor only. No additional sidebands are created as a result of the modulation process; therefore, the bandwidth to the first image from the baseband bandwidth is the same as the output of the interpolation filters. Furthermore, pass bands do not overlap or touch. The sinc shaping at the corners of the modulated signal band is tabulated in Table 34. Figure 64, Figure 65, and Figure 66 show the effects of complex modulation with varying interpolation rates. Modulation None None 0 –2.8241 –0.0701 –22.5378 –0.4680 –6.0630 –1.3723 –4.9592 fDAC/2 fDAC/4 fDAC/8 Interpolation ×2 ×4 0 0 –0.6708 –0.1657 –1.1932 –2.3248 –9.1824 –6.1190 –0.0175 –0.2921 –3.3447 –1.9096 –0.1160 –0.0044 –1.7195 –0.7866 ×8 0 –0.0413 –3.0590 –4.9337 –0.5974 –1.3607 –0.0727 –0.4614 Figure 63. Complex Modulation Rev. B | Page 36 of 56 fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC fDAC/2 5fDAC/8 3fDAC/4 7fDAC/8 fDAC 3fDAC/8 fDAC/4 03152-063 NO NEGATIVE SIDEBAND 3fDAC/8 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 –fDAC fS/8 MODULATION fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –7fDAC/8 –fDAC FILTERED INTERPOLATION IMAGES AD9786 ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 0 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8f SIN ×4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 0 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8f SIN ×8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 0 –100 –6 –4 –2 0 2 4 6 8f SIN 03152-064 –150 –8 MOD[0] = 1 Figure 64. Complex Modulation by fDAC/2 Under All Interpolation Modes ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 0 6 8 fSIN ×4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 0 –6 –4 –2 0 2 4 0 6 8 fSIN ×8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 –50 MOD[1] = 1 –100 –6 –4 –2 0 2 4 6 8 fSIN 03152-065 –150 –8 MOD[0] = 0 Figure 65. Complex Modulation by fDAC/4 Under All Interpolation Modes ×2 INTERPOLATION 0 INTERP[1] = 0 INTERP[0] = 1 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8 fSIN ×4 INTERPOLATION INTERP[1] = 1 INTERP[0] = 0 –50 MOD[1] = 1 –100 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 0 6 8 fSIN ×8 INTERPOLATION INTERP[1] = 1 INTERP[0] = 1 –50 –150 –8 MOD[0] = 1 –6 –4 –2 0 2 4 Figure 66. Complex Modulation by fDAC/8 Under All Interpolation Modes Rev. B | Page 37 of 56 6 8 fSIN 03152-066 MOD[1] = 1 –100 AD9786 POWER DISSIPATION 60 The AD9786 has seven power-supply domains: two 3.3 V analog domains (AVDD1 and AVDD2), two 2.5 V analog domains (ADVDD and ACVDD), one 2.5 V clock domain (CLKVDD), and two digital domains (DVDD, which runs from 2.5 V; and DRVDD, which runs from 3.3 V). 4× 2× 30 1× 20 10 0 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 03152-068 The current for the 2.5 V analog supplies and the digital supplies varies depending on speed and mode of operation. Figure 67, Figure 68, and Figure 69 show this variation. Note that CLKVDD, ADVDD, and ACVDD vary with clock speed and interpolation rate, but not with modulation rate. ICLKVDD (mA) 40 The current needed for the 3.3 V analog supplies, AVDD1 and AVDD2, is consistent across speed and varying modes of the AD9786. Nominally, the current for AVDD1 is 29 mA across all speeds and modes, whereas the current for AVDD2 is 20 mA. Figure 68. CLKVDD Supply Current vs. Clock Speed and Interpolation Rates 30 2× fs/8 4× fs/8 8× fs/8 4× fs/4 25 8× fs/4 2× fs/4 IADVDD AND IACVDD (mA) 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 4× 8× 2× 1× 8× 2× 4× 20 15 1× 10 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 0 0 25 50 75 100 125 150 FDATA (MSPS) 175 200 225 250 Figure 69. ADVDD and ACVDD Supply Current vs. Clock Speed and Interpolation Rates Figure 67. DVDD Supply Current vs. Clock Speed, Interpolation, and Modulation Rates Rev. B | Page 38 of 56 03152-069 5 03152-067 IDVDD (mA) 8× 50 AD9786 fDAC 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 FILTERED INTERPOLATION IMAGES fDAC 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 fS/8 MODULATION fDAC 03152-070 7fDAC/8 3fDAC/4 5fDAC/8 fDAC/2 3fDAC/8 fDAC/4 fDAC/8 0 –fDAC/8 –fDAC/4 –3fDAC/8 –fDAC/2 –5fDAC/8 –3fDAC/4 –fDAC –7fDAC/8 fS/4 MODULATION Figure 70. Complex Modulation with Negative Frequency Aliasing Table 35. Dual Channel Complex Modulation with Hilbert Hilbert 0 1 Mode Hilbert transform off Hilbert transform on When complex modulation is performed, the entire spectrum is translated by the modulation factor. If the resulting modulated spectrum is not mirrored symmetrically about dc when the DAC synthesizes the modulated signal, negative frequency components fall on the positive frequency axis and can cause destructive summation of the signals, as shown in Figure 70. For some applications, this can distort the modulated output signal. X = Ae j2π(f + fm)t Y = Ae j2π(f + fm)t – π/2 Im Im Re Z = HILBERT(Y) C=X–Z Im Re 0 Im Re A/2 The operation of the Hilbert transform (Figure Z) rotates the negative frequency components of Figure Y by +π/2, and the positive frequency components of Figure Y by −π/2. The result of the Hilbert transform output is then summed with the complex signal in the main signal path. The result is that negative frequencies are cancelled and, therefore, do not fold back into the positive side of the frequency spectrum. The Δt block in the main signal path offsets the delay inherent in the Hilbert transform (nine DAC clock cycle delay). When the DAC synthesizes the modulated output, there are no negative frequency components to fold onto the positive frequency axis out of phase; consequently, no distortion is produced as a result of the modulation process. ALIASED NEGATIVE FREQUENCY INTERPOLATION IMAGES Re A/2 A/2 f A/2 A/2 A A/2 00 A/2 f A/2 –50 00 A/2 f A/2 f A dBFS A/2 03152-071 A/2 –100 In Figure 71, Figure X represents a complex signal typically found in the AD9786 signal path. Figure Y is identical to Figure X, but it is shifted by π/2. The phase shifting in the AD9786 occurs because the digital LO driving the digital quadrature modulator in the Hilbert transform path is phase shifted by π/2. Rev. B | Page 39 of 56 –150 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 Figure 72. Negative Frequency Aliasing Distortion 0.5 03152-072 Figure 71. Negative Frequency Image Rejection AD9786 Figure 72 shows this effect at the DAC output for a signal mirrored asymmetrically about dc that is produced by complex modulation without a Hilbert transform. The signal bandwidth was narrowed to show the aliased negative frequency interpolation images. The transfer function of an ideal Hilbert transform has a +90° phase shift for negative frequencies, and a –90° phase shift for positive frequencies. Because of the discontinuities that occur at 0 Hz and at 0.5 × the sample rate, any real implementation of the Hilbert transform trades off bandwidth vs. ripple. In contrast, Figure 73 shows the same waveform with the Hilbert transform applied. Clearly, the aliased interpolation images are not present. Figure 74 and Figure 75 show the gain of the Hilbert transform vs. frequency. Gain is essentially flat, with a pass-band ripple of 0.1 dB over the frequency range of 0.07 × the sample rate to 0.43 × the sample rate. 0 dBFS –50 –150 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 03152-073 –100 Figure 76 shows the phase response of the Hilbert transform implemented in the AD9786. The phase response for positive frequencies begins at –90° at 0 Hz, followed by a linear phase response (pure time delay) equal to nine filter taps (nine DACCLK cycles). For negative frequencies, the phase response at 0 Hz is +90°, followed by a linear phase delay of nine filter taps. To compensate for the unwanted 9-cycle delay, an equal delay of nine taps is used in the AD9786 digital signal path opposite the Hilbert transform. This delay block is shown as Δt in the Functional Block Diagram (Figure 1). 10 0 Figure 73. Effects of Hilbert Transform –10 If the output of the AD9786 is used with a quadrature modulator, negative frequency images are cancelled without the need for a Hilbert transform. –20 –30 –40 –50 HILBERT TRANSFORM IMPLEMENTATION –60 The Hilbert transform on the AD9786 is implemented as a 19-coefficient FIR. The coefficients are given in Table 36. –70 –80 Table 36. 03152-074 –90 Integer Value –6 0 –17 0 –40 0 –91 0 –318 0 +318 0 +91 0 +40 0 +17 0 +6 –100 100 200 300 400 500 600 700 800 900 1000 Figure 74. Hilbert Transform Gain 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 100 200 300 400 500 600 700 800 Figure 75. Hilbert Transform Ripple Rev. B | Page 40 of 56 900 1000 03152-075 Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) AD9786 A baseband double sideband signal modulated to IF increases IF filter complexity and reduces power efficiency. If the baseband signal is complex, a single sideband IF modulation can be used, relaxing IF filter complexity and increasing power efficiency. 4 3 2 1 The AD9786 has the ability to place the baseband single sideband complex signal either above or below the IF frequency. Figure 78, Figure 79, and Figure 80 illustrate this. 0 –1 0 –2 200 400 600 800 1000 1200 –50 dBFS –4 100 03152-076 –3 Figure 76. Phase Response of Hilbert Transform –100 Re() AD9786 –0.1 0 0.1 0.3 0.4 0.5 0.4 0.5 0 0 90 Figure 77. AD9786 Driving Quadrature Modulator dBFS –50 The AD9786 can be configured to drive a quadrature modulator, as in Figure 77. When two AD9786s are used with one AD9786 producing the real output, the second AD9786 produces the imaginary output. By configuring the AD9786 as a complex modulator coupled to a quadrature modulator, IF image rejection is possible. The quadrature modulator acts as the real part of a complex modulation, producing a double sideband spectrum at the local oscillator (LO) frequency with mirror symmetry about dc. –fIF 0 –fIF 0 BASEBAND –100 –150 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 IF SIDEBAND = 1 0 Figure 80. IF Quadrature Modulation of Real and Complex Baseband Signals Rev. B | Page 41 of 56 0.2 0.3 Figure 79. Lower IF Sideband Rejected SIDEBAND = 0 –fIF 0.2 Figure 78. Upper IF Sideband Rejected 03152-080 Q Im() –0.2 fIF LO –0.3 fIF AD9786 –0.4 fIF I –150 –0.5 03152-078 Mode Upper IF sideband rejected Lower IF sideband rejected 03152-077 Sideband 0 1 03152-079 Table 37. Dual Channel Complex Modulation Sideband Selection AD9786 The second master mode, DATACLK master mode, generates a reference clock that is at the channel data rate. In this mode, the slave devices align their internal channel data rate clock to the master. If modulator phase alignment is needed, a concurrent serial write to all slave devices is necessary. To achieve this, the CSB pin on all slaves must be connected together, and a group serial write to the MODADJ register bits must be performed. Following a successful serial write, the modulator coefficient alignment is updated upon the next rising edge of the internal state machine (see Figure 81). Modulator master mode does not need a concurrent serial write, because slaves lock to the master phase automatically. Master/Slave, Modulator/DATACLK Master Modes In applications where two or more AD9786s are used to synthesize several digital data paths, it might be necessary to ensure that the digital inputs to each device are latched synchronously. In complex data processing applications, digital modulator phase alignment might be required between two AD9786s. To allow data synchronization and phase alignment, only one AD9786 should be configured as a master device, providing a reference clock for another slave-configured AD9786. With synchronization enabled, a reference clock signal is generated on the DATACLK pin of the master. The DATACLK pins on the slave devices act as inputs for the reference clock generated by the master. The DATACLK pin on the master and all slaves must be directly connected. All master and slave devices must have the same clock source connected to their respective CLK+/CLK– pins. In a slave device, the local channel data rate clock and the digital modulator clock are created from the internal state machine. The local channel data rate clock is used by the slave to latch digital input data. At high data rates, the delay inherent in the signal path from master to slave can cause the slave to lag the master when acquiring synchronization. To accommodate for this, an integer number of the DAC update clock cycles can be programmed into the slave device as an offset. The value in DATAADJ allows the local channel data rate clock in the slave device to advance by up to eight cycles of the DAC clock, or to be delayed by up to seven cycles (see Figure 82). When configured as a master, the reference clock generated can take one of two forms. In modulator master mode, the reference clock is a square wave with a period equal to 16 cycles of the DAC update clock. Internal to the AD9786 is a 16-state, finite state machine, running at the DAC update rate. This state machine generates all internal and external synchronization clocks and modulator phasings. The rising edge of the master reference clock is time aligned to state zero of the internal state machine. Slave devices use the master reference clock to synchronize data latching and align modulator phase by aligning state zero of the local state machine to the master. The digital modulator coefficients are updated at the DAC clock rate and decoded in sequential order from the state machine according to Figure 83. The MODADJ bits can be used to align a different coefficient to the finite state machine’s zero state, as shown in Figure 84. DAC CLOCK STATE MACHINE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MODULATOR COEFFICIENT 1 0 –1 0 1 0 –1 0 1 0 –1 0 –1 0 1 0 –1 0 1 0 –1 0 1 0 MODADJ 1 0 –1 0 000 –1 0 1 0 000 03152-081 STATE MACHINE CYCLE CLOCK CHANNEL DATA RATE CLOCK Figure 81. Synchronous Serial Modulator Phase Alignment Rev. B | Page 42 of 56 AD9786 DATADJ[3:0] 0000 1111 0001 DAC CLOCK RECEIVED CHANNEL DATA RATE CLOCK –1 03152-082 LOCAL CHANNEL DATA RATE CLOCK +1 Figure 82. Local Channel Data Rate Clock Synchronized with Offset STATE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DECODE 1 0 1/ 2 0 0 0 –1/ 2 0 –1 0 –1/ 2 0 0 0 –1/ 2 0 fs/8 0 0 0 2 3 4 1 5 6 2 7 03152-083 fs/4 fs/2 1 3 1 Figure 83. Digital Modulator State Machine Decode MODADJ[2:0] 000 010 101 DAC CLOCK 14 15 0 1 2 3 15 0 1 15 0 1 2 MODULATOR COEFFICIENT –1 0 1 0 –1 0 0 –1 0 1 0 –1 0 03152-084 STATE MACHINE STATE MACHINE CYCLE CLOCK Figure 84. Local Modulator Coefficient Synchronized with Offset Rev. B | Page 43 of 56 AD9786 OPERATING THE AD9786 REV. F EVALUATION BOARD This section provides information to power up the board and verify correct operation; a description of more advanced modes of operation has been omitted. POWER SUPPLIES The AD9786 Rev. F evaluation board has five power supply connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD, CLKVDD, and DVDD, whereas the AD9786 has seven power supply domains. To reconcile the power supply domains on the chip with the power supply connectors on the evaluation board, use Table 38. Additionally, the DRVDD power supply on the AD9786 is used to supply power for the digital input bus. DRVDD should be run from 3.3 V. On the evaluation board, DRVDD is jumperselectable by JP1, which is just to the left of the chip on the evaluation board. With the jumper set to the 3.3 V position, the DRVDD chip receives its power from VDD3IN. CLKVDDS PECL CLOCK DRIVER The AD9786 system clock is driven from an external source via Connector S1. The AD9786 evaluation board includes an ON Semiconductor® MC100EPT22 PECL clock driver. In the factory, the evaluation board is set to use this PECL driver as a single-ended-to-differential clock receiver. The PECL driver can be set to run from 2.5 V from the CLKVDD power connector or 3.3 V from the VDD3IN power connector. This setting is done via Jumper JP2, situated next to the CLKVDD power connector, and by setting Input Bias Resistor R23 and Input Bias Resistor R4 on the evaluation board. The factory default is for the PECL driver to be powered from CLKVDD at 2.5 V (R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4 must be replaced with a 90.9 Ω resistor; and the position of JP2 must be changed. The schematic of the PECL driver section of the evaluation board is shown in Figure 85. A low jitter sine wave should be used as the clock source. Care must be taken to ensure that the clock amplitude does not exceed the power supply rails for the PECL driver. CLKVDDS CLK+ ACLKX R23 115Ω 7 R5 50Ω MC100EPT22 1 COND;5 U2 CLKVDDS;8 2 R4 90.9Ω R6 50Ω R7 50Ω CLK– 03152-085 C32 0.1μF Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board Evaluation Board Label/PS Domain on Chip DVDD CLKVDD ACVDD/ADVDD AVDD2 AVDD1 Nominal Power Supply Voltage (V) 2.5 2.5 2.5 3.3 3.3 Description SPI port Clock circuitry Analog circuitry containing clock and digital interface circuitry Switching analog circuitry Analog output circuitry Rev. B | Page 44 of 56 AD9786 DATA INPUTS ANALOG OUTPUT Digital data inputs to the AD9786 are accessed on the evaluation board through Connector J1 and Connector J2. These are 40-pin, right-angle connectors that are intended to be used with standard ribbon cable connectors. The input level should be 3.3 V. The data format is selectable through Register 0x02, Bit 7 (DATAFMT). With this bit set to a default 0, the AD9786 assumes that the input data is in twos complement format. With this bit set to 1, data should be input in offset binary format. The analog output of the AD9786 is accessed via Connector S3. Once all settings are selected and the current levels and SPI port functionality are verified, the analog signal at S3 can be viewed. For most of the AD9786 applications, a spectrum analyzer is the preferred instrument to verify proper performance. A typical spectral plot is shown in Figure 86, with the AD9786 synthesizing a two-tone signal in the default mode with a 200 MSPS sample rate. A single-tone CW signal should provide output power of approximately +0.5 dBm to the spectrum analyzer. When the evaluation board is first powered up and the clock and data are running, it is recommended that the proper operating current be verified. Press Reset Switch SW1 to ensure that the AD9786 is in default mode. The default mode for the AD9786 is for the interpolation set to 1×. The modulator is turned off in default mode. The nominal operating currents for the evaluation board in the power-up default mode are shown in Table 39. Table 39. Nominal Operating Currents in Power-Up Default Mode Evaluation Board Power Supply DVDD CLKVDD ACVDD/ADVDD AVDD1 AVDD2 Nominal Current @ Speed (mA) 50 100 150 200 MSPS MSPS MSPS MSPS 26 49 74 99 78 83 87 92 1 4 6 8 30 30 30 30 27 27 27 27 If the spectrum does not look correct at this point, the data input might be violating setup and hold times with respect to the input clock. To correct this, the user should vary the input data timing. If this is not possible, SPI Register 0x02, Bit 4 (DCLKPOL), can be inverted. This bit controls the clock edge upon which the data is latched. If neither of these methods corrects the spectrum, it is unlikely that the issue is timing related. In this case, verify that all instructions have been followed correctly and that the SPI port readback indicates the correct values. MARKER 1 [T1] REF LVL 0 0dBm RBW 30kHz –84.96dBm VBW 30kHz 193.00170300MHz SWT 560ms RF ATT 20dB UNIT dBm A –10 –20 –30 –40 1AVG 1MA –50 –60 Table 40. SPI Registers Bit 7 INTERP[1] Bit 6 INTERP[0] Bit 5 Bit 4 Bit 3 –70 Bit 0 –80 –90 –100 SERIAL PORT –110 SW1 is a hard reset switch that sets the AD9786 to its default state. It should be used every time the AD9786 power supply is cycled, the clock is interrupted, or new data is to be written via the SPI port. Set the SPI software to read back data from the AD9786, and then verify that the expected values are read back when the software is run. –120 Rev. B | Page 45 of 56 START 100MHz 19.9MHz/ STOP 200MHz Figure 86. Typical Spectral Plot 03152-086 Register 0x01 Rev. B | Page 46 of 56 Figure 87. Power Supply Distribution, Rev. F Evaluation Board 03152-087 S11 3.3VQ 2.5VQ CGND;3,4,5 SMAEDGE CLKVDD_IN 2 AGND; 3,4,5 SMAEDGE 1 S10 3.3V AGND2; 3,4,5 AVDD_IN S9 SMAEDGE 2.5VN DGND; 3,4,5 ADVDD3_IN S5 SMAEDGE 2.5V AGND2; 3,4,5 DVDD_IN S7 SMAEDGE ADVDD2_IN L2 FERRITE C65 22μF 16V TP6 RED TP4 RED TP2 RED TP18 BLK TP13 RED TP1 RED C69 0.1μF C68 0.1μF AVD1 C67 0.1μF C48 0.1μF C47 0.1μF POWER INPUT FILTERS FERRITE C63 + 22μF 16V L1 FERRITE + C64 22μF 16V + L3 FERRITE + C46 22μF 16V TP17 BLK L9 FERRITE + C45 22μF 16V L8 L11 FERRITE L12 TP7 BLK JP5 CVD TP5 BLK JP10 TP3 BLK AVD2 JP9 TP16 BLK VDD JP34 1 2 3 A B JP33 JP30 C76 0.1μF C34 0.1μF JP6 JP8 JP7 CLKVDDS DRVDD AVDD2 ACVDD ADVDD BLK BLK BLK BLK ACLKX BLK TP30 TP31 TP32 TP33 TP34 FERRITE + L6 JP1 2 1 3 A B C29 22μF 16V JP36 C75 0.1μF JP2 CLKVDD AVDD AVDD2 DVDDS DVDD DVDD TP12 FERRITE BLK AVD3 C32 0.1μF L7 VAL L10 VAL L13 VAL L14 VAL BLK TP36 BLK TP35 C35 0.1μF CLKVDDS R23 90.9Ω MC100EPT22 1 7 CGND; 5 U2 CLKVDDS; 8 2 R4 115Ω CLKVDDS + C28 4.7μF 6.3V 50Ω R6 50Ω R5 50Ω R7 6 4 CLKVDDS; 8 CGND; 5 U2 MC100EPT22 3 CLK– CLK+ AD9786 Figure 88. AD9786 Local Circuitry, Rev. F Evaluation Board Rev. B | Page 47 of 56 IQ B A S6 1 2 3 DGND; 3,4,5 OPCLK_3 JP28 BD15 03152-088 TP14 WHT C33 0.1μF OPCLK JP27 BD14 + C7 10μF 6.3V DVDD + C8 10μF 6.3V DVDD + C9 10μF 6.3V DVDD OPCLK S4 DATACLK S2 C54 0.001μF DGND; 3,4,5 + C31 10μF 6.3V DRVDD + C10 10μF 6.3V C26 0.001μF C23 0.001μF C24 0.001μF C25 0.001μF C36 0.1μF C39 0.1μF C41 0.1μF C40 0.1μF AD15 RESET 58 SPI_CSB 57 22 P1B5 23 P1B4 24 P1B3 AD05 AD04 AD03 DVDD6 52 29 P1B0LSB AD00 P2B2 49 P2B3 48 32 P2B15MSB-IQSEL 33 P2B14-OPCLK DVDD5 44 P2B6 43 P2B7 42 37 P2B12 38 P2B11 39 P2B10 BD12 BD11 BD10 AD9786BTSP P2B8 41 DCOM5 45 36 DVDD4 40 P2B9 P2B5 46 35 DCOM4 BD09 P2B4 47 U1 BD01 P2B1 50 31 DCLK-PLLL BD08 BD07 BD06 BD05 BD04 BD03 BD02 BD00 SPSDO SPSDI SPCLK SPCSB RESET TP11 WHT C37 0.1μF + C30 10V 10μF C17 0.1μF C19 0.1μF C15 0.1μF C66 10μF 6.3V C2 10μF 6.3V + C3 10μF 6.3V C22 0.001μF DVDD + C6 10μF 6.3V C38 0.1μF 4 6 5 4 3 DVDD 4 3 R42 49.9Ω 2 1 DRVDD AGND; 3,4,5 S8 TP29 BLK SW1 FLOAT; 5 RESET AVDD2 AGND; 3,4,5 S3 OUT1 C61 0.001μF S P 1 TTWB-1-B T2B NC = 5 R9 49.9Ω R10 49.9Ω C18 0.001μF + C5 C21 10μF 0.001μF 6.3V 6 T3 S 1 C4 0.1μF 3 P ADVDD AVDD C62 0.1μF R8 C16 2kΩ 0.1μF 0.01% TP8 WHT TP10 WHT + C55 0.001μF C14 0.1μF C20 0.001μF ACVDD C49 0.1μF P2B0LSB 51 34 P2B13 BD13 DCOM6 53 28 P1B1 AD01 30 DRVDD1 SP-SDO 54 27 P1B2 AD02 SP-SDI 55 REFIO 59 21 P1B6 AD06 SP-CLK 56 DNC1 61 FSADJ 60 20 P1B7 AD07 26 DVDD3 ADVDDP2 62 19 P1B8 AD08 25 DCOM3 ADCOMP2 63 18 P1B9 AD09 15 P1B10 AD10 ACVDDP2 64 AVDD2P2 66 14 P1B11 AD11 17 DVDD2 AVDD1P1 68 ACOM2P2 67 13 P1B12 AD12 ACCOM2P2 65 ACOM1P21 69 12 P1B13 AD13 16 DCOM2 IOUTB 70 11 P1B14 AD14 IOUTA 71 ACOM1P11 72 9 DVDD1 10 P1B15MSB AVDD1P2 73 8 DCOM1 ACOM2P12 74 7 CLKCOM2 S1 CGND; 3,4,5 CLK+ AVDD2P1 75 6 CLK– ACLKX JP23 ACOM2P1 76 DNC2 80 5 CLK+ 1 CLKVDD1 C27 1pF ACVDDP1 77 CLK– DVDD C42 0.1μF 4 CLKCOM1 3 T1 T1-1T 4 C11 0.1μF ACCOMP1 78 R1 50Ω C12 0.1μF 3 CLKVDD2 2 +C1 10μF 6.3V CLKVDD ADVDDP1 79 5 JP22 CLKVDD 2 LPF 1 6 TP15 WHT C13 0.1μF ADTL1-12 R3 10kΩ + R2 10kΩ AD9786 AD9786 R29 100Ω 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 3 4 5 6 7 8 9 10 2 AX13 3 AX12 4 AX11 5 AX10 6 AX09 7 AX08 8 AX07 1 AX06 2 AX05 3 AX04 4 AX03 5 AX02 6 AX01 7 AX00 8 1 2 3 4 5 6 7 8 9 10 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP1 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP2 22 RP6 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 AX00 R38 100Ω AX04 2 RP5 DNP 1 AX07 AX05 R1 R2 R3 R4 R5 R6 R7 R8 R9 AX14 RIBBON J1 AX06 JP12 AX11 AX15 RCOM 2 JP3 AX10 R33 100Ω 1 DATA-A AX09 R32 100Ω RCOM AX12 R28 100Ω AX08 R31 100Ω R39 100Ω R40 100Ω R34 100Ω R41 100Ω 2 3 4 5 6 7 8 9 10 RP7 DNP 16 AD15 15 AD14 14 AD13 13 AD12 12 AD11 11 AD10 10 AD09 9 AD08 16 AD07 15 AD06 14 AD05 13 AD04 12 AD03 11 AD02 10 AD01 9 AD00 1 2 3 4 5 6 7 8 9 10 RP8 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 JP21 R44 100Ω R43 100Ω 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 AX01 JP19 AX02 AX03 R46 100Ω 03152-089 AX13 R27 100Ω R30 100Ω RCOM AX14 R26 100Ω RCOM AX15 Figure 89. Digital Data Port A Input Terminations, Rev. F Evaluation Board Rev. B | Page 48 of 56 AD9786 R60 100Ω BX13 R64 100Ω 3 4 5 6 7 8 9 1 2 BX13 3 BX12 4 BX11 5 BX10 6 BX09 7 BX08 8 BX07 1 BX06 2 BX05 3 BX04 4 BX03 5 BX02 6 BX01 7 BX00 8 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 SDO 36 35 CLK 38 37 SDI 40 39 CSB 1 RIBBON J2 2 3 4 5 6 7 8 9 10 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP3 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP4 22 RP11 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 BX00 BX07 R55 100Ω BX04 2 RP12 10 DNP BX14 3 BX05 R1 R2 R3 R4 R5 R6 R7 R8 R9 BX15 4 BX06 JP31 BX11 R54 100Ω R53 100Ω R56 100Ω R47 100Ω 2 3 4 5 6 7 8 9 10 RP9 DNP 16 BD15 15 BD14 14 BD13 13 BD12 12 BD11 11 BD10 10 BD09 9 BD08 16 BD07 15 BD06 14 BD05 13 BD04 12 BD03 11 BD02 10 BD01 9 BD00 1 2 3 4 5 6 7 8 9 10 RP10 DNP R1 R2 R3 R4 R5 R6 R7 R8 R9 JP25 R51 100Ω R49 100Ω 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 BX01 JP24 BX02 BX03 R52 100Ω 03152-090 1 RCOM 2 JP26 BX10 R63 100Ω 1 DATA-B BX09 R59 100Ω RCOM BX12 BX08 R58 100Ω RCOM R61 100Ω BX14 R57 100Ω RCOM R62 100Ω BX15 Figure 90. Digital Data Port B Input Terminations, Rev. F Evaluation Board Rev. B | Page 49 of 56 AD9786 DVDDS OPCLK_3 + C52 4.7μF 6.3V C53 0.1μF 10 PRE 11 9 J Q 13 CLK 12 7 K Q_ CLR 14 74LCX112 DGND;8 U7 DVDDS;16 2 SPCSB U5 1 12 4 U5 10 3 SPSDI U5 8 5 1 U6 2 13 74AC14 R21 10kΩ R20 10kΩ 3 R48 9kΩ U5 9 R45 9kΩ U6 11 4 U6 6 12 U6 DVDDS 10 74AC14 9 74AC14 U6 74AC14 74AC14 5 11 74AC14 74AC14 SPSDO U5 74AC14 74AC14 6 13 SPI PORT P1 1 2 3 4 5 6 74AC14 74AC14 SPCLK U5 R50 9kΩ U6 8 + C43 4.7μF 6.3V C50 0.1μF 74AC14 Figure 91. SPI and One-Port Clock Circuitry, Rev. F Evaluation Board Rev. B | Page 50 of 56 + C44 4.7μF 6.3V C51 0.1μF 03152-091 OPCLK 4 PRE 3 5 J Q 1 CLK 2 6 K Q_ CLR 15 DGND;8 74LCX112 DVDDS;16 U7 03152-092 AD9786 03152-093 Figure 92. PCB Assembly, Primary Side, Rev. F Evaluation Board Figure 93. PCB Assembly, Secondary Side, Rev. F Evaluation Board Rev. B | Page 51 of 56 03152-094 AD9786 03152-095 Figure 94. PCB Assembly, Layer 1 Metal, Rev. F Evaluation Board Figure 95. PCB Assembly, Layer 6 Metal, Rev. F Evaluation Board Rev. B | Page 52 of 56 03152-096 AD9786 03152-097 Figure 96. PCB Assembly, Layer 2 Metal (Ground Plane),Rev. F Evaluation Board Figure 97. PCB Assembly, Layer 3 Metal (Power Plane),Rev. F Evaluation Board Rev. B | Page 53 of 56 03152-098 AD9786 03152-099 Figure 98. PCB Assembly, Layer 4 Metal (Power Plane), Rev. F Evaluation Board Figure 99. PCB Assembly, Layer 5 Metal (Ground Plane), Rev. F Evaluation Board Rev. B | Page 54 of 56 AD9786 OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX 12.20 12.00 SQ 11.80 80 61 61 1 60 80 1 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 1.05 1.00 0.95 0.15 0.05 SEATING PLANE 6.00 BSC SQ 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY (PINS UP) 20 41 40 21 VIEW A 41 20 21 40 0.50 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 100. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9786BSV AD9786BSVRL AD9786BSVZ1 AD9786BSVZRL1 AD9786-EB 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 80-Lead TQFP_EP 80-Lead TQFP_EP 80-Lead TQFP_EP 80-Lead TQFP_EP Evaluation Board Z = Pb-free part. Rev. B | Page 55 of 56 Package Option SV-80-1 SV-80-1 SV-80-1 SV-80-1 AD9786 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03152-0-10/05(B) Rev. B | Page 56 of 56