Dual-Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors AD5547/AD5557 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM R1A Dual channel 16-bit resolution: AD5547 14-bit resolution: AD5557 2- or 4-quadrant, 6.8 MHz BW multiplying DAC ±1 LSB DNL ±1 LSB INL Operating supply voltage: 2.7 V to 5.5 V Low noise: 12 nV/√Hz Low power: IDD = 10 µA max 0.5 µs settling time Built-in RFB facilitates current-to-voltage conversion Built-in 4-quadrant resistors allow 0 V to –10 V, 0 V to +10 V, or ±10 V outputs 2 mA full-scale current ± 20%, with VREF = 10 V Extended automotive operating temperature range −40°C to +125°C Selectable zero-scale/midscale power-on presets Compact 38-lead TSSOP package RCOMA VREFA ROFSA RFBA VDD D0 TO D15 (AD5547) D0 TO D13 (AD5557) D0..D15 OR D0..D13 INPUT REGISTER RS DAC A REGISTER RS INPUT REGISTER RS DAC B REGISTER RS DAC A IOUTA AGNDA AGNDB WR A0, A1 ADDR DECODE POWER ON RESET DGND RS MSB DAC B IOUTB RFBB ROFSB AD5547/AD5557 LDAC R1B RCOMB VREFB 04452-013 DAC A DAC B Figure 1. GENERAL DESCRIPTION The AD5547/AD5557 are dual precision, 16-/14-bit, multiplying, low power, current-output, parallel input, digital-to-analog converters (DACs). They are designed to operate from single +5 V supply with ±10 V multiplying references for 4-quadrant outputs with 6.8 MHz bandwidth. APPLICATIONS The built-in, 4-quadrant resistors facilitate resistance matching and temperature tracking, which minimize the number of components needed for multiquadrant applications. In addition, the feedback resistor (RFB) simplifies the I-to-V conversion with an external buffer. Automatic test equipment Instrumentation Digitally controlled calibration Digital waveform generation The AD5547/AD5557 are available in a compact, 38-lead TSSOP package and operate at the extended automotive temperature range of −40°C to +125°C. VREF U1 –VREF C1 R1 16/14 DATA VREFA RCOMA ROFSA ROFS R2 AD5547/AD5557 16-/14-BIT DAC A RFBA RFB C2 IOUTA VOUTA AGNDA POWER-ON RESET WR LDAC RS WR LDAC RS MSB A0, A1 U2 –VREF TO +VREF MSB A0, A1 2 (ONE CHANNEL SHOWN ONLY) 04452-002 R1A Figure 2. 16-/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Is Shown) Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5547/AD5557 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 12 Applications ....................................................................................... 1 Digital Section ............................................................................ 13 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 PCB Layout, Power Supply Bypassing, and Ground Connections ................................................................................ 13 Revision History ............................................................................... 2 Applications Information .............................................................. 14 Specifications..................................................................................... 3 Unipolar Mode ........................................................................... 14 Electrical Characteristics ............................................................. 3 Bipolar Mode .............................................................................. 16 Absolute Maximum Ratings ............................................................ 5 Reference Selection .................................................................... 18 ESD Caution .................................................................................. 5 Amplifier Selection .................................................................... 18 Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions ....................................................................... 20 Typical Performance Characteristics ........................................... 10 Ordering Guide .......................................................................... 20 Circuit Operation ........................................................................... 12 REVISION HISTORY 11/12—Rev. C to Rev. D Changes to Figure 22 ...................................................................... 15 11/11—Rev. B to Rev. C Added Figure 14; Renumbered Sequentially .............................. 11 4/10—Rev. A to Rev. B Changes to Features Section and General Description Section . 1 Changes to Table 1 ............................................................................ 3 Deleted Figure 17 and Figure 18; Renumbered Sequentially ... 10 Changes to Figure 15 and Figure 16............................................. 11 Changes to Figure 20 ...................................................................... 14 Added Reference Selection Section, Amplifier Selection Section, Table 10, and Table 11; Renumbered Sequentially ..................... 18 Added Table 12 ............................................................................... 19 9/09—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Changes to Static Performance, Relative Accuracy, Grade: AD5547C Parameter, Table 1 ..............................................3 Changes to Ordering Guide .......................................................... 19 1/04—Revision 0: Initial Version Rev. D | Page 2 of 20 Data Sheet AD5547/AD5557 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, IOUT = virtual GND, GND = 0 V, VREF = −10 V to +10 V, TA = −40°C to +125°C, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 1 Resolution Symbol Test Conditions/Comments N AD5547, 1 LSB = VREF/216 = 153 µV at VREF = 10 V AD5557, 1 LSB = VREF/214 = 610 µV at VREF = 10 V Grade: AD5557C Grade: AD5547B Grade: AD5547C Monotonic Data = zero scale, TA = 25°C Data = zero scale, TA = TA maximum Data = full scale Data = full scale Data = full scale Relative Accuracy INL Differential Nonlinearity Output Leakage Current DNL IOUT Full-Scale Gain Error Bipolar Mode Gain Error Bipolar Mode Zero-Scale Error Full-Scale Temperature Coefficient 2 REFERENCE INPUT VREF Range REF Input Resistance R1 and R2 Resistance R1-to-R2 Mismatch Feedback and Offset Resistance Input Capacitance2 ANALOG OUTPUT Output Current Output Capacitance2 LOGIC INPUT AND OUTPUT Logic Input Low Voltage Logic Input High Voltage GFSE GE GZSE TCVFS VREF REF R1 and R2 Δ(R1 to R2) RFB, ROFS CREF VIL VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Input Leakage Current Input Capacitance2 INTERFACE TIMING2, 3 Data to WR Setup Time tDS Data to WR Hold Time tDH WR Pulse Width tWR LDAC Pulse Width tLDAC RS Pulse Width tRS WR to LDAC Delay Time tLWD ±1 ±1 ±1 1 8 Data = full scale Code dependent Typ Max 16 14 −18 4 4 IOUT COUT VIH Min 5 5 ±0.5 10 5 ±1 ±2 ±1 ±1 10 20 ±4 ±4 ±3 +18 6 6 ±1.5 12 2 200 Bits Bits LSB LSB LSB LSB nA nA mV mV mV ppm/°C V kΩ kΩ Ω kΩ pF mA pF 0.8 0.4 2.4 2.1 IIL CIL Unit 10 10 V V V V µA pF See Figure 3 VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V 20 35 0 0 20 ns ns ns ns ns VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V 35 20 35 20 35 0 0 ns ns ns ns ns ns ns Rev. D | Page 3 of 20 AD5547/AD5557 Data Sheet Parameter SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity AC CHARACTERISTICS4 Output Voltage Settling Time Symbol Test Conditions/Comments VDD RANGE IDD PDISS PSS Logic inputs = 0 V Logic inputs = 0 V ∆VDD = ±5% Typ 2.7 tS Reference Multiplying BW DAC Glitch Impulse Multiplying Feedthrough Error Digital Feedthrough Total Harmonic Distortion Output Noise Density Analog Crosstalk Min To ±0.1% of full scale, data cycles from zero scale to full scale to zero scale VREF = 100 mV rms, data = full scale VREF = 0 V, midscale – 1 to midscale VREF = 100 mV rms, f = 10 kHz WR = 1, LDAC toggles at 1 MHz VREF = 5 V p-p, data = full scale, f = 1 kHz f = 1 kHz, BW = 1 Hz Signal input at Channel A and measures the output at Channel B, f = 1 kHz BW Q VOUT/VREF QD THD eN CAT 1 Max Unit 5.5 10 0.055 0.003 V μA mW %/% 0.5 μs 6.8 −3.5 −78 7 −104 12 −95 MHz nV-s dB nV-s dB nV/√Hz dB All static performance tests (except IOUT) are performed in a closed-loop system using an external precision OP97 I-to-V converter amplifier. The device RFB terminal is tied to the amplifier output. The +IN pin of the OP97 is grounded, and the IOUT of the DAC is tied to the OP97’s −IN pin. Typical values represent average readings measured at 25°C. 2 Guaranteed by design; not subject to production testing. 3 All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and are timed from a voltage level of 1.5 V. 4 All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where the AD8065 was used. Timing Diagram tWR WR DATA tDS tDH tLWD LDAC tLDAC 04452-018 tRS RS Figure 3. AD5547/AD5557 Timing Diagram Rev. D | Page 4 of 20 Data Sheet AD5547/AD5557 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD to GND RFB, ROFS, R1, RCOM, and VREF to GND Logic Inputs to GND V(IOUT) to GND Input Current to Any Pin except Supplies Thermal Resistance (θJA)1 Maximum Junction Temperature (TJ MAX) Operating Temperature Range Storage Temperature Range Lead Temperature Vapor Phase, 60 sec Infrared, 15 sec 1 Rating −0.3 V to +8 V −18 V to +18 V −0.3 V to +8 V −0.3 V to VDD + 0.3 V ±50 mA 150°C −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 215°C 220°C Package power dissipation = (TJ MAX − TA)/θJA. Rev. D | Page 5 of 20 AD5547/AD5557 Data Sheet D1 1 38 D2 D0 2 37 D3 ROFSA 3 36 D4 RFBA 4 35 D5 R1A 5 34 D6 RCOMA 6 33 D7 VREFA 7 32 D8 IOUTA 8 31 D9 30 D10 29 VDD 28 D11 IOUTB 12 27 D12 VREFB 13 26 D13 RCOMB 14 25 D14 R1B 15 24 D15 RFBB 16 23 RS ROFSB 17 22 MSB WR 18 21 LDAC A0 19 20 A1 AGNDA 9 DGND 10 AGNDA 11 AD5547 TOP VIEW (Not to Scale) 04452-003 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. AD5547 Pin Configuration Table 3. AD5547 Pin Function Descriptions Pin No. 1, 2, 24 to 28, 30 to 38 3 Mnemonic D0 to D15 Function Digital Input Data Bits D0 to D15. Signal level must be ≤ VDD + 0.3 V. ROFSA 4 5 RFBA R1A 6 RCOMA 7 VREFA 8 9 10 11 12 13 IOUTA AGNDA DGND AGNDB IOUTB VREFB 14 RCOMB 15 R1B 16 17 RFBB ROFSB 18 WR Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA ties to R1A and the external reference. Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do not connect when operating in unipolar mode. Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting node of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the associated VREFA pin. Do not connect if operating in unipolar mode. DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external reference amplifier. DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output. DAC A Analog Ground. Digital Ground. DAC B Analog Ground. DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF. Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREFB pin. Do not connect if operating in unipolar mode. 4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not connect if operating in unipolar mode. Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB ties to R1B and an external reference. Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge. Signal level must be ≤VDD + 0.3 V. Rev. D | Page 6 of 20 Data Sheet Pin No. 19 20 21 22 Mnemonic A0 A1 LDAC MSB 23 RS 29 VDD AD5547/AD5557 Function Address Pin 0. Signal level must be ≤VDD + 0.3 V. Address Pin 1. Signal level must be ≤VDD + 0.3 V. Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤VDD + 0.3 V. Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Rev. D | Page 7 of 20 Data Sheet NC 1 38 D0 NC 2 37 D1 ROFSA 3 36 D2 RFBA 4 35 D3 R1A 5 34 D4 RCOMA 6 33 D5 VREFA 7 32 D6 IOUTA 8 31 D7 AD5557 30 D8 TOP VIEW (Not to Scale) 29 VDD 28 D9 IOUTB 12 27 D10 VREFB 13 26 D11 RCOMB 14 25 D12 R1B 15 24 D13 RFBB 16 23 RS ROFSB 17 22 MSB WR 18 21 LDAC A0 19 20 A1 AGNDA 9 DGND 10 AGNDB 11 NC = NO CONNECT 04452-004 AD5547/AD5557 Figure 5. AD5557 Pin Configuration Table 4. AD5557 Pin Function Descriptions Pin No. 1, 2 3 Mnemonic NC ROFSA 4 5 RFBA R1A 6 RCOMA 7 VREFA 8 IOUTA 9 10 11 12 13 AGNDA DGND AGNDB IOUTB VREFB 14 RCOMB 15 R1B 16 17 RFBB ROFSB 18 WR 19 20 21 22 A0 A1 LDAC MSB Function No Connection. Do not connect anything other than the dummy pads to these pins. Bipolar Offset Resistor A. Accepts up to ±18 V. In 2-quadrant mode, ROFSA ties to RFBA. In 4-quadrant mode, ROFSA ties to R1A and the external reference. Internal Matching Feedback Resistor A. Connects to the external op amp for I-to-V conversion. 4-Quandrant Resistor. In 2-quadrant mode, R1A shorts to the VREFA pin. In 4-quadrant mode, R1A ties to ROFSA. Do not connect when operating in unipolar mode. Center Tap Point of the Two 4-Quadrant Resistors, R1A and R2A. In 4-quadrant mode, RCOMA ties to the inverting node of the reference amplifier. In 2-quadrant mode, RCOMA shorts to the VREFA pin. Do not connect if operating in unipolar mode. DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, VREFA is the reference input with constant input resistance vs. code. In 4-quadrant mode, VREFA is driven by the external reference amplifier. DAC A Current Output. Connects to the inverting terminal of external precision I-to-V op amp for voltage output. DAC A Analog Ground. Digital Ground. DAC B Analog Ground. DAC B Current Output. Connects to inverting terminal of external precision I-to-V op amp for voltage output. DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. If configured with an external op amp for 4-quadrant multiplying, VREFB becomes –VREF. Center Tap Point of the Two 4-Quadrant Resistors, R1B and R2B. In 4-quadrant mode, RCOMB ties to the inverting node of the reference amplifier. In 2-quadrant mode, RCOMB shorts to the VREFB pin. Do not connect if operating in unipolar mode. 4-Quandrant Resistor. In 2-quadrant mode, R1B shorts to the VREFB pin. In 4-quadrant mode, R1B ties to ROFSB. Do not connect if operating in unipolar mode. Internal Matching Feedback Resistor B. Connects to external op amp for I-to-V conversion. Bipolar Offset Resistor B. Accepts up to ±18 V. In 2-quadrant mode, ROFSB ties to RFBB. In 4-quadrant mode, ROFSB ties to R1B and an external reference. Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge. Signal level must be ≤VDD + 0.3 V. Address Pin 0. Signal level must be ≤VDD + 0.3 V. Address Pin 1. Signal level must be ≤VDD + 0.3 V. Digital Input Load DAC Control. Signal level must be ≤VDD + 0.3 V. Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal level must be ≤VDD + 0.3 V. Rev. D | Page 8 of 20 Data Sheet AD5547/AD5557 Pin No. 23 Mnemonic RS 24 to 28, 30 to 38 29 D13 to D0 Function Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be ≤VDD + 0.3 V. Digital Input Data Bits D13 to D0. Signal level must be ≤VDD + 0.3 V. VDD Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V. Table 5. Address Decoder Pins A1 0 0 1 1 A0 0 1 0 1 Output Update DAC A None DAC A and DAC B DAC B Table 6. Control Inputs RS 0 1 1 1 1 WR X 0 1 0 LDAC Register Operation X 0 1 1 1 1 0 Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1. Load the input register with data bits. Load the DAC register with the contents of the input register. The input and DAC registers are transparent. When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse. No register operation. Rev. D | Page 9 of 20 AD5547/AD5557 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE (Decimal) –1.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) 04452-010 DNL (LSB) 0.8 04452-019 INL (LSB) 1.0 Figure 9. AD5557 Differential Nonlinearity Error Figure 6. AD5547 Integral Nonlinearity Error 1.5 1.0 VREF = 2.5V TA = 25°C 0.8 1.0 LINEARITY ERROR (LSB) 0.6 0.2 0 –0.2 –0.4 –0.6 0.5 INL 0 DNL –0.5 –1.0 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 CODE (Decimal) –1.5 04452-020 –1.0 2 6 8 SUPPLY VOLTAGE VDD (V) 10 Figure 10. Linearity Error vs. Supply Voltage, VDD Figure 7. AD5547 Differential Nonlinearity Error 1.0 5 VDD = 5V TA = 25°C 0.8 SUPPLY CURRENT IDD (LSB) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 4 3 2 1 –0.8 –1.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE (Decimal) 04452-021 INL (LSB) 4 04452-022 GE –0.8 Figure 8. AD5557 Integral Nonlinearity Error 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 LOGIC INPUT VOLTAGE VIH (V) Figure 11. Supply Current vs. Logic Input Voltage Rev. D | Page 10 of 20 5.0 04452-023 DNL (LSB) 0.4 Data Sheet AD5547/AD5557 3.0 SUPPLY CURRENT (mA) 2.5 LDAC 1 2.0 0x5555 1.5 2 0x8000 1.0 0xFFFF 0x0000 VOUT 0 10k 100k 1M 10M 100M CLOCK FREQUENCY (Hz) M 200ns A CH1 2.70V B CH1 –6.20V 400.00ns 04452-024 CH1 5.00V CH2 2.00V 04452-025 0.5 Figure 15. Settling Time from Full Scale to Zero Scale Figure 12. AD5547 Supply Current vs. Clock Frequency –3.85 90 VDD = 5V ± 10% VREF = 10V 80 –3.90 70 –3.95 VOUT (V) PSRR (–dB) 60 50 40 –4.00 –4.05 30 –4.10 20 100 1k 10k FREQUENCY (Hz) 100k 1M 04452-014 0 10 –4.20 –20 0 10 20 30 40 TIME (ns) Figure 13. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 16. AD5547 Midscale Transition and Digital Feedthrough 20 2 0 0 –20 –2 –4 –40 GSIN (dB) –60 –80 –6 –8 –10 –100 –12 –120 –14 –140 0 5 10 15 FREQUENCY (kHz) 20 25 04452-114 –16 –160 Figure 14. AD5547/AD5557 Analog Total Harmonic Distortion (THD) Rev. D | Page 11 of 20 –18 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 17. AD5547 Unipolar Reference Multiplying Bandwidth 04452-017 POWER SPECTRUM (dB) –10 04452-0016 –4.15 10 AD5547/AD5557 Data Sheet CIRCUIT OPERATION The reference voltage inputs exhibit a constant input resistance of 5 kΩ ± 20%. The impedance of IOUT, the DAC output, is code dependent. External amplifier choice should take into account the variation of the AD5547/AD5557 output impedance. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise. To maintain good analog performance, it is recommended that the power supply is bypassed with a 0.01 µF to 0.1 µF ceramic or chip capacitor in parallel with a 1 µF tantalum capacitor. Also, to minimize gain error, PCB metal traces between VREF and RFB should match. DAC SECTION The AD5547/AD5557 are 16-/14-bit, multiplying, currentoutput, parallel input DACs. The devices operate from a single 2.7 V to 5.5 V supply and provide both unipolar (0 V to –VREF or 0 V to +VREF) and bipolar (±VREF) output ranges from –18 V to +18 V references. In addition to the precision conversion RFB commonly found in current output DACs, there are three additional precision resistors for 4-quadrant bipolar applications. The AD5547/AD5557 consist of two groups of precision R-2R ladders, which make up the 12/10 LSBs, respectively. Furthermore, the 4 MSBs are decoded into 15 segments of resistor value 2R. Figure 18 shows the architecture of the 16-bit AD5547. Each of the 16 segments and the R-2R ladder carries an equally weighted current of one-sixteenth of full scale. The feedback resistor RFB and 4-quadrant resistor ROFS have values of 10 kΩ. Each 4-quadrant resistor, R1 and R2, equals 5 kΩ. In 4-quadrant operation, R1, R2, and an external op amp work together to invert the reference voltage and apply it to the VREF input. With ROFS and RFB connected as shown in Figure 2, the output can swing from −VREF to +VREF. VREF 2R 80kΩ 2R 80kΩ R2 5kΩ Every code change of the DAC corresponds to a step function; gain peaking at each output step may occur if the op amp has limited GBP and excessive parasitic capacitance present at the inverting node of the op amp. A compensation capacitor, therefore, may be needed between the I-to-V op amp inverting and output nodes to smooth the step transition. Such a compensation capacitor should be found empirically, but a 20 pF capacitor is generally adequate for the compensation. The VDD power is used primarily by the internal logic to drive the DAC switches. Note that the output precision degrades if the operating voltage falls below the specified voltage. Users should also avoid using switching regulators because device power supply rejection degrades at higher frequencies. 2R 80kΩ 2R 80kΩ RCOM R1 5kΩ 4 MSB 15 SEGMENTS R1 R 40kΩ R 40kΩ R 40kΩ R 40kΩ R 40kΩ R 40kΩ R 40kΩ R 40kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ 8-BIT R2R ROFS RA R R R R RB 2R 80kΩ 2R 80kΩ 2R 80kΩ 2R 80kΩ RFB 2R 80kΩ 10kΩ 10kΩ 4-BIT R2R IOUT AGND 15 8 4 ADDRESS DECODER WR LDAC WR D15 DAC REGISTER RS INPUT REGISTER RS D14 RS D0 Figure 18. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown Rev. D | Page 12 of 20 04452-011 LDAC Data Sheet AD5547/AD5557 The AD5547/AD5557 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double buffered feature allows the simultaneous update of several AD5547s/ AD5557s. For the AD5547, the input register is loaded directly from a 16-bit controller bus when WR is brought low. The DAC register is updated with data from the input register when LDAC is brought high. Updating the DAC register updates the DAC output with the new data (see Figure 18). To make both registers transparent, tie WR low and LDAC high. The asynchronous RS pin resets the part to zero scale if MSB = 0 and to midscale if MSB = 1. ESD Protection Circuits All logic input pins contain back-biased ESD protection Zeners connected to ground (DGND) and VDD, as shown in Figure 19. As a result, the voltage level of the logic input should not be greater than the supply voltage. VDD 5kΩ DGND 04452-026 DIGITAL INPUTS Figure 19. Equivalent ESD Protection Circuits Amplifier Selection In addition to offset voltage, the bias current is important in op amp selection for precision current output DACs. A 30 nA input bias current in the op amp contributes to 1 LSB in the full-scale error of the AD5547. The OP1177 and AD8628 op amps are good candidates for the I-to-V conversion. The voltage reference temperature coefficient (TC) and longterm drift are primary considerations. For example, a 5 V reference with a TC of 5 ppm/°C means the output changes by 25 µV/°C. As a result, a reference operating at 55°C contributes an additional 750 µV full-scale error. Similarly, the same 5 V reference with a ±50 ppm long-term drift means the output may change by ±250 µV over time. Therefore, it is practical to calibrate a system periodically to maintain its optimum precision. PCB LAYOUT, POWER SUPPLY BYPASSING, AND GROUND CONNECTIONS It is a good practice to employ a compact, minimum lead length, PCB layout design. The leads to the input should be as short as possible to minimize IR drop and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. It is also essential to bypass the power supply with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supply in parallel with the ceramic capacitor to minimize transient disturbance and filter out low frequency ripple. To minimize the digital ground bounce, the AD5547/AD5557 DGND terminal should be joined with the AGND terminal at a single point. Figure 20 illustrates the basic supply bypassing configuration and AGND/DGND connection for the AD5547/AD5557. Reference Selection The initial accuracy and rated output of the voltage reference determine the full-span adjustment. The initial accuracy of the reference is usually a secondary concern because it can be trimmed. Figure 25 shows an example of a trimming circuit. The zero-scale error can also be minimized by standard op amp nulling techniques. Rev. D | Page 13 of 20 + C2 5V – VDD C1 1µF 0.1µF AD5547/AD5557 AGND DGND 04452-015 DIGITAL SECTION Figure 20. Power Supply Bypassing AD5547/AD5557 Data Sheet APPLICATIONS INFORMATION UNIPOLAR MODE In this case, the output voltage polarity is opposite the VREF polarity (see Figure 21). Table 7 shows the negative output vs. code for the AD5547. 2-Quadrant Multiplying Mode, VOUT = 0 V to –VREF The AD5547/AD5557 DAC architecture uses a current-steering R-2R ladder design that requires an external reference and op amp to convert the unipolar mode of the output voltage to VOUT = −VREF × D/65,536 (AD5547) (1) VOUT = −VREF × D/16,384 (AD5557) (2) Table 7. AD5547 Unipolar Mode Negative Output vs. Code D in Binary 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 where D is the decimal equivalent of the input code. +5V 2 U3 ADR03 C2 0.1µF VIN TRIM VOUT 5 6 +2.5V GND VREFA 4 R1A VDD C3 0.1µF ROFSA RCOMA R1 ROFS R2 RFBA 2.5V AD5547/AD5557 C6 6.8pF RFB 16-/14-BIT U1 IOUTA AGNDA VOUTA +V AD8628 –V –2.5V TO 0V 16/14 DATA WR LDAC RS WR LDAC RS MSB A0, A1 MSB A0, A1 C4 C5 2 1µF –5V Figure 21. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to –VREF Rev. D | Page 14 of 20 0.1µF 04452-007 C1 1µF VOUT (V) –VREF (65,535/65,536) –VREF/2 –VREF (1/65,536) 0 Data Sheet AD5547/AD5557 2-Quadrant Multiplying Mode, VOUT = 0 V to +VREF Table 8 shows the positive output vs. code for the AD5547. The AD5547/AD5557 are designed to operate with either positive or negative reference voltages. As a result, a positive output can be achieved with an additional op amp, (see Figure 22); the output becomes Table 8. AD5547 Unipolar Mode Positive Output vs. Code VOUT = +VREF × D/65,536 (AD5547) (3) VOUT = +VREF × D/16,384 (AD5557) (4) D in Binary 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 VOUT (V) +VREF(65,535/65,536) +VREF/2 +VREF(1/65,536) 0 U2 +5V C8 0.1µF U3 C2 1µF VIN TRIM VOUT 5 6 GND 4 C9 1µF –5V –2.5V C7 ADR03 +5V +2.5V C4 R1A VDD C3 0.1µF R1 RCOMA VREFA R2 ROFSA RFBA ROFS RFB C6 IOUTA AD5547/AD5557 C5 0.1µF U2B 16-/14-BIT AGNDA 1µF +V VOUTA AD8628 –V 16/14 DATA WR LDAC RS WR LDAC RS MSB A0, A1 MSB A0, A1 2 Figure 22. Unipolar 2-Quadrant Multiplying Mode, VOUT = 0 to +VREF Rev. D | Page 15 of 20 0V TO +2.5V 04452-005 C1 1µF AD8628 2 AD5547/AD5557 Data Sheet BIPOLAR MODE 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF Table 9 shows some of the results for the 16-bit AD5547. The AD5547/AD5557 contain on-chip all the 4-quadrant resistors necessary for precision bipolar multiplying operation. Such a feature minimizes the number of exponent components to only a voltage reference, dual op amp, and compensation capacitor (see Figure 23). For example, with a +10 V reference, the circuit yields a precision, bipolar –10 V to +10 V output. Table 9. AD5547 Output vs. Code VOUT = (D/32768 − 1) × VREF (AD5547) (5) VOUT = (D/16384 − 1) × VREF (AD5557) (6) +15V VOUT +VREF (32,767/32,768) +VREF (1/32,768) 0 –VREF (1/32,768) –VREF 2 C2 0.1µF U3 VIN TRIM VOUT 5 6 GND U2A 4 ADR01 AD8512 C8 R1A –10V VREFA RCOMA +10V ROFSA RFBA +5V VDD R1 ROFS R2 RFB C4 1µF +15V C9 U2B C3 0.1µF AD5547/AD5557 U1 16/14 DATA WR LDAC RS WR LDAC RS MSB A0, A1 16-/14-BIT DAC A C5 0.1µF IOUTA AGNDA +V VOUT AD8512 –V C6 0.1µF –10V TO +10V C7 1µF MSB A0, A1 2 –15V 04452-006 C1 1µF D in Binary 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 Figure 23. 4-Quadrant Multiplying Mode, VOUT = –VREF to +VREF Rev. D | Page 16 of 20 Data Sheet AD5547/AD5557 AC Reference Signal Attenuator System Calibration Besides handling the digital waveform decoded from the parallel input data, the AD5547/AD5557 can also handle low frequency ac reference signals for signal attenuation, channel equalization, and waveform generation applications. The maximum signal range can be up to ±18 V (see Figure 24). The initial accuracy of the system can be adjusted by trimming the voltage reference ADR0x with a digital potentiometer (see Figure 25). The AD5170 provides a one-time programmable (OTP), 8-bit adjustment that is ideal and reliable for such calibration. Analog Devices, Inc., OTP digital potentiometer comes with programmable software that simplifies factory calibration. U2A OP2177 C7 +10V –10V +15V R1A RCOMA +5V R1 VDD C1 1µF C2 0.1µF ROFSA VREFA R2 C4 RFBA ROFS C6 IOUTA 16-/14-BIT AD5547/AD5557 C5 0.1µF U2B RFB VOUTA +V OP2177 –V AGNDA U1 1µF 16/14 DATA WR LDAC RS C8 MSB A0, A1 1µF C9 0.1µF WR LDAC RS MSB A0, A1 04452-008 2 –15V Figure 24. Signal Attenuator with AC Reference +5V 2 C2 0.1µF AD5170 U3 VIN TRIM VOUT R3 5 470kΩ B 6 GND 4 U4 10kΩ R7 U2 1kΩ AD8628 ADR03 –2.5V C7 +2.5V +5V R1A VDD C3 0.1µF RCOMA R1 VREFA R2 ROFSA ROFS AD5547/AD5557 C4 RFBA 16-/14-BIT C6 U2B RFB IOUTA AGNDA U1 16/14 DATA WR LDAC RS WR LDAC REF 01/AD RS MSB A0, A1 1µF C5 0.1µF +V VOUTA AD8628 –V 0V TO +2.5V MSB A0, A1 2 04452-009 C1 1µF Figure 25. Full-Span Calibration Rev. D | Page 17 of 20 AD5547/AD5557 Data Sheet REFERENCE SELECTION When selecting a reference for use with the AD55xx series of current output DACs, pay attention to the output voltage, temperature coefficient specification of the reference. Choosing a precision reference with a low output temperature coefficient minimizes error sources. Table 10 lists some of the references available from Analog Devices, Inc., that are suitable for use with this range of current output DACs. AMPLIFIER SELECTION The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the input offset voltage of an op amp is multiplied by the variable gain of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the DAC to be nonmonotonic. The input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, RFB. Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error at the voltage output of the circuit. Provided that the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage-switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, minimize capacitance at the VREF node (the voltage output node in this application) of the DAC. This is done by using low input capacitance buffer amplifiers and careful board design. Analog Devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in Table 11 and Table 12. Table 10. Suitable Analog Devices Precision References Part No. ADR01 ADR01 ADR02 ADR02 ADR03 ADR03 ADR06 ADR06 ADR420 ADR421 ADR423 ADR425 ADR431 ADR435 ADR391 ADR395 Output Voltage (V) 10 10 5.0 5.0 2.5 2.5 3.0 3.0 2.048 2.50 3.00 5.00 2.500 5.000 2.5 5.0 Initial Tolerance (%) 0.05 0.05 0.06 0.06 0.1 0.1 0.1 0.1 0.05 0.04 0.04 0.04 0.04 0.04 0.16 0.10 Maximum Temperature Drift (ppm/°C) 3 9 3 9 3 9 3 9 3 3 3 3 3 3 9 9 ISS (mA) 1 1 1 1 1 1 1 1 0.5 0.5 0.5 0.5 0.8 0.8 0.12 0.12 Output Noise (µV p-p) 20 20 10 10 6 6 10 10 1.75 1.75 2 3.4 3.5 8 5 8 Package(s) SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8 TSOT-5, SC70-5 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, MSOP-8 TSOT-5 TSOT-5 Table 11. Suitable Analog Devices Precision Op Amps Part No. OP97 OP1177 AD8675 AD8671 ADA4004-1 AD8603 AD8607 AD8605 AD8615 AD8616 Supply Voltage (V) ±2 to ±20 ±2.5 to ±15 ±5 to ±18 ±5 to ±15 ±5 to ±15 1.8 to 5 1.8 to 5 2.7 to 5 2.7 to 5 2.7 to 5 VOS Maximum (µV) 25 60 75 75 125 50 50 65 65 65 IB Maximum (nA) 0.1 2 2 12 90 0.001 0.001 0.001 0.001 0.001 0.1 Hz to 10 Hz Noise (µV p-p) 0.5 0.4 0.1 0.077 0.1 2.3 2.3 2.3 2.4 2.4 Rev. D | Page 18 of 20 Supply Current (µA) 600 500 2300 3000 2000 40 40 1000 2000 2000 Package(s) SOIC-8 , PDIP-8 MSOP-8, SOIC-8 MSOP-8, SOIC-8 MSOP-8, SOIC-8 SOIC-8, SOT-23-5 TSOT-5 MSOP-8, SOIC-8 WLCSP-5, SOT-23-5 TSOT-5 MSOP-8, SOIC-8 Data Sheet AD5547/AD5557 Table 12. Suitable Analog Devices High Speed Op Amps Part No. AD8065 AD8066 AD8021 AD8038 ADA4899 AD8057 AD8058 AD8061 AD8062 AD9631 Supply Voltage (V) 5 to 24 5 to 24 5 to 24 3 to 12 5 to 12 3 to 12 3 to 12 2.7 to 8 2.7 to 8 ±3 to ±6 BW @ ACL (MHz) 145 145 490 350 600 325 325 320 320 320 Slew Rate (V/µs) 180 180 120 425 310 1000 850 650 650 1300 VOS (Max) (µV) 1500 1500 1000 3000 35 5000 5000 6000 6000 10,000 IB (Max) (nA) 0.006 0.006 10,500 750 100 500 500 350 350 7000 Package(s) SOIC-8, SOT-23-5 SOIC-8, MSOP-8 SOIC-8, MSOP-8 SOIC-8, SC70-5 LFCSP-8, SOIC-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOT-23-5, SOIC-8 SOIC-8, MSOP-8 SOIC-8, PDIP-8 Table 13 lists the latest DACS available from Analog Devices. Table 13. ADI Current Output DACs Model AD5425 AD5426 AD5450 AD5424 AD5429 AD5428 AD5432 AD5451 AD5433 AD5439 AD5440 AD5443 AD5452 AD5445 AD5444 AD5449 AD5415 AD5447 AD5405 AD5453 AD5553 AD5556 AD5446 AD5555 AD5557 AD5543 AD5546 AD5545 AD5547 Bits 8 8 8 8 8 8 10 10 10 10 10 12 12 12 12 12 12 12 12 14 14 14 14 14 14 16 16 16 16 Outputs 1 1 1 1 2 2 1 1 1 2 2 1 1 1 1 2 2 2 2 1 1 1 1 2 2 1 1 2 2 Interface SPI, 8-Bit Load SPI SPI Parallel SPI Parallel SPI SPI Parallel SPI Parallel SPI SPI Parallel SPI SPI SPI Parallel Parallel SPI SPI Parallel SPI SPI Parallel SPI Parallel SPI Parallel Package MSOP-10 MSOP-10 TSOT-8 TSSOP-16 TSSOP-16 TSSOP-20 MSOP-10 TSOT-8 TSSOP-20 TSSOP-16 TSSOP-24 MSOP-10 TSOT-8 TSSOP-20 MSOP-10 TSSOP-16 TSSOP-24 TSSOP-24 LFCSP-40 TSOT-8 MSOP-8 TSSOP-28 MSOP-10 TSSOP-16 TSSOP-38 MSOP-8 TSSOP-28 TSSOP-16 TSSOP-38 Comments Fast 8-bit load; see also AD5426 See also AD5425 fast load See also AD5425 fast load See also AD5452 and AD5444 Higher accuracy version of AD5443; see also AD5444 Higher accuracy version of AD5443; see also AD5452 Uncommitted resistors Uncommitted resistors MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426 Rev. D | Page 19 of 20 AD5547/AD5557 Data Sheet OUTLINE DIMENSIONS 9.80 9.70 9.60 20 38 4.50 4.40 4.30 6.40 BSC 1 19 PIN 1 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.50 BSC 0.27 0.17 SEATING PLANE 0.20 0.09 8° 0° 0.70 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-BD-1 Figure 26. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimension s shown in millimeters ORDERING GUIDE Model 1 AD5547BRU AD5547BRU-REEL7 AD5547BRUZ AD5547CRUZ AD5547CRUZ-REEL7 AD5557CRU AD5557CRU-REEL7 AD5557CRUZ 1 Resolution (Bits) 16 16 16 16 16 14 14 14 DNL (LSB) ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 INL (LSB) ±2 ±2 ±2 ±1 ±1 ±1 ±1 ±1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04452-0-11/12(D) Rev. D | Page 20 of 20 Package Description 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP 38-Lead TSSOP Package Option RU-38 RU-38 RU-38 RU-38 RU-38 RU-38 RU-38 RU-38 Ordering Quantity 50 1,000 50 50 1,000 50 1,000 50