TI1 ADC08131 8-bit high-speed serial i/o a/d converter Datasheet

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ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters with
Multiplexer Options, Voltage Reference, and Track/Hold Function
Check for Samples: ADC08131, ADC08134, ADC08138
FEATURES
DESCRIPTION
•
•
•
The ADC08131/ADC08134/ADC08138 are 8-bit
successive approximation A/D converters with serial
I/O and configurable input multiplexers with up to 8
channels. The serial I/O is configured to comply with
the MICROWIRE serial data exchange standard for
easy interface to the COPS™ family of controllers,
and can easily interface with standard shift registers
or microprocessors.
1
23
•
•
•
•
Serial Digital Data Link Requires Few I/O Pins
Analog Input Track/Hold Function
4- or 8-Channel Input Multiplexer Options with
Address Logic
On-Chip 2.5V Band-Gap Reference (±2% Over
Temperature Ensured)
No Zero or Full Scale Adjustment Required
TTL/CMOS Input/Output Compatible
0V to 5V Analog Input Range with Single 5V
Power Supply
All three devices provide a 2.5V band-gap derived
reference
with
ensured
performance
over
temperature.
APPLICATIONS
A track/hold function allows the analog voltage at the
positive input to vary during the actual A/D
conversion.
•
•
•
•
The analog inputs can be configured to operate in
various combinations of single-ended, differential, or
pseudo-differential modes. In addition, input voltage
spans as small as 1V can be accommodated.
Digitizing Automotive Sensors
Process Control/Monitoring
Remote Sensing in Noisy Environments
Embedded Diagnostics
KEY SPECIFICATIONS
•
•
•
•
•
•
•
•
Resolution: 8 Bits
Conversion Time (fC = 1 MHz): 8 µs (Max)
Power Dissipation: 20 mW (Max)
Single Supply: 5 VDC (±5%)
Total Unadjusted Error: ±½ LSB and ±1 LSB
Linearity Error (VREF = 2.5V): ±½ LSB
No Missing Codes (Over Temperature)
On-Board Reference: +2.5V ±1.5% (Max)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
COPS is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Connection Diagrams
Figure 1. ADC08138CIWM Small Outline Packages
Figure 2. ADC08134CIWM Small Outline Packages
Figure 3. ADC08131CIWM Small Outline Package
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (VCC)
6.5V
−0.3V to VCC + 0.3V
Voltage at Inputs and Outputs
Input Current at Any Pin (4)
Package Input Current
±5 mA
(4)
±20 mA
Power Dissipation at TA = 25°C (5)
800 mW
ESD Susceptibility (6)
1500V
N Package (10 sec.)
Soldering Information
SOIC Package
260°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
(6)
All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage (VIN) at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > AVCC) the current at that pin
should be limited to 5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 5 mA to four pins.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute
Maximum Ratings, whichever is lower. For these devices TJMAX = 125°C. The typical thermal resistances (θJA) of these parts when
board mounted for the ADC 08131 and the ADC08134 is 140°C/W and 91°C/W for the ADC08138.
Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Operating Ratings (1) (2)
Temperature Range (TMIN ≤ TA ≤ TMAX)
−40°C ≤ TA ≤ +85°C
Supply Voltage (VCC)
(1)
(2)
4.5 VDC to 6.3 VDC
Operating Ratings indicate conditions for which the device is functional. These ratings do not ensure specific performance limits. For
ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test
conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.
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Electrical Characteristics
The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and fCLK = 1 MHz unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Typical (1)
Limits (2)
Units
(Limits)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Linearity Error
VREF = +2.5 VDC
±1
LSB (max)
Full Scale Error
VREF = +2.5 VDC
±1
LSB (max)
Zero Error
VREF = +2.5 VDC
±1
LSB (max)
(3)
±1
LSB (max)
8
Bits (min)
Total Unadjusted Error
VREF = +5 VDC
Differential Linearity
VREF = +2.5 VDC
3.5
RREF
VIN
Reference Input Resistance
See
(4)
Analog Input Voltage
See (5)
DC Common-Mode Error
VREF = 2.5 VDC
VCC = +5V ±5%,
Power Supply Sensitivity
VREF = +2.5 VDC
On Channel Leakage Current
(6)
Off Channel Leakage Current (6)
kΩ
1.3
kΩ (min)
6.0
kΩ (max)
(VCC + 0.05)
V (max)
(GND − 0.05)
V (min)
±½
LSB (max)
±¼
LSB (max)
On Channel = 5V,
0.2
Off Channel = 0V
1
On Channel = 0V,
−0.2
Off Channel = 5V
−1
On Channel = 5V,
−0.2
Off Channel = 0V
−1
On Channel = 0V,
0.2
Off Channel = 5V
1
µA (max)
µA (max)
µA (max)
µA (max)
DIGITAL AND DC CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VCC = 5.25V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VCC = 4.75V
0.8
V (max)
IIN(1)
Logical “1” Input Current
VIN = 5.0V
1
µA (max)
IIN(0)
Logical “0” Input Current
VIN = 0V
−1
µA (max)
VOUT(1)
Logical “1” Output Voltage
IOUT = −360 µA
2.4
V (min)
IOUT = −10 µA
4.5
V (min)
VCC = 4.75V
0.4
V (max)
VCC = 4.75V:
VOUT(0)
(1)
(2)
(3)
(4)
(5)
(6)
4
Logical “0” Output Voltage
IOUT = 1.6 mA
Typicals are at TJ = 25°C and represent the most likely parametric norm.
Ensured to AOQL (Average Outgoing Quality Level).
Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with VREF = +5V only applies to the
ADC08134 and ADC08138. See Note 7 on the following page.
Cannot be tested for the ADC08131.
For VIN(−) ≥ VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see ADC08138 Simplified Block
Diagram) which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply.
During testing at low VCC levels (e.g., 4.5V), high level analog inputs (e.g., 5V) can cause an input diode to conduct, especially at
elevated temperatures. This will cause errors for analog inputs near full-scale. The specification allows 50 mV forward bias of either
diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be
correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0
VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial
tolerance and loading.
Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage
current the following two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining seven off channels
tied low (0 VDC), total current flow through the off channels is measured; two, with the selected channel tied low and the off channels
tied high, total current flow through the off channels is again measured. The two cases considered for determining on channel leakage
current are the same except total current flow through the selected channel is measured.
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Electrical Characteristics (continued)
The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and fCLK = 1 MHz unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Limits (2)
Units
(Limits)
VOUT = 0V
−3.0
µA (max)
VOUT = 5V
3.0
µA (max)
Conditions
Typical (1)
IOUT
TRI-STATE Output Current
ISOURCE
Output Source Current
VOUT = 0V
−6.5
mA (min)
ISINK
Output Sink Current
VOUT = VCC
8.0
mA (min)
CS = HIGH
3.0
mA (max)
6.0
mA (max)
Supply Current
ICC
ADC08134, ADC08138
ADC08131 (7)
(7)
For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger
because it includes the reference current (700 µA typical, 2 mA maximum).
Electrical Characteristics
The following specifications apply for VCC = +5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits apply for
TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
Parameter
Conditions
Typical (1)
Limits (2)
Units
(Limits)
DC08134, ADC08138
2.5
±2%
2.5 ±1.5%
V
REFERENCE CHARACTERISTICS
VREFOUT
ΔVREF/ΔT
ΔVREF/ΔIL
Output Voltage
Temperature Coefficient
Load Regulation
40
(3)
Line Regulation
ppm/°C
Sourcing
(0 ≤ IL ≤ +4 mA)
ADC08134,
ADC08138
0.003
0.1
Sourcing
(0 ≤ IL ≤ +2 mA)
ADC08131
0.003
0.1
Sinking
(−1 ≤ IL ≤ 0 mA)
ADC08134,
ADC08138
0.2
0.5
Sinking
(−1 ≤ IL ≤ 0 mA)
ADC08131
0.2
0.5
4.75V ≤ VCC ≤ 5.25V
0.5
6
8
25
%/mA
(max)
mV (max)
VREF = 0V
ADC08134,
ISC
Short Circuit Current
VREF = 0V
ADC08131
TSU
Start-Up Time
ΔVREF/Δt
Long Term Stability
(1)
(2)
(3)
mA
(max)
ADC08138
VCC: 0V → 5V
CL = 100 µF
8
25
20
ms
200
ppm/1 kHr
Typicals are at TJ = 25°C and represent the most likely parametric norm.
Ensured to AOQL (Average Outgoing Quality Level).
Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the
ADC08131 has the on-board reference as a permanent load.
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Electrical Characteristics
The following specifications apply for VCC = +5 VDC, VREF = +2.5 VDC and tr = tf = 20 ns unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
Symbol
fCLK
Parameter
Conditions
Typical (1)
10
Clock Frequency
Conversion Time (Not Including
MUX Addressing Time)
tCA
Acquisition Time
tSELECT
CLK High while CS is High
fCLK = 1 MHz
% (min)
60
% (max)
8
1/fCLK (max)
8
µs (max)
½
1/fCLK (max)
Data Input Valid after CLK Rising Edge
tpd1, tpd0
CLK Falling Edge to Output Data Valid (4)
ns
25
ns (min)
20
ns (min)
Data MSB First
250
ns (max)
Data LSB First
200
ns (max)
Valid to CLK Rising Edge
tHOLD
MHz (max)
40
50
CS Falling Edge or Data Input
tSET-UP
Units (Limits)
kHz (min)
1
Clock Duty Cycle (3)
TC
Limits (2)
CL = 100 pF:
CL = 10 pF, RL = 10 kΩ
t1H, t0H
TRI-STATE Delay from Rising Edge of
CS to Data Output and SARS Hi-Z
50
(see TRI-STATE Test Circuits
and Waveforms)
CL = 100 pF, RL = 2 kΩ
ns
180
ns (max)
CIN
Capacitance of Logic Inputs
5
pF
COUT
Capacitance of Logic Outputs
5
pF
(1)
(2)
(3)
(4)
6
Typicals are at TJ = 25°C and represent the most likely parametric norm.
Ensured to AOQL (Average Outgoing Quality Level).
A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle
outside of these limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or
low is 100 µs.
Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see
ADC08138 Simplified Block Diagram) to allow for comparator response time.
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ADC08138 Simplified Block Diagram
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Typical Converter Performance Characteristics (1)
Linearity Error vs Reference Voltage
Linearity Error vs Temperature
Figure 4.
Figure 5.
Linearity Error vs Clock Frequency
Power Supply Current vs Temperature
(ADC08138, ADC08134)
Figure 6.
Figure 7.
Output Current vs Temperature
Power Supply Current vs Clock Frequency
Figure 8.
(1)
(2)
8
Figure 9.
(2)
For ADC08131 add IREF
For the ADC08131 VREFIN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger
because it includes the reference current (700 µA typical, 2 mA maximum).
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Typical Reference Performance Characteristics
(1)
Load Regulation (1)
Line Regulation (3 Typical Parts)
Figure 10.
Figure 11.
Output Drift vs Temperature (3 Typical Parts)
Available Output Current vs Supply Voltage
Figure 12.
Figure 13.
Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the
ADC08131 has the on-board reference as a permanent load.
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TRI-STATE Test Circuits and Waveforms
Figure 14. t1H
Figure 15. t1H
Figure 16. t0H
Figure 17. t0H
Timing Diagrams
*To reset these devices, CLK and CS must be simultaneously high for a period of tSELECT or greater. Otherwise these
devices are compatible with industry standards ADC0831/4/8.
Figure 18. Data Input Timing
Figure 19. Data Output Timing
10
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Figure 20. ADC08131 Start Conversion Timing
*LSB first output not available on ADC08131.
LSB information is maintained for remainder of clock periods until CS goes high.
Figure 21. ADC08131 Timing
Figure 22. ADC08134 Timing
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*Make sure clock edge #18 clocks in the LSB before SE is taken low
Figure 23. ADC08138 Timing
12
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ADC08138 Functional Block Diagram
*Some of these functions/pins are not available with other options.
For the ADC08134, the “SEL 1” Flip-Flop is bypassed. For the ADC08131, VREFOUT and VREFIN are internally tied
together.
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Functional Description
MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a
differential analog input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned “+” input terminal and a “−” input
terminal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most
positive. If the assigned “+” input voltage is less than the “−” input voltage the converter responds with an all
zeros output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with softwareconfigurable single-ended, differential, or pseudo-differential (which will convert the difference between the
voltage at any analog input and a common terminal) operation. The analog signal conditioning required in
transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One
converter package can now handle ground referenced inputs and true differential inputs as well as signals with
some arbitrary reference voltage.
A particular input configuration is assigned during the MUX addressing sequence, prior to the start of a
conversion. The MUX address selects which of the analog inputs are to be enabled and whether this input is
single-ended or differential. Differential inputs are restricted to adjacent channel pairs. For example, channel 0
and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act differentially with any other
channel. In addition to selecting differential mode the polarity may also be selected. Channel 0 may be selected
as the positive input and channel 1 as the negative input or vice versa. This programmability is best illustrated by
the MUX addressing codes shown in the following tables for the various product options.
The MUX address is shifted into the converter via the DI line. Because the ADC08131 contains only one
differential input channel with a fixed polarity assignment, it does not require addressing.
The common input line (COM) on the ADC08138 can be used as a pseudo-differential input. In this mode the
voltage on this pin is treated as the “−” input for any of the other input channels. This voltage does not have to be
analog ground; it can be any reference potential which is common to all of the inputs. This feature is most useful
in single-supply applications where the analog circuity may be biased up to a potential other than ground and the
output signals are all referred to this potential.
Table 1. Multiplexer/Package Options
Part
Number of Analog Channels
Number
Number of
Single-Ended
Differential
Package Pins
ADC08131
1
1
8
ADC08134
4
2
14
ADC08138
8
4
20
Table 2. MUX Addressing: ADC08138
Single-Ended MUX Mode
MUX Address
START
14
Analog Single-Ended Channel #
SGL/
ODD/
SELECT
DIF
SIGN
1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
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0
1
2
3
4
5
6
7
COM
−
+
−
+
−
+
−
+
−
+
−
+
−
+
+
−
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Table 3. MUX Addressing: ADC08138
Differential MUX Mode
MUX Address
START
Analog Differential Channel-Pair #
SGL/
ODD/
DIF
SIGN
1
SELECT
0
0
0
1
1
0
0
0
0
+
−
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
−
1
2
2
3
+
−
3
4
5
+
−
6
7
+
−
−
+
+
−
+
−
+
Table 4. MUX Addressing: ADC08134 (1)
Single-Ended MUX Mode
MUX Address
START
(1)
Channel #
SGL/
ODD/
SELECT
DIF
SIGN
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
2
3
+
+
+
+
COM is internally tied to AGND
Differential MUX Mode
MUX Address
START
Channel #
SGL/
ODD/
SELECT
DIF
SIGN
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
0
1
+
−
−
+
2
3
+
−
−
+
Since the input configuration is under software control, it can be modified as required before each conversion. A
channel can be treated as a single-ended, ground referenced input for one conversion; then it can be
reconfigured as part of a differential channel for another conversion. Figure 24 illustrates the input flexibility which
can be achieved.
The analog input voltages for each channel can range from 50 mV below ground to 50 mV above VCC (typically
5V) without degrading conversion accuracy.
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THE DIGITAL INTERFACE
A most important characteristic of these converters is their serial data link with the controlling processor. Using a
serial communication format offers two very significant system improvements; it allows many functions to be
included in a small package and it can eliminate the transmission of low level analog signals by locating the
converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
To understand the operation of these converters it is best to refer to the Timing Diagrams and ADC08138
Functional Block Diagram and to follow a complete conversion sequence. For clarity a separate timing diagram is
shown for each device.
1. A conversion is initiated by pulling the CS (chip select) line low. This line must be held low for the entire
conversion. The converter is now waiting for a start bit and its MUX assignment word.
2. On each rising edge of the clock the status of the data in (DI) line is clocked into the MUX address shift
register. The start bit is the first logic “1” that appears on this line (all leading zeros are ignored). Following
the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word.
3. When the start bit has been shifted into the start location of the MUX register, the input channel has been
assigned and a conversion is about to begin. An interval of ½ clock period is automatically inserted to allow
for sampling the analog input. The SARS line goes high at the end of this time to signal that a conversion is
now in progress and the DI line is disabled (it no longer accepts data).
4. The data out (DO) line now comes out of TRI-STATE and provides a leading zero.
5. During the conversion the output of the SAR comparator indicates whether the analog input is greater than
(high) or less than (low) a series of successive voltages generated internally from a ratioed capacitor array
(first 5 bits) and a resistor ladder (last 3 bits). After each comparison the comparator's output is shipped to
the DO line on the falling edge of CLK. This data is the result of the conversion being shifted out (with the
MSB first) and can be read by the processor immediately.
6. After 8 clock periods the conversion is completed. The SARS line returns low to indicate this ½ clock cycle
later.
7. The stored data in the successive approximation register is loaded into an internal shift register. If the
programmer prefers the data can be provided in an LSB first format [this makes use of the shift enable (SE)
control line]. On the ADC08138 the SE line is brought out and if held high the value of the LSB remains valid
on the DO line. When SE is forced low the data is clocked out LSB first. On devices which do not include the
SE control line, the data, LSB first, is automatically shifted out the DO line after the MSB first data stream.
The DO line then goes low and stays low until CS is returned high. The ADC08131 is an exception in that its
data is only output in MSB first format.
8. All internal registers are cleared when the CS line is high and the tSELECT requirement is met. See Figure 18.
If another conversion is desired CS must make a high to low transition followed by address information.
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The DI and DO lines can be tied together and controlled through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at” during the MUX addressing interval while the DO line is
still in a high impedance state.
8 Single-Ended
4 Differential
8 Psuedo-Differential
Mixed Mode
Figure 24. Analog Input Multiplexer Options for the ADC08138
REFERENCE CONSIDERATIONS
The VREFIN pin on these converters is the top of a resistor divider string and capacitor array used for the
successive approximation conversion. The voltage applied to this reference input defines the voltage span of the
analog input (the difference between VIN(MAX) and VIN(MIN) over which the 256 possible output codes apply). The
reference source must be capable of driving the reference input resistance, which can be as low as 1.3 kΩ.
For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08134 and the ADC08138 provide the output of a 2.5V band-gap
reference at VREFOUT. This voltage does not vary appreciably with temperature, supply voltage, or load current
(see Reference Timing under Electrical Characteristics) and can be tied directly to VREFIN for an analog input
span of 0V to 2.5V. This output can also be used to bias external circuits and can therefore be used as the
reference in ratiometric applications. Bypassing VREFOUT with a 100 µF capacitor is recommended.
For the ADC08131, the output of the on-board reference is internally tied to the reference input. Consequently,
the analog input span for this device is set at 0V to 2.5V. The pin VREFC is provided for bypassing purposes and
biasing external circuits as suggested above.
The maximum value of the reference is limited to the VCC supply voltage. The minimum value, however, can be
quite small (see Typical Converter Performance Characteristics) to allow direct conversions of transducer outputs
providing less than a 5V output span. Particular care must be taken with regard to noise pickup, circuit layout and
system error voltage sources when operating with a reduced span due to the increased sensitivity of the
converter (1 LSB equals VREF/256).
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Reference Examples
Figure 25. Ratiometric
Figure 26. Absolute
THE ANALOG INPUTS
The most important feature of these converters is that they can be located right at the analog signal source and
through just a few wires can communicate with a controlling processor with a highly noise immune serial bit
stream. This in itself greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most
susceptible to noise pickup. However, a few words are in order with regard to the analog inputs should the input
be noisy to begin with or possibly riding on a large common-mode voltage.
The differential input of these converters actually reduces the effects of common-mode input noise, a signal
common to both selected “+” and “−” inputs for a conversion (60 Hz is most typical). The time interval between
sampling the “+” input and then the “−” input is ½ of a clock period. The change in the common-mode voltage
during this short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
where
•
•
•
fCM is the frequency of the common-mode signal
VPEAK is its peak voltage value
fCLK is the A/D clock frequency
(1)
For a 60Hz common-mode signal to generate a ¼ LSB error (≈5 mV) with the converter running at 250kHz, its
peak value would have to be 6.63V which would be larger than allowed as it exceeds the maximum analog input
limits.
Source resistance limitation is important with regard to the DC leakage currents of the input multiplexer. While
operating near or at maximum speed bypass capacitors should not be used if the source resistance is greater
than 1kΩ. The worst-case leakage current of ±1µA over temperature will create a 1mV input error with a 1kΩ
source resistance. An op amp RC active low pass filter can provide both impedance buffering and noise filtering
should a high impedance signal source be required.
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OPTIONAL ADJUSTMENTS
Zero Error
The zero of the A/D does not require adjustment. If the minimum analog input voltage value, VIN(MIN), is not
ground a zero offset can be done. The converter can be made to output 0000 0000 digital code for this minimum
input voltage by biasing any VIN (−) input at this VIN(MIN) value. This utilizes the differential mode operation of the
A/D.
The zero error of the A/D converter relates to the location of the first riser of the transfer function and can be
measured by grounding the VIN (−) input and applying a small magnitude positive voltage to the VIN (+) input.
Zero error is the difference between the actual DC input voltage which is necessary to just cause an output
digital code transition from 0000 0000 to 0000 0001 and the ideal ½ LSB value (½ LSB = 9.8mV for VREF =
5.000VDC).
Full Scale
A full-scale adjustment can be made by applying a differential input voltage which is 1½ LSB down from the
desired analog full-scale voltage range and then adjusting the magnitude of the VREFIN input for a digital output
code which is just changing from 1111 1110 to 1111 1111 (See Figure 31). This is possible only with the
ADC08134 and ADC08138. (The reference is internally connected to VREFIN of the ADC08131).
Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from ground (for example, to accommodate an analog input
signal which does not go to ground), this new zero reference should be properly adjusted first. A VIN (+) voltage
which equals this desired zero reference plus ½ LSB (where the LSB is calculated for the desired analog span,
using 1 LSB = analog span/256) is applied to selected “+” input and the zero reference voltage at the
corresponding “−” input should then be adjusted to just obtain the 00HEX to 01HEX code transition.
The full-scale adjustment should be made [with the proper VIN (−) voltage applied] by forcing a voltage to the VIN
(+) input which is given by:
where
•
•
VMAX = the high end of the analog input range
VMIN = the low end (the offset zero) of the analog range.
(2)
(Both are ground referenced.)
The VREFIN (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure.
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APPLICATIONS
*Pinouts shown for ADC08138.
For all other products tie to pin functions as shown.
Figure 27. A “Stand-Alone” Hook-Up for ADC08138 Evaluation
Figure 28. Low-Cost Remote Temperature Sensor
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Diodes are 1N914
Figure 29. Protecting the Input
*VIN(−) = 0.15 VREF
15% of VREF ≤ VXDR ≤ 85% of VREF
Figure 30. Operating with Ratiometric Transducers
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Figure 31. Span Adjust; 0V ≤ VIN ≤ 3V
Figure 32. Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V
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REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
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