NSC ADC10831CIN 10-bit plus sign serial i/o a/d converters with mux, sample/hold and reference Datasheet

ADC10831, ADC10832, ADC10834, ADC10838
10-Bit Plus Sign Serial I/O A/D Converters
with MUX, Sample/Hold and Reference
General Description
Features
This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The
1, 2, 4 or 8-channel multiplexers can be software configured
for single-ended or differential mode of operation.
An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRETM serial data exchange standard for easy interface to the COPSTM and HPCTM families of controllers,
and can easily interface with standard shift registers and
microprocessors.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Key Specifications
Y
Y
Y
Applications
Y
Y
Y
Y
Y
Medical instruments
Remote instrumentation
Test equipment
b 5V to a 5V analog voltage range with g 5V supplies
Serial I/O (MICROWIRE compatible)
1, 2, 4, or 8-channel differential or single-ended
multiplexer
Software or hardware power down
Analog input sample/hold function
Ratiometric or Absolute voltage referencing
No zero or full scale adjustment required
No missing codes over temperature
TTL/MOS input/output compatible
Standard DIP and SO packages
Y
Y
Resolution
Dual supply
Power dissipation
In power down mode
Conversion time
Sampling rate
Band-gap reference
10 bits plus sign
g 5V
59 mW (Max)
33 mW
5 ms (Max)
74 kHz (Max)
2.5V g 2% (Max)
ADC10838 Simplified Block Diagram
TL/H/11391 – 1
COPSTM , HPCTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/H/11391
RRD-B30M75/Printed in U. S. A.
ADC10831, ADC10832, ADC10834, ADC10838 10-Bit Plus Sign Serial I/O
A/D Converters with MUX, Sample/Hold and Reference
December 1994
Connection Diagrams for Dual-In-Line and SO Packages
TL/H/11391–2
Top View
See NS Package Number N16E or M16B
TL/H/11391 – 4
Top View
See NS Package Number N20A or M20B
TL/H/11391–3
Top View
See NS Package Number N20A or M20B
TL/H/11391 – 5
Top View
See NS Package Number N24A or M24B
Ordering Information
Industrial Temperature Range
b 40§ C s TA s a 85§ C
Package
ADC10831CIN
ADC10831CIWM
ADC10832CIN
ADC10832CIWM
ADC10834CIN
ADC10834CIWM
ADC10838CIN
ADC10838CIWM
N16E
M16B
N20A
M20B
N20A
M20B
N24A
M24B
2
Absolute Maximum Ratings (Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b 40§ C to a 150§ C
Operating Ratings (Notes 2 and 3)
Operating Temperature Range
TMIN s TA s TMAX
ADC10831CIN, ADC10831CIWM,
ADC10832CIN, ADC10832CIWM,
ADC10834CIN, ADC10834CIWM,
ADC10838CIN, ADC10838CIWM b40§ C s TA s a 85§ C
a 6.0V
Positive Supply Voltage (V a e AV a e DV a )
b 6.0V
Negative Supply Voltage (Vb)
Total Supply Voltage (V a b Vb)
12V
a 6.0V
Total Reference Voltage (VREF a – VREFb)
Voltage at Analog Inputs
(CH0-CH7 and COM)
V a a 0.3V to Vb b 0.3V
Voltage at other Inputs and Outputs V a a 0.3V to b0.3V
Input Current at Any Pin (Note 4)
30 mA
Package Input Current (Note 4)
120 mA
Package Dissipation at TA e 25§ C (Note 5)
500 mW
ESD Susceptability (Note 6)
Human Body Model
2500V
Machine Model
150V
Soldering Information
N packages (10 seconds)
260§ C
SO Package (Note 7)
Vapor Phase (60 seconds)
215§ C
Infrared (15 seconds)
220§ C
a 4.5V to a 5.5V
Positive Supply Voltage
(V a e AV a e DV a )
Negative Supply Voltage (Vb)
VREF a
VREFb
VREF (VREF a –VREFb)
b 4.5V to b 5.5V
AV a a 50 mV to b50 mV
AV a a 50 mV to b50 mV
a 0.5V to V a
Electrical Characteristics
The following specifications apply for V a e AV a e DV a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e VINb e GND,
Vb e b5.0VDC, and fCLK e 2.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all
other limits TA e TJ e a 25§ C. (Notes 8, 9 and 10)
Limits
(Note 12)
Units
(Limits)
10 a Sign
Bits
g 2.0
LSB(max)
g 1.25
LSB(max)
Positive and Negative
Full-Scale Error
g 1.5
LSB(max)
Offset Error
g 1.5
LSB(max)
g 0.2
g 1.0
g 0.2
g 1.0
g 0.1
g 0.75
LSB(max)
LSB(max)
LSB(max)
g 0.15
g 0.6
LSB(max)
Symbol
Parameter
Conditions
Typical
(Note 11)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
TUE
Total Unadjusted Error (Note 13)
INL
Positive and Negative Integral
Linearity Error
Power Supply Sensitivity
Offset Error
a Full-Scale Error
b Full-Scale Error
V a e a 5.0V g 10%
or Vb e b5.0 g 10%
DC Common Mode Error (Note 14)
VIN a e
VINb e
VIN where
a 5.0V t VIN t b 5V
Multiplexer Channel to
Channel Matching
g 0.1
3
LSB
Electrical Characteristics (Continued)
The following specifications apply for V a e AV a e DV a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e VINb e GND,
Vb e b5.0 VDC, and fCLK e 2.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX;
all other limits TA e TJ e a 25§ C. (Notes 8, 9 and 10) (Continued)
Symbol
Conditions
Typical
(Note 11)
VIN e 8.0 VPP,
Sampling Rate e 74 kHz
and fIN e 1 kHz to 15 kHz
67
dB
VIN e 8.0 VPP,
Sampling Rate e 74 kHz
and fIN e 1 kHz to 15 kHz
10.8
Bits
VIN e 8.0 VPP,
Sampling Rate e 74 kHz
and fIN e 1 kHz to 15 kHz
b 78
dB
VIN e 8.0 VPP,
Sampling Rate e 74 kHz
and fIN e 1 kHz to 15 kHz
b 85
dB
VIN e 8.0 VPP, where
S/(N a D) Decreases 3 dB
Sampling Rate e 74 kHz
380
kHz
fIN e 15 kHz
Sampling Rate e 74 kHz
b 80
dB
Parameter
Limits
(Note 12)
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
S/(N a D)
ENOB
THD
IMD
Signal-to-Noise Plus Distortion Ratio
Effective Number of Bits
Total Harmonic Distortion
Intermodulation Distortion
Full-Power Bandwidth
Multiplexer Channel to Channel Crosstalk
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance
7
5.0
9.5
CREF
Reference Input Capacitance
70
MUX Input Voltage
CIM
Off Channel Leakage Current (Note 15)
On Channel Leakage Current (Note 15)
pF
Vb b50 mV
AV a a 50 mV
MUX Input Capacitance
47
On Channel e a 5V and
Off Channel e b5V
On Channel e b5V and
Off Channel e a 5V
On Channel e a 5V and
Off Channel e a 5V
On Channel e b5V and
Off Channel e a 5V
4
kX
kX(min)
kX(max)
(min)
(max)
pF
b 0.4
b 3.0
mA(max)
0.4
3.0
mA(max)
0.4
3.0
mA(max)
b 0.4
b 3.0
mA(max)
Electrical Characteristics (Continued)
The following specifications apply for V a e AV a e DV a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e VINb e GND,
Vb e b5.0 VDC, and fCLK e 2.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX;
all other limits TA e TJ e a 25§ C. (Notes 8, 9 and 10) (Continued)
Symbol
Parameter
Conditions
Typical
(Note 11)
Limits
(Note 12)
2.5V g 0.5%
2.5V g 2%
Units
(Limits)
REFERENCE CHARACTERISTICS
VREFOut
Reference Output Voltage
DVREF/DT
VREFOut Temperature Coefficient
DVREF/DIL
Load Regulation, Sourcing
0 mA s IL s a 4 mA
g 0.003
g 0.05
%/mA(max)
DVREF/DIL
Load Regulation, Sinking
0 mA s IL s b1 mA
g 0.2
g 0.6
%/mA(max)
g 0.3
g 2.5
mV(max)
13
22
mA(max)
g 40
Line Regulation
5V g 10%
ISC
Short Circuit Current
VREFOut e 0V
Noise Voltage
10 Hz to 10 kHz, CL e 100 mF
DVREF/Dt
Long-term Stability
tSU
Start-Up Time
CL e 100 mF
V(max)
ppm/§ C
5
mV
g 120
ppm/kHr
100
ms
DIGITAL AND DC CHARACTERISTICS
VIN(1)
Logical ‘‘1’’ Input Voltage
V a e 5.5V
2.0
V(min)
VIN(0)
Logical ‘‘0’’ Input Voltage
V a e 4.5V
0.8
V(max)
IIN(1)
Logical ‘‘1’’ Input Current
VIN e 5.0V
0.005
a 2.5
mA(max)
IIN(0)
Logical ‘‘0’’ Input Current
VIN e 0V
b 0.005
b 2.5
mA(min)
VOUT(1)
Logical ‘‘1’’ Output Voltage
V a e 4.5V, IOUT e b360 mA
V a e 4.5V, IOUT e b10 mA
2.4
4.5
V(min)
V(min)
VOUT(0)
Logical ‘‘0’’ Output Voltage
V a e 4.5V, IOUT e 1.6 mA
IOUT
TRI-STATE Output Current
VOUT e 0V
VOUT e 5V
a ISC
Output Short-Circuit Source
Current
VOUT e 0V, V a e 4.5V
V(min)
b 3.0
a 3.0
mA(min)
mA(max)
b 30
b 15
mA(max)
b ISC
Output Short-Circuit Sink Current
VOUT e V a e
30
15
mA(min)
ID a
Digital Supply Current
(Note 17)
CS e HIGH, Power Up
CS e HIGH, Power Down
CS e HIGH, Power Down,
and CLK Off
0.9
0.2
0.5
1.3
0.4
50
mA(max)
mA(max)
mA(max)
IA a
Positive Analog Supply Current
(Note 17)
CS e HIGH, Power Up
CS e HIGH, Power Down
2.7
3.0
6.0
15
mA(max)
mA(max)
IA b
Negative Analog Supply Current
(Note 17)
CS e HIGH, Power Up
CS e HIGH, Power Down
b 2.7
b 3.0
b 4.5
b 15
mA(min)
mA(min)
IREF
Reference Input Current
VREF a e a 2.5V and
CS e HIGH, Power Up
0.6
mA(max)
5
4.5V
0.4
b 0.1
a 0.1
Electrical Characteristics (Continued)
The following specifications apply for V a e AV a e DV a e a 5.0 VDC, VREF a e a 4.096 VDC, VREFb e VIN e GND,
Vb e b5.0 VDC, and fCLK e 2.5 MHz unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX;
all other limits TA e TJ e a 25§ C. (Note 16)
Symbol
Parameter
Conditions
Typical
(Note 11)
Limits
(Note 12)
Units
(Limits)
3.0
5
2.5
MHz(max)
kHz(min)
40
60
%(min)
%(max)
12
Clock
Cycles
ms(max)
AC CHARACTERISTICS
fCLK
Clock Frequency
Clock Duty Cycle
tC
Conversion Time
12
5
5
tA
Acquisition Time
4.5
4.5
tSCS
CS Set-Up Time, Set-Up Time from Falling Edge of
CS to Rising Edge of Clock
tSDI
Clock
Cycles
ms(max)
2
2
14
(1 tCLK
b 14 ns)
30
(1 tCLK
b 30 ns)
ns(min)
(max)
DI Set-Up Time, Set-Up Time from Data Valid on
DI to Rising Edge of Clock
16
25
ns(min)
tHDI
DI Hold Time, Hold Time of DI Data from Rising
Edge of Clock to Data not Valid on DI
2
25
ns(min)
tAT
DO Access Time from Rising Edge of CLK When
CS is ‘‘Low’’ during a Conversion
30
50
ns(min)
tAC
DO or SARS Access Time from CS, Delay from
Falling Edge of CS to Data Valid on DO or SARS
30
70
ns(max)
tDSARS
Delay from Rising Edge of Clock to Falling Edge of
SARS when CS is ‘‘Low’’
100
200
ns(max)
tHDO
DO Hold Time, Hold Time of Data on DO after
Falling Edge of Clock
20
45
ns(max)
tAD
DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO
40
80
ns(max)
t1H, t0H
Delay from Rising Edge of CS to DO or SARS
TRI-STATE
40
50
ns(max)
tDCS
Delay from Falling Edge of Clock to Falling Edge of
CS
20
30
ns(min)
tCS(H)
CS ‘‘HIGH’’ Time for A/D Reset after Reading of
Conversion Result
1 CLK
1 CLK
cycle(min)
tCS(L)
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
Conversion
1 CLK
1 CLK
cycle(min)
tSC
Time from End of Conversion to CS Going ‘‘Low’’
5 CLK
5 CLK
cycle(min)
tPD
Delay from Power-Down command to 10% of
Operating Current
1
tPC
Delay from Power-Up Command to Ready to Start
a New Conversion
10
CIN
Capacitance of Logic Inputs
7
pF
COUT
Capacitance of Logic Outputs
12
pF
6
ms
ms
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: When the input voltage (VIN) at any pin exceeds the power supplies (VIN k Vb or VIN l AV a or DV a ), the current at that pln should be limited to 30 mA.
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, iJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD e (TJmax b TA)/iJA or the number given In the Absolute Maximum Ratings, whichever is lower. For this
device, TJmax e 150§ C. The typical thermal resistance (iJA) of these Paris when board mounted can be found in the following table:
Part Number
Thermal Resistance
Package Type
ADC10831CIN
82§ C/W
N16E
ADC10831CIWM
90§ C/W
M16B
ADC10832CIN
47§ C/W
N20A
ADC10832CIWM
80§ C/W
M20B
ADC10834CIN
47§ C/W
N20A
ADC10834CIWM
80§ C/W
M20B
ADC10838CIN
60§ C/W
N24A
ADC10838CIWM
75§ C/W
M24B
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kX resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 7: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titied ‘‘Surtace Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices.
Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below Vb or one
diode drop greater than V a supply. Be careful during testing at low V a and Vb levels ( g 4.5V), as high level analog inputs ( g 5V) can cause an input diode to
conduct, especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this
means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be oorrect. Exceeding this range on an
unselected channel will corrupt the reading of a selected channel. If AV a and DV a are minimum (4.5 VDC) and Vb is a maximum ( b 4.5 VDC) full scale must be
s g 4.55 VDC.
TL/H/11391 – 6
Note 9: No connection exists between AV a and DV a on the chip.
To guarantee accuracy, it is required that the AV a and DV a be connected together to a power supply with separate bypass filter at eacn V a pin.
Note 10: One LSB is referenced to 10 bits of resolution.
Note 11: Typicals are at TJ e TA e 25§ C and represent most likely pararmetric norm.
Note 12: Tested limits are guaranteed to National’s AOQL (Average Outgolng Quality Level).
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 15: Channel leakage current is measured after the channel selection.
Note 16: All the timing specifications are tested at the TTL logic levels, VIL e 0.8V for a falling edge and VIH e 2.0V for a rising. TRl-STATE voltage level is forced
to 1.4V.
Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low e 0V
and logic High e 5V). TTL levels increase the power down current to about 300 mA.
7
Electrical Characteristics (Continued)
TL/H/11391 – 7
FIGURE 1A. Transfer Characteristic
TL/H/11391 – 8
FIGURE 1B. Simplified Error Curve vs Output Code
8
Leakage Current Test Circuit
TL/H/11391 – 9
9
Typical Performance Characteristics
Analog Supply Current (IA a )
vs Temperature
Analog Supply Current (IA a )
vs Clock Frequency
Digital Supply Current (ID a )
vs Temperature
Digital Supply Current (ID a )
vs Clock Frequency
Offset Error
vs Reference Voltage
Offset Error
vs Temperature
Linearity Error
vs Clock Frequency
Linearity Error
vs Reference Voltage
Linearity Error
vs Temperature
10-Bit Unsigned
Signal-to-Noise a THD Ratio
vs Input Signal Level
Spectral Response with
34 kHz Sine Wave
Power Bandwidth Response
with 380 kHz Sine Wave
TL/H/11391 – 10
10
Typical Reference Performance Characteristics
Load Regulation
Line Regulation
Output Drift
vs Temperature
(3 Typical Parts)
Available
Output Current
vs Supply Voltage
TL/H/11391 – 11
11
TRI-STATE Test Circuits and Waveforms
TL/H/11391–12
TL/H/11391 – 13
TL/H/11391–14
TL/H/11391 – 15
Timing Diagrams
TL/H/11391 – 16
FIGURE 2. DI Timing
TL/H/11391 – 17
FIGURE 3. DO Timing
12
Timing Diagrams (Continued)
TL/H/11391 – 18
FIGURE 4. Delayed DO Timing
TL/H/11391 – 19
FIGURE 5. Hardware Power Up/Down Sequence
TL/H/11391 – 20
FIGURE 6. Software Power Up/Down Sequence
13
Timing Diagrams (Continued)
TL/H/11391 – 21
Note: If CS is low during power up of the power supply voltages (AV a and DV a ) then CS needs to go high for tCS(H). The data output after the first conversion is
invalid.
FIGURE 7. ADC10831 CS Low during Conversion
14
15
Note: If CS is low during power up of the power supply voltages (AV a and DV a ) then CS needs to go high for tCS(H). The data output after the first conversion is not valid.
FIGURE 8. ADC10832, ADC10834 and ADC10838 CS Low during Conversion
TL/H/11391 – 22
Timing Diagrams (Continued)
16
Note: If CS is low during power up of the power supply voltages (AV a and DV a ) then CS needs to go high for tCS(H). The data output after the first conversion is not valid.
FIGURE 9. ADC10831 Using CS to Delay Output of Data afer a Conversion has Completed
TL/H/11391 – 23
Timing Diagrams (Continued)
17
Note: If CS is low during power up of the power supply voltages (AV a and DV a ) then CS needs to go high for tCS(H). The data output after the first conversion is not valid.
FIGURE 10. ADC10832, ADC10834 and ADC10838 Using CS to Delay Output of Data after a Conversion has Completed
TL/H/11391 – 24
Timing Diagrams (Continued)
TABLE I. ADC10838 Multiplexer Address Assignment
MUX Address
Channel Number
MA0
MA1
MA2
MA3
PU
SING/
DIFF
ODD/
SIGN
SEL1
SEL0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
a
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
a
0
X
X
X
X
MUX
MODE
MA4
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
a
b
b
b
b
b
b
b
b
a
a
a
a
a
a
Single-Ended
b
a
b
a
b
a
b
b
Differential
a
b
a
b
a
b
a
Power Down (All Channels Disconnected)
TABLE II. ADC10834 Multiplexer Address Assignment
MUX Address
MA0
MA1
Channel Number
MA2
MA3
MUX
MODE
MA4
CH0
CH1
PU
SING/
DIFF
ODD/
SIGN
SEL1
SEL0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
a
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
a
b
b
a
0
X
X
X
X
CH2
CH3
COM
a
b
b
b
b
a
a
a
Single-Ended
b
Differential
b
a
Power Down (All Channels Disconnected)
TABLE III. ADC10832 Multiplexer Address Assignment
MUX Address
MA0
MA1
MA2
Channel Number
MA3
CH1
COM
MUX
MODE
a
b
b
Single-Ended
MA4
CH0
PU
SlNG/
DIFF
ODD/
SIGN
SEL1
SEL0
1
1
1
1
0
1
0
0
0
0
a
1
1
0
0
0
1
0
0
0
0
a
b
0
X
X
X
X
b
a
Differential
Power Down (All Channels Disconnected)
18
Pin Descriptions
CLK
DI
DO
CS
PD
SARS
CH0 – CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the rising edge of CLK into the address register (see
Tables I – III).
The voltage applied to these inputs should not
exceed AV a or go below Vb by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM
This pin is another analog input. When the analog multiplexer is single ended this input serves
as the zero reference level for inputs CH0 – CH7
(see Tables I-III). COM can serve as a ‘‘pseudo
ground’’ that has an input voltage range of AV a
a 50 mV to V b b 50 mV. In most cases, COM
will be grounded. When the MUX is set in the
differential pairs mode, COM is not used and
may be grounded.
VREF a
This is the positive analog voltage reference input. In order to malntaln accuracy, the voltage
range VREF (VREF e VREF a –VREFb) is
0.5 VDC to 5.0 VDC and the voltage at VREF a
cannot exceed AV a a 50 mV.
The negative voltage reference input. In order to
VREFb
maintain accuracy, the voltage at this pin must
not go below GND b 50 mV or exceed AV a
a 50 mV. VREF b must always be less than
VREF a .
AV a ,
DV a
These are the analog and digital positive power
supply pins. These pins should be tied to the
same power supply and bypassed separately.
The operating voltage range of AV a and DV a
is 4.5 VDC to 5.5 VDC.
This is the negative analog supply pin. The operVb
ating voltage range of Vb is b4.5V to b5.5V.
This supply pin needs to be bypassed with
0.1 mF ceramic and 10 mF tantalum capacitors
to the system analog ground.
DGND
This is the digital ground pin.
AGND
This is the analog ground pin.
The clock applied to this input controls the successive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts
the data resulting from the A/D conversion out
on DO. CS enables or disables the above functions. The clock frequency applied to this input
can be between 5 kHz and 3 MHz.
This is the serial data input pin. The data applied
to this pln is shifted by CLK into the multiplexer
address register. Tables I through III show the
multiplexer address assignment.
The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the falling edge
of CLK on this pin.
This is the chip select input pin. When a logic
low is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered up.
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.
19
Applications Hints
The ADC10831/2/4/8 use successive approximation to
digitize an analog input voltage. The DAC portion of the A/D
converters uses a capacitive array and a resistive ladder
structure. The structure of the DAC allows a very simple
switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The
ADC10831/2/4/8 have a 2.5V CMOS bandgap reference.
The serial digital I/O interfaces to MICROWIRE and
MICROWIRE a .
device during power down. CMOS logic levels will give the
least amount of current drain (3 mA). TTL logic levels will
increase the total power down current drain to 300 mA.
1.0 DIGITAL INTERFACE
There are two modes of operation. The fastest throughput
rate is obtained when CS is kept low during a conversion.
The timing diagrams in Figures 7 and 8 show the operation
of the devices in this mode. CS must be taken high for at
least tCS(H) (1 CLK) between conversions. This is necessary
to reset the internal logic. Figures 9 and 10 show the operation of the devices when CS is taken high while the
ADC10831/2/4/8 is converting. CS may be taken high during the conversion and kept high indefinitely to delay the
output data. This mode simplifies the interface to other devices while the ADC10831/2/4/8 is busy converting.
2.0 ARCHITECTURE
Before a conversion is started, during the analog input sampling period, (tA), the sampled data comparator is zeroed.
As the comparator is being zeroed the channel assigned to
be the positive input is connected to the A/D’s input capacitor. (The assignment procedure is explained in the Pin Descriptions section.) This charges the input 32C capacitor of
the DAC to the positive analog input voltage. The switches
shown in the DAC portion of Figure 11 are set for this zeroing/acquisition period. The voltage at the input and output
of the comparator are at equilibrium at this time. When the
conversion is started, the comparator feedback switches
are opened and the 32C input capacitor is then switched to
the assigned negative input voltage. When the comparator
feedback switch opens, a fixed amount of charge is trapped
on the common plates of the capacitors. The voltage at the
input of the comparator moves away from equilibrium when
the 32C capacitor is switched to the assigned negative input
voltage, causing the output of the comparator to go high
(‘‘1’’) or low (‘‘0’’). The SAR next goes through an algorithm,
controlled by the output state of the comparator, that redistributes the charge on the capacitor array by switching the
voltage on one side of the capacitors in the array. The objective of the SAR algorithm is to return the voltage at the
input of the comparator as close as possible to equilibrium.
The switch position information at the completion of the
successive approximation routine is a direct representation
of the digital output. This data is then available to be shifted
on the D0 pin.
These devices have resistive reference ladders which draw
600 mA with a 2.5V reference voltage. The internal band
gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the device.
1.1 Getting Started with a Conversion
The ADC10831/2/4/8 need to be initialized after the power
supply voltage is applied. If CS is low when the supply voltage is applied then CS needs to be taken high for at least
tCS(H) (1 clock period). The data output after the first conversion is not valid.
1.2 Software and Hardware Power Up/Down
These devices have the capability of software or hardware
power down. Figures 5 and 6 show the timing diagrams for
hardware and software power up/down. In the case of hardware power down note that CS needs to be high for tPC
after PD is taken low. When PD is high the device is powered down. The total quiescent current, when powered
down, is typically 200 mA with the clock at 2.5 MHz and
3 mA with the clock off. The actual voltage level applied to a
digital input will affect the power consumption of the
20
FIGURE 11. Detailed Diagram of the ADC10838 DAC and Analog Multiplexer Stages
TL/H/11391 – 25
Applications Hints (Continued)
21
Applications Hints (Continued)
output noise can be obtained by increasing the output capacitance. A 100 mF capacitor will yield a typical noise floor
of 200 nV/0Hz. The pseudo-differential and differential multiplexer modes allow for more flexibility in the analog input
voltage range since the ‘‘zero’’ reference voltage is set by
the actual voltage applied to the assigned negative input
pin.
In a ratiometric system (Figure 13a) , the analog input voltage is proportional to the voltage used for the A/D reference. This voltage may also be the system power supply, so
VREF a can also be tied to AV a . This technique relaxes the
stability requirements of the system reference as the analog
input and A/D reference move together maintaining the
same output code for a given input condition.
For absolute accuracy (Figure 13b) , where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time- and temperature-stable voltage
source that has excellent initial accuracy. The LM4040,
LM4041 and LM185 references are suitable for use with the
ADC10831/2/4/8.
The minimum value of VREF (VREF e VREF a –VREFb) can
be quite small (see Typical Performance Characteristics) to
allow direct conversion of transducer outputs providing less
than a 5V output span. Particular care must be taken with
regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals VREF/
1024).
3.0 APPLICATIONS INFORMATION
3.1 Multiplexer Configuration
The design of these converters utilizes a sampled-data
comparator structure, which allows a differential analog input to be converted by the successive approximation routine.
The actual voltage converted is always the difference between an assigned ‘‘ a ’’ input terminal and a ‘‘b’’ input terminal. The polarity of each input terminal or pair of input
terminals being converted indicates which line the converter
expects to be the most positive.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, singleended, or pseudo-differential. Figure 12 illustrates the three
modes using the 4-channel MUX of the ADC10834. The
eight inputs of the ADC10838 can also be configured in any
of the three modes. The single-ended mode has CH0–CH3
assigned as the positive input with COM serving as the negative input. In the differential mode, the ADC10834 channel
inputs are grouped in pairs, CH0 with CH1 and CH2 with
CH3. The polarity assignment of each channel in the pair is
interchangeable. Finally, in the pseudo-differential mode
CH0 – CH3 are positive inputs referred to COM which is now
a pseudo-ground. This pseudo-ground input can be set to
any potential within the input common-mode range of the
converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package
can now handle ground-referred inputs and true differential
inputs as well as signals referred to a specific voltage.
The analog input voltages for each channel can range from
50 mV below Vb to 50 mV above V a e DV a e AV a
without degrading conversion accuracy. If the voltage on an
unselected channel exceeds these limits it may corrupt the
reading of the selected channel.
3.3 The Analog Inputs
Due to the sampling nature of the analog inputs, at the clock
edges short duration spikes of current will be seen on the
selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
1 kX since they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
may be used when the source impedance is very low without any degradation in performance.
In a true differential input stage, a signal that is common to
both ‘‘ a ’’ and ‘‘b’’ inputs is canceled. For the
ADC10831/2/4/8, the positive input of a selected channel
pair is only sampled once before the start of a conversion
during the acquisition time (tA). The negative input needs to
be stable during the complete conversion sequence because it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present
on the analog inputs will not be completely canceled and
will cause some conversion errors. For a sinusoid commonmode signal this error is:
VERROR(max) e VPEAK (2 q fCM) (tC)
3.2 Reference Considerations
The voltage difference between the VREF a and VREFb inputs defines the analog input voltage span (the difference
between VIN(Max) and VIN(Min)) over which 1023 positive
and 1024 negative possible output codes apply.
The value of the voltage on the VREF a or VREFb inputs
can be anywhere between AV a a 50 mV and GND
b 50 mV, so long as VREF a is greater than VREF b . The
ADC10831/2/4/8 can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable
of driving the minimum reference input resistance of 5 kX.
The
internal
2.5V
bandgap
reference
in
the
ADC10831/2/4/8 is available as an output on the VREFOut
pin. To ensure optimum performance this output needs to
be bypassed to ground with 100 mF aluminum electrolytic or
tantalum capacitor. The reference output can be unstable
with capacitive loads greater than 100 pF and less than
100 mF. Any capacitive loading less than 100 pF and
greater than 100 mF will not cause oscillation. Lower
where fCM is the frequency of the common-mode signal,
VPEAK is its peak voltage value, and tC is the A/D’s conversion time (tC e 12/fCLK). For example, for a 60 Hz common-mode signal to generate a (/4 LSB error (0.61 mV) with
a 4.8 ms conversion time, its peak value would have to be
approximately 337 mV.
22
Applications Hints (Continued)
4 Single-Ended
4 PsuedoDifferential
2 Differential
2 Single-Ended
and 1 Differential
TL/H/11391 – 26
FIGURE 12. Analog Input Multiplexer Options
a. Ratiometric Using the Internal Reference
TL/H/11391 – 27
b. Absolute Using a g 4.096V Span
*0.1% Resistors
TL/H/11391 – 28
FIGURE 13. Different Reference Configurations
23
Applications Hints (Continued)
3.4 Optional Adjustments
3.5 The Input Sample and Hold
3.4.1 Zero Error
The ADC10831/2/4/8’s sample/hold capacitor is implemented in the capacitor array. After the channel address is
loaded, the array is switched to sample the selected positive
analog input. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time
(tA) 4.5 clock cycles.
This acquisition window of 4.5 clock cycles is available to
allow the voltage on the capacitor array to settle to the positive analog input voltage. Any change in the analog voltage
on a selected positive input before or after the acquisition
window will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is determined by the RON (3 kX) of the multiplexer switches, the
stray input capacitance CS1 (3.5 pF) and the total array (CL)
and stray (CS2) capacitance (48 pF). For a large source
resistance the analog input can be modeled as an RC network as shown in Figure 14 . The values shown yield an
acquisition time of about 1.1 ms for 10-bit unipolar or 10-bit
plus sign accuracy with a zero-to-full-scale change in the
input voltage. External source resistance and capacitance
will lengthen the acquisition time and should be accounted
for. Slowing the clock will lengthen the acquisition time,
thereby allowing a larger external source resistance.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function (see Figure 1 ) and
can be measured by grounding the minus input and applying
a small magnitude voltage to the plus input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from
000 0000 0000 to 000 0000 0001 and the ideal (/2 LSB value
((/2 LSB e 2.0 mV for VREF e a 4.096V).
The zero error of the A/D does not require adjustment. If
the minimum analog input voltage value, VIN(Min), is not
ground, the effective ‘‘zero’’ voltage can be adjusted to a
convenient value. The converter can be made to output an
all zeros digital code for this minimum input voltage by biasing any minus input to VIN(Min). This is useful for either the
differential or pseudo-differential input channel configurations.
3.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the VREF
voltage (VREF e VREF a – VREFb) for a digital output code
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus (/2 LSB is applied to
selected plus input and the zero reference voltage at the
corresponding minus input should then be adjusted to just
obtain the 000 0000 0000 to 000 0000 0001 code transition.
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
Ð
TL/H/11391 – 29
FIGURE 14. Analog Input Model
The signal-to-noise ratio of an ideal A/D is the ratio of the
RMS value of the full scale input signal amplitude to the
value of the total error amplitude (including noise) caused
by the transfer function of the ideal A/D. An ideal 10-bit plus
sign A/D converter with a total unadjusted error of 0 LSB
would have a signal-to-(noise a distortion) ratio of about 68
dB, which can be derived from the equation:
S/(N a D) e 6.02(n) a 1.8
(
(VMAX b VMIN)
2n
where VMAX equals the high end of the analog input range,
VMIN equals the low end (the offset zero) of the analog
range. Both VMAX and VMIN are ground referred. The VREF
(VREF e VREF a b VREFb) voltage is then adjusted to provide a code change from 011 1111 1110 to 011 1111 1111.
Note, when using a pseudo-differential or differential multiplexer mode where VREF a and VREFb are placed within
the V a and GND range, the individual values of VREF and
VREFb do not matter, only the difference sets the analog
input voltage span. This completes the adjustment procedure.
VIN( a ) fs adj e VMAX b 1.5
where S/(N a D) is in dB and n is the number of bits.
24
Applications Hints (Continued)
(R1 a R2)//R3 s 1k
TL/H/11391 – 30
Note 1: Diodes are 1N914.
Note 2: The protection diodes should be able to withstand the output current of the op amp under current limit.
FIGURE 15. Protecting the Analog Inputs
25
Physical Dimensions inches (millimeters)
Order Number ADC10831CIWM
NS Package Number M16B
26
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10832CIWM and ADC10834CIWM
NS Package Number M20B
27
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10838CIWM
NS Package Number M24B
Order Number ADC10831CIN
NS Package Number N16E
28
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10832CIN and ADC10834CIN
NS Package Number N20A
29
ADC10831, ADC10832, ADC10834, ADC10838 10-Bit Plus Sign Serial I/O
A/D Converters with MUX, Sample/Hold and Reference
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10838CIN
NS Package Number N24A
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