AD ADG508AKRZ-REEL71 Cmos 4-/8-channel analog multiplexer Datasheet

CMOS 4-/8-Channel
Analog Multiplexers
ADG508A/ADG509A
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
44 V supply maximum rating
VSS to VDD analog signal range
Single-/dual-supply specifications
Wide supply range: 10.8 V to 16.5 V
Extended plastic temperature range: −40°C to +85°C
Low power dissipation: 28 mW maximum
Low leakage: 20 pA typical
Available in 16-lead DIP/SOIC and 20-lead PLCC/LCC
packages
Superior alternative to
DG508A, HI-508
DG509A, HI-509
ADG508A
D
S1
S8
00051-001
DECODER
A0 A1 A2 EN
Figure 1. ADG508A
ADG509A
DA
S1A
S4A
DB
S1B
S4B
A0
A1
EN
00051-002
DECODER
Figure 2. ADG509A
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG508A and ADG509A are CMOS monolithic analog
multiplexers with eight channels and dual four channels, respectively. The ADG508A switches one of eight inputs to a common
output, depending on the state of three binary addresses and an
enable input. The ADG509A switches one of four differential
inputs to a common differential output, depending on the state
of two binary addresses and an enable input. Both devices have
TTL and 5 V CMOS logic-compatible digital inputs.
1.
Single-/Dual-Supply Specifications with a Wide Tolerance.
The devices are specified in the 10.8 V to 16.5 V range for
both single and dual supplies.
2.
Extended Signal Range. The enhanced LC2MOS processing
results in a high breakdown and an increased analog signal
range of VSS to VDD.
3.
Break-Before-Make Switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
4.
Low Leakage. Leakage currents in the range of 20 pA make
these multiplexers suitable for high precision circuits.
The ADG508A and ADG509A are designed on an enhanced
LC2MOS process that gives an increased signal capability of VSS
to VDD and enables operation over a wide range of supply voltages.
The devices can comfortably operate anywhere in the 10.8 V to
16.5 V single- or dual-supply range. These multiplexers also
feature high switching speeds and low RON.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADG508A/ADG509A
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Functional Block Diagrams ............................................................. 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................8
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 10
Revision History ............................................................................... 2
Test Circuits ..................................................................................... 11
Specifications..................................................................................... 3
Single-Supply Octal DAC Application ........................................ 13
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 14
Single Supply ................................................................................. 5
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/09—Rev. C to Rev. D
Changes to Table 4 ............................................................................ 8
3/07—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Table 3 ............................................................................ 6
Inserted Table 4 ................................................................................. 7
Inserted Table 6 ................................................................................. 8
Changes to Figure 24 ...................................................................... 12
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 15
Rev. D | Page 2 of 16
ADG508A/ADG509A
SPECIFICATIONS
DUAL SUPPLY
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
RON
ADG508A/
ADG509A
K Version
−40°C to
+25°C +85°
ADG508A/
ADG509A
B Version
−40°C to
+25°C +85°C
ADG508A/
ADG509A
T Version
−55°C to
+25°C +125°C
Unit
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
VSS
VDD
280
VSS
VDD
V min
V max
Ω typ
450
300
600
400
450
300
600
400
450
600
300
RON Drift
RON Match
IS (Off ), Off Input Leakage
0.6
5
0.02
1
0.04
50
ID (Off), Off Output Leakage
1
1
0.04
1
1
100
50
ADG508A
ADG509A
ID (On), On Channel Leakage
ADG508A
ADG509A
IDIFF, Differential Off Output
Leakage (ADG509A Only)
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
CIN Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION 1
tOPEN1
tON (EN)1
tOFF (EN)1
OffF Isolation
0.6
5
0.02
100
50
25
0.6
5
0.02
1
0.04
50
1
1
0.04
1
1
100
50
2.4
0.8
1
400
100
50
25
Ω max
%/°C typ
% typ
nA typ
1
0.04
50
1
1
0.04
1
1
100
50
100
50
25
nA max
nA max
nA typ
nA max
nA max
nA max
8
8
8
200
200
200
ns typ
50
400
10
400
400
300
50
25
200
300
200
300
68
50
400
10
400
400
2.4
0.8
1
nA max
nA typ
V min
V max
μA max
pF max
300
50
25
200
300
200
300
68
2.4
0.8
1
Ω max
Ω max
300
50
25
200
300
200
300
68
50
Rev. D | Page 3 of 16
400
10
400
400
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
dB typ
dB min
Comments
−10 V ≤ VS ≤ +10 V, IDS = 1 mA;
see Figure 14
VDD = 15 V (±10%),
VSS = −15 V (±10%)
VDD = 15 V (±5%),
VSS = −15 V (±5%)
VS = 0, IDS = 1 mA
−10 V ≤ VS ≤ +10 V, IDS = 1 mA
V1 = ±10 V, V2 = m 10 V;
see Figure 15
V1 = ±10 V, V2 = m 10 V;
see Figure 16
V1 = V2 = ±10 V; see Figure 17
V1 = ±10 V, V2 = m 10 V;
see Figure 18
VIN = 0 to VDD
V1 = ±10 V, V2 = m 10 V;
see Figure 19
See Figure 20
See Figure 21
See Figure 21
VEN = 0.8 V, RL = 1 kΩ, CL = 15 pF,
VS = 7 V rms, f = 100 kHz
ADG508A/ADG509A
Parameter
CS (Off )
CD (Off )
ADG508A
ADG509A
QINJ, Charge Injection
POWER SUPPLY
IDD
ADG508A/
ADG509A
K Version
−40°C to
+25°C +85°
5
ADG508A/
ADG509A
B Version
−40°C to
+25°C +85°C
5
ADG508A/
ADG509A
T Version
−55°C to
+25°C +125°C
5
Unit
pF typ
Comments
VEN = 0.8 V
22
11
4
22
11
4
22
11
4
pF typ
pF typ
pC typ
VEN = 0.8 V
mA typ
mA max
μA typ
mA max
mW typ
mW max
VIN = VINL or VINH
0.6
0.6
1.5
ISS
20
20
0.2
Power Dissipation
10
1.5
20
0.2
10
28
1
0.6
1.5
0.2
10
28
Sample tested at 25°C to ensure compliance.
Rev. D | Page 4 of 16
28
RS = 0 Ω, VS = 0; see Figure 22
VIN = VINL or VINH
ADG508A/ADG509A
SINGLE SUPPLY
VDD = 10.8 V to 16.5 V, VSS = GND = 0 V, unless otherwise noted.
Table 2.
ADG508A/
ADG509A
K Version
−40°C to
+25°C +85°C
ADG508A/
ADG509A
B Version
−40°C to
+25°C +85°C
ADG508A/
ADG509A
T Version
−55°C to
+25°C +125°C
Unit
GND
VDD
GND
VDD
500
GND
VDD
GND
VDD
500
GND
VDD
RON
GND
VDD
500
V min
V max
Ω typ
700
0.6
5
0.02
1000
700
0.6
5
0.02
1000
700
0.6
5
0.02
1000
RON Drift
RON Match
IS (Off ), Off Input Leakage
1
0.04
50
1
0.04
50
1
0.04
50
ID (Off), Off Output Leakage
ADG508A
ADG509A
ID (On), On Channel Leakage
1
1
0.04
100
50
1
1
0.04
100
50
1
1
0.04
100
50
1
1
100
50
25
1
1
100
50
25
1
1
100
50
25
nA max
nA max
nA max
2.4
0.8
1
Parameter
ANALOG SWITCH
Analog Signal Range
ADG508A
ADG509A
IDIFF, Differential Off Output
Leakage (ADG509A Only)
DIGITAL CONTROL
VINH, Input High Voltage
VINL, Input Low Voltage
IINL or IINH
CIN Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION 1
tOPEN1
tON (EN)1
tOFF (EN)1
Off Isolation
CS (Off )
CD (Off )
ADG508A
ADG509A
QINJ, Charge Injection
2.4
0.8
1
nA max
nA typ
nA max
nA max
nA typ
8
8
8
V min
V max
μA max
pF max
300
300
300
ns typ
450
50
25
250
450
250
450
68
600
10
600
600
2.4
0.8
1
Ω max
%/°C typ
% typ
nA typ
450
50
25
250
450
250
450
68
600
10
600
600
450
50
25
250
450
250
450
68
600
10
600
600
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
dB typ
50
5
50
5
50
5
dB min
pF typ
22
11
4
22
11
4
22
11
4
pF typ
pF typ
pC typ
Rev. D | Page 5 of 16
Comments
GND ≤ VS ≤ 10 V, IDS = 0.5 mA;
see Figure 14
VS = 0, IDS = 0.5 mA
GND ≤ VS ≤ 10 V, IDS = 0.5 mA
V1 = 10 V/GND, V2 = GND/10 V;
see Figure 15
V1 = 10 V/GND, V2 = GND/10 V;
see Figure 16
V1 = V2 = 10 V/GND;
see Figure 17
V1 = 10 V/GND, V2 = GND/10 V;
see Figure 18
VIN = 0 to VDD
V1 = 10 V/GND, V2 = GND/10 V;
see Figure 19
See Figure 20
See Figure 21
See Figure 21
VEN = 0.8 V, RL = 1kΩ, CL = 15 pF,
VS = 3.5 V rms, f = 100 kHz
VEN = 0.8 V
VEN = 0.8 V
RS = 0 Ω, VS = 0 V; see Figure 22
ADG508A/ADG509A
Parameter
POWER SUPPLY
IDD
ADG508A/
ADG509A
K Version
−40°C to
+25°C +85°C
ADG508A/
ADG509A
B Version
−40°C to
+25°C +85°C
ADG508A/
ADG509A
T Version
−55°C to
+25°C +125°C
0.6
0.6
0.6
1.5
Power Dissipation
10
10
25
1
1.5
1.5
10
25
Sample tested at 25°C to ensure compliance.
Rev. D | Page 6 of 16
25
Unit
Comments
mA typ
mA max
mW typ
mW max
VIN = VINL or VINH
ADG508A/ADG509A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Voltage at S, D
Continuous Current, S or D
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle
Digital Inputs1
Voltage at A, EN
Power Dissipation (Any Package)
Up to 75°C
Derates Above 75°C by
Operating Temperature
Commercial (K Version)
Industrial (B Version)
Extended (T Version)
Storage Temperature Range
Ratings
44 V
32 V
–32 V
VSS − 2 V to VDD + 2 V or 20 mA,
whichever occurs first
20 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
40 mA
VSS − 4 V to VDD + 4 V or 20 mA,
whichever occurs first
470 mW
6 mW/°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
1
Overvoltage at A, EN, S, or D is clamped by diodes. Current should be limited
to the maximum rating shown in Table 3.
Rev. D | Page 7 of 16
ADG508A/ADG509A
VDD
5
12
S5
S3
6
11
S6
S4
7
10
S7
D
8
9
S8
5
16
NC
NC
6
15
S5
S2
7
14
S6
S3
8
ADG508A
TOP VIEW
(Not to Scale)
S2 7
S3 8
NC = NO CONNECT
Figure 3. ADG508A DIP, SOIC
9
10 11 12 13
Figure 4. ADG508A LCC
A0
NC
A1
A2
EN
A2
NC
A1
A0
S1
NC 6
00051-003
S2
VSS
V DD
19
ADG508A
TOP VIEW
(Not to Scale)
9
10
11
12
13
18
GND
17
VDD
16
NC
15
S5
14
S6
NC = NO CONNECT
Figure 5. ADG508A PLCC
Table 4. ADG508A Pin Function Description
Pin Number
DIP/SOIC
PLCC/LCC
1
2
2
3
Mnemonic
A0
EN
3
4
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A
N/A
N/A
N/A
5
7
8
9
10
12
13
14
15
17
18
19
20
1
6
11
16
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
NC
NC
NC
NC
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to ground.
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
No Connect.
No Connect.
No Connect.
No Connect.
Table 5. ADG508A Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
X
EN
0
1
1
1
1
1
1
1
1
X = don’t care.
Rev. D | Page 8 of 16
On Switch
None
1
2
3
4
5
6
7
8
00051-005
13
4
GND
17
20
S7
TOP VIEW
(Not to Scale)
S1
18
S1 5
1
S8
GND
3
V SS 4
2
PIN 1
IDENTIFIER
NC
ADG508A
14
VSS
3
4
D
A2
20 19
S4
15
1
00051-004
2
2
S7
EN
3
S8
A1
NC
16
D
1
S4
A0
EN
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
4
S1A
5
VSS
3
ADG509A
14
VDD
NC
6
S1A
4
13
S1B
S2A
7
S2A
5
TOP VIEW
(Not to Scale)
12
S2B
S3A
8
11
S3B
S3A
6
S4A
7
10
S4B
DA
8
9
DB
A0
NC
A1
GND
19
PIN 1
IDENTIFIER
17 S1B
ADG509A
15 S2B
14 S3B
S4A
00051-006
16 NC
TOP VIEW
(Not to Scale)
9
Figure 6. ADG509A DIP, SOIC
18 VDD
10
11
12
13
NC = NO CONNECT
Figure 7. ADG509A PLCC
Table 6. ADG509A Pin Function Description
Pin Number
DIP/SOIC PLCC/LCC
1
2
2
3
Mnemonic
A0
EN
3
4
VSS
4
5
6
7
8
9
10
11
12
13
14
15
16
N/A
N/A
N/A
N/A
5
7
8
9
10
12
13
14
15
17
18
19
20
1
6
11
16
S1A
S2A
S3A
S4A
DA
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
NC
NC
NC
NC
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to ground.
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Drain Terminal A. Can be an input or an output.
Drain Terminal B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
No Connect.
No Connect.
No Connect.
No Connect.
Table 7. ADG509A Truth Table
A1
X1
0
0
1
1
1
A0
X1
0
1
0
1
X
EN
0
1
1
1
1
On Switch Pair
None
1
2
3
4
X = don’t care.
Rev. D | Page 9 of 16
00051-008
VSS
GND
20
S4B
A1
15
1
DB
16
2
2
NC
1
3
DA
A0
EN
EN
ADG508A/ADG509A
ADG508A/ADG509A
TYPICAL PERFORMANCE CHARACTERISTICS
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700
700
600
600
VDD = +5V
VSS = –5V
500
400
VDD = +10.8V
VSS = –10.8V
200
VDD = 10.8V
VSS = 0V
400
300
VDD = 15V
VSS = 0V
200
VDD = +15V
VSS = –15V
0
–20
–15
–10
–5
100
0
5
VD [VS] (V)
10
15
20
0
–20
00051-009
100
Figure 8. RON as a Function of VD (VS): Dual-Supply Voltage, TA = 25°C
–15
–10
–5
0
5
VD [VS] (V)
10
15
20
00051-012
300
RON (Ω)
RON (Ω)
500
Figure 11. RON as a Function of VD (VS) Single-Supply Voltage, TA = 25°C
1.9
100
10
TRIGGER LEVEL (V)
1.8
ID (ON)
ID (OFF)
1
IS (OFF)
35
45
75
55
65
85
TEMPERATURE (°C)
95
105
115
125
1.5
Figure 9. Leakage Current as a Function of Temperature
(Note: Leakage Currents Reduce as the Supply Voltages Reduce)
5
6
7
8
9
10
11
12
13
14
15
SUPPLY VOLTAGE (V)
00051-013
25
1.7
1.6
0.1
00051-010
LEAKAGE CURRENT (nA)
VDD = +16.5V
VSS = –16.5V
Figure 12. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply,
TA = 25°C
800
1.0
700
0.8
500
IDD (mA)
tTRANSITION (ns)
600
SINGLE
SUPPLY
400
0.6
0.4
DUAL
SUPPLY
300
0.2
5
6
7
8
9
10
11
SUPPLY VOLTAGE (V)
12
13
14
15
Figure 10. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25°C
(Note: For VDD and lVSSl < 10 V; V1 = VDD/VSS, V2 = VSS/VDD. (see Figure 19))
Rev. D | Page 10 of 16
0
5
6
7
8
9
10 11 12 13
SUPPLY VOLTAGE (V)
14
15
16
17
Figure 13. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25°C
00051-014
100
00051-011
200
ADG508A/ADG509A
TEST CIRCUITS
Note: All digital input signal rise and fall times measured from 10% to 90% of 3 V. tR = tF = 20 ns.
IDS
VSS
VDD
VSS
IS (OFF)
VS
00051-015
V1
RON = V1/IDS
VDD
VSS
D
D
A
D
VSS
GND
V2
Figure 14. RON
EN
0.8V
GND
V1
Figure 16. ID (Off)
VDD
VSS
VDD
VSS
EN
VSS
VDD
VSS
0.8V
DA
A
ADG509A
D
ID (ON)
V1
50%
Figure 18. IDIFF = IDB (Off)
ADDRESS
DRIVE (VIN)
VDD
VSS
VDD
VSS
A2
0V
VIN
S1
A1
50Ω
A0
S8
ADG508A1
OUTPUT
90%
V1
S2–S7
90%
tTRANSITION
V2
GND
Figure 17. ID (On)
3V
A
2.4V
OUTPUT
D
EN
GND
tTRANSITION
V2
1MΩ
1SIMILAR CONNECTION FOR ADG509A.
Figure 19. Switching Time of Multiplexer, tTRANSITION
Rev. D | Page 11 of 16
35pF
00051-020
V2
00051-018
GND
V1
EN
00051-019
DB
A
2.4V
ID (OFF)
0.8V
A
V2
Figure 15. IS (Off)
VDD
EN
00051-016
S
VDD
00051-017
V1
VDD
ADG508A/ADG509A
ADDRESS
DRIVE (VIN)
0V
VSS
VDD
VSS
A2
VIN
S1
A1
50Ω
A0
50%
5V
S2–S7
S8
ADG508A1
OUTPUT
2.4V
tOPEN
OUTPUT
D
EN
1kΩ
GND
35pF
00051-021
3V
VDD
1SIMILAR CONNECTION FOR ADG509A.
Figure 20. Break-Before-Make Delay, tOPEN
0V
VDD
VSS
A2
ENABLE
DRIVE (VIN)
50%
VSS
S1
A1
A0
90%
tON
(EN)
OUTPUT
10%
tOFF
(EN)
ADG508A1
OUTPUT
D
EN
VIN
5V
S2–S8
50Ω
1kΩ
GND
35pF
00051-022
3V
VDD
1SIMILAR CONNECTION FOR ADG509A.
Figure 21. Enable Delay, tON (EN), tOFF (EN)
VDD
VSS
VDD
VSS
A0
VIN
3V
A1
0V
A2
ADG508A1
RS
QINJ = CL × ΔVO
S1
D
EN
VS
VIN
GND
CL
1nF
VO
50Ω
1SIMILAR
Figure 22. Charge Injection
Rev. D | Page 12 of 16
CONNECTION FOR ADG509A.
00051-023
ΔVO
VO
ADG508A/ADG509A
SINGLE-SUPPLY OCTAL DAC APPLICATION
The following circuit shows the ADG508A connected as a demultiplexer to provide eight separate, digitally programmable voltages
(0 V to 10 V) from the AD7245A. The AD7245A is a complete
12-bit, voltage output DAC with output amplifier and Zener
voltage reference on a monolithic CMOS chip.
The entire system operates from a single 15 V power supply.
The ADG508A is ideally suited for the application because it
has both low charge injection and IS (OFF) leakage current.
15V
15V
DB11
RFB
DB0
VOUT
CS
WR
LDAC
CLR
DGND
1/4 TLC274
0.01µF
ADG508A
ROFS
VSS
VOUT1
S1
D
AD7245A
15V
VDD
EN
VDD
GND
15V
VSS
AGND
VOUT8
S8
REF OUT
A0
A1
A2
0.01µF
1/4 TLC274
10Ω
+
10µF
00051-024
0.1µF
Figure 23. ADG508A in a Single-Supply Octal DAC Circuit
Rev. D | Page 13 of 16
ADG508A/ADG509A
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
9
1
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.210 (5.33)
MAX
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 24. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-16)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN
0.098 (2.49) MAX
16
9
1
PIN 1
8
0.310 (7.87)
0.220 (5.59)
0.100 (2.54) BSC
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 25. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
Rev. D | Page 14 of 16
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
ADG508A/ADG509A
10.00 (0.3937)
9.80 (0.3858)
4.00 (0.1575)
3.80 (0.1496)
9
16
1
6.20 (0.2441)
5.80 (0.2283)
8
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
060606-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22 )
0.042 (1.07)
3
0.048 (1.22)
0.042 (1.07)
4
0.056 (1.42)
0.042 (1.07)
PIN 1
IDENTIFIER
18
TOP VIEW
(PINS DOWN)
8
0.020
(0.51)
R
0.20 (0.51)
MIN
19
9
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
14
13
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.03)
SQ
0.385 (9.78)
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
R
0.025 (0.64)
0.120 (3.04)
0.090 (2.29)
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 27. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.088 (2.24)
0.054 (1.37)
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
0.075 (1.91)
REF
0.095 (2.41)
0.075 (1.90)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.055 (1.40)
0.045 (1.14)
19
18
3
20
4
0.028 (0.71)
0.022 (0.56)
1
BOTTOM
VIEW
0.050 (1.27)
BSC
8
14
13
9
45° TYP
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
Rev. D | Page 15 of 16
022106-A
0.100 (2.54)
0.064 (1.63)
ADG508A/ADG509A
ORDERING GUIDE
Model
ADG508AKN
ADG508AKNZ 1
ADG508AKR
ADG508AKR-REEL
ADG508AKR-REEL7
ADG508AKRZ1
ADG508AKRZ-REEL1
ADG508AKRZ-REEL71
ADG508AKP
ADG508AKP-REEL
ADG508AKPZ1
ADG508AKPZ-REEL1
ADG508ABQ
ADG508ATQ
ADG508ATE
ADG508ABCHIPS
ADG508ATCHIPS
ADG509AKN
ADG509AKNZ1
ADG509AKR
ADG509AKR-REEL
ADG509AKR-REEL7
ADG509AKRZ-REEL1
ADG509AKRZ-REEL71
ADG509AKP
ADG509AKP-REEL
ADG509AKPZ1
ADG509AKPZ-REEL1
ADG509ABQ
ADG509ATQ
ADG509ATQ/883B
ADG509ABCHIPS
ADG509ATCHIPS
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
Package Description
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
16-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Ceramic Dual In-Line Package [CERDIP]
20-Terminal Ceramic Leadless Chip Carrier [LCC]
Package Option
N-16
N-16
R-16
R-16
R-16
R-16
R-16
R-16
P-20
P-20
P-20
P-20
Q-16
Q-16
E-20-1
DIE
DIE
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
−55°C to +125°C
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
20-Lead Plastic Leaded Chip Carrier [PLCC]
16-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Ceramic Dual In-Line Package [CERDIP]
DIE
DIE
Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00051-0-7/09(D)
Rev. D | Page 16 of 16
N-16
N-16
R-16
R-16
R-16
R-16
R-16
P-20
P-20
P-20
P-20
Q-16
Q-16
Q-16