a Microprocessors Supervisory Circuit in 4-Lead SOT-143 ADM811/ADM812 FEATURES Superior Upgrade for MAX811/MAX812 Specified Over Temperature Low Power Consumption (5 A Typ) Precision Voltage Monitor: +3 V, +3.3 V, +5 V Options Reset Assertion Down to 1 V VCC 140 ms Min Power-On Reset Logic Low RESET Output (ADM811) Logic High RESET Output (ADM812) Built-In Manual Reset FUNCTIONAL BLOCK DIAGRAM ADM811/ADM812 VCC RESET GENERATOR VREF MR RESET/RESET DEBOUNCE GND APPLICATIONS Microprocessor Systems Controllers Intelligent Instruments Automotive Systems Safety Systems Portable Instruments GENERAL DESCRIPTION The ADM811/ADM812 are reliable voltage monitoring devices suitable for use in most voltage monitoring applications. The ADM811/ADM812 are designed to monitor five different voltages, each allowing for a 5% or 10% degradation of standard PSU voltages before a reset occurs. These voltages have been selected for the effective monitoring of +3 V, +3.3 V and +5 V supply voltage levels. Included in this circuit is a debounced Manual Reset input. Reset can be activated using an electrical switch (or an input from another digital device) or by a degradation of the supply voltage. The Manual Reset function is very useful especially if the circuit in which the ADM811/ADM812 is operating enters into a state that can only be detected by the user. Allowing the user to manually reset a system can reduce the damage or danger that could be otherwise caused by an out-of-control or locked up system. VCC VCC mP SYSTEM ADM811 MR RESET RESET 100kV GND GND Figure 1. Typical Operating Circuit REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. 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Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ADM811/ADM812–SPECIFICATIONS Parameter SUPPLY Voltage Min 1.0 1.2 Current RESET VOLTAGE THRESHOLD ADM81_L ADM81_L ADM81_M ADM81_M ADM81_T ADM81_T ADM81_S ADM81_S ADM81_R ADM81_R 4.54 4.50 4.30 4.25 3.03 3.00 2.88 2.85 2.58 2.55 RESET THRESHOLD TEMPERATURE COEFFICIENT VCC TO RESET/RESET DELAY RESET ACTIVE TIMEOUT PERIOD MANUAL RESET Minimum Pulsewidth Glitch Immunity RESET/RESET Propagation Delay Pull-Up Resistance The Manual Reset Circuit Will Act On An Input Rising Above An Input Falling Below An Input Rising Above An Input Falling Below RESET Output Voltage Low (ADM812R/S/T) Low (ADM812L/M) High (ADM812R/S/T/L/M) Low (ADM811R/S/T) Low (ADM811L/M) Low (ADM811R/S/T/L/M) High (ADM811R/S/T) High (ADM811L/M) Typ (VCC = Full Operating Range, TA = TMIN to TMAX, VCC typ = +5 V for L/M, +3.3 V for T/S, +3 V for R Models unless otherwise noted) Max Units Test Conditions/Comments 5.5 TA = 0°C to +70°C TA = –40°C to +85°C VCC < +5.5 V, ADM81_L/M, IOUT = 0 A VCC < +3.6 V, ADM81_R/S/T, I OUT = 0 A TA = +25°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C TA = +25°C TA = –40°C to +85°C 8 5 15 10 V V µA µA 4.63 4.72 4.75 4.46 4.50 3.14 3.15 2.98 3.00 2.68 2.70 V V V V V V V V V V 4.38 3.08 2.93 2.63 30 ppm/°C 40 20 µs µs VOD = 125 mV, ADM81_L/M VOD = 125 mV, ADM81_R/S/T 560 700 ms ms VCC = VTH(MAX) (ADM811-3T Only) 30 µs ns µs kΩ 140 300 10 10 100 0.5 20 2.3 0.7 × VCC 0.8 0.25 × VCC 0.3 0.4 0.8 VCC 0.3 0.4 0.3 0.8 VCC VCC – 1.5 V V V V VCC > VTH(MAX), ADM81_L/M VCC > VTH(MAX), ADM81_L/M VCC > VTH(MAX), ADM81_R/S/T VCC > VTH(MAX), ADM81_R/S/T V V V V V V V V VCC = VTH(MAX), ISINK = 1.2 mA VCC = VTH(MAX), ISINK = 3.2 mA 1.8 V < VCC < VTH(MIN), ISOURCE = 150 µA VCC = VTH(MIN), ISINK = 1.2 mA VCC = VTH(MIN), ISINK = 3.2 mA VCC > 1.0 V, ISINK = 50 µA VCC > VTH(MAX), ISOURCE = 500 µA VCC > VTH(MAX), ISOURCE = 800 µA Specifications subject to change without notice. Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +160°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV ABSOLUTE MAXIMUM RATINGS* (Typical values are at T A = +25°C unless otherwise noted) Terminal Voltage (With Respect to Ground) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V All Other Inputs . . . . . . . . . . . . . . . . .–0.3 V to VCC + 0.3 V Input Current VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output Current RESET, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation (TA = +70°C) RT-4, SOT-143 . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW Derate by 4 mW/°C above +70°C θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 330°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. –2– REV. 0 ADM811/ADM812 PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Pin Mnemonic 1 2 2 3 4 Function GND 1 GND 0 V. Ground reference for all signals. RESET (ADM811) Active Low Logic Output. RESET remains low while VCC is below the reset threshold or when MR is low, RESET then remains low for at least 140 ms (at least 300 ms for the ADM811-3T) after VCC rises above the reset threshold. RESET (ADM812) Active High Logic Output. RESET remains high while VCC is below the reset threshold or when MR is low, RESET then remains high for 240 ms (typical) after VCC rises above the reset threshold. MR Manual Reset. This active low debounced input will ignore input pulses of 100 ns or less (typical) and is guaranteed to accept input pulses of greater than 10 µs. Leave floating when not used. +3 V, +3.3 V or +5 V monitored VCC supply voltage. ADM811/ ADM812 4 VCC TOP VIEW RESET/RESET 2 (Not to Scale) 3 MR ORDERING GUIDE Model* Reset Threshold Temperature Range Brand Information Quantity ADM811LART-REEL ADM811LART-REEL-7 ADM811MART-REEL ADM811MART-REEL-7 ADM811TART-REEL ADM811TART-REEL-7 ADM811-3TART-REEL ADM811-3TART-RL7 ADM811SART-REEL ADM811SART-REEL-7 ADM811RART-REEL ADM811RART-REEL-7 4.63 V 4.63 V 4.38 V 4.38 V 3.08 V 3.08 V 3.08 V 3.08 V 2.93 V 2.93 V 2.63 V 2.63 V –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C MBV MBV MBT MBT MBG MBG MB3 MB3 MBE MBE MBB MBB 10K 3K 10K 3K 10K 3K 10K 3K 10K 3K 10K 3K ADM812LART-REEL ADM812LART-REEL-7 ADM812MART-REEL ADM812MART-REEL-7 ADM812TART-REEL ADM812TART-REEL-7 ADM812SART-REEL ADM812SART-REEL-7 ADM812RART-REEL ADM812RART-REEL-7 4.63 V 4.63 V 4.38 V 4.38 V 3.08 V 3.08 V 2.93 V 2.93 V 2.63 V 2.63 V –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C MCV MCV MCT MCT MCG MCG MCE MCE MCB MCB 10K 3K 10K 3K 10K 3K 10K 3K 10K 3K *Only available in reels. Parts in bold are ex-stock, please contact factory for availability. REV. 0 –3– ADM811/ADM812 –Typical Performance Characteristics 10 12 9 IDD @ VCC = 5.5V IDD @ VCC = 5.5V 10 8 7 IDD @ VCC = 3V IDD – mA IDD – mA 8 6 IDD @ VCC = 3V 6 5 4 4 3 IDD @ VCC = 1V 2 IDD @ VCC = 1V 2 1 900 800 TEMPERATURE – 8C 125 120 110 90 100 85 80 70 60 125 120 110 100 90 85 80 Figure 6. Power-Down RESET Delay vs. Temperature (ADM81_L/M) 1.007 289 1.006 284 ADM81_L/M NORMALIZED RESET THRESHOLD 279 274 269 264 259 254 ADM81_R/S/T 249 1.005 1.004 1.003 1.002 1.001 1.000 0.999 0.998 0.997 125 120 110 90 100 85 80 70 60 50 40 30 25 20 0 10 –10 –20 –30 0.995 125 120 110 100 90 85 80 70 60 50 40 30 25 20 10 0 –10 –20 –30 –40 0.996 –40 POWER-UP RESET TIMEOUT – ms 50 TEMPERATURE – 8C Figure 3. Power-Down RESET Delay vs. Temperature (ADM81__R/S/T) 244 70 –20 –40 VOD = 200mV –30 0 125 120 110 100 90 85 80 70 60 50 40 30 25 20 10 0 –40 –20 VOD = 200mV –30 VOD = 125mV 100 60 VOD = 125mV 200 50 200 300 40 VOD = 20mV VOD = 20mV 400 30 400 500 25 500 600 20 600 700 10 700 0 800 –10 POWER-DOWN RESET DELAY – ms 900 –10 POWER-DOWN RESET DELAY – ms 1000 0 40 Figure 5. Supply Current vs. Temperature (ADM81_L/M) Figure 2. Supply Current vs. Temperature (ADM81_R/S/T) 100 30 TEMPERATURE – 8C TEMPERATURE – 8C 300 25 20 0 10 –10 –20 –40 125 120 110 90 100 85 80 70 60 50 40 30 25 20 0 10 –10 –20 –30 –40 –30 0 0 TEMPERATURE – 8C TEMPERATURE – 8C Figure 7. Reset Threshold Deviation vs. Temperature Figure 4. Power-Up Reset Timeout vs. Temperature –4– REV. 0 ADM811/ADM812 CIRCUIT INFORMATION GLITCH IMMUNITY RESET THRESHOLDS The ADM811/ADM812 contain internal filtering circuitry providing glitch immunity from fast transient glitches on the power supply line. The reset output provides a RESET (for the ADM811) or a RESET (for the ADM812) output to the microprocessor whenever the VCC input is below the reset threshold. The actual reset threshold is dependant on whether a L, M, T, S or R suffix is used. Please refer to Table I. VCC RESET Table I. Reset Threshold Options Model RESET Threshold ADM811LART ADM811MART ADM811TART ADM811-3TART ADM811SART ADM811RART 4.63 V 4.38 V 3.08 V 3.08 V 2.93 V 2.63 V ADM812LART ADM812MART ADM812TART ADM812SART ADM812RART 4.63 V 4.38 V 3.08 V 2.93 V 2.63 V VREF VREF t1 t1 t1 = RESET TIME = 240ms TYPICAL VREF = RESET VOLTAGE THRESHOLD Figure 8. Power Fail RESET Timing INTERFACING TO OTHER DEVICES Output The ADM811/ADM812 series is designed to integrate with as many devices as possible. One feature of the ADM811/ ADM812 is the reset output, which is directly proportional to VCC (this is guaranteed only while VCC is greater than 1 V). This enables the part to be used in both 3 V and 5 V or any nominal voltage within the minimum and maximum specifications for VCC. THE BENEFITS OF A VERY ACCURATE RESET THRESHOLD Parts in bold type are ex-stock, please contact factory for availability. Because the ADM811/ADM812 series can operate effectively even when there are large degradations of the supply voltages, the possibility of a malfunction during a power failure is greatly reduced. Another advantage of the ADM811/ADM812 series is its very accurate internal voltage reference circuit. Combined, these benefits produce an exceptionally reliable Microprocessor Supervisory Circuit. RESET OUTPUT On power-up and after VCC rises above the reset threshold, an internal timer holds the reset output active for 240 ms (typical). This is intended as a power-on reset signal for the processor. It allows time for both the power supply and the microprocessor to stabilize after power-up. If a power supply brownout or interruption occurs, the reset output is similarly activated and remains active for 240 ms (typical) after the supply recovers. This allows time for the power supply and microprocessor to stabilize. VCC VCC The ADM811 provides an active low reset output (RESET) while the ADM812 provides an active high output (RESET). ADM811 RESET During power-down of the ADM811, the RESET output remains valid (low) with VCC as low as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the supply falls and also ensures that no spurious activity can occur via the µP as it powers up. GND Figure 9. Ensuring a Valid RESET Output Down to VCC = 0 V MANUAL RESET ENSURING A VALID RESET OUTPUT DOWN TO VCC = 0 V The ADM811/ADM812 is equipped with a manual reset input. This input is designed to operate in a noisy environment where unwanted glitches could be induced. These glitches could be produced by the bouncing action of a switch contact or where a Manual Reset switch may be located some distance away from the circuit (the cabling of which may pickup noise). When VCC falls below 0.8 V, ADM811s RESET no longer sinks current. Therefore, a high impedance CMOS logic input connected to RESET may drift to undetermined logic levels. To eliminate this problem a 100 kΩ resistor should be connected from RESET to ground. The Manual Reset input is guaranteed to ignore logically valid inputs which are faster than 100 ns and accept inputs longer in duration than 10 µs. REV. 0 VREF VREF –5– ADM811/ADM812 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 4-Lead Plastic Surface Mount Package (SOT-143) 4 3 0.055 (1.40) 0.047 (1.20) 0.098 (2.50) 0.083 (2.10) 1 78 0.004 (0.10) 0.001 (0.03) 2 0.080 (2.03) 0.070 (1.78) 0.120 (3.05) 0.105 (2.67) SEATING 0.037 (0.94) PLANE 0.030 (0.77) 0.040 (1.02) 0.031 (0.79) 0.021 (0.54) 0.015 (0.38) 0.0059 (0.089) 0.0035 (0.15) 88 08 0.010 (0.25) 0.005 (0.13) PRINTED IN U.S.A. PIN 1 C3140–8–3/99 0.079 (2.00) 0.071 (1.80) –6– REV. 0