AD ADM8694 Microprocessor supervisory circuit Datasheet

a
FEATURES
Upgrade for ADM690/ADM695, MAX690–MAX695
Specified Over Temperature
Low Power Consumption (0.7 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V VCC
Low Switch On-Resistance 0.7 V Normal,
7 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
400 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (3 ns)
Voltage Monitor for Power Fail
Available in TSSOP Package
Microprocessor
Supervisory Circuits
ADM8690–ADM8695
FUNCTIONAL BLOCK DIAGRAMS
VBATT
VOUT
VCC
RESET
GENERATOR2
4.65V1
WATCHDOG
INPUT (WDI)
WATCHDOG
TRANSITION DETECTOR
(1.6s)
ADM8690
ADM8692
ADM8694
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.3V
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
RESET
1VOLTAGE
DETECTOR = 4.65V (ADM8690, ADM8694)
4.40V (ADM8692)
2RESET PULSE WIDTH = 50ms (AD8690, ADM8692)
200ms (ADM8694)
BATT ON
VBATT
GENERAL DESCRIPTION
The ADM8690–ADM8695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection and power failure warning.
The complete family provides a variety of configurations to satisfy most microprocessor system requirements.
The ADM8690, ADM8692 and ADM8694 are available in
8-pin DIP packages and provide:
1. Power-on reset output during power-up, power-down and
brownout conditions. The RESET output remains operational with VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than +5 V.
The ADM8691, ADM8693 and ADM8695 are available in
16-pin DIP and small outline packages (including TSSOP) and
provide three additional functions:
1. Write protection of CMOS RAM or EEPROM.
2. Adjustable reset and watchdog timeout periods.
3. Separate watchdog timeout, backup battery switchover, and
low VCC status outputs.
ADM8691
ADM8693
ADM8695
VCC
CEIN
VOUT
CEOUT
LOW LINE
4.65V1
RESET
OSC IN
OSC SEL
WATCHDOG
INPUT (WDI)
RESET AND
WATCHDOG
TIMEBASE
RESET
GENERATOR
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
TIMER
POWER FAIL
INPUT (PFI)
WATCHDOG
OUTPUT (WDO)
POWER FAIL
OUTPUT (PFO)
1.3V
1VOLTAGE
RESET
DETECTOR = 4.65V (ADM8691, ADM8695)
4.40V (ADM8693)
The ADM8690–ADM8695 family is fabricated using an advanced epitaxial CMOS process combining low power consumption (0.7 mW), extremely fast Chip Enable gating (3 ns)
and high reliability. RESET assertion is guaranteed with VCC as
low as 1 V. In addition, the power switching circuitry is designed for minimal voltage drop thereby permitting increased
output current drive of up to 100 mA without the need of an
external pass transistor.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
(VCC = Full Operating Range, VBATT = +2.8 V, TA = TMIN to
MAX unless otherwise noted)
ADM8690–ADM8695–SPECIFICATIONS T
Parameter
BATTERY BACKUP SWITCHING
VCC Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
VBATT Operating Voltage Range
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
VOUT Output Voltage
VOUT in Battery Backup Mode
Supply Current (Excludes IOUT)
Supply Current in Battery Backup Mode
Battery Standby Current
(+ = Discharge, – = Charge)
Battery Switchover Threshold
VCC – VBATT
Battery Switchover Hysteresis
BATT ON Output Voltage
BATT ON Output Short Circuit Current
Min
Max
Units
4.75
4.5
5.5
5.5
V
V
2.0
2.0
VCC – 0.005 VCC – 0.0025
VCC – 0.2
VCC – 0.125
VBATT – 0.005 VBATT – 0.002
140
0.4
4.25
4.0
200
1
V
V
V
V
V
µA
µA
–0.1
+0.02
70
50
20
0.3
0.5
RESET AND WATCHDOG TIMER
Reset Voltage Threshold
ADM8690, ADM8691, ADM8694, ADM8695
ADM8692, ADM8693
Reset Threshold Hysteresis
Reset Timeout Delay
ADM8690, ADM8691, ADM8692, ADM8693
ADM8694, ADM8695
Watchdog Timeout Period, Internal Oscillator
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
RESET Output Voltage @ VCC = +1 V
RESET, LOW LINE Output Voltage
Typ
55
2.5
25
4.5
4.25
4.65
4.4
40
4.73
4.48
V
V
mV
35
140
1.0
70
3840
768
50
50
200
1.6
100
4064
1011
70
280
2.25
140
4097
1025
4
0.05
20
0.4
ms
ms
s
ms
Cycles
Cycles
ns
mV
V
V
V
V
µA
mA
3.5
RESET, WDO Output Voltage
Output Short Circuit Source Current
Output Short Circuit Sink Current
WDI Input Threshold
Logic Low
Logic High
WDI Input Current
POWER FAIL DETECTOR
PFI Input Threshold
PFI Input Current
PFO Output Voltage
PFO Short Circuit Source Current
PFO Short Circuit Sink Current
0.4
3.5
1
10
25
25
IOUT = 1 mA
IOUT ≤ 100 mA
IOUT = 250 µA, VCC < VBATT – 0.2 V
IOUT = 100 µA
VCC = 0 V, VBATT = 2.8 V
5.5 V > VCC > VBATT + 0.2 V
TA = +25°C
Power-Up
Power-Down
ISINK = 3.2 mA
BATT ON = VOUT = 4.5 V Sink Current
BATT ON = 0 V Source Current
OSC SEL = HIGH
OSC SEL = HIGH
Long Period
Short Period
Long Period
Short Period
VIL = 0.4, VIH = 3.5 V
ISINK = 10 µA, VCC = 1 V
ISINK = 1.6 mA, VCC = 4.25 V
ISOURCE = 1 µA
ISINK = 1.6 mA
ISOURCE = 1 µA
Note 1
0.8
3.5
1
–1
10
–10
1.25
–25
1.3
± 0.01
1.35
+25
0.4
3.5
1
3
25
CHIP ENABLE GATING
CEIN Threshold
25
0.8
3.0
CEIN Pull-Up Current
CEOUT Output Voltage
3
0.4
VOUT – 1.5
VOUT – 0.05
CE Propagation Delay
µA
mV
mV
mV
V
mA
µA
Test Conditions/Comments
3
7
–2–
V
V
µA
µA
WDI = VOUT
WDI = 0 V
V
nA
V
V
µA
mA
VCC = +5 V
V
V
µA
V
V
V
ns
VIL
VIH
ISINK = 3.2 mA
ISOURCE = 1 µA
PFI = Low, PFO = 0 V
PFI = High, PFO = VOUT
ISINK = 3.2 mA
ISOURCE = 3.0 mA
ISOURCE = 1 µA, VCC = 0 V
REV. 0
ADM8690–ADM8695
Parameter
OSCILLATOR
OSC IN Input Current
OSC SEL Input Pull-Up Current
OSC IN Frequency Range
OSC IN Frequency with External Capacitor
Min
Typ
Max
±2
5
0
500
4
Units
Test Conditions/Comments
µA
µA
kHz
kHz
OSC SEL = 0 V
OSC SEL = 0 V, C OSC = 47 pF
NOTE
1
WDI is a three level input which is internally biased to 38% of V CC and has an input impedance of approximately 5 MΩ.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VOUT + 0.5 V
Input Current
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 400 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W
Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W
Power Dissipation, RU-16 DIP . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W
Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . . 600 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Model
Temperature Range
Package Options*
ADM8690AN
ADM8690ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM8691AN
ADM8691ARN
ADM8691ARW
ADM8691ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
R-16
RU-16
ADM8692AN
ADM8692ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM8693AN
ADM8693ARN
ADM8693ARW
ADM8693ARU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16A
R-16
RU-16
ADM8694AN
ADM8694ARN
–40°C to +85°C
–40°C to +85°C
N-8
SO-8
ADM8695AN
ADM8695ARW
–40°C to +85°C
–40°C to +85°C
N-16
R-16
*N = Plastic DIP; R = Small Outline (Wide); R = Small Outline (Narrow);
RU = Thin Shrink Small Outline; SO = Small Outline.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8690–ADM8695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADM8690–ADM8695
PIN FUNCTION DESCRIPTION
Mnemonic
Function
VCC
Power Supply Input: +5 V Nominal.
VBATT
Backup Battery Input.
VOUT
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT
can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
GND
0 V. Ground reference for all signals.
RESET
Logic Output. RESET goes low if
1. VCC falls below the Reset Threshold
2. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/
ADM8695) after VCC returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is
enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the ADM8691/ADM8693/
ADM8695 as shown in Table I. The RESET output has an internal 3 µA pull up, and can either connect
to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.
WDI
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
period, RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO
goes low. Connect PFI to GND or VOUT when not used.
PFO
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The
comparator is turned off and PFO goes low when VCC is below VBATT.
CEIN
Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and 6.
BATT ON
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT
is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of VOUT.
LOW LINE
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises
above the reset threshold.
RESET
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull-up (see Table I).
OSC IN
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watchdog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM8691/ADM8693) or 200 ms typ (ADM8695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
WDO
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.
–4–
REV. 0
ADM8690–ADM8695
PIN CONFIGURATIONS
VBATT 1
VOUT 1
VCC 2
GND 3
ADM8690
ADM8692
ADM8694
8 VBATT
VOUT 2
7 RESET
VCC 3
6 WDI
GND 4
TOP VIEW
PFI 4 (Not to Scale) 5 PFO
16 RESET
15 RESET
ADM8691
ADM8693
ADM8695
14 WDO
13 CEIN
TOP VIEW 12 CEOUT
(Not to Scale)
6
11 WDI
LOW LINE
BATT ON 5
10 PFO
OSC IN 7
OSC SEL 8
9 PFI
PRODUCT SELECTION GUIDE
Part
Number
Nominal Reset
Time
Nominal VCC
Reset Threshold
Nominal Watchdog
Timeout Period
Battery Backup
Switching
Base Drive
Ext PNP
Chip Enable
Signals
ADM8690
ADM8691
ADM8692
ADM8693
ADM8694
ADM8695
50 ms
50 ms or ADJ
50 ms
50 ms or ADJ
200 ms
200 ms or ADJ
4.65 V
4.65 V
4.4 V
4.4 V
4.65 V
4.65 V
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
1.6 s
100 ms, 1.6 s, ADJ
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
CIRCUIT INFORMATION
Battery Switchover Section
If the continuous output current requirement at VOUT exceeds
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel with
the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the external transistor.
The battery switchover circuit compares VCC to the VBATT
input, and connects VOUT to whichever is higher. Switchover
occurs when VCC is 50 mV higher than VBATT as VCC falls, and
when VCC is 70 mV greater than VBATT as VCC rises. This
20 mV of hysteresis prevents repeated rapid switching if VCC
falls very slowly or remains nearly equal to the battery voltage.
A 7 Ω MOSFET switch connects the VBATT input to VOUT during battery backup. This MOSFET has very low input-to-output differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low power
CMOS circuitry. The supply current in battery back up is typically 0.4 µA.
VCC
VOUT
VBATT
The ADM8690/ADM8691/ADM8694/ADM8695 operates with
battery voltages from 2.0 V to 4.25 V, and the ADM8692/
ADM8693 operates with battery voltages from 2.0 V to 4.0 V.
High value capacitors, either standard electrolytic or the farad
size double layer capacitors, can also be used for short-term
memory backup. A small charging current of typically 10 nA
(0.1 µA max) flows out of the VBATT terminal. This current is
useful for maintaining rechargeable batteries in a fully charged
condition. This extends the life of the backup battery by compensating for its self discharge current. Also note that this current poses no problem when lithium batteries are used for
backup since the maximum charging current (0.1 µA) is safe for
even the smallest lithium cells.
GATE DRIVE
100
mV
700
mV
INTERNAL
SHUTDOWN SIGNAL
WHEN
VBATT > (VCC + 0.7V)
BATT ON
(ADM8690,
ADM8695)
Figure 1. Battery Switchover Schematic
During normal operation, with VCC higher than VBATT, VCC is
internally switched to VOUT via an internal PMOS transistor
switch. This switch has a typical on-resistance of 0.7 Ω and can
supply up to 100 mA at the VOUT terminal. VOUT is normally
used to drive a RAM memory bank which may require instantaneous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to VOUT. The capacitor
will provide the peak current transients to the RAM. A capacitance value of 0.1 µF or greater may be used.
REV. 0
If the battery switchover section is not used, VBATT should be
connected to GND and VOUT should be connected to VCC.
–5–
ADM8690–ADM8695
Power Fail RESET Output
Watchdog Timer RESET
RESET is an active low output that provides a RESET signal
to the Microprocessor whenever VCC is at an invalid level.
When VCC falls below the reset threshold, the RESET output
is forced low. The nominal reset voltage threshold is 4.65 V
(ADM8690/ADM8691/ADM8694/ADM8695) or 4.4 V
(ADM8692/ADM8693).
The watchdog timer circuit monitors the activity of the microprocessor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
ADM8690/ADM8692/ADM8694. The ADM8691/ADM8693/
ADM8695 may be configured for either a fixed “short” 100 ms
or a “long” 1.6 second timeout period or for an adjustable
timeout period. If the “short” period is selected, some systems
may be unable to service the watchdog timer immediately after a
reset, so the ADM8691/ADM8693/ADM8695 automatically selects the “long” timeout period directly after a reset is issued.
The watchdog timer is restarted at the end of reset, whether the
reset was caused by lack of activity on WDI or by VCC falling below the reset threshold.
VCC
RESET
V2
V1
t1
V2
V1
t1
LOW LINE
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power Fail Reset Timing
On power-up, RESET will remain low for 50 ms (200 ms for
ADM8694 and ADM8695) after VCC rises above the appropriate reset threshold. This allows time for the power supply and
microprocessor to stabilize. On power-down, the RESET output remains low with VCC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” (1.6 s) timeout period. The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
This RESET active time is adjustable on the ADM8691/
ADM8693/ADM8695 by using an external oscillator or by
connecting an external capacitor to the OSC IN pin. Refer to
Table I and Figure 4.
WDI
The guaranteed minimum and maximum thresholds of the
ADM8690/ADM8691/ADM8694/ADM8695 are 4.5 V and
4.73 V, while the guaranteed thresholds of the ADM8692/
ADM8693 are 4.25 V and 4.48 V. The ADM8690/ADM8691/
ADM8694/ADM8695 is, therefore, compatible with 5 V supplies with a +10%, –5% tolerance while the ADM8692/
ADM8693 is compatible with 5 V ± 10% supplies. The reset
threshold comparator has approximately 50 mV of hysteresis.
The response time of the reset voltage comparator is less than 1
µs. If glitches are present on the VCC line which could cause
spurious reset pulses, then VCC should be decoupled close to
the device.
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 3. Watchdog Timeout Period and Reset Active
Time
In addition to RESET the ADM8691/ADM8693/ADM8695
contain an active high RESET output. This is the complement
of RESET and is intended for processors requiring an active
high RESET signal.
–6–
REV. 0
ADM8690–ADM8695
Table I. ADM8691, ADM8693, ADM8695 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
OSC IN
Watchdog Timeout Period
Immediately
Normal
After Reset
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLKS
400 ms × C/47 pF
100 ms
1.6 s
4096 CLKS
1.6 s × C/47 pF
1.6 s
1.6 s
Reset Active Period
ADM8691/ADM8693
ADM8695
512 CLKS
200 ms × C/47 pF
50 ms
50 ms
2048 CLKS
520 ms × C/47 pF
200 ms
200 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF)
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 seconds but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configurations that can be used to adjust the reset pulse width and
watchdog timeout period.
8
ADM8691
ADM8693
ADM8695
7
OSC IN
COSC
Figure 4b. External Capacitor
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; while
with it connected low, the 100 ms timeout period is selected. In
either case, immediately after a reset the timeout period is 1.6
seconds. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, then the 100 ms watchdog period becomes effective after the first transition of WDI. The software
should be written such that the I/O port driving WDI is left in
its power-up reset state until the initialization routines are completed and the microprocessor is able to toggle WDI at the minimum watchdog timeout period of 70 ms.
Watchdog Output (WDO)
The Watchdog Output WDO (ADM8691/ADM8693/
ADM8695) provides a status output which goes low if the
watchdog timer “times out” and remains low until set high by
the next transition on the Watchdog Input. WDO is also set
high when VCC goes below the reset threshold.
8
OSC SEL
ADM8691
ADM8693
ADM8695
NC
7
OSC IN
Figure 4c. Internal Oscillator (1.6 Second Watchdog)
8
OSC SEL
ADM8691
ADM8693
ADM8695
7
OSC IN
Figure 4d. Internal Oscillator (100 ms Watchdog)
OSC SEL
ADM8691
ADM8693
ADM8695
CLOCK
0 TO 500kHz
7
OSC IN
Figure 4a. External Clock Source
REV. 0
NC
NC
8
OSC SEL
–7–
ADM8690–ADM8695
CE Gating and RAM Write Protection (ADM8691/ADM8693/
ADM8695)
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry which ensures the integrity of data
in memory by preventing write operations when VCC is at an invalid level. There are two additional pins, CEIN and CEOUT,
which may be used to control the Chip Enable or Write inputs
of CMOS RAM. When VCC is present, CEOUT is a buffered replica of CEIN, with a 3 ns propagation delay. When VCC falls below the reset voltage threshold or VBATT, an internal gate forces
CEOUT high, independent of CEIN.
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider that
senses either the unregulated dc input to the system’s 5 V regulator or the regulated 5 V output. The voltage divider ratio can
be chosen such that the voltage at PFI falls below 1.3 V several
milliseconds before the +5 V power supply falls below the reset
threshold. PFO is normally used to interrupt the microprocessor
so that data can be stored in RAM and the shut down procedure
executed before power is lost
ADM869x
INPUT
POWER
CEOUT typically drives the CE, CS or write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when VCC is at an invalid level. Similar protection of EEPROMs can be achieved by
using the CEOUT to drive the store or write inputs.
R1
R2
1.3V
PFO
POWER
FAIL
OUTPUT
POWER
FAIL
INPUT
Figure 7. Power Fail Comparator
ADM869x
CEIN
Table II. Input and Output Status In Battery Backup Mode
CEOUT
VCC LOW = 0
VCC OK = 1
Figure 5. Chip Enable Gating
VCC
RESET
V2
V1
t1
V2
Signal
Status
VOUT
VOUT is connected to VBATT via an internal
PMOS switch.
RESET
Logic low.
RESET
Logic high. The open circuit output voltage is
equal to VOUT.
LOW LINE
Logic low.
BATT ON
Logic high. The open circuit voltage is equal to
VOUT.
WDI
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and VOUT. The input voltage
does not affect supply current.
WDO
Logic high. The open circuit voltage is equal
to VOUT.
PFI
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
PFO
Logic low.
CEIN
CEIN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is
between GND and VOUT. The input voltage
does not affect supply current.
CEOUT
Logic high. The open circuit voltage is equal to
VOUT.
OSC IN
OSC IN is ignored.
OSC SEL
OSC SEL is ignored.
V1
t1
LOW LINE
CEIN
CEOUT
t1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 6. Chip Enable Timing
Power Fail Warning Comparator
An additional comparator is provided for early warning of failure in the microprocessor’s power supply. The Power Fail Input
–8–
REV. 0
Typical Performance Curves–ADM8690–ADM8695
2.8
5.00
2.798
4.99
A4
3.36 V
1V
1V
100
2.796
90
VOUT – Volts
VOUT – Volts
4.98
4.97
2.794
2.792
4.96
2.79
10
0%
4.95
2.788
4.94
2.786
150 250 350 450 550 650 750 850 950 1050
IOUT – µA
20
30
40
50 60 70
IOUT – mA
80
90 100
Figure 8. VOUT vs. IOUT Normal
Operation
Figure 9. VOUT vs. IOUT Battery
Backup
4.69
53
VCC = +5V
1.31
RESET ACTIVE TIME – ms
PFI INPUT THRESHOLD – Volts
1.315
Figure 10. Reset Output Voltage vs
Supply Voltage
RESET VOLTAGE THRESHOLD – V
10
1.305
1.3
1.295
1.29
52
51
ADM8690
ADM8691
ADM8692
ADM8693
50
1.285
1.28
–60
–30
0
30
60
90
120
49
20
40
TEMPERATURE – °C
Figure 11. PFI Input Threshold vs.
Temperature
6
60
80
100
TEMPERATURE – °C
120
Figure 12. Reset Active Time vs.
Temperature
4
3
VPFI
PFO
2
1.3V
30pF
1
5
VCC = +5V
4.67
4.65
4.63
4.61
4.59
4.57
4.55
–60
VCC = 5V
TA = +25°C
5
4
3
3
30pF
0
0
0
1.35
1.35
1.35
1.25
1.25
1.25
Figure 14. Power Fail Comparator
Response Time
REV. 0
120
+5V
1
PFO
1.3V
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TIME – µs
90
VCC = 5V
TA = +25°C
2
VPFI
1
0
0
30
60
TEMPERATURE – °C
Figure 13. Reset Voltage Threshold
vs. Temperature
4
2
–30
6
6
VCC = 5V
TA = +25°C
5
500ms
0 10 20 30 40 50 60
TIME – µs
70 80
90
Figure 15. Power Fail Comparator
Response Time
–9–
10kΩ
VPFI
PFO
1.3V
0
30pF
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME – µs
Figure 16. Power Fail Comparator
Response Time with Pull-Up Resistor
ADM8690–ADM8695
Monitoring the Status of the Battery
+APPLICATION INFORMATION
Increasing the Drive Current
If the continuous output current requirements at VOUT exceed
100 mA, or if a lower VCC–VOUT voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8693/ADM8695) can directly drive the base of the external transistor.
PNP TRANSISTOR
+5V INPUT
POWER
0.1µF
0.1µF
VCC
BATT
ON
The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery voltage and generates an active low PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery voltage. This can be done under processor control using CEOUT.
Since CEOUT is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
VOUT
+5V INPUT
POWER
ADM8691
ADM8693
ADM8695
VBATT
BATTERY
Figure 17. Increasing the Drive Current
20kΩ
OPTIONAL
TEST LOAD
Using a Rechargeable Battery for Backup
If a capacitor or a rechargeable battery is used for backup then
the charging resistor should be connected to VOUT since this
eliminates the discharge path that would exist during powerdown if the resistor is connected to VCC.
R
0.1µF
R
0.1µF
VBATT
RECHARGEABLE
BATTERY
ADM869x
10MΩ
CEIN
CEOUT
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
Figure 20. Monitoring the Battery Status
The watchdog feature can be enabled and disabled under program control by driving WDI with a three-state buffer (Figure
21a). When three-stated, the WDI input will float, thereby disabling the watchdog timer.
VOUT
VCC
LOW BATTERY
SIGNAL TO
µP I/O PIN
Alternate Watchdog Input Drive Circuits
VOUT – VBATT
I=
PFO
10MΩ
PFI
+5V INPUT
POWER
VCC
VBATT
BATTERY
ADM869x
WATCHDOG
STROBE
WDI
ADM869x
CONTROL
INPUT
Figure 18. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is noninverting, hysteresis can be added simply by connecting a resistor between the PFO output and the PFI input as shown in Figure 19.
When PFO is low, resistor R3 sinks current from the summing
junction at the PFI pin. When PFO is high, the series combination of R3 and R4 source current into the PFI summing junction. This results in differing trip levels for the comparator.
+7V TO +15V
INPUT
POWER
7805
+5V
R4
VCC
R1
PFO
1.3V
PFI
TO µP NMI
ADM869x
R2
R3
R
R
VH = 1.3V 1+ 1 + 1
R2 R3
5V
PFO
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously three-state the buffer. This
would then prevent the ADM869x from detecting that the microprocessor is no longer operating correctly. In most cases a
better method is to extend the watchdog period rather than disabling the watchdog. This may be done under program control
using the circuit shown in Figure 21b. When the control input is
high, the OSC SEL pin is low and the watchdog timeout is set
by the external capacitor. A 0.01 µF capacitor sets a watchdog
timeout delay of 100 seconds. When the control input is low,
the OSC SEL pin is driven high, selecting the internal oscillator.
The 100 ms or the 1.6 s period is chosen, depending on which diode in Figure 21b is used. With D1 inserted, the internal timeout is
set at 100 ms; with D2 inserted the timeout is set at 1.6 s.
CONTROL
INPUT*
(
)
(
R1 R1 (5V – 1.3V)
–
R2 1.3V (R3 + R4)
VL = 1.3V 1+
Figure 21a. Programming the Watchdog Input
D1
0V
VL
VH
VIN
HYSTERESIS VH – VL = 5V
D2
ADM869x
OSC IN
)
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
ASSUMING R4 < < R3 THEN
0V
OSC SEL
( RR1 )
Figure 21b. Programming the Watchdog Input
2
Figure 19. Adding Hysteresis to the Power Fail Comparator
–10–
REV. 0
ADM8690–ADM8695
TYPICAL APPLICATIONS
ADM8690, ADM8692 and ADM8694
Figure 22b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regulator. This gives an earlier warning of an impending power failure. It is useful with processors operating at low speeds or where
there are a significant number of housekeeping tasks to be completed before the power is lost.
Figure 22a shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. VOUT
powers the CMOS RAM. Under normal operating conditions
with VCC present, VOUT is internally connected to VCC. If a
power failure occurs, VCC will decay and VOUT will be switched
to VBATT thereby maintaining power for the CMOS RAM. A
RESET pulse is also generated when VCC falls below 4.65 V for
the ADM8690/ADM8694 or 4.4 V for the ADM8692. RESET
will remain low for 50 ms (200 ms for ADM8694) after VCC returns to 5 V.
INPUT
POWER
V > 8V
+5V
7805
0.1µF
R1
µP POWER
VCC
VOUT
PFI
ADM8690
ADM8692
ADM8694
R2
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indicates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
CMOS RAM
POWER
0.1µF
µP SYSTEM
µP RESET
RESET
VBATT
+
PFO
µP NMI
WDI
I/O LINE
BATTERY
GND
If the watchdog timer is not needed, the WDI input should be
left floating.
Figure 22b. ADM8690/ADM8692/ADM8694 Typical Application Circuit B
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is compared with a precision 1.3 V internal reference. If the input voltage drops below 1.3 V, a power fail output (PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT.
ADM8691, ADM8693 and ADM8695
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 23. CMOS RAM is powered from VOUT.
When 5 V power is present this is routed to VOUT. If VCC fails
then VBATT is routed to VOUT. VOUT can supply up to 100 mA
from VCC, but if more current is required, an external PNP transistor can be added. When VCC is higher than VBATT, the BATT
ON output goes low, providing up to 25 mA of base drive for
the external transistor. A 0.1 µF capacitor is connected to VOUT
to supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20 Ω MOSFET connects the
backup battery to VOUT.
INPUT POWER
+5V
+5V
R1
VCC
R2
µP POWER
ADM8690
ADM8692
ADM8694
RESET
VBATT
PFO
+
BATTERY
GND
WDI
0.1µF
CMOS RAM
POWER
VOUT
PFI
0.1µF
VCC
0.1µF
3V
BATTERY
µP SYSTEM
VBATT
R1
µP RESET
PFI
GND
µP NMI
R2
I/O LINE
NC
BATT
ON
OSC IN
LOW LINE
CMOS
RAM
CEOUT
ADM8691
ADM8693
ADM8695
OSC SEL
Figure 22a. ADM8690/ADM8692/ADM8694 Typical Application Circuit A
VOUT
CEIN
ADDRESS
DECODE
A0–A15
WDI
I/O LINE
PFO
NMI
RESET
RESET
WDO
RESET
0.1µF
SYSTEM STATUS
INDICATORS
Figure 23. ADM8691/ADM8693/ADM8695 Typical
Application
REV. 0
–11–
µP
ADM8690–ADM8695
RESET Output
RAM Write Protection
The internal voltage detector monitors VCC and generates a
RESET output to hold the microprocessor’s Reset line low
when VCC is below 4.65 V (4.4 V for ADM8693). An internal
timer holds RESET low for 50 ms (200 ms for the ADM8695)
after VCC rises above 4.65 V (4.4 V for ADM8693). This prevents repeated toggling of RESET even if the 5 V power drops
out and recovers with each power line cycle.
The ADM8691/ADM8693/ADM8695 CEOUT line drives the
Chip Select inputs of the CMOS RAM. CEOUT follows CEIN as
long as VCC is above the 4.65 V (4.4 V for ADM8693) reset
threshold.
The crystal oscillator normally used to generate the clock for
microprocessors can take several milliseconds to stabilize. Since
most microprocessors need several clock cycles to reset, RESET
must be held low until the microprocessor clock oscillator has
started. The power-up RESET pulse lasts 50 ms (200 ms for the
ADM8695) to allow for this oscillator start-up time. If a different reset pulse width is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4. The manual reset switch and the
0.1 µF capacitor connected to the reset line can be omitted if a
manual reset is not needed. An inverted, active high, RESET
output is also available.
Power Fail Detector
The +5 V VCC power line is monitored via a resistive potential
divider connected to the Power Fail Input (PFI). When the
voltage at PFI falls below 1.3 V, the Power Fail Output (PFO)
drives the processor’s NMI input low. If for example a Power
Fail threshold of 4.8 V is set with resistors R1 and R2, the microprocessor will have the time when VCC falls from 4.8 V to 4.65 V
to save data into RAM. An earlier power fail warning can be generated if the unregulated dc input to the 5 V regulator is available for monitoring. This will allow more time for microprocessor housekeeping tasks to be completed before power is
lost.
If VCC falls below the reset threshold, CEOUT goes high, independent of the logic level at CEIN. This prevents the microprocessor from writing erroneous data into RAM during power-up,
power-down, brownouts and momentary power interruptions.
Watchdog Timer
The microprocessor drives the Watchdog Input (WDI) with an
I/O line. When OSC IN and OSC SEL are unconnected, the
microprocessor must toggle the WDI pin once every 1.6 seconds
to verify proper software execution. If a hardware or software
failure occurs such that WDI is not toggled, the ADM8691/
ADM8693 will issue a 50 ms (200 ms for ADM8695) RESET
pulse after 1.6 seconds. This typically restarts the microprocessor’s power-up routine. A new RESET pulse is issued
every 1.6 seconds until WDI is again strobed. If a different
watchdog timeout period is required, then a capacitor should be
connected to OSC IN or an external clock may be used. Please
refer to Table I and Figure 4.
The Watchdog Output (WDO) goes low if the watchdog timer
is not serviced within its timeout period. Once WDO goes low,
it remains low until a transition occurs at WDI. The watchdog
timer feature can be disabled by leaving WDI unconnected.
The RESET output has an internal 3 µA pull-up, and can either
connect to an open collector reset bus or directly drive a CMOS
gate without an external pull-up resistor.
–12–
REV. 0
ADM8690–ADM8695
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
1
4
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77)
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
16-Lead Plastic DIP
(N-16)
0.840 (21.33)
0.745 (18.93)
16
9
1
8
PIN 1
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
0.150
(3.81)
0.200 (5.05)
0.125 (3.18)
0.022 (0.558)
0.014 (0.356)
REV. 0
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.100
(2.54)
BSC
0.070 (1.77) SEATING
0.045 (1.15) PLANE
–13–
0.015 (0.381)
0.008 (0.204)
ADM8690–ADM8695
8-Lead Small Outline
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
PIN 1
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.2440 (6.20)
0.2284 (5.80)
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35)
BSC
0.0196 (0.50)
x 45°
0.0099 (0.25)
0.0098 (0.25)
0.0075 (0.19)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
16-Lead Small Outline (Wide Body)
(R-16)
0.413 (10.50)
16
9
0.419
(10.65)
0.299
(7.60)
1
8
0.104
(2.65)
PIN 1
0.012
(0.3)
SEATING
PLANE
0.05 (1.27)
BSC
0.030 (0.75)
0.042 (1.07)
0.019 (0.49)
0.013 (0.32)
16-Lead Small Outline (Narrow Body)
(R-16A)
0.3937 (10.00)
0.3859 (9.80)
0.1574 (4.00)
0.1497 (5.80)
16
9
1
8
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0500
(1.27)
BSC
0.2550 (6.20)
0.2284 (5.80)
0.0192 (0.49)
0.0138 (0.35)
–14–
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
REV. 0
ADM8690–ADM8695
16-Lead Thin Shrink Small Outline
(RU-16)
0.201 (5.10)
0.193 (4.90)
9
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
16
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–15–
8°
0°
0.028 (0.70)
0.020 (0.50)
–16–
PRINTED IN U.S.A.
C2932–10–2/97