AD ADN2850BCPZ250 Nonvolatile memory, dual 1024-position digital resistor Datasheet

Nonvolatile Memory, Dual
1024-Position Digital Resistor
ADN2850
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
GENERAL DESCRIPTION
RDAC1
REGISTER
CLK
SDI
W1
SERIAL
INTERFACE
SDO
PR
WP
RDY
EEMEM1
POWER-ON
RESET
RDAC1
B1
RDAC1
REGISTER
EEMEM
CONTROL
W2
B2
EEMEM2
RDAC2
26 BYTES
USER EEMEM
I1
CURRENT
MONITOR
I2
VDD
VSS
RTOL*
GND
V1
V2
*RWB FULL SCALE TOLERANCE.
In the scratchpad programming mode, a specific setting can
be programmed directly to the RDAC2 register, which sets the
resistance between Terminal W and Terminal B. This setting can
be stored into the EEMEM and is restored automatically to the
RDAC register during system power-on.
The EEMEM content can be restored dynamically or through
external PR strobing, and a WP function protects EEMEM
contents. To simplify the programming, the independent or
simultaneous linear-step increment or decrement commands
can be used to move the RDAC wiper up or down, one step at a
time. For logarithmic ±6 dB changes in the wiper setting, the
left or right bit shift command can be used to double or halve the
RDAC wiper setting.
E
E
A
The ADN2850 is a dual-channel, nonvolatile memory , digitally
controlled resistors2 with 1024-step resolution, offering
guaranteed maximum low resistor tolerance error of ±8%. The
device performs the same electronic adjustment function as a
mechanical rheostat with enhanced resolution, solid state
reliability, and superior low temperature coefficient
performance. The versatile programming of the ADN2850 via
an SPI®-compatible serial interface allows 16 modes of
operation and adjustment including scratchpad programming,
memory storing and restoring, increment/decrement, ±6 dB/step
log taper adjustment, wiper setting readback, and extra EEMEM1
for user-defined information such as memory data for other
components, look-up table, or system identification
information.
1
2
ADN2850
ADDR
DECODE
Figure 1.
SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode
driver, optical supervisory systems
Mechanical rheostat replacement
Instrumentation gain adjustment
Programmable filters, delays, time constants
Sensor calibration
1
CS
02660-001
Dual-channel, 1024-position resolution
25 kΩ, 250 kΩ nominal resistance
Maximum ±8% nominal resistor tolerance error
Low temperature coefficient: 35 ppm/°C
2.7 V to 5 V single supply or ±2.5 V dual supply
Current monitoring configurable function
SPI-compatible serial interface
Nonvolatile memory stores wiper settings
Power-on refreshed with EEMEM settings
Permanent memory write protection
Resistance tolerance stored in EEMEM
26 bytes extra nonvolatile memory for user-defined
information
1M programming cycles
100-year typical data retention
A
A
The ADN2850 patterned resistance tolerance is stored in the
EEMEM. The actual full scale resistance can, therefore, be
known by the host processor in readback mode. The host can
execute the appropriate resistance step through a software
routine that simplifies open-loop applications as well as
precision calibration and tolerance matching applications.
The ADN2850 is available in the 5 mm × 5 mm 16-lead frame
chip scale LFCSP and thin, 16-lead TSSOP package. The part is
guaranteed to operate over the extended industrial temperature
range of −40°C to +85°C.
The terms nonvolatile memory and EEMEM are used interchangeably.
The terms digital resistor and RDAC are used interchangeably.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
ADN2850
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Daisy-Chain Operation ............................................................. 14
Applications ....................................................................................... 1
Terminal Voltage Operating Range ......................................... 15
General Description ......................................................................... 1
Advanced Control Modes ......................................................... 17
Functional Block Diagram .............................................................. 1
RDAC Structure.......................................................................... 18
Revision History ............................................................................... 2
Programming the Variable Resistor ......................................... 19
Specifications..................................................................................... 3
Programming Examples ............................................................ 19
Electrical Characteristics—25 kΩ, 250 kΩ Versions ............... 3
EVAL-ADN2850SDZ Evaluation Kit....................................... 20
Interface Timing and EEMEM Reliability Characteristics—
25 kΩ, 250 kΩ Versions ............................................................... 5
Applications Information .............................................................. 21
Absolute Maximum Ratings ............................................................ 7
Programmable Low-Pass Filter ................................................ 21
ESD Caution .................................................................................. 7
Programmable Oscillator .......................................................... 21
Pin Configuration and Function Descriptions ............................. 8
Optical Transmitter Calibration with ADN2841 ................... 22
Typical Performance Characteristics ........................................... 10
Incoming Optical Power Monitoring ...................................... 22
Test Circuits................................................................................. 12
Resistance Scaling ...................................................................... 23
Theory of Operation ...................................................................... 13
Scratchpad and EEMEM Programming.................................. 13
Resistance Tolerance, Drift, and Temperature Coefficient
Mismatch Considerations ......................................................... 24
Basic Operation .......................................................................... 13
RDAC Circuit Simulation Model ............................................. 24
EEMEM Protection .................................................................... 14
Outline Dimensions ....................................................................... 25
Digital Input and Output Configuration................................. 14
Ordering Guide .......................................................................... 25
Gain Control Compensation .................................................... 21
Serial Data Interface ................................................................... 14
REVISION HISTORY
6/12—Rev. D to Rev. E
Changes to Table 1 Conditions ....................................................... 4
Removed Positive Supply Current RDY and/or SDO Floating
Parameters and Negative Supply Current RDY and/or SDO
Floating Parameters, Table 1 ........................................................... 4
Updated Outline Dimensions ....................................................... 25
Added Endnote 2 to Ordering Guide .......................................... 25
4/11—Rev. C to Rev. D
Changes to Figure 10 ...................................................................... 10
4/11—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to EEMEM Performance ................................... Universal
Changes to Features Section............................................................ 1
Changes to Applications Section .................................................... 1
Changes to General Description Section ...................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Specifications Section .................................................. 3
Changes to Table 2 ............................................................................ 5
Changes to Absolute Maximum Ratings Section ......................... 7
Changes to Pin Configuration and Function Descriptions
Section ................................................................................................ 8
Changes to Typical Performance Characteristics Section ........ 10
Added Figure 15, Figure 16, Figure 17 ........................................ 11
Changes to Figure 21...................................................................... 12
Changes to Theory of Operation Section.................................... 13
Changes to Figure 25...................................................................... 14
Changes to Programming Variable Resister Section ................. 19
Changes to Table 13 ....................................................................... 19
Changes to EVAL-ADN2850EBZ Evaluation Kit Section ........ 20
Added Gain Control Compensation Section.............................. 21
Added Programmable Low-Pass Filter Section .......................... 21
Added Programmable Oscillator Section.................................... 21
Added Resistance Tolerance, Drift, and Temperature Coeffcient
Mistmatch Considerations Section .............................................. 24
Changes to Outline Dimensions Section .................................... 25
Changes to Ordering Guide .......................................................... 25
9/02—Rev. A to Rev. B
Changes to General Description .....................................................1
Changes to Electrical Characteristics .............................................2
Changes to Calculating Actual Full-Scale Resistance Section.....9
Changes to Table VI ..........................................................................9
Updated Outline Dimensions ....................................................... 18
Rev. E | Page 2 of 28
Data Sheet
ADN2850
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V, VA = VDD, VB = VSS, −40°C < TA < +85°C, unless otherwise noted. These
specifications apply to versions with a date code 1209 or later.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (All RDACs)
Resolution
Resistor Differential Nonlinearity 2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient 3
Wiper Resistance
Nominal Resistance Match3
RESISTOR TERMINALS
Terminal Voltage Range3
Capacitance Bx3
Capacitance Wx3
Common-Mode Leakage Current3, 4
DIGITAL INPUTS AND OUTPUTS
Input Logic 3
High
Low
Output Logic High (SDO, RDY)
Output Logic Low
Input Current
Input Capacitance3
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Symbol
N
R-DNL
R-INL
∆RWB/RWB
(∆RWB/RWB)/
∆T × 106
RW
RWB1/RWB2
V B, V W
CB
CW
ICM
VIH
VIL
VOH
VOL
IIL
CIL
VDD
VDD/VSS
IDD
ISS
EEMEM Store Mode Current
IDD (store)
EEMEM Restore Mode Current 5
ISS (store)
IDD (restore)
Power Dissipation 6
Power Supply Sensitivity3
ISS (restore)
PDISS
PSS
Conditions
RWB
RWB
Code = full scale
Code = full scale
Min
Typ 1
10
+1
+2
+8
−1
−2
−8
35
Code = half scale
VDD = 5 V
VDD = 3 V
Code = full scale
30
50
±0.1
VIH = VDD or VIL = GND
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
VDD = +2.5 V, VSS = −2.5 V
VIH = VDD or VIL = GND
∆VDD = 5 V ± 10%
VDD
11
V
pF
80
pF
0.01
±1
2.4
2.1
2.0
0.8
0.6
0.5
4.9
0.4
±1
Rev. E | Page 3 of 28
2.7
±2.25
2
−4
LSB
LSB
%
ppm/°C
Ω
Ω
%
5
VSS = 0 V
Unit
60
VSS
f = 1 MHz, measured to GND,
code = half-scale
f = 1 MHz, measured to GND,
code = half-scale
VW = VDD/2
VDD = 5 V
VDD = 2.7 V
VDD = +2.5 V, VSS = −2.5 V
VDD = 5 V
VDD = 2.7 V
VDD = +2.5 V, VSS = −2.5 V
RPULL-UP = 2.2 kΩ to 5 V (see Figure 25)
IOL = 1.6 mA, VLOGIC = 5 V (see Figure 25)
VIN = 0 V or VDD
Max
5.5
±2.75
5
µA
V
V
V
V
V
V
V
V
µA
pF
V
V
µA
−2
2
µA
mA
−2
320
mA
µA
−320
10
0.006
30
0.01
µA
µW
%/%
ADN2850
Parameter
CURRENT MONITOR TERMINALS
Current Sink at V1
Current Sink at V2
DYNAMIC CHARACTERISTICS3, 7
Resistor Noise Density
Analog Crosstalk
Data Sheet
Symbol
Conditions
I1
I2
eN_WB
CT
Min
Typ 1
0.0001
0.0001
Code= full scale
RWB = 25 kΩ/250 kΩ, TA = 25°C
VBX = GND, Measured VW1 with VW2 =
1 VRMS, f = 1 kHz, Code 1 = midscale,
Code 2 = midscale,
RWB = 25 kΩ/250 kΩ
20/64
−95/−80
Max
Unit
10
10
mA
mA
nV/√Hz
dB
Typicals represent average readings at 25°C and VDD = 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum current in each code is defined by IWB = (VDD − 1)/RWB.
(see Figure 20).
3
Guaranteed by design and not subject to production test.
4
Common-mode leakage current is a measure of the dc leakage from any Terminal B, or Terminal W to a common-mode bias level of VDD/2.
5
EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register.
6
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
7
All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.
1
2
Rev. E | Page 4 of 28
Data Sheet
ADN2850
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 3 V and VDD = 5 V.
Table 2.
Parameter
Clock Cycle Time (tCYC)
CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay 2
CLK to SDO Data Hold Time
CS High Pulse Width 3
CS High to CS High3
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store EEMEM Time 4, 5
Read EEMEM Time4
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) 6
Preset Response Time to Wiper Setting6
Power-On EEMEM Restore Time6
FLASH/EE MEMORY RELIABILITY
Endurance 7
E
A
E
A
A
E
A
A
E
A
A
10F
E
A
A
A
E
1F
E
A
A
A
E
A
A
E
A
A
12F
13F
E
A
A
14F
15F
Symbol
t1
t2
t3
t4, t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t16
t17
tPRW
tPRESP
tEEMEM
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
Min
20
10
1
10
5
5
Typ 1
40
50
50
0
10
4
0
0.15
15
7
Applies to instructions 0x2, 0x3
Applies to instructions 0x8, 0x9, 0x10
10
50
PR pulsed low to refresh wiper positions
30
30
E
A
A
TA = 25°C
1
100
Data Retention 8
100
16F
Max
0.3
50
30
Unit
ns
ns
tCYC
ns
ns
ns
ns
ns
ns
ns
ns
tCYC
ns
ms
ms
µs
ns
ns
µs
µs
MCycles
kCycles
Years
Typicals represent average readings at 25°C and VDD = 5 V.
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms, PR hardware pulse ~ 30 µs.
5
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
1
2
Rev. E | Page 5 of 28
ADN2850
Data Sheet
Timing Diagrams
CPHA = 1
CS
t12
t13
t3
t1
t2
CLK
CPOL = 1
t5
B23
B0
t17
t4
t7
SDI
t6
HIGH
OR LOW
B23 (MSB)
t8
t11
t10
t9
B23 (MSB)
B24*
SDO
HIGH
OR LOW
B0 (LSB)
B0 (LSB)
t14
t15
t16
02660-002
RDY
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE LSB OF THE CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2. CPHA = 1 Timing Diagram
CPHA = 0
CS
t12
t1
t2
t5
B23
CLK
CPOL = 0
t3
t13
t17
B0
t4
t7
t6
SDI
HIGH
OR LOW
HIGH
OR LOW
B23 (MSB IN)
B0 (LSB)
t10
t8
t11
t9
SDO
B23 (MSB OUT)
B0 (LSB)
t14
*
t15
t16
*THE EXTRA BIT THAT IS NOT DEFINED IS NORMALLY THE MSB OF THE CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 3. CPHA = 0 Timing Diagram
Rev. E | Page 6 of 28
02660-003
RDY
Data Sheet
ADN2850
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VB, VW to GND
IB, I W
Pulsed 1
Continuous
Digital Input and Output Voltage to GND
Operating Temperature Range 2
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Thermal Resistance
Junction-to-Ambient θJA,TSSOP-16
Junction-to-Ambient θJA,LFSCP-16
Junction-to-Case θJC, TSSOP-16
Package Power Dissipation
0F0F
1F1F
Rating
–0.3 V to +7 V
+0.3 V to −7 V
7V
VSS − 0.3 V to VDD + 0.3 V
±20 mA
±2 mA
−0.3 V to VDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
215°C
220°C
150°C/W
35°C/W
28°C/W
(TJ max − TA)/θJA
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Includes programming of nonvolatile memory.
1
Rev. E | Page 7 of 28
ADN2850
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16 RDY
SDI 2
15 CS
SDO 3
14 PR
ADN2850
GND 4
TOP VIEW
(Not to Scale)
VSS 5
13 WP
12 VDD
V1 6
11 V2
W1 7
10 W2
B1 8
9
B2
02660-005
CLK 1
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
CLK
SDI
SDO
4
5
GND
VSS
6
7
8
9
10
11
12
13
V1
W1
B1
B2
W2
V2
VDD
WP
E
A
Description
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
Wiper Terminal of RDAC1. ADDR (RDAC1) = 0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
Positive Power Supply.
Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PR.
E
A
E
A
A
A
E
A
14
PR
E
A
A
E
A
E
A
15
16
CS
RDY
E
A
A
E
A
E
A
A
Rev. E | Page 8 of 28
A
A
Data Sheet
ADN2850
ADN2850
14 RDY
13 CS
15 CLK
PIN 1
INDICATOR
16 SDI
TOP VIEW
(Not to Scale)
12 PR
SDO 1
GND 2
VSS 3
(EXPOSED
PAD)
V1 4
11 WP
10 VDD
02660-105
B2 7
W2 8
B1 6
W1 5
9 V2
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO VSS.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
SDO
2
3
GND
VSS
4
5
6
7
8
9
10
11
V1
W1
B1
B2
W2
V2
VDD
WP
E
A
Description
Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO
output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and
after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI
bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This
previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up
resistor in the range of 1 kΩ to 10 kΩ is needed.
Ground Pin, Logic Ground Reference.
Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink
2 mA for 15 ms when storing data to EEMEM.
Log Output Voltage 1. Generates voltage from an internal diode configured transistor.
Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.
Terminal B of RDAC1.
Terminal B of RDAC2.
Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.
Log Output Voltage 2. Generates voltage from an internal diode configured transistor.
Positive Power Supply.
Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe.
CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie WP to VDD, if not used.
Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale until EEMEM is loaded with a new value by the user. PR is activated
at the logic high transition. Tie PR to VDD, if not used.
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,
Instruction 9, Instruction 10, and PR.
Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.
Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.
Exposed Pad. The exposed pad is left floating or is tied to VSS.
E
A
E
A
A
E
A
12
PR
E
A
A
E
A
E
A
A
13
14
CS
RDY
E
A
E
A
E
A
15
16
CLK
SDI
EP
A
Rev. E | Page 9 of 28
A
A
A
ADN2850
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
60
0.20
+85°C
+25°C
–40°C
50
WIPER ON RESISTANCE (Ω)
0.15
0.10
INL ERROR (LSB)
2.7V
3.0V
3.3V
5.0V
5.5V
0.05
0
–0.05
–0.10
40
30
20
10
–0.15
200
400
600
1000
800
DIGITAL CODE
0
200
1000
3
2
0.10
IDD = 2.7V
IDD = 3.3V
IDD = 3.0V
IDD = 5.0V
IDD = 5.5V
1
0.05
IDD/ISS (µA)
0
0
–1
–0.05
–2
–0.10
0
200
400
600
1000
800
DIGITAL CODE
–3
–40
02660-009
–0.15
ISS = 2.7V
ISS = 3.3V
ISS = 3.0V
ISS = 5.0V
ISS = 5.5V
–20
0
25
40
60
85
TEMPERATURE (°C)
02660-013
DNL ERROR (LSB)
800
Figure 9. Wiper On Resistance vs. Code
+85°C
+25°C
–40°C
0.15
600
CODE (Decimal)
Figure 6. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
0.20
400
02660-012
0
02660-008
0
–0.20
Figure 10. IDD vs. Temperature, RAB = 25 kΩ
Figure 7. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 25 kΩ
50
200
180
40
160
140
30
I DD (µA)
120
100
80
20
60
10
40
20
0
256
512
768
CODE (Decimal)
1023
Figure 8. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco
1
2
3
4
5
6
7
FREQUENCY (MHz)
Figure 11. IDD vs. Clock Frequency
Rev. E | Page 10 of 28
8
9
10
02660-014
0
0
02660-011
RHEOSTAT MODE TEMPCO (ppm/°C)
FULL SCALE
MIDSCALE
ZERO SCALE
25kΩ
250kΩ
Data Sheet
ADN2850
2.5982
400
VOLTAGE (V)
200
100
1
2
3
4
5
2.5873
–19.8 –10
VDIO (V)
Figure 12. IDD vs Digital Input Voltage
20
30
40
50
60
70
80
Figure 15. Midscale Glitch Energy, RAB = 25 kΩ, Code 0x200 to Code 0x1FF
2.2492
2.2490
VDD = 5V ± 10% AC
VSS = 0V, IW (25k) = 200µA
–10 I (250k) = 20µA, V = 0V
W
B
MEASURED AT VW WITH CODE = 0x200
–20 TA = 25°C
2.2485
2.2480
2.2475
2.2470
RAB = 250kΩ
VOLTAGE (V)
–30
RAB = 25kΩ
–40
–50
2.2465
2.2460
2.2455
2.2450
2.2445
–60
VDD = 5V
VSS = GND
VB = VSS
IW = 20µA
2.2440
2.2435
–70
2.2430
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency
2.2425
–39.8
02660-019
100
0
50
100
150
200
250
300
360
TIME (µs)
Figure 16. Midscale Glitch Energy, RAB = 250 kΩ, Code 0x200 to Code 0x1FF
2.80
VDD = 5V
VSS = GND
VB = GND
IW (25k) = 200µA
IW (250k) = 20µA
2.75
WIPER VOLTAGE (V)
VDD
VW (FULL SCALE)
10µs/DIV
VDD = 5V
IW = 200µA
VB = 0V
TA = 25°C
1V/DIV
2.70
2.65
2.60
2.55
02660-020
PSRR (dB)
10
TIME (µs)
0
–80
10
0
02660-116
0
02660-015
0
VDD = 5V
VSS = GND
VB = VSS
IW = 200µA
2.50
0.7
02660-117
IDD (µA)
300
2.5975
2.5970
2.5965
2.5960
2.5955
2.5950
2.5945
2.5940
2.5935
2.5930
2.5925
2.5920
2.5915
2.5910
2.5905
2.5900
2.5895
2.5890
2.5885
2.5880
02660-115
2.7V
3.0V
3.3V
5.0V
5.5V
0.8
0.9
1.0
1.1
1.2
TIME (µs)
Figure 14. Power-On Reset
Figure 17. Digital Feedthrough
Rev. E | Page 11 of 28
1.3
1.4
1.5
ADN2850
Data Sheet
100
TA = 25°C
THEORECTICAL (IWB_MAX – mA)
CLK (5V/DIV)
SDI (5V/DIV)
1
RWB = 25kΩ
0.1
RWB = 250kΩ
0.01
02660-023
IDD (2mA/DIV)
10
0
128
256
384
512
640
768
896
CODE (Decimal)
Figure 18. IDD vs. Time when Storing Data to EEMEM
Figure 19. IWB_MAX vs. Code
TEST CIRCUITS
Figure 20 to Figure 24 define the test conditions used in the Specifications section.
DUT
RSW =
DUT
IW
W
0.1V
ISW
W
+
B
B
02660-026
VMS
0.1V
ISW
–
Figure 20. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
02660-033
VSS TO VDD
Figure 23. Incremental On Resistance
IW = VDD/RNOMINAL
VDD
DUT
B
RW = VMS1/IW
VSS GND
02660-028
VMS1
Figure 21. Wiper Resistance
VDD
W
VMS
V+ = VDD ±10%
PSRR (dB) = 20 LOG
PSS (%/%) =
ΔVMS%
ΔVDD%
(
ΔVMS
ΔVDD
)
02660-029
B
VCM
Figure 24. Common-Mode Leakage Current
IW = VDD/(RNOMINAL / 2)
~
B
NC
NC = NO CONNECT
CODE = Mid Scale
V+
ICM
W
02660-034
VW
W
Figure 22. Power Supply Sensitivity (PSS, PSRR)
Rev. E | Page 12 of 28
1023
02660-025
VDD = 5V
TA = 25°C
CS (5V/DIV)
Data Sheet
ADN2850
THEORY OF OPERATION
The ADN2850 digital programmable resistor is designed to
operate as a true variable resistor. The resistor wiper position is
determined by the RDAC register contents. The RDAC register
acts as a scratchpad register, allowing unlimited changes of
resistance settings. The scratchpad register can be programmed
with any position setting using the standard SPI serial interface by
loading the 24-bit data-word. In the format of the data-word, the
first four bits are commands, the following four bits are addresses,
and the last 16 bits are data. When a specified value is set, this
value can be stored in a corresponding EEMEM register. During
subsequent power-ups, the wiper setting is automatically loaded to
that value.
Storing data to the EEMEM register takes about 15ms and
consumes approximately 2 mA. During this time, the shift
register is locked, preventing any changes from taking place.
The RDY pin pulses low to indicate the completion of this
EEMEM storage. There are also 13 addresses with two bytes
each of user-defined data that can be stored in the EEMEM
register from Address 2 to Address 14.
The following instructions facilitate the programming needs of
the user (see Table 8 for details):
0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
SCRATCHPAD AND EEMEM PROGRAMMING
The scratchpad RDAC register directly controls the position of
the digital resistor wiper. For example, when the scratchpad register
is loaded with all 0s, the wiper is connected to Terminal B of the
variable resistor. The scratchpad register is a standard logic
register with no restriction on the number of changes allowed,
but the EEMEM registers have a program erase/write cycle
limitation.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by
loading the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the proper
wiper position is determined, the user can load the serial data
input register with Instruction 2 (0x2), which stores the wiper
position data in the EEMEM register. After 15 ms, the wiper
position is permanently stored in nonvolatile memory.
Table 6 provides a programming example listing the sequence of
the serial data input (SDI) words with the serial data output
appearing at the SDO pin in hexadecimal format.
Table 6. Write and Store RDAC Settings to EEMEM Registers
Do nothing.
Restore EEMEM content to RDAC.
Store RDAC setting to EEMEM.
Store RDAC setting or user data to EEMEM.
Decrement by 6 dB.
Decrement all by 6 dB.
Decrement by one step.
Decrement all by one step.
Reset EEMEM content to RDAC.
Read EEMEM content from SDO.
Read RDAC wiper setting from SDO.
Write data to RDAC.
Increment by 6 dB.
Increment all by 6 dB.
Increment by one step.
Increment all by one step.
Table 14 to Table 20 provide programming examples that use
some of these commands.
SDI
0xB00100
SDO
0xXXXXXX
0x20XXXX
0xB00100
0xB10200
0x20XXXX
0x21XXXX
0xB10200
Action
Writes data 0x100 to the RDAC1 register,
Wiper W1 moves to 1/4 full-scale position.
Stores RDAC1 register content into the
EEMEM1 register.
Writes Data 0x200 to the RDAC2 register,
Wiper W2 moves to 1/2 full-scale position.
Stores RDAC2 register contents into the
EEMEM2 register.
At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the corresponding
EEMEM register. The factory-preset EEMEM value is midscale.
The scratchpad register can also be refreshed with the contents
of the EEMEM register in three different ways. First, executing
Instruction 1 (0x1) restores the corresponding EEMEM value.
Second, executing Instruction 8 (0x8) resets the EEMEM values
of both channels. Finally, pulsing the PR pin refreshes both
EEMEM settings. Operating the hardware control PR function
requires a complete pulse signal. When PR goes low, the internal
logic sets the wiper at midscale. The EEMEM value is not
loaded until PR returns high.
E
A
E
A
E
A
E
A
Rev. E | Page 13 of 28
A
A
A
ADN2850
Data Sheet
EEMEM PROTECTION
VDD
The write protect (WP) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature.
E
A
A
E
A
INPUT
300Ω
WP
E
A
A
A
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to VDD, if they are not used. No
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.
E
A
GND
E
A
A
The equivalent serial data input and output logic is shown in
Figure 25. The open-drain output SDO is disabled whenever
chip-select (CS) is in logic high. ESD protection of the digital
inputs is shown in Figure 26 and Figure 27.
E
A
Figure 27. Equivalent WP Input Protection
E
A
The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.
A
PR
VALID
COMMAND
COUNTER
WP
COMMAND
PROCESSOR
AND ADDRESS
DECODE
5V
RPULL-UP
02660-039
DIGITAL INPUT AND OUTPUT CONFIGURATION
A
A
SERIAL DATA INTERFACE
The ADN2850 contains a 4-wire SPI-compatible digital
interface (SDI, SDO, CS, and CLK). The 24-bit serial data-word
must be loaded with MSB first. The format of the word is shown in
Table 7. The command bits (C0 to C3) control the operation of the
digital resistor according to the command shown in Table 8. A0
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage. Table 10 provides an
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.
E
A
A
The ADN2850 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, ADN2850
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when CS goes high but remains in the register if it
is multiple of four. In addition, the ADN2850 has a subtle
feature that, if CS is pulsed without CLK and SDI, the part
repeats the previous command (except during power-up). As a
result, care must be taken to ensure that no excessive noise exists in
the CLK or CS line that might alter the effective number-of-bits
pattern.
E
CLK
SERIAL
REGISTER
(FOR DAISY
CHAIN ONLY)
A
SDO
E
A
CS
02660-037
GND
ADN2850
SDI
A
E
A
Figure 25. Equivalent Digital Input and Output Logic
A
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.
VDD
INPUTS
300Ω
DAISY-CHAIN OPERATION
GND
Figure 26. Equivalent ESD Digital Input Protection
02660-038
LOGIC
PINS
A
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM values
using Instruction 10 and Instruction 9, respectively. The remaining
instructions (Instruction 0 to Instruction 8, Instruction 11 to
Instruction 15) are valid for daisy-chaining multiple devices in
simultaneous operations. Daisy-chaining minimizes the number
of port pins required from the controlling IC (see Figure 28). The
SDO pin contains an open-drain N-Ch FET that requires a pull-up
resistor, if this function is used. As shown in Figure 28, users need
to tie the SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
Rev. E | Page 14 of 28
Data Sheet
ADN2850
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two ADN2850s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then pulled
high to complete the operation.
A
E
A
A
VDD
ADN2850
SDI U1 SDO
CS
CLK
ADN2850
SDI U2 SDO
CLK
CS
02660-040
MOSI
MICROCONTROLLER
SCLK SS
RP
2.2kΩ
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal B, and Terminal W (see Figure 29), it is important to
power VDD and VSS first before applying any voltage to Terminal
B, and Terminal W. Otherwise, the diode is forward-biased such
that VDD and VSS are powered unintentionally. For example,
applying 5 V across Terminal W and Terminal B prior to VDD
causes the VDD terminal to exhibit 4.3 V. It is not destructive to
the device, but it might affect the rest of the user’s system. The
ideal power-up sequence is GND, VDD and VSS, digital inputs,
and VB, and VW. The order of powering VB, VW, and the digital
inputs is not important as long as they are powered after VDD
and VSS.
E
A
extends from VSS to VDD, regardless of the digital input level.
Figure 28. Daisy-Chain Configuration Using SDO
Regardless of the power-up sequence and the ramp rates of the
power supplies, when VDD and VSS are powered, the power-on
preset activates, which restores the EEMEM values to the RDAC
registers.
TERMINAL VOLTAGE OPERATING RANGE
Layout and Power Supply Bypassing
The positive VDD and negative VSS power supplies of the ADN2850
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal B, and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 29).
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
VDD
W
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 µF to 0.1 µF disk or chip ceramic capacitors.
Also, apply low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 30).
ADN2850
B
02660-041
VSS
C3
10µF
+
C1
0.1µF
C4
10µF
+
C2
0.1µF
VDD
VSS
GND
Figure 29. Maximum Terminal Voltages Set by VDD and VSS
The GND pin of the ADN2850 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the ADN2850 ground terminal should be joined remotely to
the common ground (see Figure 30). The digital input control
signals to the ADN2850 must be referenced to the device
ground pin (GND) and must satisfy the logic level defined in
the Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
Rev. E | Page 15 of 28
02660-042
VSS
VDD
Figure 30. Power Supply Bypassing
ADN2850
Data Sheet
In Table 7, command bits are C0 to C3, address bits are A0 to A3, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.
Table 7. 24-Bit Serial Data-Word
RDAC
EEMEM
MSB
C3 C2
C3 C2
C1
C1
Command Byte 0
C0 0
0
0
C0 A3 A2 A1
A0
A0
X
D15
X
D14
X
D13
Data Byte 1
X
X
D12 D11
X
D10
D9
D9
D8
D8
D7
D7
D6
D6
Data Byte 0
D5 D4 D3
D5 D4 D3
D2
D2
D1
D1
LSB
D0
D0
Command instruction codes are defined in Table 8.
Table 8. Command Operation Truth Table 1, 2, 3
17F
18F
19F
Command Byte 0
D9
X
B8
D8
X
Data Byte 0
B7
B0
D7 … D0
X
… X
…
X
X
X
…
X
X
…
X
X
X
…
X
A0
D15
…
D8
D7
…
D0
0
A0
X
…
X
X
X
…
X
X
X
X
X
…
X
X
X
…
X
0
0
0
A0
X
…
X
X
X
…
X
1
X
X
X
X
X
…
X
X
X
…
X
0
0
0
0
0
0
X
…
X
X
X
…
X
0
0
1
A3
A2
A1
A0
X
…
X
X
X
…
X
1
0
1
0
0
0
0
A0
X
…
X
X
X
…
X
11
1
0
1
1
0
0
0
A0
X
…
D9
D8
D7
…
D0
125
1
1
0
0
0
0
0
A0
X
…
X
X
X
…
X
135
1
1
0
1
X
X
X
X
X
…
X
X
X
…
X
145
1
1
1
0
0
0
0
A0
X
…
X
X
X
…
X
155
1
1
1
1
X
X
X
X
X
…
X
X
X
…
X
Command
Number
0
B23
C3
0
C2
0
C1
0
C0
0
A3
X
A2
X
1
0
0
0
1
0
2
0
0
1
0
34
0
0
1
45
0
1
55
0
65
Data Byte 1
A1
X
B16
A0
X
B15
X
X
…
…
0
0
A0
X
0
0
0
A0
1
A3
A2
A1
0
0
0
0
1
0
1
X
0
1
1
0
75
0
1
1
8
1
0
9
1
10
20F
21F
Operation
NOP. Do nothing. See Table 19
Restore EEMEM (A0) contents to RDAC (A0)
register. See Table 16.
Store wiper setting. Store RDAC (A0) setting to
EEMEM (A0). See Table 15.
Store contents of Serial Register Data Byte 0 and
Serial Register Data Bytes 1 (total 16 bits) to
EEMEM (ADDR). See Table 18.
Decrement by 6 dB. Right-shift contents of RDAC
(A0) register, stop at all 0s.
Decrement all by 6 dB. Right-shift contents of all
RDAC registers, stop at all 0s.
Decrement contents of RDAC (A0) by 1, stop at
all 0s.
Decrement contents of all RDAC registers by 1,
stop at all 0s.
Reset. Refresh all RDACs with their corresponding
EEMEM previously stored values.
Read contents of EEMEM (ADDR) from SDO
output in the next frame. See Table 19.
Read RDAC wiper setting from SDO output in the
next frame. See Table 20.
Write contents of Serial Register Data Byte 0 and
Serial Register Data Byte 1 (total 10 bits) to RDAC
(A0). See Table 14.
Increment by 6 dB: Left-shift contents of RDAC (A0),
stop at all 1s. See Table 17.
Increment all by 6 dB. Left-shift contents of all
RDAC registers, stop at all 1s.
Increment contents of RDAC (A0) by 1, stop at all
1s. See Table 15.
Increment contents of all RDAC registers by 1,
stop at all 1s.
The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or
Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instructions following Instruction 9 and Instruction 10 must also be a
full 24-bit data-word to completely clock out the contents of the serial register.
2
The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3
Execution of these operations takes place when the CS strobe returns to logic high.
4
Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of Address 0 and Address 1, only the last 10 bits are valid for wiper position setting.
5
The increment, decrement, and shift instructions ignore the contents of the shift register, Data Byte 0 and Data Byte 1.
1
Rev. E | Page 16 of 28
Data Sheet
ADN2850
ADVANCED CONTROL MODES
the RDAC register is then set to Code 1. Similarly, if the data in
the RDAC register is greater than or equal to midscale and the data
is shifted left, then the data in the RDAC register is automatically
set to full scale. This makes the left-shift function as ideal a
logarithmic adjustment as possible.
•
•
•
•
•
Scratchpad programming to any desirable values
Nonvolatile memory storage of the scratchpad RDAC
register value in the EEMEM register
Increment and decrement instructions for the RDAC wiper
register
Left and right bit shift of the RDAC wiper register to
achieve ±6 dB level changes
26 extra bytes of user-addressable nonvolatile memory
Linear Increment and Decrement Instructions
The increment and decrement instructions (Instruction 14,
Instruction 15, Instruction 6, and Instruction 7) are useful for
linear step adjustment applications. These commands simplify
microcontroller software coding by allowing the controller to
send just an increment or decrement command to the device.
The adjustment can be individual or in a ganged resistor
arrangement where both wiper positions are changed at the
same time.
For an increment command, executing Instruction 14
automatically moves the wiper to the next resistance segment
position. The master increment command, Instruction 15,
moves all resistor wipers up by one position.
Logarithmic Taper Mode Adjustment
Four programming instructions produce logarithmic taper
increment and decrement of the wiper position control by
an individual resistor or by a ganged resistor arrangement
where both wiper positions are changed at the same time. The 6
dB increment is activated by Instruction 12 and Instruction 13,
and the 6 dB decrement is activated by Instruction 4 and
Instruction 5. For example, starting with the wiper connected to
Terminal B, executing 11 increment instructions (Command
Instruction 12) moves the wiper in 6 dB steps from 0% of the RBA
(Terminal B) position to 100% of the RBA position of the
ADN2850 10-bit resistor. When the wiper position is near the
maximum setting, the last 6 dB increment instruction causes
the wiper to go to the full-scale 1023 code position. Further 6
dB per increment instructions do not change the wiper position
beyond its full scale (see Table 9).
The 6 dB step increments and 6 dB step decrements are achieved
by shifting the bit internally to the left or right, respectively. The
following information explains the nonideal ±6 dB step adjustment
under certain conditions. Table 9 illustrates the operation of the
shifting function on the RDAC register data bits. Each table row
represents a successive shift operation. Note that the left-shift
12 and 13 instructions were modified such that, if the data in
the RDAC register is equal to zero and the data is shifted left,
The Right-Shift 4 instruction and Right-Shift 5 instruction are
ideal only if the LSB is 0 (ideal logarithmic = no error). If the
LSB is 1, the right-shift function generates a linear half-LSB
error, which translates to a number-of-bits dependent logarithmic
error, as shown in Figure 31. Figure 31 shows the error of the odd
numbers of bits for the ADN2850.
Table 9. Detail Left-Shift and Right-Shift Functions for 6 dB
Step Increment and Decrement
Left-Shift (+6 dB/Step)
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0100
00 0000 1000
00 0001 0000
00 0010 0000
00 0100 0000
00 1000 0000
01 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Right-Shift(–6 dB/Step)
11 1111 1111
01 1111 1111
00 1111 1111
00 0111 1111
00 0011 1111
00 0001 1111
00 0000 1111
00 0000 0111
00 0000 0011
00 0000 0001
00 0000 0000
00 0000 0000
00 0000 0000
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right-Shift 4 command and Right-Shift 5 command execution
contains an error only for odd numbers of bits. Even numbers of
bits are ideal. Figure 31 shows plots of log error [20 × log10
(error/code)] for the ADN2850. For example, Code 3 log error =
20 × log10 (0.5/3) = −15.56 dB, which is the worst case. The log
error plot is more significant at the lower codes (see Figure 31).
0
–20
–40
–60
–80
Rev. E | Page 17 of 28
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
CODE (From 1 to 1023 by 2.0 × 103)
Figure 31. Log Error Conformance for Odd Numbers of Bits Only
(Even Numbers of Bits Are Ideal)
02660-043
Key programming features include the following:
GAIN (dB)
The ADN2850 digital resistor includes a set of user
programming features to address the wide number of
applications for these universal adjustment devices.
ADN2850
Data Sheet
For example, if RWB_RATED = 250 kΩ and the data in the SDO
shows XXXX XXXX 1001 1100 0000 1111, RWB at full scale can
be calculated as follows:
Using CS to Re-Execute a Previous Command
Another subtle feature of the ADN2850 is that a subsequent CS
strobe, without clock and data, repeats a previous command.
E
A
MSB: 1 = positive
Next 7 LSB: 001 1100 = 28
8 LSB: 0000 1111 = 15 × 2−8 = 0.06
% tolerance = 28.06%
Therefore, RWB at full scale = 320.15 kΩ
Using Additional Internal Nonvolatile EEMEM
The ADN2850 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other components,
look-up tables, or system identification information. Table 10 provides an address map of the internal storage registers shown in the
functional block diagram (see Figure 1) as EEMEM1, EEMEM2,
and 26 bytes (13 addresses × 2 bytes each) of User EEMEM.
RDAC STRUCTURE
The RDAC contains multiple strings of equal resistor segments
with an array of analog switches that acts as the wiper
connection. The number of positions is the resolution of the device.
The ADN2850 has 1024 connection points, allowing it to provide
better than 0.1% setability resolution. Figure 32 shows an
equivalent structure of the connections among the three
terminals of the RDAC. The SWB is always on, while the
switches, SW(0) to SW(2N − 1), are on one at a time, depending on
the resistance position decoded from the data bits. Because the
switch is not ideal, there is a 30 Ω wiper resistance, RW. Wiper
resistance is a function of supply voltage and temperature. The
lower the supply voltage or the higher the temperature, the
higher the resulting wiper resistance. Users should be aware of
the wiper resistance dynamics, if accurate prediction of the
output resistance is needed.
Table 10. EEMEM Address Map
EEMEM No.
1
2
3
4
…
15
16
Address
0000
0001
0010
0011
…
1110
1111
EEMEM Content for …
RDAC11
RDAC2
USER12
USER2
…
USER13
RWB1 tolerance3
RDAC data stored in EEMEM locations is transferred to the corresponding
RDAC register at power-on, or when Instruction 1, Instruction 8, and PR are
executed.
2
USERx are internal nonvolatile EEMEM registers available to store and
retrieve constants and other 16-bit information using Instruction 3 and
Instruction 9, respectively.
3
Read only.
1
E
A
A
SW(2N – 1)
Calculating Actual End-to-End Terminal Resistance
RDAC
WIPER
REGISTER
AND
DECODER
The resistance tolerance is stored in the EEMEM register during
factory testing. The actual end-to-end resistance can, therefore,
be calculated, which is valuable for calibration, tolerance matching,
and precision applications. Note that this value is read only and
the RWB2 at full scale matches with RWB1 at full scale, typically
0.1%.
The resistance tolerance in percentage is contained in the last
16 bits of data in EEMEM Register 15. The format is the sign
magnitude binary format with the MSB designate for sign
(0 = negative and 1 = positive), the next 7 MSB designate the
integer number, and the 8 LSB designate the decimal number
(see Table 12).
RS
W
SW(2N – 2)
RS
SW(1)
RS
SW(0)
RS = RWB_NOMINAL/2N
DIGITAL
CIRCUITRY
OMITTED FOR
CLARITY
SWB
B
02660-044
A
Figure 32. Equivalent RDAC Structure
Table 11. Nominal Individual Segment Resistor Values
Device Resolution
1024-Step
25 kΩ
24.4Ω
250 kΩ
244Ω
Table 12. Calculating End-to-End Terminal Resistance
Bit
Sign
Mag
D15
D14
D13
Sign
26
25
D12
D11
D10
D9
24
23
22
21
7 Bits for Integer Number
D8
20
.
Decimal
Point
Rev. E | Page 18 of 28
D7
D6
D5
D4
D3
D2
D1
D0
2−1
2−2
2−3
2−4
2−5
2−6
8 Bits for Decimal Number
2−7
2−8
Data Sheet
ADN2850
PROGRAMMING THE VARIABLE RESISTOR
The nominal resistance of the RDAC between Terminal W and
Terminal B, RWB, is available with 25 kΩ and 250 kΩ with
1024 positions (10-bit resolution). The final digits of the part
number determine the nominal resistance value, for example,
25 kΩ = 24.4 Ω; 250 kΩ = 244 Ω.
The 10-bit data-word in the RDAC latch is decoded to select one of
the 1024 possible settings. The following description provides the
calculation of resistance, RWB, at different codes of a 25 kΩ part.
The first connection of the wiper starts at Terminal B for
Data 0x000. RWB(0) is 30 Ω because of the wiper resistance, and
it is independent of the nominal resistance. The second connection
is the first tap point where RWB(1) becomes 24.4 Ω + 30 Ω = 54.4 Ω
for Data 0x001. The third connection is the next tap point
representing RWB(2) = 48.8 Ω + 30 Ω = 78.8 Ω for Data 0x002,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at RWB(1023) =
25006 Ω. See Figure 32 for a simplified diagram of the equivalent
RDAC circuit.
100
RWB
of 30 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal switches.
The typical distribution of RWB_NOM from channel to channel is
±0.2% within the same package. Device-to-device matching is
process lot dependent upon the worst case of ±30% variation.
However, the change in RWB at full scale with temperature has a
35 ppm/°C temperature coefficient.
PROGRAMMING EXAMPLES
The following programming examples illustrate a typical sequence
of events for various features of the ADN2850. See Table 8 for
the instructions and data-word format. The instruction numbers,
addresses, and data appearing at the SDI and SDO pins are in
hexadecimal format.
Table 14. Scratchpad Programming
SDI
0xB00100
SDO
0xXXXXXX
0xB10200
0xB00100
Action
Writes Data 0x100 into RDAC1 register,
Wiper W1 moves to 1/4 full-scale
position.
Loads Data 0x200 into RDAC2 register,
Wiper W2 moves to 1/2 full-scale
position.
RWB(D) (% RWF)
75
Table 15. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM
50
SDI
0xB00100
SDO
0xXXXXXX
0xE0XXXX
0xB00100
0xE0XXXX
0xE0XXXX
0x20XXXX
0xXXXXXX
0
0
256
512
CODE (Decimal)
768
02660-045
25
1023
Figure 33. RWB(D) vs. Decimal Code
Action
Writes Data 0x100 into RDAC1
register, Wiper W1 moves to 1/4 fullscale position.
Increments RDAC1 register by one to
0x101.
Increments RDAC1 register by one to
0x102. Continue until desired wiper
position is reached.
Stores RDAC2 register data into
EEMEM1. Optionally, tie WP to GND to
protect EEMEM values.
E
The general equation that determines the programmed output
resistance between Terminal Bx and Terminal Wx is
RWB (D ) =
D
× RWB _ NOM + RW
1024
(1)
where:
D is the decimal equivalent of the data contained in the RDAC
register.
RWB_NOM is the nominal resistance value
RW is the wiper resistance.
A
The EEMEM values for the RDACs can be restored by poweron, by strobing the PR pin, or by the two commands shown in
Table 16.
E
A
RWB(D) (Ω)
25,006
12,530
54.4
30
A
Table 16. Restoring the EEMEM Values to RDAC Registers
SDI
0x10XXXX
Table 13. RWB (D) at Selected Codes for RWB_NOM = 25 kΩ
D (Dec)
1023
512
1
0
A
Output State
Full scale
Midscale
1 LSB
Zero scale (wiper contact resistor)
Note that, in the zero-scale condition, a finite wiper resistance
Rev. E | Page 19 of 28
SDO
0xXXXXXX
Action
Restores the EEMEM1 value to the
RDAC1 register.
ADN2850
Data Sheet
Table 17. Using Left-Shift by One to Increment 6 dB Steps
Table 19. Reading Back Data from Memory Locations
SDI
0xC0XXXX
SDO
0xXXXXXX
SDI
0x92XXXX
SDO
0xXXXXXX
0x00XXXX
0x92AAAA
0xC1XXXX
0xC0XXXX
Action
Moves Wiper 1 to double the
present data contained in the
RDAC1 register.
Moves Wiper 2 to double the
present data contained in the
RDAC2 register.
Action
Prepares data read from USER1
EEMEM location.
NOP Instruction 0 sends a 24-bit word
out of SDO, where the last 16 bits
contain the contents in USER1 EEMEM
location.
Table 18. Storing Additional User Data in EEMEM
Table 20. Reading Back Wiper Settings
SDI
0x32AAAA
SDO
0xXXXXXX
SDI
0xB00200
0xC0XXXX
SDO
0xXXXXXX
0xB00200
0x335555
0x32AAAA
0xA0XXXX
0xC0XXXX
0xXXXXXX
0xA003FF
Action
Stores Data 0xAAAA in the extra
EEMEM location USER1. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
Stores Data 0x5555 in the extra
EEMEM location USER2. (Allowable to
address in 13 locations with a
maximum of 16 bits of data.)
Action
Writes RDAC1 to midscale.
Doubles RDAC1 from midscale to full
scale.
Prepares reading wiper setting from
RDAC1 register.
Reads back full-scale value from SDO.
EVAL-ADN2850SDZ EVALUATION KIT
Analog Devices, Inc., offers a user-friendly EVALADN2850SDZ evaluation kit that can be controlled by a PC in
conjunction with the DSP platform. The driving program is
self-contained; no programming languages or skills are needed.
Rev. E | Page 20 of 28
Data Sheet
ADN2850
APPLICATIONS INFORMATION
C1
GAIN CONTROL COMPENSATION
A digital resistor is commonly used in gain control such as the
noninverting gain amplifier shown in Figure 34.
C2
2.2pF
+2.5V
R1
R2
B
VI
W
R2
250kΩ
B
V+
W
AD8601
R
R
B
C2
U1
ADJUSTED
CONCURRENTLY
VO
VI
Figure 35. Sallen-Key Low-Pass Filter
02660-047
C1
11pF
–2.5V
02660-055
W
The design equations are
Figure 34. Typical Noninverting Gain Amplifier
When the RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a zero for the 1/βO
term with 20 dB/dec, whereas a typical op amp gain bandwidth
product (GBP) has −20 dB/dec characteristics. A large R2 and
finite C1 can cause the frequency of this zero to fall well below
the crossover frequency. Therefore, the rate of closure becomes
40 dB/dec, and the system has a 0° phase margin at the crossover
frequency. If an input is a rectangular pulse or step function, the
output can ring or oscillate. Similarly, it is also likely to ring when
switching between two gain values; this is equivalent to a stop
change at the input.
Depending on the op amp GBP, reducing the feedback resistor
might extend the frequency of the zero far enough to overcome
the problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option because of the variation of R2. As a result, one can
use the previous relationship and scale C2 as if R2 were at its
maximum value. Doing this might overcompensate and
compromise the performance when R2 is set at low values.
VO
=
VI
ωf 2
ωf
S2 +
S + ωf 2
Q
ωO =
1
R1 R2 C1 C2
(11)
1
1
+
R1 C1 R2 C2
(12)
Q=
(10)
First, users should select convenient values for the capacitors.
To achieve maximally flat bandwidth, where Q = 0.707, let C1
be twice the size of C2 and let R1 equal R2. As a result, the user
can adjust R1 and R2 concurrently to the same setting to
achieve the desirable bandwidth.
PROGRAMMABLE OSCILLATOR
In a classic Wien bridge oscillator, the Wien network (R||C, R'C')
provides positive feedback, whereas R1 and R2 provide negative
feedback (see Figure 36).
Alternatively, it avoids the ringing or oscillation at the worst
case. For critical applications, find C2 empirically to suit the
oscillation. In general, C2 in the range of a few picofarads to no
more than a few tenths of picofarads is usually adequate for the
compensation.
Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.
PROGRAMMABLE LOW-PASS FILTER
In analog-to-digital conversions (ADCs), it is common to
include an antialiasing filter to band limit the sampling signal.
Therefore, the dual-channel ADN2850 can be used to construct
a second-order Sallen-Key low-pass filter, as shown in Figure 35.
Rev. E | Page 21 of 28
FREQUENCY
ADJUSTMENT
C
2.2nF
R
25kΩ
B
R'
25kΩ
C'
VP
A
W
+2.5V
2.2nF
W
+
B
U1
V+
VO
OP1177
– V–
–2.5V
R = R' = ADN2850
R2B = AD5231
D1 = D2 = 1N4148
R2B
10kΩ
B
W
R1
1kΩ
A
R2A
2.1kΩ
D1
D2
AMPLITUDE
ADJUSTMENT
02660-056
R1
47kΩ
VO
V–
U1
Figure 36. Programmable Oscillator with Amplitude Control
ADN2850
Data Sheet
At the resonant frequency, fO, the overall phase shift is zero, and
the positive feedback causes the circuit to oscillate. With R = R',
VCC
C = C', and R2 = R2A /(R2B + RDIODE), the oscillation frequency is
CS
CONTROL
RDAC1
B2
EEMEM
W2
At resonance, setting R2/R1 = 2 balances the bridge. In practice,
R2/R1 should be set slightly larger than 2 to ensure that the
oscillation can start. On the other hand, the alternate turn-on
of the diodes, D1 and D2, ensures that R2/R1 is smaller than 2,
momentarily stabilizing the oscillation.
ERSET
RDAC2
CLKN
CLKP
DATAP
DATAN
Figure 37. Optical Supervisory System
When the frequency is set, the oscillation amplitude can be
turned by R2B because
2
VO = I D R2B + V D
3
IBIAS
SDI
02660-057
(14)
PSET IMODP
W1
DATAN
D
× RWB _ NOM + RW
1024
CLK
B1
EEMEM
DATAP
where R is equal to RWA such that :
RWB ( D ) =
ADN2841
(13)
CLKP
1
1
or fO =
RC
2πRC
IMPD
ADN2850
CLKN
ωO =
VCC
(15)
VO, ID, and VD are interdependent variables. With proper
selection of R2B, an equilibrium is reached such that VO
converges. R2B can be in series with a discrete resistor to
increase the amplitude, but the total resistance cannot be too
large to saturate the output.
In Figure 35 and Figure 36, the frequency tuning requires that
both RDACs be adjusted concurrently to the same settings.
Because the two channels might be adjusted one at a time, an
intermediate state occurs that might not be acceptable for some
applications. Of course, the increment/decrement instructions
(Instruction 5, Instruction 7, Instruction 13, and Instruction 15)
can all be used. Different devices can also be used in daisy-chain
mode so that parts can be programmed to the same settings
simultaneously.
OPTICAL TRANSMITTER CALIBRATION WITH
ADN2841
The ADN2850, together with the multirate 2.7 Gbps laser diode
driver, ADN2841, forms an optical supervisory system in which
the dual digital resistor can be used to set the laser average optical
power and extinction ratio (see Figure 37). The ADN2850 is
particularly suited for the optical parameter settings because of
its high resolution and superior temperature coefficient
characteristics.
The ADN2841 is a 2.7 Gbps laser diode driver that uses a
unique control algorithm to manage the average power and
extinction ratio of the laser after its initial factory calibration.
The ADN2841 stabilizes the data transmission of the laser by
continuously monitoring its optical power and correcting the
variations caused by temperature and the degradation of the
laser over time. In the ADN2841, the IMPD monitors the laser
diode current. Through its dual-loop power and extinction
ratio control calibrated by the dual RDACs of the ADN2850, the
internal driver controls the bias current, IBIAS, and consequently
the average power. It also regulates the modulation current,
IMODP, by changing the modulation current linearly with slope
efficiency. Therefore, any changes in the laser threshold current or
slope efficiency are compensated for. As a result, the optical
supervisory system minimizes the laser characterization efforts
and, therefore, enables designers to apply comparable lasers
from multiple sources.
INCOMING OPTICAL POWER MONITORING
The ADN2850 comes with a pair of matched diode connected
PNPs, Q1 and Q2, that can be used to configure an incoming
optical power monitoring function. With a reference current
source, an instrumentation amplifier, this feature can be used to
monitor the optical power by knowing the dc average photodiode
current from the following relationships:
V1 = V BE1 = VT ln
I C1
I S1
(16)
V2 = V BE 2 = VT ln
IC2
I S2
(17)
Knowing IC1 = α1 × IPD, IC2 = α2 x IREF, and Q1-Q2 are matched,
therefore α and IS are matched. Combining Equation 16 and
Equation 17 theoretically yields:
V2 − V1 = VT ln
Rev. E | Page 22 of 28
I REF
I PD
(18)
Data Sheet
ADN2850
0.30
V2 – V1 (V)
0.25
(VT = 26 mV @ 25°C)
k is the Boltzmann’s constant, 1.38e-23 Joules/Kelvin.
q is the electron charge, 1.6e-19 coulomb.
T is the temperature in Kelvin.
IPD is the photodiode current.
IREF is the reference current.
0.20
6
0.15
3
0.10
0
0.05
–3
Figure 38 shows a conceptual circuit.
0
0.1µ
–6
1µ
10µ
POST
AMP
TIA
LPF
0.75 BIT RATE
9
ERROR
APPROXIMATING ERROR (%)
IS1 and IS2 are saturation current.
V1, V2 are VBE, base-emitted voltages of the diode connector
transistors.
VT is the thermal voltage, which is equal to k × T/q
12
IREF = 1mA
TA = 25°C
DEVICE 1
DEVICE 2
DEVICE 3
CURVE FIT
100µ
02660-138
where:
1m
IPD (A)
DATA
Figure 39. V2 – V1 Error Versus Input Current.
CDR
CLOCK
10nF
RESISTANCE SCALING
IPD
The ADN2850 offers 25 kΩ or 250 kΩ nominal resistance.
When users need lower resistance but must maintain the
number of adjustment steps, they can parallel multiple devices. For
example, Figure 40 shows a simple scheme of paralleling two
channels of RDACs. To adjust half the resistance linearly per
step, program both RDACs concurrently with the same settings.
VT COMPENSATION
IREF
(1 + 100k/RG) × (V1 – V2)
RG
AD623
IN AMP
LOG
AVERAGE
POWER
ADN2850
W2
V1
Q1
VSS B
1
B2
V2
Q2
°C
PRC
THERMISTOR
GND
LOG AMP
–5V
W1
W2
B2
B1
02660-058
W1
02660-137
VDD
Figure 38. Conceptual Incoming Optical Power Monitoring Circuit
Equation 19 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V2 and V1. A curve fit approximation
yields
V2  V1  0.026 ln
0.001
 0.03
I PD
Figure 40. Reduce Resistance by Half with Linear Adjustment Characteristics
Figure 40 shows that the digital rheostat change steps linearly.
Alternatively, pseudo log taper adjustment is usually preferred in
applications such as audio control. Figure 41 shows another type
of resistance scaling. In this configuration, the smaller the R2
with respect to RAB, the more the pseudo log taper characteristic
of the circuit behaves.
W1
B1
(19)
The offset is caused by the transistors self-heating and the
thermal gradient effect. As seen in Figure 39, the error between
an approximation and the actual performance ranges is less
than 0% to –4% from 0.1 mA to 0.1 μA.
R
02660-060
The output voltage represents the average incoming optical
power. The output voltage of the log stage does not have to be
accurate from device to device, as the responsivity of the
photodiode will change between devices. An op amp stage is
shown after the log amp stage, which compensates for VT
variation over temperature.
Figure 41. Resistor Scaling with Pseudo Log Adjustment Characteristics
The equation is approximated as
R EQUIVALENT 
RWB  51, 200
RWB  51, 200  1024  R
(17)
Users should also be aware of the need for tolerance matching
as well as for temperature coefficient matching of the components.
Rev. E | Page 23 of 28
ADN2850
Data Sheet
RDAC CIRCUIT SIMULATION MODEL
In operation, such as gain control, the tolerance mismatch
between the digital resistor and the discrete resistor can cause
repeatability issues among various systems (see Figure 42).
Because of the inherent matching of the silicon process, it is
practical to apply the dual-channel device in this type of
application. As such, R1 can be replaced by one of the channels
of the digital resistor and programmed to a specific value. R2 can
be used for the adjustable gain. Although it adds cost, this approach
minimizes the tolerance and temperature coefficient mismatch
between R1 and R2. This approach also tracks the resistance
drift over time. As a result, these less than ideal parameters
become less sensitive to system variations.
B R2
W
C1
R1*
–
AD8601
+
VO
U1
* REPLACED WITH ANOTHER
CHANNEL OF RDAC
02660-061
Vi
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. A parasitic
simulation model is shown in Figure 43.
RDAC
25kΩ
B
CB
11pF
80pF
W
02660-063
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS
Figure 43. RDAC Circuit Simulation Model (RDAC = 25 kΩ)
The following code provides a macro model net list for the
25 kΩ RDAC:
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT DPOT ( W, B)
*
CW W 0 80E-12
RWB W B {D/1024 * RDAC + 50}
CB B 0 11E-12
*
.ENDS DPOT
Figure 42. Linear Gain Control with Tracking Resistance Tolerance,
Drift, and Temperature Coefficient
Rev. E | Page 24 of 28
Data Sheet
ADN2850
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.60 MAX
2.40 REF
0.60 MAX
13
1
12
0.80
BSC
4.75 BSC
SQ
3.25
3.10 SQ
2.95
EXPOSED
PAD
9
0.75
0.60
0.50
TOP VIEW
1.00
0.85
0.80
4
8
BOTTOM VIEW
0.80 MAX
0.65 TYP
12° MAX
0.35
0.30
0.25
SEATING
PLANE
5
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
05-09-2012-A
PIN 1
INDICATOR
PIN 1
INDICATOR
16
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 44. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 × 5 mm Body, Very Thin Quad
(CP-16-6)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 45. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADN2850BRUZ25
ADN2850BRUZ25-RL7
ADN2850BCPZ25
ADN2850BCPZ25-RL7
ADN2850BCPZ250
ADN2850BCPZ250-RL7
EVAL-ADN2850SDZ
1
2
RWB (kΩ)
25
25
25
25
250
250
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
RU-16
RU-16
CP-16-6
CP-16-6
CP-16-6
CP-16-6
Z = RoHS Compliant Part.
The evaluation board is shipped with the 25 kΩ RWB resistor option; however, the board is compatible with all available resistor value options.
Rev. E | Page 25 of 28
ADN2850
Data Sheet
NOTES
Rev. E | Page 26 of 28
Data Sheet
ADN2850
NOTES
Rev. E | Page 27 of 28
ADN2850
Data Sheet
NOTES
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02660-0-6/12(E)
Rev. E | Page 28 of 28