A-Data ADS6616A4A Synchronous DRAM 1M x 16 Bit x 4 Banks General Description Features The ADS6616A4A are four-bank Synchronous DRAMs organized as 1,048,576 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system clock •Burst Read single write operation •Auto & Self refresh •4096 refresh cycle •DQM for masking •Package:54-pins 400 mil TSOP-Type II Ordering Information. Part No. Frequency Interface Package ADS6616A4A-5 ADS6616A4A-6 200Mhz 166Mhz LVTTL LVTTL 400mil 54pin TSOPII 400mil 54pin TSOPII ADS6616A4A-7 ADS6616A4A-7.5 143Mhz 133Mhz LVTTL LVTTL 400mil 54pin TSOPII 400mil 54pin TSOPII Pin Assignment VDD 1 54 Vss DQ0 2 53 DQ15 VDDQ 3 52 VssQ DQ1 4 51 DQ14 DQ2 5 50 DQ13 VSS 6 49 VDDQ DQ3 7 48 DQ12 DQ4 8 47 DQ11 VDDQ 9 46 VSSQ DQ5 10 45 DQ10 DQ6 11 44 DQ9 VSSQ 12 43 VDDQ DQ7 13 42 DQ8 VDD 14 41 VSS LDQM 15 40 NC /WE 16 39 UDQM /CAS 17 38 CLK /RAS 18 37 CKE /CS 19 36 NC BA0 20 35 A11 BA1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 VDD 27 28 VSS 54-pin plastic TSOP II 400 mil Rev 1.1 April, 2001 1 A-Data ADS6616A4A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM A0~A11 Address Row / Column address are multiplexed on the same pins. Row address : RA0~RA11 Column address : CA0~CA7 BA0~BA1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ15 Data Data inputs / outputs are multiplexed on the same pins. L(U)DQM Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VDD/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Bank3 Bank2 Bank1 Mode Register Address Buffer & Refresh Counter Row Decoder Address Bank0 /CAS /WE Rev 1.1 April, 2001 Column Address Buffer & Refresh Counter L(U)DQM Column Decoder Data Control Circuit 2 Data Latch /RAS Control Logic /CS Command Decoder Amplifier DQ A-Data ADS6616A4A Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -0.3 ~ VDD+0.3 V VDD, VDDQ -0.3 ~ 4.6 V TSTG -55 ~ +150 ℃ Power dissipation PD 1 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH=-2mA Output logic low voltage VOL - - 0.4 V IOL=2mA Input leakage current IIL -5 - 5 uA 3 Output leakage current IOL -5 - 5 uA 4 Note Supply voltage Note Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable. 2.VIL(min)=-1.5V AC for pulse width ≦ 10ns acceptable. 3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≦ VOUT ≦ VDD. AC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 ℃ Parameter Symbol Value Unit VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input rise / fall time TR / tF 1 Ns Output timing measurement reference level Voutfef 1.4 V CL 50 pF AC input high / low level voltage Input timing measurement reference level voltage Output load capacitance for access time measurement Note: 1. 3.15V ≦ VDD 2 ≦ 3.6V is applied for ADS6616A4A5. 2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details, refer to AC/DC output load circuit. Rev 1.1 April, 2001 3 A-Data ADS6616A4A Capacitance TA=25℃, f-=1Mhz, VDD=3.3V Parameter Pin Input capacitance Symbol Min Max Unit CLK Cl1 2.5 4 pF A0~A11,BA0,BA1,CKE,/CS,/RAS, Cl2 2.5 5 pF CI/O 4 6.5 pF /CAS,/WE,DQM Data input / output capacitance DQM Output load circuit 3.3 V 1200 ohms VOH(DC) = 2.4V,I OH= -2mA Output VOL(DC) = 0.4V,I OL= 2mA 50 pF 870 ohms DC Characteristics I Parameter Symbol Min Max Unit Note Input leakage current ILI -5 5 uA 1 Output leakage current ILO -5 5 uA 2 Output high voltage VOH 2.4 - V IOH = -4mA Output low voltage VOL - 0.4 V IOL = 4mA Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V. 2.DOUT is disabled, VOUT = 0 to 3.6. Rev 1.1 April, 2001 4 A-Data ADS6616A4A DC Characteristics II Speed Parameter Symbol Test condition -5 -6 -7 -7.5 105 90 80 80 Unit Note mA 1 Burst length=1, One bank active Operating Current Precharge standby IDD1 IDD2P tRC≧tRC(min),IOL=0mA CKE≦VIL(max), tCK=min 1 current in power down mode mA IDD2PS CKE≦VIL(max), tCK=∞ 1 CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Precharge standby IDD2N changed one time during 2clks. current in Non power All other pins ≧VDD-0.2V or ≦ down mode 0.2V 35 mA CKE≧VIH(min), tCK=∞ IDD2NS 8 Input signals are stable. Active standby IDD3P CKE≦VIL(max), tCK=min 5 mA current in power down mode IDD3PS CKE≦VIL(max), tCK=∞ 5 CKE≧VIH(min), /CS≧VIH(min), tCK=min input signals are Active standby IDD3N changed one time during 2clks. current in Non power All other pins ≧VDD-0.2V or ≦ down mode 0.2V 30 mA CKE≧VIH(min), tCK=∞ IDD3NS 20 Input signals are stable. tCK≧tCK(min),IOL=0 mA Burst mode operating IDD4 current 185 165 145 145 mA 1 120 mA 2 1 mA All banks active tRRC≧tRRC(min), All banks Auto refresh current IDD5 active Self refresh current IDD6 CKE≦0.2V Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC is shown at AC characteristics. Rev 1.1 April, 2001 5 A-Data ADS6616A4A AC Characteristics -5 Parameter -7 -7.5 Unit Note Min System clock /CAS Latency = 3 -6 Symbol tCK3 Max 5 Min Max 6 1000 Min Max 7 Max 7 1000 ns 2 - ns 1 - 2 - ns 1 - 5.5 - 5.5 ns 2 5.5 - 6 - 6 60 - 65 - 65 - - 60 - 65 - 65 - 14 - 18 - 20 - 20 - ns tRAS 40 100K 42 100K 42 120K 42 120K ns /RAS precharge time tRP 14 - 18 - 20 - 20 - ns /RAS to /RAS bank active delay tRRD 10 - 12 - 14 - 14 - ns /CAS to /CAS delay tCCD 1 - 1 - 1 - 1 - CLK Data – out hold time tOH 1.5 - 2 - 2 - 2 - ns Data – input setup time tDS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Data – input hold time tDH 1 - 1 - 1 - 1 - ns 1 Address setup time tAS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Address hold time tAH 1 - 1 - 1 - 1 - ns 1 CKE setup time tCKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 CKE hold time tCKH 1 - 1 - 1 - 1 - ns 1 Command setup time tCS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Command hold time tCH 1 - 1 - 1 - 1 - ns 1 Refresh time tREF 64 - 64 - 64 - 64 - ms Cycle time /CAS Latency = 2 1000 Min 7.5 1000 tCK2 7 8 8 Clock high pulse width tCHW 1.5 - 2 - 2 - Clock low pulse width tCLW 1.5 - 2 - 2 Access time /CAS Latency = 3 tAC3 - 4.5 5 form clock /CAS Latency = 2 tAC2 - 5.5 /RAS cycle Operation tRC 54 - time Auto Refresh tRRC 54 /RAS to /CAS delay tRCD /RAS active time ns Note : 1. Assume tR / tF (input rise and fall time) is 1 ns. 2. Access times to be measured with input signals of 1v / ns edge rate. 3.A new command can be given tRRC after self refresh exit. Rev 1.1 April, 2001 6 A-Data ADS6616A4A Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM Mode Register Set H X L L L L X OP code H X X X No Operation H X X X L H H H Bank Active H X L L H H X H X L H L H X ADDR A10/AP RA Read BA V L CA Read with Auto Precharge Write H X L H L L X CA Write with Auto Precharge H X L L H L X Precharge select Bank Burst Stop H DQM H Auto Refresh H H L L L Entry H L L L X L H H H X Exit L H L X X L H X X X H X X X Precharge L H H H Power down H X X X L H H H H X X X L V V V Exit Rev 1.1 April, 2001 L X X L X H X X L Clock Suspend V H H H L X H L X V H H H X L Entry V X X X Self Refresh Exit L H Precharge All Bank Entry V H X H X 7 X X A-Data ADS6616A4A Package Information SYMBOL A A1 A2 B c D HE E e L L1 MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40 S θ 0° MILLIMETER NOM. 0.10 1.00 0.35 22.22 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 MIN. 0.002 0.037 0.012 0.005 0.60 0.460 0.390 0.031 0.016 8° 0° 400mil 54pin TSOP II Package Rev 1.1 April, 2001 8 INCH NOM. 0.004 0.039 0.014 0.875 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.018 0.008 0.470 0.410 0.024 8°