a
Low Cost DSP Microcomputers
ADSP-2104/ADSP-2109
FUNCTIONAL BLOCK DIAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports and Timer
FEATURES
20 MIPS, 50 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC Package
GENERAL DESCRIPTION
The ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
DATA ADDRESS
GENERATORS
DAG 1
DAG 2
MEMORY
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
TIMER
SPORT 1
ADSP-2100 CORE
The ADSP-2100 Family’s flexible architecture and comprehensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:
•
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
The ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
The ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
The ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
The ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADSP-2104/ADSP-2109
The ADSP-2109 is a memory-variant version of the ADSP2104 and contains factory-programmed on-chip ROM program
memory.
The ADSP-2109 eliminates the need for an external boot EPROM
in your system, and can also eliminate the need for any external
program memory by fitting the entire application program in
on-chip ROM. This device provides an excellent option for
volume applications where board space and system cost constraints
are of critical concern.
Development Tools
The ADSP-2104/ADSP-2109 processors are supported by a
complete set of tools for system development. The ADSP-2100
Family Development Software includes C and assembly
language tools that allow programmers to write code for any
ADSP-21xx processor. The ANSI C compiler generates ADSP21xx assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-2104
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Information
This data sheet provides a general overview of ADSP-2104/
ADSP-2109 processor functionality. For detailed design
information on the architecture and instruction set, refer to the
ADSP-2100 Family User’s Manual, available from Analog
Devices.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 8
ADSP-2109 Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Procedure for ADSP-2109 ROM Processors . . . . 9
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPECIFICATIONS (ADSP-2104/ADSP-2109) . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 14
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS (ADSP-2104L/ADSP-2109L) . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . .
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS (ADSP-2104/ADSP-2109) . . . . .
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) . .
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–2–
16
16
16
17
18
18
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
REV. 0
ADSP-2104/ADSP-2109
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
PROGRAM
MEMORY
DATA
MEMORY
SRAM
or ROM
SRAM
PROGRAM
SEQUENCER
24
14 PMA BUS
BOOT
ADDRESS
GENERATOR
16
TIMER
PMA BUS
14
14 DMA BUS
24
MUX
DMA BUS
PMD BUS
PMD BUS
24
BUS
EXCHANGE
16
EXTERNAL
ADDRESS
BUS
MUX
DMD BUS
DMD BUS
INPUT REGS
INPUT REGS
INPUT REGS
ALU
MAC
SHIFTER
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
16
R Bus
EXTERNAL
DATA
BUS
COMPANDING
CIRCUITRY
TRANSMIT REG
TRANSMIT REG
RECEIVE REG
RECEIVE REG
SERIAL
PORT 0
SERIAL
PORT 1
5
5
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
ARCHITECTURE OVERVIEW
Figure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data directly
and have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. The MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
REV. 0
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) onchip memory.
Efficient data transfer is achieved with the use of five internal
buses:
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permitting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. The processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The memory interface supports slow memories and memorymapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
One bus grant execution mode (GO Mode) allows the ADSP2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
–3–
ADSP-2104/ADSP-2109
The ADSP-2104/ADSP-2109 can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET signal.
Flexible Interrupt Scheme—Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, the ADSP-2104 to use a 150 ns EPROM as external
boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.
Multichannel Capability (SPORT0 Only)—SPORT0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
Alternate Configuration—SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Interrupts
The interrupt controller lets the processor respond to interrupts
with a minimum of overhead. Up to three external interrupt
input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is
always available as a dedicated pin; IRQ1 and IRQ0 may be
alternately configured as part of Serial Port 1. The ADSP-2104/
ADSP-2109 also supports internal interrupts from the timer,
and serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities are shown in Table I.
Serial Ports
The ADSP-2104/ADSP-2109 processor includes two synchronous serial ports (“SPORTs”) for serial communications and
multiprocessor communication.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of operation are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Table I. Interrupt Vector Addresses & Priority
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
Function
SCLK
RFS
TFS
DR
DT
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
The serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-buffered
transmit and receive function.
ADSP-2104/ADSP-2109
Interrupt
Source
Interrupt
Vector Address
RESET Startup
IRQ2
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0x0000
0x0004 (High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018 (Low Priority)
The ADSP-2104/ADSP-2109 uses a vectored interrupt scheme:
when an interrupt is acknowledged, the processor shifts program
control to the interrupt vector address corresponding to the
interrupt received. Interrupts can be optionally nested so that a
higher priority interrupt can preempt the currently executing
interrupt service routine. Each interrupt vector location is four
instructions in length so that simple service routines can be
coded entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Flexible Clocking—Each SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals internally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
Different Word Lengths—Each SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
A-law and µ-law companding according to CCITT recommendation G.711.
–4–
REV. 0
ADSP-2104/ADSP-2109
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the
interrupt instruction is executed.
Pin Definitions
Table II shows pin definitions for the ADSP-2104/ADSP-2109
processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock Signals
The ADSP-2104/ADSP-2109’s CLKIN input may be driven by
a crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used.
Table II. ADSP-2104/ADSP-2109 Pin Definitions
Pin
Name(s)
# of
Pins
Input /
Output
Address
Data1
14
24
O
I/O
RESET
IRQ2
BR2
BG
PMS
DMS
BMS
RD
WR
MMAP
CLKIN, XTAL
CLKOUT
VDD
GND
SPORT0
SPORT1
or Interrupts & Flags:
IRQ0 (RFS1)
IRQ1 (TFS1)
FI (DR1)
FO (DT1)
1
1
1
1
1
1
1
1
1
1
2
1
I
I
I
O
O
O
O
O
O
I
I
O
5
5
I/O
I/O
Address outputs for program, data and boot memory.
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
Processor Reset Input
External Interrupt Request #2
External Bus Request Input
External Bus Grant Output
External Program Memory Select
External Data Memory Select
Boot Memory Select
External Memory Read Enable
External Memory Write Enable
Memory Map Select Input
External Clock or Quartz Crystal Input
Processor Clock Output
Power Supply Pins
Ground Pins
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
1
1
1
1
I
I
I
O
External Interrupt Request #0
External Interrupt Request #1
Flag Input Pin
Flag Output Pin
Function
NOTES
1
Unused data bus lines may be left floating.
2
BR must be tied high (to V DD) if not used.
REV. 0
–5–
ADSP-2104/ADSP-2109
CLKIN
XTAL
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.
CLKOUT
ADSP-2104/
ADSP-2109
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the onchip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
Figure 2. External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET signal initiates a complete reset of the processor.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The external address bus is 14 bits wide.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
The processor writes data from the 16-bit registers to 24-bit
program memory using the PX register to provide the lower
eight bits. When the processor reads 16-bit data from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
ADSP-2104
or ADSP-2109
14
A13-0
ADDR13-0
1x CLOCK
or
CRYSTAL
CLKIN
D23-22
ADDR
XTAL
CLKOUT
24
DATA23-0
D15-8
DATA
RESET
IRQ2
OE
CS
BMS
BR
ADDR
D23-0
MMAP
DATA
(OPTIONAL)
SPORT 1
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
RD
WR
OE
WE
CS
SERIAL
DEVICE
(OPTIONAL)
PROGRAM
MEMORY
(OPTIONAL)
A13-0
ADDR
D23-8
SPORT 0
SCLK0
RFS0
TFS0
DT0
DR0
e.g. EPROM
2764
27128
27256
27512
A13-0
BG
SERIAL
DEVICE
BOOT
MEMORY
DATA
PMS
DMS
OE
WE
CS
DATA
MEMORY
&
PERIPHERALS
(OPTIONAL)
THE TWO MSBs OF THE DATA BUS (D23-22) ARE USED TO SUPPLY THE TWO MSBs OF THE
BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.
Figure 3. ADSP-2104/ADSP-2109 System
–6–
REV. 0
ADSP-2104/ADSP-2109
Program Memory Maps
Data Memory Interface
Program memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
INTERNAL RAM
0x0000
0x0000
512 WORDS
LOADED FROM
EXTERNAL
BOOT MEMORY
0x01FF
0x0200
RESERVED
The ADSP-2104/ADSP-2109 processors support memorymapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.
EXTERNAL
14K
1.5K
0x07FF
0x0800
0x37FF
0x3800
Data Memory Map
ADSP-2104
0x39FF
0x3A00
On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
INTERNAL RAM
EXTERNAL
14K
512 WORDS
RESERVED
1.5K
0x3FFF
0x3FFF
MMAP=0
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
MMAP=1
No Booting
0x0000
1K EXTERNAL
DWAIT0
Figure 4. ADSP-2104 Program Memory Maps
0x0400
1K EXTERNAL
DWAIT1
0x0000
0x0000
0x0800
2K
EXTERNAL
4K
INTERNAL
ROM
0x07FF
0x0800
0x0FF0
0x0FF0
0x3000
RESERVED
RESERVED
1K EXTERNAL
DWAIT3
0x0FFF
0x1000
0x0FFF
0x1000
EXTERNAL
RAM
10K EXTERNAL
DWAIT2
2K
INTERNAL
ROM
0x3400
1K EXTERNAL
DWAIT4
10K
EXTERNAL
12K
EXTERNAL
0x3800
256 WORDS
0x37FF
0x3800
0x3900
2K
INTERNAL
ROM
0x3FFF
0x3FFF
MMAP=0
0x3C00
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
MMAP=1
0x3FFF
Figure 5. ADSP-2109 Program Memory Maps
Figure 6. Data Memory Map
ADSP-2104
When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Interface”) is automatically initiated when RESET is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 512 words between addresses 0x3800–0x39FF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
REV. 0
INTERNAL
RAM
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state requirements. All zones default to seven wait states after RESET.
–7–
ADSP-2104/ADSP-2109
Boot Memory Interface
Boot memory is an external 16K by 8 space, divided into eight
separate 2K by 8 pages. The 8-bit bytes are automatically
packed into 24-bit instruction words by the processor, for
loading into on-chip program memory.
Three bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.
The boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. This allows
the ADSP-2104 to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. To accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
The ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
The BR signal is recognized during the booting sequence. The
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.
Bus Interface
The ADSP-2104/ADSP-2109 can relinquish control of their
data and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the processor is not performing an external
memory access, it responds to the active BR input in the next
cycle by:
•
Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,
•
•
Asserting the bus grant (BG) signal,
and halting program execution.
If the Go mode is set, however, the ADSP-2104/ADSP-2109
will not halt program execution until it encounters an instruction that requires an external memory access.
If the processor is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the cycle
after the access completes (up to eight cycles later depending on
the number of wait states). The instruction does not need to be
completed when the bus is granted; the processor will grant the
bus in between two memory accesses if an instruction requires
more than one external memory access.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to VDD).
Low Power IDLE Instruction
The IDLE instruction places the processor in low power state in
which it waits for an interrupt. When an interrupt occurs, it is
serviced and execution continues with instruction following
IDLE. Typically this next instruction will be a JUMP back to
the IDLE instruction. This implements a low-power standby
loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
IDLE n;
where n = 16, 32, 64, or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is increased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
–8–
REV. 0
ADSP-2104/ADSP-2109
ADSP-2109 Prototyping
You can prototype your ADSP-2109 system with the ADSP2104 RAM-based processor. When code is fully developed and
debugged, it can be submitted to Analog Devices for conversion
into a ADSP-2109 ROM product.
The ADSP-2101 EZ-ICE emulator can be used for development of ADSP-2109 systems. For the 3.3 V ADSP-2109, a
voltage converter interface board provides 3.3 V emulation.
Additional overlay memory is used for emulation of ADSP-2109
systems. It should be noted that due to the use of off-chip
overlay memory to emulate the ADSP-2109, a performance loss
may be experienced when both executing instructions and
fetching program memory data from the off-chip overlay
memory in the same cycle. This can be overcome by locating
program memory data in on-chip memory.
Ordering Procedure for ADSP-2109 ROM Processor
To place an order for a custom ROM-coded ADSP-2109, you
must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-2109 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a minimum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
REV. 0
–9–
ADSP-2104/ADSP-2109
Instruction Set
The ADSP-2104/ADSP-2109 assembly language uses an algebraic
syntax for ease of coding and readability. The sources and
destinations of computations and data movements are written
explicitly in each assembly statement, eliminating cryptic
assembler mnemonics.
Every instruction assembles into a single 24-bit word and
executes in a single cycle. The instructions encompass a wide
variety of instruction types along with a high degree of
operational parallelism. There are five basic categories of
instructions: data move instructions, computational instructions, multifunction instructions, program flow control instructions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
ALU Instructions
[IF cond]
AR|AF
=
=
=
=
=
=
=
=
=
=
=
=
=
=
xop + yop [+ C] ;
xop – yop [+ C– 1] ;
yop – xop [+ C– 1] ;
xop AND yop ;
xop OR yop ;
xop XOR yop ;
PASS xop ;
– xop ;
NOT xop ;
ABS xop ;
yop + 1 ;
yop – 1 ;
DIVS yop, xop ;
DIVQ xop ;
Add/Add with Carry
Subtract X – Y/Subtract X – Y with Borrow
Subtract Y – X/Subtract Y – X with Borrow
AND
OR
XOR
Pass, Clear
Negate
NOT
Absolute Value
Increment
Decrement
Divide
xop * yop ;
MR + xop * yop ;
MR – xop * yop ;
MR ;
0;
Multiply
Multiply/Accumulate
Multiply/Subtract
Transfer MR
Clear
Conditional MR Saturation
MAC Instructions
[IF cond]
IF MV
MR|MF =
=
=
=
=
SAT MR ;
Shifter Instructions
[IF cond]
[IF cond]
[IF cond]
[IF cond]
[IF cond]
SR = [SR OR] ASHIFT xop ;
SR = [SR OR] LSHIFT xop ;
SR = [SR OR] ASHIFT xop BY <exp>;
SR = [SR OR] LSHIFT xop BY <exp>;
SE = EXP xop ;
SB = EXPADJ xop ;
SR = [SR OR] NORM xop ;
Arithmetic Shift
Logical Shift
Arithmetic Shift Immediate
Logical Shift Immediate
Derive Exponent
Block Exponent Adjust
Normalize
Data Move Instructions
reg = reg ;
reg = <data> ;
reg = DM (<addr>) ;
dreg = DM (Ix , My) ;
dreg = PM (Ix , My) ;
DM (<addr>) = reg ;
DM (Ix , My) = dreg ;
PM (Ix , My) = dreg ;
Register-to-Register Move
Load Register Immediate
Data Memory Read (Direct Address)
Data Memory Read (Indirect Address)
Program Memory Read (Indirect Address)
Data Memory Write (Direct Address)
Data Memory Write (Indirect Address)
Program Memory Write (Indirect Address)
Multifunction Instructions
<ALU>|<MAC>|<SHIFT> , dreg = dreg ;
<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;
<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;
DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;
PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;
Computation with Register-to-Register Move
Computation with Memory Read
Computation with Memory Read
Computation with Memory Write
Computation with Memory Write
Data & Program Memory Read
ALU/MAC with Data & Program Memory Read
–10–
REV. 0
ADSP-2104/ADSP-2109
Program Flow Instructions
DO <addr> [UNTIL term] ;
[IF cond] JUMP (Ix) ;
[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;
[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN
JUMP <addr>;
IF [NOT ] FLAG_IN
CALL <addr>;
[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;
[IF cond] RTS ;
[IF cond] RTI ;
IDLE [(n)] ;
Do Until Loop
Jump
Call Subroutine
Jump/Call on Flag In Pin
Modify Flag Out Pin
Return from Subroutine
Return from Interrupt Service Routine
Idle
Miscellaneous Instructions
NOP ;
MODIFY (Ix , My);
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;
ENA|DIS
SEC_REG [, ...] ;
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
No Operation
Modify Address Register
Stack Control
Mode Control
Notation Conventions
Ix
My
<data>
<addr>
<exp>
<ALU>
<MAC>
<SHIFT>
cond
term
dreg
reg
;
,
[
]
[, ...]
option1 | option2
Index registers for indirect addressing
Modify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
Condition code for conditional instruction
Termination code for DO UNTIL loop
Data register (of ALU, MAC, or Shifter)
Any register (including dregs)
A semicolon terminates the instruction
Commas separate multiple operations of a single instruction
Optional part of instruction
Optional, multiple operations of an instruction
List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0 * MY1 ( RND), MX0=DM(I2,M1);
{MF=error * b eta}
MR=MX0 * MF ( RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:
PM(I6,M6)= A R, MR=MX0 * MF ( RND);
MODIFY(I2,M3);
MODIFY(I6,M7);
REV. 0
{Point to oldest data}
{Point to start of data}
–11–
ADSP-2104/ADSP-2109–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
Min
Max
Unit
4.50
0
5.50
+70
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
3, 5
VIH
VIH
VIL
VOH
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 7
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Lo-Level Output Voltage2, 3, 7
Hi-Level Input Current1
Lo-Level Input Current1
Three-State Leakage Current4
Three-State Leakage Current4
Input Pin Capacitance1, 8, 9
Output Pin Capacitance4, 8, 9, 10
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA8
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max6
@ VDD = max, VIN = 0 V6
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
2.2
Max
Unit
V
V
V
V
V
V
µA
µA
µA
µA
pF
pF
0.8
2.4
VDD – 0.3
0.4
10
10
10
10
8
8
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
3
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
4
Three-state pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.
5
Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.
6
0 V on BR, CLKIN Active (to force three-state condition).
7
Although specified for TTL outputs, all ADSP-2104/ADSP-2109 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
8
Guaranteed but not tested.
9
Applies to PGA, PLCC, PQFP package types.
10
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . –55ºC to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300°C
Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2104/ADSP-2109 processor features proprietary ESD protection circuitry to dissipate
high energy electrostatic discharges (Human Body Model), permanent damage may occur to devices
subjected to such discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality. Unused devices must be stored in conductive foam
or shunts, and the foam should be discharged to the destination socket before the devices are
removed. Per method 3015 of MIL-STD-883, the ADSP-2104/ADSP-2109 processor has been
classified as Class 1 device.
–12–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104/ADSP-2109)
SUPPLY CURRENT & POWER
Parameter
Test Conditions
IDD
Supply Current (Dynamic)1
IDD
Supply Current (Idle)1, 3
Min
@ VDD = max, tCK = 50 ns2
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 50 ns
@ VDD = max, tCK = 72.3 ns
Max
Unit
31
24
11
10
mA
mA
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-2104/ADSP-2109 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 7.
IDD DYNAMIC1
220
200
POWER – mW
180
170mW
160
VDD = 5.5V
140
128mW
129mW
120
VDD = 5.0V
100
95mW
100mW
VDD = 4.5V
80
74mW
60
10.00
13.83
20.00
25.00
FREQUENCY – MHz
IDD IDLE1, 2
70
60mW
55mW
IDD IDLE
50
40
38mW
42mW
VDD = 5.0V
31mW
28mW
VDD = 4.5V
55
41mW
IDLE 16
42mW
41mW
40mW
IDLE 128
45
40
10
35
13.83
20.00
25.00
FREQUENCY – MHz
55mW
50
20
0
10.00
60mW
60
VDD = 5.5V
POWER – mW
POWER – mW
IDD IDLE n MODES3
65
60
30
30.00
30
10.00
30.00
13.83
20.00
25.00
FREQUENCY – MHz
30.00
1
2
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-2104/ADSP-2109 OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3 MAXIMUM POWER DISSIPATION AT V
DD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
Figure 7. ADSP-2104/ADSP-2109 Power (Typical) vs. Frequency
REV. 0
–13–
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104/ADSP-2109)
CAPACITIVE LOADING
Figures 8 and 9 show capacitive loading characteristics.
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
8
RISE TIME (0.8V - 2.0V) – ns
7
C = load capacitance, f = output switching frequency.
Example:
In an ADSP-2104 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
VDD = 4.5V
6
5
4
3
2
1
0
0
25
50
75
100
CL – pF
125
150
175
Figure 8. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
The application operates at VDD = 5.0 V and tCK = 50 ns.
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation (from Figure 7).
5
Output
# of
Pins 3 C
Address, DMS
Data, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
VALID OUTPUT DELAY OR HOLD – ns
(C × VDD2 × f ) is calculated for each output:
3 VDD2 × f
× 52 V
× 52 V
× 52 V
× 52 V
× 20 MHz
× 10 MHz
× 10 MHz
× 20 MHz
=
=
=
=
40.0 mW
22.5 mW
2.5 mW
5.0 mW
70.0 mW
4
VDD = 4.5V
3
2
1
0
–1
–2
–3
0
Total power dissipation for this example = PINT + 70.0 mW.
25
50
75 100 125
CL – pF
150
175
ENVIRONMENTAL CONDITIONS
Figure 9. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Package
uJA
uJC
uCA
PLCC
27°C/W
16°C/W
11°C/W
–14–
REV. 0
ADSP-2104/ADSP-2109
The decay time, tDECAY, is dependent on the capacitative load,
CL , and the current load, iL , on the output pin. It can be
approximated by the following equation:
SPECIFICATIONS (ADSP-2104/ADSP-2109)
TEST CONDITIONS
Figure 10 shows voltage reference levels for ac measurements.
INPUT
from which
tDIS = tMEASURED – tDECAY
2.0V
1.5V
0.8V
OUTPUT
CL × 0.5 V
iL
t DECAY =
3.0V
1.5V
0.0V
Figure 10. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 11. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 11. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
OUTPUT
VOL (MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOH (MEASURED)
VOL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 11. Output Enable/Disable
IOL
TO
OUTPUT
PIN
+1.5V
50pF
IOH
Figure 12. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
REV. 0
–15–
ADSP-2104L/ADSP-2109L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
Supply Voltage
Ambient Operating Temperature
VDD
TAMB
Min
Max
Unit
3.00
0
3.60
+70
V
°C
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
CI
CO
Hi-Level Input Voltage1, 3
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage2, 3, 6
Lo-Level Output Voltage2, 3, 6
Hi-Level Input Current1
Lo-Level Input Current1
Three-State Leakage Current4
Three-State Leakage Current4
Input Pin Capacitance1, 7, 8
Output Pin Capacitance4, 7, 8, 9
Test Conditions
Min
@ VDD = max
@ VDD = min
@ VDD = min, IOH = –0.5 mA6
@ VDD = min, IOL = 2 mA6
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max5
@ VDD = max, VIN = 0 V5
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
2.0
Max
0.4
2.4
0.4
10
10
10
10
8
8
Unit
V
V
V
V
µA
µA
µA
µA
pF
pF
NOTES
1
Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.
2
Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.
3
Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.
4
Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.
5
0 V on BR, CLKIN Active (to force three-state condition).
6
All outputs are CMOS and will drive to V DD and GND with no dc loads.
7
Guaranteed but not tested.
8
Applies to PLCC package type.
9
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) PLCC . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
–16–
REV. 0
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L /ADSP-2109L)
SUPPLY CURRENT & POWER (ADSP-2104L /ADSP-2109L)
Parameter
IDD
IDD
Test Conditions
Supply Current (Dynamic)1
Supply Current (Idle)1, 3
Min
@ VDD = max, tCK = 72.3 ns2
@ VDD = max, tCK = 72.3 ns
Max
Unit
14
4
mA
mA
NOTES
1
Current reflects device operating with no output loads.
2
VIN = 0.4 V and 2.4 V.
3
Idle refers to ADSP-2104L/ADSP-2109L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
For typical supply current (internal power dissipation) figures, see Figure 13.
IDLE DYNAMIC 1,2
50
48mW
45
POWER – mW
40
VDD = 3.6V
35
VDD = 3.30V
37mW
29mW
30
25
24mW
20
19mW
15
VDD = 3.0V
15mW
10
5
0
5.00
7.00
10.00
13.83
FREQUENCY – MHz
IDD IDLE1
14
15.00
IDD IDLE n MODES3
14
13mW
13mW
12
12
10mW
10
POWER – mW
POWER – mW
VDD = 3.6V
10
9mW
8
6
VDD = 3.30V
8mW
6mW
5mW
VDD = 3.0V
9mW
8
IDLE 16
6
4
4
2
2
0
5.00
7.00
10.00
13.83
FREQUENCY – MHz
IDD IDLE
0
5.00
15.00
5mW
4mW
7mW
6mW
IDLE 128
7.00
10.00
13.83
FREQUENCY – MHz
15.00
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
IDLE REFERS TO ADSP-2104L/ADSP-2109L OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3 MAXIMUM POWER DISSIPATION AT V
DD = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
2
Figure 13. ADSP-2104L/ADSP-2109L Power (Typical) vs. Frequency
REV. 0
–17–
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L /ADSP-2109L)
POWER DISSIPATION EXAMPLE
CAPACITIVE LOADING
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
Figures 14 and 15 show capacitive loading characteristics.
RISE TIME (0.8V-2.0V) – ns
C = load capacitance, f = output switching frequency.
Example:
In an ADSP-2104L application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:
•
30
25
VDD = 3.0V
20
15
10
5
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
25
50
75
100
CL – pF
125
150
Figure 14. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
The application operates at VDD = 3.3 V and tCK = 100 ns.
VALID OUTPUT DELAY OR HOLD – ns
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation (from Figure 13).
(C × VDD2 × f ) is calculated for each output:
Output
# of
Pins × C
Address, DMS
Data, WR
RD
CLKOUT
8
9
1
1
× 10 pF
× 10 pF
× 10 pF
× 10 pF
3
VDD2
× 3.32 V
× 3.32 V
× 3.32 V
× 3.32 V
3f
× 10 MHz
× 5 MHz
× 5 MHz
× 10 MHz
=
=
=
=
8.71 mW
4.90 mW
0.55 mW
1.09 mW
+8
+6
+4
VDD = 3.0V
+2
NOMINAL
–2
25
50
75
100
CL – pF
125
150
15.25 mW
Total power dissipation for this example = PINT + 15.25 mW.
ENVIRONMENTAL CONDITIONS
Figure 15. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
Ambient Temperature Rating:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ JA = Thermal Resistance (Junction-to-Ambient)
θ JC = Thermal Resistance (Junction-to-Case)
Package
uJA
uJC
uCA
PLCC
27°C/W
16°C/W
11°C/W
–18–
REV. 0
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
TEST CONDITIONS
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
Figure 16 shows voltage reference levels for ac measurements.
VDD
2
INPUT
t DECAY =
from which
VDD
2
OUTPUT
CL × 0.5 V
iL
tDIS = tMEASURED – tDECAY
Figure 16. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
Output Disable Time
Output Enable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 17. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t E NA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 17. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
REFERENCE
SIGNAL
tMEASURED
tENA
tDIS
VOH (MEASURED)
OUTPUT
VOL (MEASURED)
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.
Figure 17. Output Enable/Disable
IOL
TO
OUTPUT
PIN
VDD
2
50pF
IOH
Figure 18. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)
REV. 0
–19–
VOH (MEASURED)
VOL (MEASURED)
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-2104/ADSP-2109 timing
parameters, for your convenience.
Memory
Device
Specification
ADSP-2104/ADSP-2109
Timing
Parameter
Timing
Parameter
Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
–20–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
CLOCK SIGNALS & RESET
Frequency
Dependency
20 MHz
Parameter
Timing Requirement:
tCK
CLKIN Period
tCKL
CLKIN Width Low
CLKIN Width High
tCKH
RESET Width Low
tRSP
Switching Characteristic:
CLKOUT Width Low
tCPL
CLKOUT Width High
tCPH
tCKOH
CLKIN High to CLKOUT High
Min
Max
50
20
20
250
150
Min
20
20
5tCK1
15
15
0
0.5tCK – 10
0.5tCK – 10
20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
NOTE
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 19. Clock Signals
REV. 0
–21–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
INTERRUPTS & FLAGS
Frequency
Dependency
20 MHz
Parameter
Min
Timing Requirement:
IRQx1 or FI Setup before
tIFS
CLKOUT Low2, 3
tIFH
IRQx1 or FI Hold after CLKOUT
High2, 3
Switching Characteristic:
tFOH
FO Hold after CLKOUT High
tFOD
FO Delay from CLKOUT High
Max
Min
Max
Unit
27.5
0.25tCK + 15
ns
12.5
0.25tCK
ns
0
ns
ns
0
15
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized
during the following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further
information on interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
tIFH
IRQx
FI
tIFS
Figure 20. Interrupts & Flags
–22–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
BUS REQUEST/GRANT
Frequency
Dependency
20 MHz
Parameter
Min
Timing Requirement:
BR Hold after CLKOUT High 1
tBH
BR Setup before CLKOUT Low 1
tBS
Switching Characteristic:
tSD
CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
tSDB
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS,
tSE
BMS, RD, WR Enable
DMS, PMS, BMS, RD, WR
tSEC
Enable to CLKOUT High
Max
Min
17.5
32.5
Max
0.25tCK + 5
0.25tCK + 20
32.5
Unit
ns
ns
0.25tCK + 20
ns
0
0
ns
0
0
ns
2.5
0.25tCK – 10
ns
NOTES
1
If BR meets the t BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
Figure 21. Bus Request/Grant
REV. 0
–23–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
MEMORY READ
20 MHz
Parameter
Min
Timing Requirement:
tRDD
RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH
Data Hold from RD High
Max
Unit
12
19.5
ns
ns
22.5
ns
ns
ns
0
Switching Characteristic:
tRP
tCRD
tASR
tRDA
tRWR
RD Pulse Width
CLKOUT High to RD Low
A0–A13, PMS, DMS, BMS Setup before
RD Low
A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
RD High to RD or WR Low
17
7.5
2.5
3.5
ns
20
ns
Frequency Dependency
(CLKIN ≤ 20 MHz)
Parameter
Min
Timing Requirement:
tRDD RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH Data Hold from RD High
Switching Characteristic:
tRP
RD Pulse Width
tCRD CLKOUT High to RD Low
tASR A0–A13, PMS, DMS, BMS Setup before
RD Low
tRDA A0–A13, PMS, DMS, BMS Hold after RD
Deasserted
tRWR RD High to RD or WR Low
Max
Unit
0.5tCK – 13 + w
0.75tCK – 18 + w
ns
ns
0.25tCK + 10
ns
ns
0
0.5tCK – 8 + w
0.25tCK – 5
0.25tCK – 10
ns
0.25tCK – 9
0.5tCK – 5
ns
ns
NOTE
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tAA
tRDD
tRDH
WR
Figure 22. Memory Read
–24–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
MEMORY WRITE
20 MHz
Parameter
Min
Switching Characteristic:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A0–A13, DMS, PMS Setup before
WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A0–A13, DMS, PMS, Setup before WR
Deasserted
tWRA
A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR
WR High to RD or WR Low
Max
12
2.5
17
0
2.5
ns
ns
ns
ns
ns
2.5
7.5
15.5
Parameter
Switching Characteristic:
tDW Data Setup before WR High
tDH Data Hold after WR High
tWP WR Pulse Width
tWDE WR Low to Data Enabled
tASW A0–A13, DMS, PMS Setup before WR Low
tDDR Data Disable before WR or RD Low
tCWR CLKOUT High to WR Low
tAW A0–A13, DMS, PMS, Setup before WR
Deasserted
tWRA A0–A13, DMS, PMS Hold after WR
Deasserted
tWWR WR High to RD or WR Low
22.5
ns
20
ns
Frequency Dependency
(CLKIN ≤ 20 MHz)
Min
Max
Unit
ns
ns
ns
0.25tCK + 10
ns
0.25tCK – 9
0.5tCK – 5
ns
ns
A0 – A13
DMS, PMS
tWRA
WR
tWP
tWWR
tAW
tDH
tCWR
D
tDW
RD
Figure 23. Memory Write
REV. 0
–25–
ns
ns
ns
0.75tCK – 22 + w
CLKOUT
tWDE
ns
ns
ns
3.5
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
0
0.25tCK – 10
0.25tCK – 10
0.25tCK – 5
tASW
Unit
tDDR
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104/ADSP-2109)
SERIAL PORTS
13.824 MHz*
Parameter
Min
Timing Requirement:
tSCK SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH DR/TFS/RFS Hold after SCLK Low
tSCP SCLKIN Width
Switching Characteristic:
tCC
CLKOUT High to SCLKOUT
tSCDE SCLK High to DT Enable
tSCDV SCLK High to DT Valid
tRH
TFS/RFSOUT Hold after SCLK High
tRD
TFS/RFSOUT Delay from SCLK High
tSCDH DT Hold after SCLK High
tTDE TFS (Alt) to DT Enable
tTDV TFS (Alt) to DT Valid
tSCDD SCLK High to DT Disable
tRDV RFS (Multichannel, Frame Delay Zero)
to DT Valid
Max
Frequency
Dependency
Min
Max
72.3
8
10
28
Unit
ns
ns
ns
ns
18.1
0
33.1
0.25tCK
0.25tCK + 15
20
20
18
25
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*Maximum serial port operating frequency is 13.824 MHz.
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCS
tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 24. Serial Ports
–26–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
MEMORY REQUIREMENTS
The table below shows common memory device specifications
and the corresponding ADSP-2104L/ADSP-2109L timing
parameters, for your convenience.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Memory Specification
ADSP-2104L/ADSP-2109L
Timing Parameter
Timing Parameter Definition
Address Setup to Write Start
Address Setup to Write End
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tASW
tAW
tWRA
tDW
tDH
tRDD
tAA
A0–A13, DMS, PMS Setup before WR Low
A0–A13, DMS, PMS Setup before WR Deasserted
A0–A13, DMS, PMS Hold after WR Deasserted
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, DMS, PMS, BMS to Data Valid
REV. 0
–27–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
CLOCK SIGNALS & RESET
Parameter
Timing Requirement:
tCK
CLKIN Period
tCKL
CLKIN Width Low
tCKH
CLKIN Width High
tRSP
RESET Width Low
Switching Characteristic:
tCPL
CLKOUT Width Low
tCPH
CLKOUT Width High
tCKOH CLKIN High to CLKOUT High
13.824 MHz
Min
Max
Frequency
Dependency
Min
Max
Unit
72.3
20
20
361.5
20
20
5tCK1
ns
ns
ns
ns
150
26.2
26.2
0
0.5tCK – 10
0.5tCK – 10
20
ns
ns
ns
NOTE
1
Applies after powerup sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator startup time).
tCK
tCKH
CLKIN
tCKL
tCKOH
tCPH
CLKOUT
tCPL
Figure 25. Clock Signals
–28–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
INTERRUPTS & FLAGS
Parameter
Timing Requirement:
tIFS
IRQx1 or FI Setup before CLKOUT Low2, 3
tIFH
IRQx1 or FI Hold after CLKOUT High2, 3
Switching Characteristic:
tFOH
FO Hold after CLKOUT High
tFOD
FO Delay from CLKOUT High
13.824 MHz
Min
Max
Frequency
Dependency
Min
Max
Unit
33.1
18.1
0.25tCK + 15
0.25tCK
ns
ns
0
15
ns
ns
NOTES
1
IRQx=IRQ0, IRQ1, and IRQ2.
2
If IRQx and FI inputs meet t IFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized during the
following cycle. (Refer to the “Interrupt Controller” section in Chapter 3, Program Control, of the ADSP-2100 Family User’s Manual for further information on
interrupt servicing.)
3
Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.
CLKOUT
tFOD
tFOH
FLAG
OUTPUT(S)
t IFH
IRQx
FI
t IFS
Figure 26. Interrupts & Flags
REV. 0
–29–
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
BUS REQUEST/GRANT
Parameter
Timing Requirement:
tBH
BR Hold after CLKOUT High1
tBS
BR Setup before CLKOUT Low1
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS, RD, WR Disable
tSDB
DMS, PMS, BMS, RD, WR Disable to BG Low
tSE
BG High to DMS, PMS, BMS, RD, WR Enable
tSEC
DMS, PMS, BMS, RD, WR Enable to CLKOUT High
13.824 MHz
Min
Max
Frequency
Dependency
Min
Max
Unit
23.1
38.1
0.25tCK + 5
0.25tCK + 20
ns
ns
38.1
0.25tCK + 20
0
0
8.1
0
0
0.25tCK – 10
ns
ns
ns
ns
NOTES
1
If BR meets the t BS and tBH setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR
requires a pulse width greater than 10 ns.
Note: BG is asserted in the cycle after BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
tSD
tSEC
tSDB
tSE
Figure 27. Bus Request/Grant
–30–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
MEMORY READ
Frequency
Dependency
Min
Max
13.824 MHz
Min
Max
Parameter
Timing Requirement:
tRDD
RD Low to Data Valid
tAA
A0–A13, PMS, DMS, BMS to Data Valid
tRDH
Data Hold from RD High
Switching Characteristic:
tRP
RD Pulse Width
tCRD
CLKOUT High to RD Low
tASR
A0–A13, PMS, DMS, BMS Setup before RD Low
tRDA
A0–A13, PMS, DMS, BMS Hold after RD Deasserted
tRWR
RD High to RD or WR Low
23.2
36.2
0.5tCK – 13 + w
0.75tCK – 18 + w
0
28.2
13.1
8.1
9.1
31.2
28.1
0
ns
ns
ns
0.5tCK – 8 + w
0.25tCK – 5
0.25tCK + 10
0.25tCK – 10
0.25tCK – 9
0.5tCK – 5
ns
ns
ns
ns
ns
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
BMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tAA
tRDD
WR
Figure 28. Memory Read
REV. 0
–31–
Unit
tRDH
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
MEMORY WRITE
Parameter
13.824 MHz
Min
Max
Switching Characteristic:
tDW
Data Setup before WR High
tDH
Data Hold after WR High
tWP
WR Pulse Width
tWDE
WR Low to Data Enabled
tASW
A0–A13, DMS, PMS Setup before WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
tAW
A0–A13, DMS, PMS, Setup before WR Deasserted
tWRA
A0–A13, DMS, PMS Hold After WR Deasserted
tWWR
WR High to RD or WR Low
23.2
8.1
28.2
0
8.1
8.1
13.1
32.2
9.1
31.2
Frequency
Dependency
Min
28.1
Max
Unit
0.5tCK – 13 + w
0.25tCK – 10
0.5tCK – 8 + w
ns
ns
ns
0.25tCK – 10
0.25tCK – 10
0.25tCK – 5
0.25tCK + 10
0.75tCK – 22 + w
0.25tCK – 9
0.5tCK – 5
ns
ns
ns
ns
ns
ns
w = wait states × tCK.
CLKOUT
A0 – A13
DMS, PMS
tWRA
WR
tASW
tWP
tWWR
tAW
tDH
tCWR
tDDR
D
tWDE
tDW
RD
Figure 29. Memory Write
–32–
REV. 0
ADSP-2104/ADSP-2109
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L)
SERIAL PORTS
13.824 MHz
Min
Max
Parameter
Timing Requirement:
tSCK
SCLK Period
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
tSCP
SCLKin Width
Switching Characteristic:
tCC
CLKOUT High to SCLKout
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
tRH
TFS/RFSout Hold after SCLK High
tRD
TFS/RFSout Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS (alt) to DT Enable
tTDV
TFS (alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero)
to DT Valid
CLKOUT
Frequency
Dependency
Min
Max
72.3
8
10
28
18.1
0
ns
ns
ns
ns
33.1
0.25tCK
20
20
0
0
18
25
20
tCC
tSCK
SCLK
tSCP
tSCS
tSCH
tSCP
DR
RFSIN
TFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDE
tSCDH
DT
tTDE
tTDV
TFS
( ALTERNATE
FRAME MODE )
tRDV
RFS
( MULTICHANNEL MODE,
FRAME DELAY 0 {MFD = 0} )
Figure 30. Serial Ports
REV. 0
0.25tCK + 15
0
tCC
–33–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2104/ADSP-2109
PIN CONFIGURATIONS
GND 10
D4
D3
D5
D7
68 67 66 65 64 63 62 61
D6
1
D9
2
D8
3
D10
4
GND
5
D11
6
D13
7
D12
D14
8
D16
9
D15
D18
D17
68-Lead PLCC
PIN 1
IDENTIFIER
60
D2
59
D1
D20 12
58
D0
D21 13
57
VDD
D22 14
56
SCLK1
55
FI (DR1)
54
IRQ0 (RFS1)
53
IRQ1 (TFS1)
52
FO (DT1)
51
SCLK0
RESET 20
50
DR0
A0 21
49
GND
A1 22
48
RFS0
A2 23
47
TFS0
A3 24
46
DT0
A4 25
45
RD
VDD 26
44
WR
D19 11
ADSP-2104
ADSP-2104L
ADSP-2109
ADSP-2109L
D23 15
VDD 16
MMAP 17
BR 18
TOP VIEW
(PINS DOWN)
IRQ2 19
CLKOUT
XTAL
CLKIN
BG
BMS
DMS
A13
PMS
A12
A11
A10
A9
A7
A8
GND
A6
A5
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
PLCC
Pin
Number Name
PLCC
Pin
Number Name
PLCC
Pin
Number Name
PLCC
Pin
Number Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
D11
GND
D12
D13
D14
D15
D16
D17
D18
GND
D19
D20
D21
D22
D23
VDD
MMAP
BR
IRQ2
RESET
A0
A1
A2
A3
A4
VDD
A5
A6
GND
A7
A8
A9
A10
A11
–34–
A12
A13
PMS
DMS
BMS
BG
XTAL
CLKIN
CLKOUT
WR
RD
DT0
TFS0
RFS0
GND
DR0
SCLK0
FO
(DT1)
IRQ1 (TFS1)
IRQ0 (RFS1)
FI
(DR1)
SCLK1
VDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
REV. 0
ADSP-2104/ADSP-2109
OUTLINE DIMENSIONS
ADSP-2104/ADSP-2109
68-Lead Plastic Leaded Chip Carrier (PLCC)
9
61
e
PIN 1 IDENTIFIER
D2
b
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
D
b1
A1
D1
D
A
SYMBOL
INCHES
MIN
TYP
MAX
A
0.169
A1
0.175
4.29
0.104
14.37
4.45
12.64
b
0.017
0.018
0.019
0.43
10.46
0.48
b1
0.027
0.028
0.029
0.69
10.71
0.74
D
0.985
0.990
0.995
25.02
25.15
25.27
D1
0.950
0.952
0.954
24.13
24.18
24.23
D2
0.895
0.910
0.925
22.73
23.11
23.50
D
e
REV. 0
0.172
MILLIMETERS
MIN
TYP
MAX
0.050
11.27
0.004
–35–
10.10
ADSP-2104/ADSP-2109
Part Number*
Ambient
Temperature
Range
Instruction
Rate
Package
Description
Package
Option
ADSP-2104KP-80
ADSP-2109KP-80
ADSP-2104LKP-55
ADSP-2109LKP-55
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20.0 MHz
20.0 MHz
13.824 MHz
13.824 MHz
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
P-68A
P-68A
P-68A
P-68A
PRINTED IN U.S.A.
*K = Commercial Temperature Range (0°C to +70°C).
*P = PLCC (Plastic Leaded Chip Carrier).
C2145–16–7/96
ORDERING GUIDE
–36–
REV. 0