AD ADSP-21161N Sharc processor Datasheet

SHARC Processor
ADSP-21161N
SUMMARY
Integrated peripherals—integrated I/O processor, 1M bit onchip dual-ported SRAM, SDRAM controller, glueless multiprocessing features, and I/O ports (serial, link, external
bus, SPI, and JTAG)
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit
floating-point formats
100 MHz/110 MHz core instruction rate
Single-cycle instruction execution, including SIMD operations in both computational units
Up to 660 MFLOPs peak and 440 MFLOPs sustained
performance
225-ball 17 mm 17 mm CSP_BGA package
High performance 32-Bit DSP—applications in audio, medical, military, wireless communications, graphics, imaging,
motor-control, and telephony
Super Harvard Architecture—four independent buses for
dual data fetch, instruction fetch, and nonintrusive zerooverhead I/O
Code compatible with all other sharc family DSPs
Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units,
each with a multiplier, ALU, shifter, and register file
Serial ports offer I2S support via 8 programmable and simultaneous receive or transmit pins, which support up to 16
transmit or 16 receive channels of audio
DUAL-PORTED SRAM
INSTRUCTION
CACHE
32 u 48-BIT
DAG2
8 u 4 u 32
DATA
DATA
ADDR
DAG1
8 u 4 u 32
I/O PORT
PROCESSOR PORT
ADDR
BLOCK 0
TIMER
TWO INDEPENDENT
DUAL-PORTED BLOCKS
DATA
ADDR
DATA
JTAG TEST
AND EMULATION
BLOCK 1
CORE PROCESSOR
GPIO
FLAGS
SDRAM
CONTROLLER
IOD
64
PM ADDRESS BUS
12
ADDR
PROGRAM
SEQUENCER
32
6
IOA
18
8
EXTERNAL PORT
ADDR BUS
MUX
32
24
DM ADDRESS BUS
64
BUS
CONNECT
(PX)
PM DATA BUS
MULTIPROCESSOR
INTERFACE
64
DM DATA BUS
DATA BUS
MUX
MULT
DATA
REGISTER
FILE
(PEX)
16 u 40-BIT
BARREL
SHIFTER
ALU
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 u 40-BIT
32
HOST PORT
MULT
IOP
REGISTERS
(MEMORY MAPPED)
ALU
S
CONTROL,
STATUS, &
DATA BUFFERS
DMA
CONTROLLER
5
16
SERIAL PORTS (4)
20
LINK PORTS (2)
SPI PORTS (1)
4
I/O PROCESSOR
Figure 1. ADSP-21161N Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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©2013 Analog Devices, Inc. All rights reserved.
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ADSP-21161N
TABLE OF CONTENTS
Summary ............................................................... 1
Absolute Maximum Ratings ................................... 19
General Description ................................................. 3
ESD Caution ...................................................... 19
ADSP-21161N Family Core Architecture .................... 3
Timing Specifications ........................................... 19
ADSP-21161N Memory and I/O Interface Features ....... 5
Power Dissipation ............................................... 20
Development Tools ............................................... 9
Output Drive Currents ......................................... 54
Additional Information ........................................ 10
Test Conditions .................................................. 54
Related Signal Chains .......................................... 10
Environmental Conditions .................................... 55
Pin Function Descriptions ....................................... 11
225-Ball CSP_BGA Ball Configurations ....................... 56
Boot Modes ....................................................... 16
Outline Dimensions ................................................ 58
Specifications ........................................................ 17
Surface-Mount Design .......................................... 58
Operating Conditions .......................................... 17
Ordering Guide ..................................................... 58
Electrical Characteristics ....................................... 18
Package Information ........................................... 19
REVISION HISTORY
1/13—Rev. B to Rev. C
Updated Development Tools ...................................... 9
Added section, Related Signal Chains .......................... 10
Added footnote 3 to Table 16 in
Memory Read — Bus Master .................................... 27
Rev. C |
Page 2 of 60 |
January 2013
ADSP-21161N
GENERAL DESCRIPTION
The ADSP-21161N SHARC® DSP is a low cost derivative of the
ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code
compatible with the ADSP-21160 and with first generation
ADSP-2106x SHARC processors in SISD (Single-Instruction,
Single-Data) mode. Like other SHARC DSPs, the ADSP21161N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161N includes a
100 MHz or 110 MHz core, a dual-ported on-chip SRAM, an
integrated I/O processor with multiprocessing support, and
multiple internal buses to eliminate I/O bottlenecks.
As was first offered in the ADSP-21160, the ADSP-21161N
offers a single-instruction multiple-data (SIMD) architecture.
Using two computational units (ADSP-2106x SHARC processors have one), the ADSP-21161N can double cycle
performance versus the ADSP-2106x on a range of DSP
algorithms.
Fabricated in a state of the art, high speed, low power CMOS
process, the ADSP-21161N has a 10 ns or 9 ns instruction cycle
time. With its SIMD computational hardware running at
110 MHz, the ADSP-21161N can perform 660 million floatingpoint operations per second. Table 1 shows performance benchmarks for the ADSP-21161N.
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code, for
both single and dual-channel processing, see the Analog Devices
Inc. website.
• Two processing elements, each made up of an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core processor cycle
• Interval timer
• On-Chip SRAM (1M bit)
• SDRAM controller for glueless interface to SDRAMs
• External port that supports:
• Interfacing to off-chip memory peripherals
• Glueless multiprocessing support for six
ADSP-21161N SHARCs
• Host port read/write of IOP registers
• DMA controller
• Four serial ports
• Two link ports
• SPI compatible interface
• JTAG test access port
• 12 general-purpose I/O pins
Figure 2 shows a typical single-processor system. A multiprocessing system appears in Figure 5 on Page 8.
Table 1. Benchmarks
Benchmark Algorithm
1024 Point Complex FFT
(Radix 4, with Reversal)
FIR Filter (Per Tap)
IIR Filter (Per Biquad)
Matrix Multiply (Pipelined)
[3 3]  [3 1]
[4 4]  [4 1]
Divide (y/x)
Inverse Square Root
DMA Transfers
The block diagram of the ADSP-21161N on Page 1 illustrates
the following architectural features:
100 MHz
Instruction
Rate
92 μs
110 MHz
Instruction
Rate
83.6 μs
5 ns
20 ns
4.5 ns
18.18 ns
45 ns
80 ns
60 ns
40 ns
800M bytes/s
40.9 ns
72.72 ns
54.54 ns
36.36 ns
880M bytes/s
ADSP-21161N FAMILY CORE ARCHITECTURE
The ADSP-21161N includes the following architectural features
of the ADSP-2116x family core. The ADSP-21161N is code
compatible at the assembly level with the ADSP-21160,
ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L.
SIMD Computational Engine
The ADSP-21161N continues SHARC’s industry-leading standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include a 1M bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels,
four serial ports, two link ports, SDRAM controller, SPI interface, external parallel bus, and glueless multiprocessing.
Rev. C |
Page 3 of 60 |
The ADSP-21161N contains two computational processing elements that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing elements, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
January 2013
ADSP-21161N
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the register file.
Data Register File
A general-purpose data register file is contained in each processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC enhanced Harvard
architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are
referred to as R0–R15 and in PEY as S0–S15.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floating-point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
3
12
CLK_CFG1-0
CLKDBL
EBOOT
LBOOT
IRQ2-0
FLAG11-0
DATA
CLKIN
XTAL
ADDRESS
2
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 2). With the ADSP-21161N’s separate program and
data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data
bus) and an instruction (from the cache), all in a single cycle.
CONTROL
ADSP-21161N
CLOCK
Single-Cycle Fetch of Instruction and Four Operands
BMS
CS
ADDR
BRST
DATA
ADDR23-0
ADDR
TIMEXP
RPBA
ID2-0
LINK
DEVICES
(2 MAX)
(OPTIONAL)
MEMORY
DATA
AND
OE
PERIPHERALS
WE
(OPTIONAL)
ACK
CS
DATA47-16
RD
WR
LXCLK
ACK
LXACK
MS3-0
LXDAT7-0
SERIAL
DEVICE
(OPTIONAL)
SCLK0
FS0
D0A
D0B
SERIAL
DEVICE
(OPTIONAL)
SCLK1
FS1
D1A
D1B
SERIAL
DEVICE
(OPTIONAL)
SCLK2
FS2
D2A
D2B
BOOT
EPROM
(OPTIONAL)
RAS
RAS
CAS
CAS
SDRAM
DQM (OPTIONAL)
DQM
SDWE
SDCLK1-0
WE
CLK
SDCKE
CKE
SDA10
A10
CS
ADDR
DATA
CLKOUT
DMAR2-1
DMA DEVICE
(OPTIONAL)
DMAG2-1
SERIAL
DEVICE
(OPTIONAL)
SPI
COMPATIBLE
DEVICE
(HOST OR SLAVE)
(OPTIONAL)
SCLK3
FS3
D3A
D3B
SPICLK
SPIDS
MOSI
MISO
DATA
CS
HBR
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
HBG
REDY
BR6-1
ADDR
PA
DATA
SBTS
RESET RSTOUT JTAG
7
Figure 2. System Diagram
Rev. C |
Page 4 of 60 |
January 2013
ADSP-21161N
Instruction Cache
The ADSP-21161N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache enables full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Hardware Circular Buffers
The ADSP-21161N’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21161N contain sufficient registers to allow the creation of up to 32 circular
buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wrap-around, reduce
overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21161N can conditionally execute a multiply, an add,
and a subtract in both processing elements, while branching, all
in a single instruction.
ADSP-21161N MEMORY AND I/O INTERFACE
FEATURES
Off-Chip Memory and Peripherals Interface
The ADSP-21161N’s external port provides the processor’s
interface to off-chip memory and peripherals. The 62.7-M word
off-chip address space (254.7-M word if all SDRAM) is included
in the ADSP-21161N’s unified address space. The separate onchip buses—for PM addresses, PM data, DM addresses, DM
data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 24-bit
address bus and a single 32-bit data bus. Every access to external
memory is based on an address that fetches a 32-bit word.
When fetching an instruction from external memory, two 32-bit
data locations are being accessed for packed instructions.
Unused link port lines can also be used as additional data lines
DATA15–DATA0, allowing single-cycle execution of instructions from external memory, at up to 110 MHz. Figure 4 shows
the alignment of various accesses to external memory.
The external port supports asynchronous, synchronous, and
synchronous burst accesses. Synchronous burst SRAM can be
interfaced gluelessly. The ADSP-21161N also can interface gluelessly to SDRAM. Addressing of external memory devices is
facilitated by on-chip decoding of high-order address lines to
generate memory bank select signals. The ADSP-21161N provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to memory and
peripherals with variable access, hold, and disable time
requirements.
SDRAM Interface
The ADSP-21161N adds the following architectural features to
the ADSP-2116x family core.
Dual-Ported On-Chip Memory
The ADSP-21161N contains one megabit of on-chip SRAM,
organized as two blocks of 0.5M bits (Figure 3). Each block can
be configured for different combinations of code and data storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O processor.
The dual-ported memory in combination with three separate
on-chip buses allow two data transfers from the core and one
from the I/O processor, in a single cycle. On the ADSP-21161N,
the memory can be configured as a maximum of 32K words of
32-bit data, 64K words of 16-bit data, 21K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to one megabit. All of the memory can be accessed as
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the amount
of data that may be stored on-chip. Conversion between the
32-bit floating-point and 16-bit floating-point formats is done
in a single instruction. While each memory block can store
combinations of code and data, accesses are most efficient when
one block stores data using the DM bus for transfers, and the
other block stores instructions and data using the PM bus for
transfers. Using the DM bus and PM bus, with one dedicated to
Rev. C |
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
Page 5 of 60 |
The SDRAM interface enables the ADSP-21161N to transfer
data to and from synchronous DRAM (SDRAM) at the core
clock frequency or at one-half the core clock frequency. The
synchronous approach, coupled with the core clock frequency,
supports data transfer at a high throughput—up to 440M
bytes/s for 32-bit transfers and up to 660M bytes/s for 48-bit
transfers.
The SDRAM interface provides a glueless interface with standard SDRAMs—16Mb, 64Mb, 128Mb, and 256Mb— and
includes options to support additional buffers between the
ADSP-21161N and SDRAM. The SDRAM interface is
extremely flexible and provides capability for connecting
SDRAMs to any one of the ADSP-21161N’s four external memory banks, with up to all four banks mapped to SDRAM.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21161N supports pipelining of the address and control signals to enable such buffering between itself and multiple
SDRAM devices.
Target Board JTAG Emulator Connector
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21161N
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
January 2013
ADSP-21161N
IOP REGISTERS
INTERNAL
MEMORY
SPACE
ADDRESS
ADDRESS
0x0000 0000 - 0x0001 FFFF
0x0020 0000
LONG WORD ADDRESSING
0x0002 0000 - 0x0002 1FFF (BLK 0)
0x0002 8000 - 0x0002 9FFF (BLK 1)
NORMAL WORD ADDRESSING
0x0004 0000 - 0x0004 3FFF (BLK 0)
0x0005 0000 - 0x0005 3FFF (BLK 1)
SHORT WORD ADDRESSING
0x0008 0000 - 0X0008 7FFF (BLK 0)
0x000A 0000 - 0x000A 7FFF (BLK 1)
MS0
BANK 0
0x00FF FFFF (NON-SDRAM)
0x03FF FFFF (SDRAM)
0x0400 0000
IOP REGISTERS OF ADSP-21161N
WITH ID = 001
0x0010 0000 - 0x0011 FFFF
IOP REGISTERS OF ADSP-21161N
WITH ID = 010
0x0012 0000 - 0x0013 FFFF
IOP REGISTERS OF ADSP-21161N
WITH ID = 011
0x0014 0000 - 0x0015 FFFF
IOP REGISTERS OF ADSP-21161N
WITH ID = 100
0x0016 0000 - 0x0017 FFFF
IOP REGISTERS OF ADSP-21161N
WITH ID = 101
0x0018 0000 - 0x0019 FFFF
MS1
BANK 1
MULTIPROCESSOR
MEMORY
SPACE
0x04FF FFFF (NON-SDRAM)
0x07FF FFFF (SDRAM)
0x0800 0000
MS2
BANK 2
IOP REGISTERS OF ADSP-21161N
WITH ID = 110
0x001A 0000 - 0x001B FFFF
0x08FF FFFF (NON-SDRAM)
0x0BFF FFFF (SDRAM)
0x001C 0000
RESERVED
0x0C00 0000
0x001F FFFF
EXTERNAL MEMORY SPACE
MS3
BANK 3
0x0CFF FFFF (NON-SDRAM)
0x0FFF FFFF (SDRAM)
NOTE: BANK SIZES ARE FIXED
Figure 3. Memory Map
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on SHARC Analog Devices DSP
Tools product line of JTAG emulator operation, see the appropriate Emulator Hardware User’s Guide. For detailed information on the interfacing of Analog Devices JTAG emulators
with Analog Devices DSP products with JTAG emulation ports,
please refer to Engineer to Engineer Note EE-68: Analog Devices
JTAG Emulation Technical Reference. Both of these documents
can be found on the Analog Devices website.
DMA Controller
The ADSP-21161N’s on-chip DMA controller enables zerooverhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
Rev. C |
Page 6 of 60 |
core is simultaneously executing its program instructions. DMA
transfers can occur between the ADSP-21161N’s internal memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP21161N’s internal memory and its serial ports, link ports, or the
SPI-compatible (Serial Peripheral Interface) port. External bus
packing and unpacking of 32-, 48-, or 64-bit words in internal
memory is performed during DMA transfers from either 8-,
16-, or 32-bit wide external memory. Fourteen channels of
DMA are available on the ADSP-21161N—two are shared
between the SPI interface and the link ports, eight via the serial
ports, and four via the processor’s external port (for host processor, other ADSP-21161Ns, memory, or I/O transfers).
Programs can be downloaded to the ADSP-21161N using DMA
transfers. Asynchronous off-chip peripherals can control two
DMA channels using DMA Request/Grant lines (DMAR2–1,
DMAG2–1). Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
January 2013
ADSP-21161N
DATA47–16
47
40 39
32 31
its own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port transfers.
Transfers are programmable as either transmit or receive.
DATA15–0
24 23
PROM
BOOT
16 15
8 7
0
L1DATA7–0
L0DATA7–0
DAT A15-8
DA TA7–0
Serial Ports
The ADSP-21161N features four synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. Each serial port is made up of
two data lines, a clock and frame sync. The data lines can be
programmed to either transmit or receive.
8-BIT PACKED DMA D ATA
8-BIT PACKED INST RUCT ION
EXECUTION
16-BIT PACKED DMA DATA
16-BIT PACKED INSTRUCTION EXECUTION
F LOAT OR FIXED, D31–D0,
32-BIT PA CKED
32-BIT PA CKED INSTRUCT ION
48-BIT INSTRUCT ION FETCH
(NO PACKING)
NOTE:
EXTRA DA TA LINES DATA15–0 AR E ONLY ACCESSIBLE IF LINK PORT S
ARE DISABLED. ENAB LE THESE ADDITIONAL DATA L INKS BY SELECTING IPACK1–0 = 01 IN SYSCON.
Figure 4. External Data Alignment Options
Multiprocessing
The ADSP-21161N offers powerful features tailored to
multiprocessing DSP systems. The external port and link ports
provide integrated glueless multiprocessing support.
The external port supports a unified address space (see Figure 3)
that enables direct interprocessor accesses of each ADSP21161N’s internal memory-mapped (I/O processor) registers.
All other internal memory can be indirectly accessed via DMA
transfers initiated via the programming of the IOP DMA
parameter and control registers. Distributed bus arbitration
logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21161Ns and a host processor
(Figure 5). Master processor change over incurs only one cycle
of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock enables indivisible read-modify-write
sequences for semaphores. A vector interrupt is provided for
interprocessor commands. Using an instruction rate of
110 MHz, maximum throughput for interprocessor data transfer is 440M bytes/s over the external port.
Two link ports provide a second method of multiprocessing
communications. Each link port can support communications
to another ADSP-21161N. The ADSP-21161N, running at
110 MHz, has a maximum throughput for interprocessor communications over the links of 220M bytes/s. The link ports and
cluster multiprocessing can be used concurrently or
independently.
The serial ports operate at up to half the clock rate of the core,
providing each with a maximum data rate of 55M bit/s. The
serial data pins are programmable as either a transmitter or
receiver, providing greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via a dedicated DMA. Each of the serial ports
features a Time Division Multiplex (TDM) multichannel mode,
where two serial ports are TDM transmitters and two serial
ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx,
SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports
also support the I2S protocol (an industry standard interface
commonly used by audio codecs, ADCs and DACs), with two
data pins, allowing four I2S channels (using two I2S stereo
devices) per serial port, with a maximum of up to 16 I2S channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For I2S mode, data-word lengths are selectable between
8 bits and 32 bits. Serial ports offer selectable synchronization
and transmit modes as well as optional μ-law or A-law companding. Serial port clocks and frame syncs can be internally or
externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard synchronous serial link, enabling the ADSP-21161N SPIcompatible port to communicate with other SPI-compatible
devices. SPI is a 4-wire interface consisting of two data pins, one
device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes.
The SPI port can operate in a multimaster environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The ADSP-21161N SPI-compatible peripheral implementation also features programmable
baud rate and clock phase/polarities. The ADSP-21161N SPIcompatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
Host Processor Interface
Link Ports
The ADSP-21161N features two 8-bit link ports that provide
additional I/O capabilities. With the capability of running at
110 MHz, each link port can support 110M bytes/s. Link port
I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can
operate independently and simultaneously, with a maximum
data throughput of 220M bytes/s. Link port data is packed into
48- or 32-bit words and can be directly read by the core processor or DMA-transferred to on-chip memory. Each link port has
Rev. C |
Page 7 of 60 |
The ADSP-21161N host interface enables easy connection to
standard 8-bit, 16-bit, or 32-bit microprocessor buses with little
additional hardware required. The host interface is accessed
through the ADSP-21161N’s external port. Four channels of
DMA are available for the host interface; code and data transfers
are accomplished with low software overhead. The host processor requests the ADSP-21161N’s external bus with the host bus
request (HBR), host bus grant (HBG), and chip select (CS) signals. The host can directly read and write the internal IOP
registers of the ADSP-21161N, and can access the DMA channel
January 2013
ADSP-21161N
DATA
ADDRESS
ADSP-21161N #3
CONTROL
ADSP-21161N #4
CLOCK RESET
ADDR23-0
DATA47-16
CLKIN
RESET
3
ID2-0
CONTROL
ADSP-21161N #2
CLKIN
ADDR23-0
DATA47-16
RESET
2
ID2-0
CONTROL
ADDR
DATA
ADSP-21161N #1
CS
BMS
CLKIN
ADDR23-0
ADDR
DATA47-16
DATA
RESET
1
ID2-0
RD
OE
WR
WE
ACK
ACK
BOOT
EPROM
(OPTIONAL)
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
CS
MS3-0
SBTS
CS
CONTROL
HBR
HBG
REDY
ADDR
DATA
DATA
ADDRESS
CONTROL
BR6-2
BR1
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
RAS
RAS
CAS
CAS
DQM
DQM
SDWE
WE
SDCLK1-0
CLK
SDCKE
CKE
SDRAM
(OPTIONAL)
SDA10
A10
CS
ADDR
DATA
Figure 5. Shared Memory Multiprocessing System
setup and message registers. DMA setup via a host would allow
it to access any internal memory address via DMA transfers.
Vector interrupt support provides efficient execution of host
commands.
Rev. C |
Page 8 of 60 |
The host processor interface can be used in either multiprocessor or single processor SHARC systems. For multiprocessor
systems, host access to the SHARC requires address pins
ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.
It is not enough to tie these pins to ground through a resistor
January 2013
ADSP-21161N
(for example 10k ohm). These pins must be driven low with a
strong enough drive strength (10–50 ohms) to overcome the
SHARC keeper latches present on these pins. If the drive
strength provided is not strong enough, data access failures can
occur.
For single processor SHARC systems using this host access feature, address pins ADDR17, ADDR18, ADDR19, and ADDR20
may be tied low (for example through a 10k ohm resistor),
driven low by a buffer/driver, or left floating. Any of these
options is sufficient.
General-Purpose I/O Ports
The ADSP-21161N also contains 12 programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21161N can be booted at
system power-up from either an 8-bit EPROM, a host processor,
the SPI interface, or through one of the link ports. Selection of
the boot source is controlled by the Boot Memory Select (BMS),
EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins.
8-, 16-, or 32-bit host processors can also be used for booting.
Phase-Locked Loop and Crystal Double Enable
The ADSP-21161N uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. The CLK_CFG1–0 pins
are used to select ratios of 2:1, 3:1, and 4:1. In addition to the
PLL ratios, the CLKDBL pin can be used for more clock ratio
options. The (1/2 CLKIN) rate set by the CLKDBL
pin determines the rate of the PLL input clock and the rate at
which the external port operates. With the combination of
CLK_CFG1–0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1
between the core and CLKIN are supported. See also Figure 8
on Page 20.
Power Supplies
The ADSP-21161N has separate power supply connections for
the analog (AVDD/AGND), internal (VDDINT), and external
(VDDEXT) power supplies. The internal and analog supplies must
meet the 1.8 V requirement. The external supply must meet the
3.3 V requirement. All external supply pins must be connected
to the same supply.
Note that the analog supply (AVDD) powers the ADSP-21161N’s
clock generator PLL. To produce a stable clock, provide an
external circuit to filter the power input to the AVDD pin. Place
the filter as close as possible to the pin. The AVDD filter circuit
shown in Figure 6 must be added for each ADSP-21161N in the
multiprocessor system. To prevent noise coupling, use a wide
trace for the analog ground (AGND) signal and install a decoupling capacitor as close as possible to the pin.
Rev. C |
Page 9 of 60 |
10 ⍀
AVDD
VDDINT
0.01␮F
0.1␮F
AGND
Figure 6. Analog Power (AVDD) Filter Circuit
DEVELOPMENT TOOLS
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embedded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Integrated Development Environments (IDEs)
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
EclipseTM framework. Supporting most Analog Devices processor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports processor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZKIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of CrossJanuary 2013
ADSP-21161N
Core Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZKITs or any custom system utilizing supported Analog Devices
processors.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly integrate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware packages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
Board Support Packages for Evaluation Hardware
Software support for the EZ-KIT Lite evaluation boards and EZExtender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZExtender product. The link is found in the Product Download
area of the product web page.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
• www.analog.com/ucos3
• www.analog.com/ucfs
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the
ADSP-21161N architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture and
instruction set, refer to the ADSP-21161 SHARC DSP Hardware
Reference and the ADSP-21160 SHARC DSP Instruction Set
Reference.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in
Wikipedia or the Glossary of EE Terms on the Analog Devices
website.
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
The Application Signal Chains page in the Circuits from the
LabTM site (http://www.analog.com/signal chains) provides:
• www.analog.com/ucusbd
• www.analog.com/lwip
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
Algorithmic Modules
To speed development, Analog Devices offers add-ins that perform popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules” or “SHARC software
modules”.
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices supplies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emulator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set breakpoints, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emulators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
Rev. C |
Page 10 of 60 |
January 2013
ADSP-21161N
PIN FUNCTION DESCRIPTIONS
ADSP-21161N pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
VDDEXT or GND, except for the following:
• ADDR23–0, DATA47–0, BRST, CLKOUT (Note: These
pins have a logic-level hold circuit enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
• PA, ACK, RD, WR, DMARx, DMAGx, (ID2–0 = 00x)
(Note: These pins have a pull-up enabled on the
ADSP-21161N DSP with ID2–0 = 00x.)
• LxCLK, LxACK, LxDAT7–0 (LxPDRDE = 0) (Note: See
Link Port Buffer Control Register Bit definitions in the
ADSP-21161N SHARC DSP Hardware Reference.)
The following symbols appear in the Type column of Table 2:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State (when SBTS is
asserted or when the ADSP-21161N is a bus slave).
Unlike previous SHARC processors, the ADSP-21161N contains internal series resistance equivalent to 50  on all
input/output drivers except the CLKIN and XTAL pins.
Therefore, for traces longer than six inches, external series resistors on control, data, clock, or frame sync pins are not required
to dampen reflections from transmission line effects for pointto-point connections. However, for more complex networks
such as a star configuration, series termination is still
recommended.
• DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU,
TMS,TRST, TDI (Note: These pins have a pull-up.)
Table 2. Pin Function Descriptions
Pin
ADDR23–0
Type
I/O/T
DATA47–16
I/O/T
MS3–0
I/O/T
RD
I/O/T
WR
I/O/T
Function
External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these
pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other
ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that
is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or
multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP’s ADDR23-0 pins
maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with
ID2–0=00x.
External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up
resistors on unused data pins are not necessary. A keeper latch on the DSP’s DATA47–16 pins maintains the
input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2–0=00x.
Note: DATA15–8 pins (multiplexed with L1DAT7–0) can also be used to extend the data bus if the link ports are
disabled and will not be used. In addition, DATA7–0 pins (multiplexed with L0DAT7–0) can also be used to extend
the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM
(system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half
the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1–0=0x1)
to enable this full instruction Width/No-packing Mode of operation.
Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank sizes are fixed to 16 M words for non-SDRAM and 64M words for SDRAM.
The MS3–0 outputs are decoded memory address lines. In asynchronous access mode, the MS3–0 outputs
transition with the other address outputs. In synchronous access modes, the MS3–0 outputs assert with the
other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a
multiprocessor system, the MSx signals are tracked by slave SHARCs.
Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from
the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD
for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven
by the bus master. RD has a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP
registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers.
In a multiprocessing system, the bus master drives WR. WR has a 20 k internal pull-up resistor that is enabled
for DSPs with ID2–0=00x.
Rev. C |
Page 11 of 60 |
January 2013
ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
Pin
BRST
Type
I/O/T
ACK
I/O/S
SBTS
I/S
CAS
I/O/T
RAS
I/O/T
SDWE
I/O/T
DQM
O/T
SDCLK0
SDCLK1
I/O/S/T
O/S/T
SDCKE
I/O/T
SDA10
O/T
IRQ2–0
I/A
FLAG11–0
I/O/A
TIMEXP
O
HBR
I/A
HBG
I/O
CS
I/A
Function
Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data associated with consecutive
addresses is being read or written. A slave device samples the initial address and increments an internal
address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol.
BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for
the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP’s
BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N
with ID2–0=00x.
Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory
access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous
access of its IOP registers. ACK has a 20 k internal pull-up resistor that is enabled during reset or on DSPs
with ID2–0=00x.
Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to
access external memory while SBTS is asserted, the processor will halt and the memory access will not be
completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N
deadlock.
SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10,
defines the operation for the SDRAM to perform.
SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines
the operation for the SDRAM to perform.
SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the
operation for the SDRAM to perform.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command
and during SDRAM power-up initialization.
SDRAM Clock Output 0. Clock for SDRAM devices.
SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices,
handles the increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or
both SDCLKx pins can be three-stated.
SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the
SDRAM device.
SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a non-SDRAM accesses or host
accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.
Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered
or level-sensitive.
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a
condition. As an output, it can be used to signal external peripherals.
Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to
zero.
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-21161N’s external
bus. When HBR is asserted in a multiprocessing system, the ADSP-21161N that is bus master will relinquish
the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe
lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6–1) in a multiprocessing system.
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of
the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing
system, HBG is output by the ADSP-21161N bus master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 tCK (1 CLKIN cycle). To avoid erroneous
grants, HBG should be pulled up with a 20 k to 50 k external resistor.
Chip Select. Asserted by host processor to select the ADSP-21161N.
Rev. C |
Page 12 of 60 |
January 2013
ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
Pin
REDY
Type
O (O/D)
DMAR1
I/A
DMAR2
I/A
DMAG1
O/T
DMAG2
O/T
BR6–1
I/O/S
BMSTR
O
ID2–0
I
RPBA
I/S
PA
I/O/T
DxA
I/O
DxB
I/O
SCLKx
I/O
FSx
I/O
SPICLK
I/O
Function
Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its
IOP registers when CS and HBR inputs are asserted.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has
a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has
a 20 k internal pull-up resistor that is enabled for DSPs with ID2–0=00x.
DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the
next cycle. Driven by bus master only. DMAG1 has a 20 k internal pull-up resistor that is enabled for DSPs
with ID2–0=00x.
DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the
next cycle. Driven by bus master only. DMAG2 has a 20 k internal pull-up resistor that is enabled for DSPs
with ID2–0=00x.
Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An
ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2–0 inputs) and monitors all
others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled
high; the processor's own BRx line must not be pulled high or low because it is an output.
Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master
of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a singleprocessor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes.
Multiprocessing ID. Determines which multiprocessing bus request (BR6–BR1) is used by ADSP-21161N.
ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in singleprocessor systems. These lines are a system configuration selection that should be hardwired or only changed
at reset.
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus
arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection that must be set to the same value on every ADSP-21161N. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N.
Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA
transfers and gain access to the external bus. PA is connected to all ADSP-21161Ns in the system. If access
priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k internal pull-up
resistor that is enabled for DSPs with ID2–0=00x.
Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This
signal can be either internally or externally generated.
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally. It can be active high or low or an early or a late frame
sync, in reference to the shifting of serial data.
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is
transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word.
Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge
of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data
are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 k internal
pull-up resistor.
Rev. C |
Page 13 of 60 |
January 2013
ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
Pin
SPIDS
Type
I
MOSI
I/O (o/d)
MISO
I/O (o/d)
LxDAT7–0
[DATA15–0]
I/O
[I/O/T]
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
BMS
I/O/T
CLKIN
I
XTAL
O
CLK_CFG1-0
I
Function
Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input
signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster
mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other
device is also trying to be the master device. If asserted low when the device is in master mode, it is considered
a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0 are used, this pin must
be tied or pulled high to VDDEXT on the master device. For ADSP-21161N to ADSP-21161N SPI interaction, any
of the master ADSP-21161N’s FLAG3–0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI
slave device.
SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit
(output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a
data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out
from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal
pull-up resistor.
SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive
(input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data
transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted
out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an
internal pull-up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time.
Link Port Data (Link Ports 0–1).
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data
pin; or a 20 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 k internal pull-down resistor that is enabled
or disabled by the LxPDRDE bit of the LCTL register.
Note: L1DAT7–0 are multiplexed with the DATA15–8 pins L0DAT7–0 are multiplexed with the DATA7–0 pins. If link
ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at
up to the full clock rate from external memory. See DATA47–16 for more information.
Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 k resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 k resistor that is
enabled or disabled by the LxPDRDE bit of the LCTL register.
EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This
signal is a system configuration selection that should be hardwired.
Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is
a system configuration selection that should be hardwired.
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4).
This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA
channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used.
Three-state only in EPROM boot mode (when BMS is an output).
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP21161N to use either its internal clock generator or an external clock source. Connecting the necessary
components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN
while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an
external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction
cycle rate is a multiple of the CLKIN frequency; it is programmable at power-up via the CLK_CFG1–0 pins.
CLKIN may not be halted, changed, or operated below the specified frequency.
Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP-21161N’s internal clock
oscillator or to disable it to use an external clock source. See CLKIN.
Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n  PLLICLK where
n is user selectable to 2, 3, or 4, using the CLK_CFG1–0 inputs. These pins can also be used in combination
with the CLKDBL pin to generate additional core clock rates of 6  CLKIN and 8  CLKIN (see the Clock Rate
Ratios table in the CLKDBL description).
Rev. C |
Page 14 of 60 |
January 2013
ADSP-21161N
Table 2. Pin Function Descriptions (Continued)
1
Pin
CLKDBL
Type
I
CLKOUT
O/T
RESET
I/A
RSTOUT1
O
TCK
TMS
TDI
I
I/S
I/S
TDO
TRST
O
I/A
EMU
O (O/D)
VDDINT
VDDEXT
AVDD
P
P
P
AGND
GND
NC
G
G
Function
Crystal Double Mode Enable. This pin is used to enable the 2 clock double circuitry, where CLKOUT can
be configured as either 1 or 2 the rate of CLKIN. This CLKIN double circuit is primarily intended to be used
for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock
generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to
a maximum of 27.5 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 55 MHz
input into the PLL. The 2 clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is
connected to VDDEXT for 1 clock mode. For example, this enables the use of a 27.5 MHz crystal to enable 110
MHz core clock rates and a 55 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0.
This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The
possible clock rate ratio options (up to 110 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal
input) are shown in Table 3 on Page 16. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100
MHz core (instruction clock) rate and a 25 MHz CLKOUT (external port) clock rate. See also Figure 8 on Page 20.
Note: When using an external crystal, the maximum crystal frequency cannot exceed 27.5 MHz. For all other
external clock sources, the maximum CLKIN frequency is 55 MHz.
Local Clock Out. CLKOUT is 1 or 2 and is driven at either 1 or 2 the frequency of CLKIN frequency by the
current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the
ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the
DSP’s CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP21161N with ID2–0=00x.
If CLKDBL enabled, CLKOUT=2 CLKIN
If CLKDBL disabled, CLKOUT=1 CLKIN
Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 CLKIN or 2  CLKIN.
Do not use CLKOUT in multiprocessing systems. Use CLKIN instead.
Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory
location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted
4080 cycles after RESET is deasserted indicating that the PLL is stable and locked.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up
resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-21161N. TRST has a 20 k internal pull-up resistor.
Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG
emulators target board connector only. EMU has a 50 k internal pull-up resistor.
Core Power Supply. Nominally +1.8 V dc and supplies the DSP’s core processor (14 pins).
I/O Power Supply. Nominally +3.3 V dc. (13 pins).
Analog Power Supply. Nominally +1.8 V dc and supplies the DSP’s internal PLL (clock generator). This pin
has the same specifications as VDDINT, except that added filtering circuitry is required. For more information,
see Power Supplies on Page 9.
Analog Power Supply Return.
Power Supply Return. (26 pins).
Do Not Connect. Reserved pins that must be left open and unconnected. (4 pins)
RSTOUT exists only for silicon revisions 1.2 and greater.
Rev. C |
Page 15 of 60 |
January 2013
ADSP-21161N
Table 3. Clock Rate Ratios
CLKDBL
1
1
1
0
0
0
CLK_CFG1
0
0
1
0
0
1
CLK_CFG0
0
1
0
0
1
0
Core:CLKIN
2:1
3:1
4:1
4:1
6:1
8:1
BOOT MODES
Table 4. Boot Mode Selection
EBOOT
1
0
0
0
0
1
LBOOT
0
0
1
1
0
1
BMS
Output
1 (Input)
0 (Input)
1 (Input)
0 (Input)
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select.)
Host Processor
Serial Boot via SPI
Link Port
No Booting. Processor executes from external memory.
Reserved
Rev. C |
Page 16 of 60 |
January 2013
CLKIN:CLKOUT
1:1
1
1
1:2
1:2
1:2
ADSP-21161N
SPECIFICATIONS
OPERATING CONDITIONS
100 MHz
Parameter1 Description
VDDINT
AVDD
VDDEXT
VIH
VIL
TCASE
Internal (Core) Supply Voltage
Analog (PLL) Supply Voltage
External (I/O) Supply Voltage
High Level Input Voltage2
Low Level Input Voltage2
Case Operating Temperature3
Test Conditions
@ VDDEXT = Max
@ VDDEXT = Min
110 MHz
Min
Max
Min
Max
Unit
1.71
1.71
3.13
2.0
–0.5
–40
1.89
1.89
3.47
VDDEXT +0.5
+0.8
+105
1.71
1.71
3.13
2.0
–0.5
–40
1.89
1.89
3.47
VDDEXT +0.5
+0.8
+125
V
V
V
V
V
C
1
Specifications subject to change without notice.
Applies to input and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, DMAR1, DMAR2, BR6–1, ID2–0,
RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE,
CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI.
3
See Thermal Characteristics on Page 55 for information on thermal specifications.
2
Rev. C |
Page 17 of 60 |
January 2013
ADSP-21161N
ELECTRICAL CHARACTERISTICS
Parameter Description
VOH
VOL
IIH
IIL
IIHC
IILC
IIKH
IIKL
IIKH-OD
IIKL-OD
IILPU
IOZH
IOZL
IOZLPU1
IOZLPU2
IOZHPD1
IOZHPD2
IDD-INPEAK
High Level Output Voltage1
Low Level Output Voltage1
High Level Input Current3, 4
Low Level Input Current3
CLKIN High Level Input Current5
CLKIN Low Level Input Current5
Keeper High Load Current6
Keeper Low Load Current6
Keeper High Overdrive Current6, 7, 8
Keeper Low Overdrive Current6, 7, 8
Low Level Input Current Pull-Up4
Three-State Leakage Current9, 10, 11
Three-State Leakage Current9, 12, 13
Three-State Leakage Current Pull-Up110
Three-State Leakage Current Pull-Up211
Three-State Leakage Current Pull-Down112
Three-State Leakage Current Pull-Down213
Supply Current (Internal)14, 15
IDD-INHIGH
Supply Current (Internal)15, 16
IDD-INLOW
Supply Current (Internal)15, 17
IDD-IDLE
Supply Current (Idle)15, 18
AIDD
CIN
Supply Current (Analog)19
Input Capacitance20, 21
Test Conditions
Min
@ VDDEXT = Min, IOH = –2.0 mA2
@ VDDEXT = Min, IOL = 4.0 mA2
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 2.0 V
@ VDDEXT = Max, VIN = 0.8 V
@ VDDEXT = Max
@ VDDEXT = Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = 0 V
@ VDDEXT = Max, VIN = VDDEXT Max
@ VDDEXT = Max, VIN = VDDEXT Max
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
tCCLK = 9.0 ns, VDDINT = Max
tCCLK = 10.0 ns, VDDINT = Max
@ AVDD = Max
fIN = 1 MHz, TCASE = 25°C, VIN = 1.8 V
2.4
1
–250
50
–300
300
Max
0.4
10
10
35
35
–100
200
350
10
10
500
350
350
500
965
900
700
650
535
500
425
400
10
4.7
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
mA
mA
mA
mA
mA
pF
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
2
See Output Drive Currents on Page 54 for typical drive current capabilities.
3
Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
4
Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5
Applies to CLKIN only.
6
Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7
Current required to switch from kept high to low or from kept low to high.
8
Characterized, but not tested.
9
Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
BRST.
10
Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.
11
Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
12
Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher.
13
Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
14
The test program used to measure IDDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.
15
Current numbers are for VDDINT and AVDD supplies combined.
16
IDDINHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.
17
IDDINLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.
18
Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.
19
Characterized, but not tested.
20
Applies to all signal pins.
21
Guaranteed, but not tested.
Rev. C |
Page 18 of 60 |
January 2013
ADSP-21161N
PACKAGE INFORMATION
ESD CAUTION
The information presented in Figure 7 provides details about
how to read the package brand and relate it to specific product
features.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
a
ADSP-21161N
tppZ-cc
TIMING SPECIFICATIONS
vvvvvv.x n.n
#yyww country_of_origin
The ADSP-21161N’s internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the
internal clock, the DSP uses an internal phase-locked loop
(PLL). This PLL-based clocking minimizes the skew between
the system clock (CLKIN) signal and the DSP’s internal clock
(the clock source for the external port logic and I/O pads).
S
Figure 7. Typical Package Brand
Table 5. Package Brand Information
Brand Key
ADSP-21161N
t
pp
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vvvvv.x
n.n
#
yyww
The ADSP-21161N’s internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor
core, link ports, serial ports, and external port (as required for
read/write strobes in asynchronous access mode). During reset,
program the ratio between the DSP’s internal clock frequency
and external (CLKIN) clock frequency with the CLK_CFG1–0
and CLKDBL pins. Even though the internal clock is the clock
source for the external port, it behaves as described in the Clock
Rate Ratio chart in Table 3 on Page 16. To determine switching
frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port
(DIVx for the serial ports and LxCLKD for the link ports).
Field Description
Model Number
Temperature Range
Package Type
RoHS Compliance Option
Assembly Lot Code
Silicon Revision
RoHS Compliance Designation
Date Code
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 6 may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 6. Absolute Maximum Ratings
Parameter
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (AVDD)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Rating
–0.3 V to +2.2 V
–0.3 V to +2.2 V
–0.3 V to +4.6 V
–0.5 V to VDDEXT + 0.5 V
–0.5 V to VDDEXT + 0.5 V
200 pF
–65C to +150C
Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control (Table 7).
Figure 8 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and
8:1 with external oscillator or crystal. It also shows support for
CLKOUT-to-CLKIN ratios of 1:1 and 2:1.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See Figure 37 on Page 54 under Test Conditions for voltage reference levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Rev. C |
Page 19 of 60 |
January 2013
ADSP-21161N
ASYNCHRONOUS EP
MULTIPROCESSING
SBSRAM
HOST
SRAM
CLOCK DOUBLER
x1, x2
CCLK
(33.3–110 MHz)
CLKIN
(CRYSTAL OSCILLATOR
4.2–55 MHz)
CORE
I/O PROCESSOR
HARDWARE
INTERRUPT
I/O FLAG
TIMER
PLLICLK
(4.2–50MHz)
SYNCHRONOUS EP
PLL
CLKDBL
CLKOUT
SDRAM
x1, x1/2
SERIAL PORTS
x1/2 MAX
RATIOS
x2, x3, x4
XTAL
(QUARTZ CRYSTAL
27.5 MHz MAX)
LINK PORTS
x1, x1/2, x1/3, x1/4
SPI
x1/8 MAX
CLK_CFG1–0
Figure 8. Core Clock and System Clock Relationship to CLKIN
Table 7. CLKOUT and CCLK Clock Generation Operation
Timing Requirements
CLKIN
CLKOUT
PLLICLK
CCLK
tCK
tCCLK
tLCLK
tSCLK
tSDK
tSPICLK
1
Description1
Input Clock
External Port System Clock
PLL Input Clock
Core Clock
CLKIN Clock Period
(Processor) Core Clock Period
Link Port Clock Period
Serial Port Clock Period
SDRAM Clock Period
SPI Clock Period
where:
LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)
SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)
SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)
LCLK = Link Port Clock
SCLK = Serial Port Clock
SDK = SDRAM Clock
SPICLK = SPI Clock
POWER DISSIPATION
Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output
drivers.
Internal power dissipation depends on the instruction execution
sequence and the data operands involved. Using the current
specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from the
Electrical Characteristics on Page 18 and the current-versusoperation information in Table 8, the programmer can estimate
the ADSP-21161N’s internal power supply (VDDINT) input current for a specific application, according to the following
formula:
% Peak  IDD-INPEAK
% High  IDD-INHIGH
% Low  IDD-INLOW
+ % Peak  IDD-IDLE
= IDDINT
Rev. C |
Page 20 of 60 |
January 2013
Calculation
1/tCK
1/tCKOP
1/tPLLIN
1/tCCLK
1/CLKIN
1/CCLK
(tCCLK) LR
(tCCLK)  SR
(tCCLK)  SDCKR
(tCCLK)  SPIR
ADSP-21161N
Table 8. Operation Types Versus Input Current
Operation
Instruction Type
Instruction Fetch
Core Memory Access2
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
1
2
Peak Activity1 (IDDINPEAK)
Multifunction
Cache
2 per tCK cycle (DM64 and PM64)
1 per 2 tCCLK cycles
1 per external port cycle (32)
Worst case
High Activity1 (IDDINHIGH)
Multifunction
Internal Memory
1 per tCK cycle (DM64)
1 per 2 tCCLK cycles
1 per external port cycle (32)
Random
Low Activity1 (IDDINLOW)
Single Function
Internal Memory
None
N/A
N/A
N/A
The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 19.
• The bus cycle time is 55 MHz
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• The external SDRAM clock rate is 110 MHz
• The number of output pins that switch during each cycle
(O)
• Ignoring SDRAM refresh cycles
• Addresses are incremental and on the same page
• The maximum frequency at which they can switch (f)
The PEXT equation is calculated for each class of pins that can
drive, as shown in Table 9.
• Their load capacitance (C)
• Their voltage swing (VDD)
and is calculated by:
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
2
P EXT = O  C  V DD  f
P TOTAL = P EXT + P INT + P PLL
The load capacitance should include the processor package
capacitance (CIN). The switching frequency includes driving the
load high and then back low. At a maximum rate of 1/tCK,
address and data pins can drive high and low, while writing to a
SDRAM memory.
Where:
PEXT is from Table 9.
PINT is IDDINT × 1.8 V, using the calculation IDDINT listed in Power
Dissipation on Page 20.
PPLL is AIDD × 1.8 V, using the value for AIDD listed in the Electrical Characteristics on Page 18.
Example: Estimate PEXT with the following assumptions:
• A system with one bank of external memory (32 bit)
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
• Two 1M ⴛ 16 SDRAM chips are used, each with a load of
10 pF (ignoring trace capacitance)
• External Data Memory writes can occur every cycle at a
rate of 1/tCK with 50% of the pins switching
Table 9. External Power Calculations—110 MHz Instruction Rate
Pin Type
Address
MSx
SDWE
Data
SDCLK0
Number of Pins
11
4
1
32
1
% Switching
20
0
0
50
100
Rev. C |
ⴛC
24.7 pF
24.7 pF
24.7 pF
14.7 pF
24.7 pF
Page 21 of 60 |
ⴛf
55 MHz
N/A
N/A
55 MHz
110 MHz
January 2013
ⴛ VDD2
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
= PEXT
= 0.033 W
= 0.000 W
= 0.000 W
= 0.141 W
= 0.030 W
PEXT = 0.204 W
ADSP-21161N
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
Power-Up Sequencing — Silicon Revision 1.2 and Greater
The timing requirements for DSP startup are given in Table 10.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
DC INPUT
SOURCE
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in Figure 9. It protects the
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
3.3V I/O
VOLTAGE
REGULATOR
VDDEXT
1.8V CORE
VOLTAGE
REGULATOR
VDDINT
ADSP-21161N
Figure 9. Dual Voltage Schottky Diode
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)
Parameter
Timing Requirements
tRSTVDD
RESET Low Before VDDINT/VDDEXT on
tIVDDEVDD
VDDINT on Before VDDEXT
tCLKVDD
CLKIN Valid After VDDINT/VDDEXT Valid1
tCLKRST
CLKIN Valid Before RESET Deasserted2
tPLLRST
PLL Control Setup Before RESET Deasserted3
tWRST
Subsequent RESET Low Pulsewidth4
Switching Requirements
tCORERST
DSP core reset deasserted after RESET deasserted
Min
0
–50
0
10
20
4tCK
Max
+200
200
Unit
ns
ms
ms
μs
μs
ns
4080tCK3, 5
1
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4080 cycle count depends on tSRST specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4081 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKRST
tCLKVDD
CLKIN
CLKDBL
CLK_CFG1-0
tPLLRST
tCORERST
RSTOUT
Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)
Rev. C |
Page 22 of 60 |
January 2013
ADSP-21161N
Clock Input
In systems that use multiprocessing or SBSRAM, CLKDBL cannot be enabled nor can the systems use an external crystal as the
CLKIN source.
Do not use CLKOUT as the clock source for the SBSRAM
device. Using an external crystal in conjunction with CLKDBL
to generate a CLKOUT frequency is not supported. Negative
hold times can result from the potential skew between CLKIN
and CLKOUT.
Table 11. Clock Input
Parameter
Timing Requirements
CLKIN Period1
tCK
tCKL
CLKIN Width Low1
tCKH
CLKIN Width High1
CLKIN Rise/Fall (0.4 V–2.0 V)
tCKRF
tCCLK
CCLK Period
Switching Characteristics
tDCKOO CLKOUT Delay After CLKIN
tCKOP
CLKOUT Period
tCKWH CLKOUT Width High
tCKWL CLKOUT Width Low
1
100 MHz
Max
Min
20
7.5
7.5
Min
18
7
7
10
238
119
119
3
30
0
tCK –1
tCKOP/2–2
tCKOP/2–2
2
tCK +1
tCKOP/2+2
tCKOP/2+2
9
ns
ns
ns
ns
ns
0
tCK –1
tCKOP/2–2
tCKOP/2–2
2
tCK +1
tCKOP/2+2
tCKOP/2+2
ns
ns
ns
ns
tCK
CLKIN
tCKH
tCKL
tCKOP1
tCKWH1
tCKWL1
CLKOUT
tDCKOO2
tCKOP2
tDCKOO2
tCKWL 2
tCKWH2
CLKOUT
NOTES:
1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING EDGE, ONLY.
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING OR FALLING EDGE.
Figure 11. Clock Input
Rev. C |
Page 23 of 60 |
January 2013
Unit
238
119
119
3
30
CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired tCCLK.
tDCKOO1
110 MHz
Max
ADSP-21161N
Clock Signals
The ADSP-21161N can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21161N to use its internal clock generator by connecting
CLKIN
the necessary components to CLKIN and XTAL. Figure 12
shows the component connections used for a crystal operating
in fundamental mode.
XTAL
X1
C1
27pF
C2
27pF
SUGGESTED COMPONENTS FOR 100MHz OPERATION:
ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)
C1 = 27pF
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz
CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK
WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.
Figure 12. 100 MHz Operation (Fundamental Mode Crystal)
Reset
Table 12. Reset
Parameter
Timing Requirements
tWRST
RESET Pulsewidth Low1
RESET Setup Before CLKIN High2
tSRST
1
2
Min
Max
4tCK
8.5
Unit
ns
ns
Applies after the power-up sequence is complete.
Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21161Ns
communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
tSRST
tWRST
RESET
Figure 13. Reset
Rev. C |
Page 24 of 60 |
January 2013
ADSP-21161N
Interrupts
Table 13. Interrupts
Parameter
Timing Requirements
tSIR
IRQ2–0 Setup Before CLKIN1
tHIR
IRQ2–0 Hold After CLKIN1
tIPW
IRQ2–0 Pulsewidth2
1
2
Min
Max
Unit
6
0
tCKOP + 2
ns
ns
ns
Only required for IRQx recognition in the following cycle.
Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2–0
tIPW
Figure 14. Interrupts
Timer
Table 14. Timer
Parameter
Switching Characteristic
tDTEX
CCLK to TIMEXP
Min
Max
Unit
1
7
ns
CCLK
tDTEX
tDTEX
TIMEXP
Figure 15. Timer
Rev. C |
Page 25 of 60 |
January 2013
ADSP-21161N
Flags
Table 15. Flags
Parameter
Timing Requirement
tSFI
FLAG11–0IN Setup Before CLKIN1
tHFI
FLAG11–0IN Hold After CLKIN1
tDWRFI
FLAG11–0IN Delay After RD/WR Low1
tHFIWR
FLAG11–0IN Hold After RD/WR Deasserted1
Switching Characteristics
FLAG11–0OUT Delay After CLKIN
tDFO
tHFO
FLAG11–0OUT Hold After CLKIN
tDFOE
CLKIN to FLAG11–0OUT Enable
tDFOD
CLKIN to FLAG11–0OUT Disable
1
100 MHz
Max
Min
Min
4
1
110 MHz
Max
4
1
12
9
0
0
9
9
1
1
1
1
5
5
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
CLKIN
tDFO
tDFOE
tDFO
tHFO
FLAG11–0OUT
FLAG OUTPUT
CLKIN
tSFI
tHFI
FLAG11–0IN
tDWRFI
tHFIWR
⌹⌬, ⑁ ⌹
FLAG INPUT
Figure 16. Flags
Rev. C |
Page 26 of 60 |
January 2013
tDFOD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21161N
Memory Read — Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 4 of
Table 16. These specifications apply when the ADSP-21161N is
the bus master accessing external memory space in asynchronous access mode.
Table 16. Memory Read — Bus Master
100 MHz
110 MHz
Parameter
Min
Max
Min
Max
Timing Requirements
tDAD
Address, Selects Delay to
tCKOP –0.25tCCLK –8.5+W
tCKOP –0.25tCCLK –6.75+W
Data Valid1, 2, 3
tDRLD
RD Low to Data Valid1,3
0.75tCKOP –11+W
0.75tCKOP –11+W
tHDA
Data Hold from Address, 0
0
Selects4
tSDS
Data Setup to RD High
8
8
4
tHDRH
Data Hold from RD High 1
1
tDAAK
ACK Delay from Address,
tCKOP –0.5tCCLK –12+W
tCKOP –0.5tCCLK –12+W
Selects2, 5
tDSAK
ACK Delay from RD Low5
tCKOP –0.75tCCLK –11+W
tCKOP –0.75tCCLK –11+W
tSAKC
ACK Setup to CLKIN5
0.5tCCLK+3
0.5tCCLK+3
tHAKC
ACK Hold After CLKIN
1
1
Switching Characteristics
tDRHA
0.25tCCLK–1+H
Address Selects Hold
0.25tCCLK–1+H
After RD High
tDARL
Address Selects to RD
0.25tCCLK –3
0.25tCCLK –3
Low2
tRW
RD Pulsewidth
tCKOP–0.5tCCLK –1+W
tCKOP–0.5tCCLK –1+W
tRWR
RD High to WR, RD,
0.5tCCLK –1+HI
0.5tCCLK –1+HI
DMAGx Low
W = (number of wait states specified in WAIT register) × tCKOP.
HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCKOP (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.
The falling edge of MSx, BMS is referenced.
3
The maximum limits of timing requirement values for tDAD and tDRLD parameters are applicable for the case where ACK is always high.
4
Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on Page 54 for the calculation of hold times given capacitive
and dc loads.
5
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be
met for both assertion and deassertion of ACK signal.
2
Rev. C |
Page 27 of 60 |
January 2013
ADSP-21161N
tHDA
ADDRESS
MSx, BMS
tDARL
tDRHA
tRW
RD
tSDS
tDRLD
tDAD
tHDRH
DATA
tDSAK
tDAAK
tRWR
ACK
tHAKC
tSAKC
CLKIN
WR, DMAG
Figure 17. Memory Read — Bus Master
Rev. C |
Page 28 of 60 |
January 2013
ADSP-21161N
Memory Write — Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to
CLKIN except for ACK pin requirements listed in footnote 1 of
Table 17. These specifications apply when the ADSP-21161N is
the bus master accessing external memory space in asynchronous access mode.
Table 17. Memory Write — Bus Master
Parameter
Min
Max
Timing Requirements
ACK Delay from Address, Selects1, 2
tCKOP–0.5tCCLK–12+W
tDAAK
tDSAK
ACK Delay from WR Low1
tCKOP–0.75tCCLK–11+W
tSAKC
ACK Setup to CLKIN1
0.5tCCLK +3
tHAKC
ACK Hold After CLKIN1
1
Switching Characteristics
tDAWH
Address, Selects to WR Deasserted2
tCKOP – 0.25tCCLK – 3+W
2
Address, Selects to WR Low
0.25tCCLK – 3
tDAWL
tWW
WR Pulsewidth
tCKOP – 0.5tCCLK – 1+W
tDDWH
Data Setup Before WR High
tCKOP –0.25tCCLK – 13.5+W
tDWHA
Address Hold After WR Deasserted
0.25tCCLK – 1+H
tDWHD
Data Hold After WR Deasserted
0.25tCCLK – 1+H
tDATRWH
Data Disable After WR Deasserted3
0.25tCCLK – 2+H
0.25tCCLK+2.5+H
WR High to WR, RD, DMAGx Low
0.5tCCLK – 1.25+HI
tWWR
tDDWR
Data Disable Before WR or RD Low
0.25tCCLK – 3+I
tWDE
WR Low to Data Enabled
–0.25tCCLK – 1
W = (number of wait states specified in WAIT register) × tCKOP.
H = tCKOP (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCKOP (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
For asynchronous access, ACK is sampled only after the programmed wait states for the access have been counted. For the first CLKIN cycle of a new external memory access,
ACK must be driven low (deasserted) by tDAAK, tDSAK, or tSAKC. For the second and subsequent cycles of an asynchronous external memory access, the tSAKC and tHAKC must be
met for both assertion and deassertion of ACK signal.
2
The falling edge of MSx, BMS is referenced.
3
See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.
Rev. C |
Page 29 of 60 |
January 2013
ADSP-21161N
ADDRESS
MSx, BMS
tDAWH
tDAWL
tDWHA
tWW
WR
tWWR
tDATRWH
tWDE
tDDWH
tDDWR
DATA
tDSAK
tDWHD
tDAAK
ACK
tHAKC
tSAKC
CLKIN
RD, DMAG
Figure 18. Memory Write — Bus Master
Rev. C |
Page 30 of 60 |
January 2013
ADSP-21161N
Synchronous Read/Write — Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a
slave ADSP-21161N (in multiprocessor memory space). When
accessing a slave ADSP-21161N, these switching characteristics
must meet the slave's timing requirements for synchronous
read/writes (see Synchronous Read/Write — Bus Slave on
Page 32). The slave ADSP-21161N must also meet these (bus
master) timing requirements for data and acknowledge setup
and hold times.
Table 18. Synchronous Read/Write — Bus Master
Parameter
Timing Requirements
tSSDATI
Data Setup Before CLKIN
tHSDATI
Data Hold After CLKIN
ACK Setup Before CLKIN
tSACKC
tHACKC
ACK Hold After CLKIN
Switching Characteristics
tDADDO
Address, MSx, BMS, BRST, Delay After CLKIN
tHADDO
Address, MSx, BMS, BRST, Hold After CLKIN
tDRDO
RD High Delay After CLKIN
WR High Delay After CLKIN
tDWRO
tDRWL
RD/WR Low Delay After CLKIN
tDDATO
Data Delay After CLKIN
tHDATO
Data Hold After CLKIN
Min
Max
5.5
1
0.5tCCLK+3
1
ns
ns
ns
ns
10
1.5
0.25tCCLK–1
0.25tCCLK–1
0.25tCCLK–1
0.25tCCLK+9
0.25tCCLK+9
0.25tCCLK+9
12.5
1.5
CLKIN
tHADDO
tDADDO
ADDRESS
MSx, BRST
tSACKC
tHACKC
ACK
(IN)
READ CYCLE
tDRWL
tDRDO
RD
tSSDATI
tHSDATI
DATA
(IN)
WRITE CYCLE
tDRWL
tDWRO
WR
tDDATO
tHDATO
DATA (OUT)
Figure 19. Synchronous Read/Write — Bus Master
Rev. C |
Page 31 of 60 |
January 2013
Unit
ns
ns
ns
ns
ns
ns
ns
ADSP-21161N
Synchronous Read/Write — Bus Slave
Use these specifications for ADSP-21161N bus master accesses
of a slave’s IOP registers in multiprocessor memory space. The
bus master must meet these (bus slave) timing requirements.
Table 19. Synchronous Read/Write — Bus Slave
Parameter
Timing Requirements
Address, BRST Setup Before CLKIN
tSADDI
tHADDI
Address, BRST Hold After CLKIN
tSRWI
RD/WR Setup Before CLKIN
tHRWI
RD/WR Hold After CLKIN
tSSDATI
Data Setup Before CLKIN
tHSDATI
Data Hold After CLKIN
Switching Characteristics
tDDATO
Data Delay After CLKIN
tHDATO
Data Hold After CLKIN
tDACKC
ACK Delay After CLKIN
tHACKO
ACK Hold After CLKIN
Min
Max
5
1
5
1
5.5
1
ns
ns
ns
ns
ns
ns
12.5
1.5
10
1.5
CLKIN
tSADDI
tHADDI
ADDRESS
tHACKO
tDACKC
ACK
tSRWI
READ ACCESS
tHRWI
RD
tDDATO
tHDATO
DATA
(OUT)
WRITE ACCESS
tHRWI
tSRWI
WR
tSSDATI
DATA
(IN)
Figure 20. Synchronous Read/Write — Bus Slave
Rev. C |
Page 32 of 60 |
January 2013
Unit
tHSDATI
ns
ns
ns
ns
ADSP-21161N
Host Bus Request
Use these specifications for asynchronous host bus requests of
an ADSP-21161N (HBR, HBG).
Table 20. Host Bus Request
Parameter
Timing Requirements
tHBGRCSV
HBG Low to RD/WR/CS Valid
tSHBRI
HBR Setup Before CLKIN1
tHHBRI
HBR Hold After CLKIN1
HBG Setup Before CLKIN
tSHBGI
tHHBGI
HBG Hold After CLKIN
Switching Characteristics
tDHBGO
HBG Delay After CLKIN
tHHBGO
HBG Hold After CLKIN
tDRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low2
REDY (O/D) Disable or REDY (A/D) High from HBG2
tTRDYHG
tARDYTR
REDY (A/D) Disable from CS or HBR High2
1
2
Min
100 MHz
Max
19
6
1
6
1
7
1.5
10
Page 33 of 60 |
ns
ns
ns
ns
ns
7
ns
ns
ns
ns
ns
1.5
tCKOP + 14
10
tCKOP + 12
11
January 2013
Unit
19
6
1
6
1
Only required for recognition in the current cycle.
(O/D) = open drain, (A/D) = active drive.
Rev. C |
Min
110 MHz
Max
11
ADSP-21161N
CLKIN
tSH B R I
tH H BR I
HBR
tD H BG O
tH H B GO
HBG (OUT)
tSH B GI
tH H B GI
HBG (IN)
HBR
CS
tD R DY C S
tTR D YH G
REDY
(O/D)
tA R D YTR
REDY
(A/D)
tH B GR CS V
HBG (OUT)
RD
WR
CS
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 21. Host Bus Request
Rev. C |
Page 34 of 60 |
January 2013
ADSP-21161N
Multiprocessor Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21161Ns (BRx).
Table 21. Multiprocessor Bus Request
Parameter
Timing Requirements
tSBRI
BRx Setup Before CLKIN High
tHBRI
BRx Hold After CLKIN High
tSPAI
PA Setup Before CLKIN High
tHPAI
PA Hold After CLKIN High
RPBA Setup Before CLKIN High
tSRPBAI
tHRPBAI
RPBA Hold After CLKIN High
Switching Characteristics
tDBRO
BRx Delay After CLKIN High
tHBRO
BRx Hold After CLKIN High
tDPASO
PA Delay After CLKIN High, Slave
PA Disable After CLKIN High, Slave
tTRPAS
tDPAMO
PA Delay After CLKIN High, Master
tPATR
PA Disable Before CLKIN High, Master
Min
Max
Unit
9
0.5
9
1
6
2
ns
ns
ns
ns
ns
ns
8
1.0
8
1.5
0.25tCCLK+9
0.25tCCLK–5
CLKIN
tD B RO
tH B RO
BRx (OUT)
t DP A SO
tTR PA S
PA (OUT)
(SLAVE)
tD PA MO
tP AT R
PA (OUT)
(MASTER)
tSB R I
tH BR I
BRx (IN)
tS PA I
PA (IN)
(O/D)
tS R PB A I
t HR P B AI
RPBA
O/D = OPEN DRAIN
Figure 22. Multiprocessor Bus Request
Rev. C |
Page 35 of 60 |
January 2013
tH PA I
ns
ns
ns
ns
ns
ns
ADSP-21161N
Asynchronous Read/Write — Host to ADSP-21161N
Use these specifications for asynchronous host processor
accesses of an ADSP-21161N, after the host has asserted CS and
HBR (low). After HBG is returned by the ADSP-21161N, the
host can drive the RD and WR pins to access the
ADSP-21161N’s IOP registers. HBR and HBG are assumed low
for this timing. Although the DSP will recognize HBR asserted
before reset, a HBG will not be returned by the DSP until after
reset is deasserted and the DSP completes bus synchronization.
Note: Host internal memory access is not supported.
Table 22. Read Cycle
Parameter
Timing Requirements
tSADRDL
Address Setup and CS Low Before RD Low
tHADRDH
Address Hold and CS Hold Low After RD
tWRWH
RD/WR High Width
tDRDHRDY
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
tDRDHRDY
Switching Characteristics
tSDATRDY
Data Valid Before REDY Disable from Low
tDRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low
tRDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read
tHDARWH
Data Disable After RD High
Min
Max
0
2
3.5
0
0
ns
ns
ns
ns
ns
2
10
1.5tCCLK
2
Unit
6
ns
ns
ns
ns
Table 23. Write Cycle
Parameter
Timing Requirements
tSCSWRL
CS Low Setup Before WR Low
tHCSWRH
CS Low Hold After WR High
tSADWRH
Address Setup Before WR High
tHADWRH
Address Hold After WR High
tWWRL
WR Low Width
tWRWH
RD/WR High Width
tDWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before WR High
tSDATWH
tHDATWH
Data Hold After WR High
Switching Characteristics
tDRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low1
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write1
1
Min
0
0
6
2
tCCLK
3.5
0
5
4
Page 36 of 60 |
January 2013
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
Only when slave write FIFO is full.
Rev. C |
Max
ns
ns
ADSP-21161N
READ CYCLE
ADDRESS/CS
tSADRDL
tHADRDH
tWRWH
RD
tHDARW H
DATA (OUT)
tS DAT RDY
tDRDY RDL
tDRDHRDY
tRDYPRD
REDY (O/D)
REDY (A/D)
WRITE CYCLE
ADDRESS
tS ADW RH
tSCS WRL
tHADW RH
tHCSWRH
CS
t WWRL
tW RW H
WR
tSDATWH
tHDATWH
DATA (IN)
tDRDY WRL
tRDYPW R
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 23. Asynchronous Read/Write — Host to ADSP-21161N
Rev. C |
Page 37 of 60 |
January 2013
tDWRHRDY
ADSP-21161N
During reset, the DSP will not respond to SBTS, HBR, and MMS
accesses. Although the DSP will recognize HBR asserted before
reset, a HBG will not be returned by the DSP until after reset is
deasserted and the DSP completes bus synchronization.
Three-State Timing — Bus Master, Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the
SBTS pin.
Table 24. Three-State Timing — Bus Master, Bus Slave
Parameter
Timing Requirements
tSTSCK
SBTS Setup Before CLKIN
tHTSCK
SBTS Hold After CLKIN
Switching Characteristics
tMIENA
Address/Select Enable After CLKIN High
Strobes Enable After CLKIN High1
tMIENS
tMIENHG
HBG Enable After CLKIN
tMITRA
Address/Select Disable After CLKIN High
tMITRS
Strobes Disable After CLKIN High
tMITRHG
HBG Disable After CLKIN2
tDATEN
Data Enable After CLKIN3
Data Disable After CLKIN3
tDATTR
tACKEN
ACK Enable After CLKIN High
tACKTR
ACK Disable After CLKIN High
tCDCEN
CLKOUT Enable After CLKIN2
tCDCTR
CLKOUT Disable After CLKIN
tATRHBG
Address/Select Disable Before HBG Low4
tSTRHBG
RD/WR/DMAGx Disable Before HBG Low4
BMS Disable Before HBG Low4
tBTRHBG
tMENHBG
Memory Interface Enable After HBG High4
Min
Max
6
2
ns
ns
1.5
–1.5
1.5
0.5tCKOP–20
tCKOP–0.25tCCLK–17
0.5tCKOP+NtCCLK–20
1.5
1.5
1.5
0.2
0.5tCKOP+NtCCLK
tCKOP–5
1.5tCKOP–6
tCKOP+0.25tCCLK–4
0.5tCKOP–4
tCKOP–5
1
9
+9
9
0.5tCKOP–15
tCKOP–0.25tCCLK–12.5
0.5tCKOP+NtCCLK–15
10
6
9
5
0.5tCKOP+NtCCLK+5
tCKOP
1.5tCKOP+2
tCKOP+0.25tCCLK+3
0.5tCKOP+2
tCKOP+5
Strobes = RD, WR, DMAGx.
Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.
3
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
4
Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.
2
Rev. C |
Page 38 of 60 |
Unit
January 2013
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21161N
CLKIN
tSTSCK
tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
tMITRA, tMITRS, tMITRHG
MEMORY
INTERFACE
tDATEN
tDATTR
tACKEN
tACKTR
DATA
ACK
CLKIN
tCDCEN
tCDCTR
CLKOUT
HBG
tMENHBG
tATRHBG, tSTRHBG, tBTRHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)
Figure 24. Three-State Timing — Bus Master, Bus Slave
Rev. C |
Page 39 of 60 |
January 2013
ADSP-21161N
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR23–0, RD, WR, MS3–0, ACK, and
DMAG signals. For Paced Master mode, the data transfer is
controlled by ADDR23–0, RD, WR, MS3–0, and ACK (not
DMAG). For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/WriteBus Master timing specifications for ADDR23–0, RD, WR,
MS3–0, DATA47–16, and ACK also apply.
Table 25. DMA Handshake
100 MHz
110 MHz
Parameter
Min
Max
Timing Requirements
tSDRC
DMARx Setup Before CLKIN1
3.5
tWDR
DMARx Width Low
tCCLK +4.5
(Nonsynchronous)2
tSDATDGL
Data Setup After DMAGx Low3
tCKOP – 0.5tCCLK –7
tHDATIDG
Data Hold After DMAGx High
2
tDATDRH
Data Valid After DMARx High3
tCKOP +3
tDMARLL
DMARx Low Edge to Low Edge4
tCKOP
tDMARH
DMARx Width High2
tCCLK +4.5
Switching Characteristics
tDDGL
DMAGx Low Delay After CLKIN
0.25tCCLK +1
0.25tCCLK +9
tWDGH
DMAGx High Width
0.5tCCLK – 1+HI
tWDGL
DMAGx Low Width
tCKOP – 0.5tCCLK – 1
tHDGC
DMAGx High Delay After CLKIN
tCKOP – 0.25tCCLK +1.0 tCKOP – 0.25tCCLK +9
tVDATDGH Data Valid Before DMAGx High5
tCKOP – 0.25tCCLK – 8
tCKOP – 0.25tCCLK +5
tDATRDGH Data Disable After DMAGx High6
0.25tCCLK – 3
0.25tCCLK +4
WRx Low Before DMAGx Low
–1.5
+2
tDGWRL
tDGWRH
DMAGx Low Before WRx High
tCKOP – 0.5tCCLK – 2 +W
tDGWRR
WRx High Before DMAGx High7
–1.5
+2
tDGRDL
RDx Low Before DMAGx Low
–1.5
+2
tDRDGH
RDx Low Before DMAGx High
tCKOP – 0.5tCCLK –2+W
tDGRDR
RDx High Before DMAGx High7
–1.5
+2
DMAGx High to WRx, RDx Low
0.5tCCLK – 2+HI
tDGWR
tDADGH
Address/Select Valid to DMAGx High 15
tDDGHA
Address/Select Hold After DMAGx
1
High
W = (number of wait states specified in WAIT register)  tCKOP.
HI = tCKOP (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1
Min
Max
3.5
tCCLK +4.5
ns
ns
tCKOP – 0.5tCCLK –7
2
tCKOP +3
tCKOP
tCCLK +4.5
0.25tCCLK +1
0.5tCCLK – 1+HI
tCKOP – 0.5tCCLK – 1
tCKOP – 0.25tCCLK +1.0
tCKOP – 0.25tCCLK – 8
0.25tCCLK – 3
–1.5
tCKOP – 0.5tCCLK – 2 +W
–1.5
–1.5
tCKOP – 0.5tCCLK –2+W
–1.5
0.5tCCLK – 2+HI
13
1
Unit
ns
ns
ns
ns
ns
0.25tCCLK +9
ns
ns
ns
tCKOP – 0.25tCCLK +9 ns
tCKOP – 0.25tCCLK +5 ns
0.25tCCLK +4
ns
+2
ns
ns
+2
ns
+2
ns
ns
+2
ns
ns
ns
ns
Only required for recognition in the current cycle.
Maximum throughput (@ 110 MHz) using DMARx/DMAGx handshaking equals tWDR + tDMARH = (tCCLK +4.5) + (tCCLK +4.5)=27 ns (37 MHz). This throughput limit applies
to non-synchronous access mode only.
3
tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can
be driven tDATDRH after DMARx is brought high.
4
Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH.
5
tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCKOP – 0.25tCCLK – 8 + (n × tCKOP) where
n equals the number of extra cycles that the access is prolonged.
6
See Example System Hold Time Calculation on Page 54 for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.
2
Rev. C |
Page 40 of 60 |
January 2013
ADSP-21161N
CLKIN
tDMARLL
tSDRC
tSDRC
tDMARH
tWDR
DMARx
tHDGC
tDDGL
tWDGL
tWDGH
DMAGx
TRANSFERS BETWEEN ADSP-21161N
INTERNAL MEMORY AND EXTERNAL DEVICE
tDATRDGH
tVDATDGH
DATA
(FROM ADSP-2116x TO EXTERNAL DRIVE)
tDATDRH
tHDATIDG
tSDATDGL
DATA
(FROM EXTERNAL DRIVE TO ADSP-21161N)
TRANSFERS BETWEEN EXTERNAL DEVICE AND
EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE)
tDGWRL
WR
tDGWRH
(EXTERNAL DEVICE TO EXTERNAL MEMORY)
tDGRDR
tDGRDL
RD
tDGWR
tDGWRR
(EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDRDGH
tDADGH
ADDRESS
MSx
1MEMORY
READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR23–0, RD, WR, MS3-0 AND ACK ALSO APPLY HERE.
Figure 25. DMA Handshake
Rev. C |
Page 41 of 60 |
January 2013
tDDGHA
ADSP-21161N
SDRAM Interface — Bus Master
Use these specifications for ADSP-21161N bus master accesses
of SDRAM:
Table 26. SDRAM Interface — Bus Master
Parameter
Min
Timing Requirements
tSDSDK
Data Setup Before SDCLK
tHDSDK
Data Hold After SDCLK
Switching Characteristics
First SDCLK Rise Delay After CLKIN1, 2
tDSDK1
tSDK
SDCLK Period
tSDKH
SDCLK Width High
tSDKL
SDCLK Width Low
tDCADSDK
Command, Address, Data, Delay After SDCLK3
tHCADSDK
Command, Address, Data, Hold After SDCLK3
Data Three-State After SDCLK4
tSDTRSDK
tSDENSDK
Data Enable After SDCLK5
tSDCTR
Command Three-State After CLKIN
tSDCEN
Command Enable After CLKIN
tSDSDKTR
SDCLK Three-State After CLKIN
tSDSDKEN
SDCLK Enable After CLKIN
Address Three-State After CLKIN
tSDATR
tSDAEN
Address Enable After CLKIN
100 MHz
Max
2.0
2.3
Min
110 MHz
Max
2.0
2.3
0.75tCCLK + 1.5
tCCLK
4
4
0.75tCCLK + 8.0
2  tCCLK
0.75tCCLK + 1.5
tCCLK
3
3
0.25tCCLK +2.5
2.0
ns
ns
0.75tCCLK + 8.0
2  tCCLK
0.25tCCLK +2.5
2.0
0.5tCCLK + 2.0
0.75tCCLK
0.5tCCLK –1.5
2
0
1
0.25 tCCLK5
0.4
0.5tCCLK + 6.0
5
3
4
0.25tCCLK
+7.2
0.5tCCLK + 2.0
0.75tCCLK
0.5tCCLK –1.5
2
0
1
0.25 tCCLK5
0.4
Unit
0.5tCCLK + 6.0
5
3
4
0.25tCCLK
+7.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the SDCKR
value and the core clock to CLKIN ratio.
2
Subtract tCCLK from result if value is greater than or equal to tCCLK.
3
Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.
4
SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.
5
Valid when DSP transitions to SDRAM master from SDRAM slave.
SDRAM Interface — Bus Slave
These timing requirements allow a bus slave to sample the bus
master’s SDRAM command and detect when a refresh occurs:
Table 27. SDRAM Interface — Bus Slave
Parameter
Timing Requirements
tSSDKC1
First SDCLK Rise after CLKOUT1, 2, 3
Command Setup before SDCLK4
tSCSDK
tHCSDK
Command Hold after SDCLK4
Min
Max
Unit
SDCK  tCCLK0.5tCCLK 0.5
2
1
SDCKR  tCCLK0.25tCCLK + 2.0
ns
ns
ns
1
For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the
SDCKR value and the Core clock to CLKOUT ratio.
SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.
3
Subtract tCCLK from result if value is greater than or equal to tCCLK.
4
Command = SDCKE, RAS, CAS, and SDWE.
2
Rev. C |
Page 42 of 60 |
January 2013
ADSP-21161N
CLKIN
tDSDK1
tSDKH
tSDK
SDCLK
tSDSDK
tSDKL
tHDSDK
DATA(IN)
tSDTRSDK
tDCADSDK
tSDENSDK
tHCADSDK
DATA(OUT)
CMND1ADDR
(OUT)
tDCADSDK
tHCADSDK
tSDCEN
tSDCTR
CMND1(OUT)
ADDR
(OUT)
tSDAEN
tSDATR
CLKIN
tSDSDKTR
tSDSDKEN
SDCLK
CLKOUT
tSSDKC1
SDCLK (IN)
tSCSDK
CMND2 (IN)
tHCSDK
1COMMAND
2COMMAND
= SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10.
= SDCKE, RAS, CAS, AND SDWE.
Figure 26. SDRAM Interface
Rev. C |
Page 43 of 60 |
January 2013
ADSP-21161N
tions made directly from speed specifications will result in
unrealistically small skew times because they include multiple
tester guardbands. The setup and hold skew times shown below
are calculated to include only one tester guardband.
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK,
(setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the
maximum delay that can be introduced in LCLK relative to
LDATA, (hold skew = tLCLKTWL min – tHLDCH – tHLDCL). Calcula-
ADSP-21161N Setup Skew = 1.5 ns max
ADSP-21161N Hold Skew = 1.5 ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Table 28. Link Ports — Receive
Parameter
Timing Requirements
tSLDCL
Data Setup Before LCLK Low
tHLDCL
Data Hold After LCLK Low
tLCLKIW
LCLK Period
tLCLKRWL
LCLK Width Low
LCLK Width High
tLCLKRWH
Switching Characteristics
tDLALC
LACK Low Delay After LCLK High1
1
Min
Max
1
3.5
tLCLK
4.0
4.0
ns
ns
ns
ns
ns
8
12
LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
RECEIVE
tLCLKIW
tLCLKRWH
tLCLKRWL
LCLK
tSLDCL
tHLDCL
IN
LDAT7-0
tDLALC
LACK (OUT)
Figure 27. Link Ports—Receive
Rev. C |
Page 44 of 60 |
January 2013
Unit
ns
ADSP-21161N
Table 29. Link Ports — Transmit
Parameter
Timing Requirements
tSLACH
LACK Setup Before LCLK High
LACK Hold After LCLK High
tHLACH
Switching Characteristics
tDLDCH
Data Delay After LCLK High
tHLDCH
Data Hold After LCLK High
tLCLKTWL
LCLK Width Low
tLCLKTWH
LCLK Width High
tDLACLK
LCLK Low Delay After LACK High
Min
Max
Unit
8
–2
ns
ns
3
0
0.5tLCLK–1.0
0.5tLCLK–1.0
0.5tLCLK+3
0.5tLCLK+1.0
0.5tLCLK+1.0
3tLCLK+11
TRANSMIT
tLCLKTWH
tLCLKTWL
LAST NIBBLE/BYTE
TRANSMITTED
FIRST NIBBLE/BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK
tDLDCH
tHLDCH
LDAT7-0
OUT
tSLACH
tHLACH
LACK (IN)
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
Figure 28. Link Ports—Transmit
Rev. C |
Page 45 of 60 |
January 2013
tDLACLK
ns
ns
ns
ns
ns
ADSP-21161N
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 30. Serial Ports — External Clock
Parameter
Timing Requirements
tSFSE
Transmit/Receive FS Setup Before Transmit/Receive SCLK1
tHFSE
Transmit/Receive FS Hold After Transmit/Receive SCLK1
Receive Data Setup Before Receive SCLK1
tSDRE
tHDRE
Receive Data Hold After Receive SCLK1
tSCLKW
SCLKx Width
tSCLK
SCLKx Period
1
Min
Max
Unit
3.5
2
1.5
4
7
2tCCLK
ns
ns
ns
ns
ns
ns
Referenced to sample edge.
Table 31. Serial Ports — Internal Clock
Parameter
Timing Requirements
tSFSI
FS Setup Time Before SCLK (Transmit/Receive Mode)1
tHFSI
FS Hold After SCLK (Transmit/Receive Mode)1
tSDRI
Receive Data Setup Before SCLK1
tHDRI
Receive Data Hold After SCLK1
1
Min
Max
Unit
8
0.5tCCLK+1
4
3
ns
ns
ns
ns
Referenced to sample edge.
Table 32. Serial Ports — External Clock
Parameter
Switching Characteristics
tDFSE
FS Delay After SCLK (Internally Generated FS) 1, 2, 3
tHOFSE
FS Hold After SCLK (Internally Generated FS)1, 2 , 3
Transmit Data Delay After SCLK 1, 2
tDDTE
tHDTE
Transmit Data Hold After SCLK 1, 2
Min
100 MHz
Max
Min
110 MHz
Max
13
3
13
2.75
16
0
16
0
Unit
ns
ns
ns
ns
1
Referenced to drive edge.
2
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
3
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
Table 33. Serial Ports — Internal Clock
Parameter
Switching Characteristics
tDFSI
FS Delay After SCLK (Internally Generated FS)1, 2, 3
tHOFSI
FS Hold After SCLK (Internally Generated FS)1, 2, 3
tDDTI
Transmit Data Delay After SCLK1, 2
tHDTI
Transmit Data Hold After SCLK1, 2
tSCLKIW
SCLK Width2
Min
4.5
ns
ns
ns
ns
ns
7.5
0
0.5tSCLK–2.5
Referenced to drive edge.
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
3
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
2
Page 46 of 60 |
Unit
–1.5
1
Rev. C |
Max
January 2013
0.5tSCLK+2
ADSP-21161N
Table 34. Serial Ports —– Enable and Three-State
Parameter
Switching Characteristics
tDDTEN
Data Enable from External Transmit SCLK1, 2
Data Disable from External Transmit SCLK1
tDDTTE
tDDTIN
Data Enable from Internal Transmit SCLK1
tDDTTI
Data Disable from Internal Transmit SCLK1
Min
Max
4
Unit
3
ns
ns
ns
ns
Max
Unit
13
ns
10
0
1
Referenced to drive edge.
2
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
Table 35. Serial Ports — External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit FS or External Receive FS with
MCE = 1, MFD = 01
tDDTENFS
Data Enable from Late FS or MCE = 1, MFD = 01
0.5
1
MCE = 1, Transmit FS enable and Transmit FS valid follow tDDTLFSE and tDDTENFS.
Rev. C |
Page 47 of 60 |
January 2013
ns
ADSP-21161N
DATA RECEIVE— INTERNAL CLOCK
DRIVE EDGE
DATA RECEIVE— EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
SCLK
SCLK
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
FS
tHOFSE
tSFSE
tHFSE
tSDRE
tHDRE
FS
tSDRI
tHDRI
DXA/DXB
DXA/DXB
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT — EXTERNAL CLOCK
DATA TRANSMIT — INTERNAL CLOCK
DRIVE EDGE
DRIVE EDGE
SAMPLE EDGE
SAMPLE EDGE
tSCLKIW
tSCLKW
SCLK
SCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
FS
tHOFSE
tSFSE
tHFSE
FS
tDDTI
tHDTI
tHDTE
DXA/DXB
tDDTE
DXA/DXB
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE
DRIVE EDGE
SCLK
SCLK (EXT)
tDDTEN
tDDTTE
DXA/DXB
DRIVE EDGE
DRIVE EDGE
SCLK (INT)
SCLK
tDDTIN
tDDTTI
DXA/DXB
Figure 29. Serial Ports
Rev. C |
Page 48 of 60 |
January 2013
ADSP-21161N
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
SCLK
tSFSE/I
tHOFSE/I
FS
tDDTE/I
tDDTENFS
DXA/DXB
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
DRIVE
SCLK
tSFSE/I
tHOFSE/I
FS
tDDTE/I
tDDTENFS
DXA/DXB
tHDTE/I
1ST BIT
2ND BIT
tDDTLFSE
Figure 30. Serial Ports — External Late Frame Sync
Rev. C |
Page 49 of 60 |
January 2013
ADSP-21161N
SPI Interface Specifications
Table 36. SPI Interface Protocol — Master Switching and Timing
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SPICLK Edge (Data Input Set-up Time)
tHSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
Switching Characteristics
tSPICLKM
Serial Clock Cycle
tSPICHM
Serial Clock High Period
Serial Clock Low Period
tSPICLM
tDDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tSDSCIM_0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 0
tSDSCIM_1
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 1
tHDSM
Last SPICLK Edge to FLAG3–0 High
tSPITDM
Sequential Transfer Delay
100 MHz
Max
Min
Min
tSPICHM
tSPICLM
tSPICLM
tSPICHM
0.5tCCLK+10
0.5tCCLK+1
ns
ns
8tCCLK
4tCCLK–4
4tCCLK–4
8tCCLK–4
4tCCLK–4
4tCCLK–4
0
5tCCLK
0
5tCCLK
ns
ns
ns
ns
ns
ns
3tCCLK
3tCCLK
ns
tCCLK–3
2tCCLK
tCCLK–3
2tCCLK
ns
ns
3
tSPICLKM
3
tHDSM
tSPIT DM
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t HDSPIDM
tD D S P I D M
MOSI
(OUTPUT)
MSB
LSB
tS S P I D M
CPHASE = 1
tSSPIDM
MSB
VALID
LSB
VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHASE = 0
MISO
(INPUT)
tH S P I D M
tHSPIDM
MISO
(INPUT)
tHDSPIDM
MSB
tSSPIDM
LSB
tHSPIDM
MSB
VALID
LSB
VALID
Figure 31. SPI Interface Protocol — Master Switching and Timing
Rev. C |
Unit
0.5tCCLK+10
0.5tCCLK+1
FLAG3-0
(OUTPUT)
tSDSCIM
110 MHz
Max
Page 50 of 60 |
January 2013
ADSP-21161N
Table 37. SPI Interface Protocol — Slave Switching and Timing
Parameter
Timing Requirements
tSPICLKS
Serial Clock Cycle
Serial Clock High Period
tSPICHS
tSPICLS
Serial Clock Low Period
tSDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
tHDS
Last SPICLK Edge to SPIDS Not Asserted
CPHASE = 0
tSSPIDS
Data Input Valid to SPICLK Edge (Data Input Set-up Time)
tHSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
tSDPPW
SPIDS Deassertion Pulsewidth (CPHASE = 0)
Switching Characteristics
tDSOE
SPIDS Assertion to Data Out Active
tDSDHI
SPIDS Deassertion to Data High Impedance
tDDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
tHDSPIDS1
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
tHDLSBS1
SPICLK Edge to Last Bit Out Not Valid
(Data Out Hold Time) for LSB
tDSOV2
SPIDS Assertion to Data Out Valid (CPHASE = 0)
1
2
Min
Page 51 of 60 |
Unit
8tCCLK
4tCCLK–4
4tCCLK–4
ns
ns
ns
3.5tCCLK+8
1.5tCCLK+8
ns
ns
0
0
tCCLK+1
tCCLK
ns
ns
ns
ns
2
1.5
0.5tCCLK+5.5
0.5tCCLK+5.5
0.75tCCLK+3
0.25tCCLK+3
0.5tSPICLK+4.5tCCLK
1.5tCCLK+7
When CPHASE = 0 and baud rate is greater than 1, tHDLSBS affects the length of the last bit transmitted.
Applies to the first deassertion of SPIDS only.
Rev. C |
Max
January 2013
ns
ns
ns
ns
ns
ns
ADSP-21161N
SPIDS
(INPUT)
tSPICHS
tSPICLS
tS P I C L K S
tHDS
SPICLK
(CP = 0)
(INPUT)
tSPICLS
tS D S C O
SPICLK
(CP = 1)
(INPUT)
tSPICHS
tDSD HI
tDDSPIDS
tDSOE
tS D P P W
tD D S P I D S
MISO
(OUTPUT)
t H D S P ID S
MSB
LSB
t H S P ID S
tSSPIDS
CPHASE = 1
tSSPIDS
MOSI
(INPUT)
MSB VALID
LSB VALID
tDSOV
MISO
(OUTPUT)
t H D S PI D S
LSB
MSB
CPHASE = 0
MOSI
(INPUT)
t H D LS B S
tDDSPIDS
tDSOE
t H S P ID S
tSSPIDS
MSB VALID
LSB VALID
Figure 32. SPI Interface Protocol — Slave Switching and Timing
Rev. C |
Page 52 of 60 |
January 2013
tDSDHI
ADSP-21161N
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
Parameter
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
tHTAP
TDI, TMS Hold After TCK High
tSSYS
System Inputs Setup Before TCK Low1
tHSYS
System Inputs Hold After TCK Low1
tTRSTW
TRST Pulsewidth
Switching Characteristics
tDTDO
TDO Delay from TCK Low
tDSYS
System Outputs Delay After TCK Low2
Min
Max
tCK
5
6
2
15
4tCK
Unit
ns
ns
ns
ns
ns
ns
13
30
1
ns
ns
System Inputs = DATA47–16, ADDR23–0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2–1, CLK_CFG1–0, CLKDBL, CS, HBR, SBTS, ID2–0, IRQ2–0, RESET,
BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6–1, PA, MS3–0, FLAG11–0.
2
System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7–0, LxCLK, LxACK, DATA47–16, SDWE, ACK, HBG, RAS, CAS, SDCLK1–0, SDCKE,
BRST, RD, WR, BR6–1, PA, MS3–0, ADDR23–0, FLAG11–0, DMAG2–1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 33. JTAG Test Access Port and Emulation
Rev. C |
Page 53 of 60 |
January 2013
tHSYS
ADSP-21161N
OUTPUT DRIVE CURRENTS
Figure 34 shows typical I-V characteristics for the output drivers of the ADSP-21161N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
VOH
(MEASURED)
80
60
VDDEXT = 3.47V, –40°C
VOL
(MEASURED)
50
VDDEXT = 3.3V, +25°C
40
LOAD (VDDEXT) CURRENT – mA
30
VDDEXT = 3.13V, +105°C
VOH (MEASURED) – ⌬V
VOH
2.0V (MEASURED)
VOL (MEASURED) + ⌬V
1.0V
tDECAY
OUTPUT STOPS DRIVING
20
10
VOL
(MEASURED)
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
0
–10
Figure 35. Output Enable/Disable
–20
–30
VDDEXT = 3.47V, –40°C
–40
Example System Hold Time Calculation
VDDEXT = 3.3V, +25°C
–50
–60
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose V
to be the difference between the ADSP-21161N’s output voltage
and the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. CL is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable
time (i.e., tDATRWH for the write cycle).
VDDEXT = 3.13V, +105°C
–80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SWEEP (VDDEXT) VOLTAGE – V
Figure 34. Typical Drive Currents
TEST CONDITIONS
The DSP is tested for output enable, disable, and hold time.
50⍀
TO
OUTPUT
PIN
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output has reached a specified high
or low trip point, as shown in the Output Enable/Disable diagram (Figure 35). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to start
driving.
Output Disable Time
Output pins are considered to be disabled when they stop driving, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, CL and
the load current, IL. This decay time can be approximated by the
following equation:
1.5V
30pF
Figure 36. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
INPUT
OR
OUTPUT
Figure 37. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
tDECAY = (CLV)/IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 35. The time tMEASURED is the interval from when the reference signal switches to when the output
voltage decays V from the measured output high or output low
voltage. tDECAY is calculated with test loads CL and IL, and with
V equal to 0.5 V.
Rev. C |
Page 54 of 60 |
1.5V
January 2013
1.5V
ADSP-21161N
Capacitive Loading
OUTPUT DELAY OR HOLD – ns
25
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 36 on Page 54). Figure 38 shows
graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output
disable delays; see Output Disable Time on Page 54.) The graphs
of Figure 38, Figure 39, and Figure 40 may not be linear outside
the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% – 80%, V = Min) vs.
Load Capacitance.
20
15
10
Y = 0.0835X - 2.42
5
NOMINAL
ENVIRONMENTAL CONDITIONS
–5
0
30
60
90
120
150
LOAD CAPACITANCE – pF
180
210
Figure 38. Typical Output Delay or Hold vs. Load Capacitance (at Max Case
Temperature)
16.0
RISE AND FALL TIMES – ns
(0.694V TO 2.77V, 20% TO 80%)
14.0
Y = 0.0743X + 1.5613
12.0
RISE TIME
10.0
The thermal characteristics in which the DSP is operating influence performance.
Thermal Characteristics
The ADSP-21161N is packaged in a 225-ball chip scale package
ball grid array (CSP_BGA). The ADSP-21161N is specified for a
case temperature (TCASE). To ensure that the TCASE data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. Use the center block of ground pins
(CSP_BGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) to provide
thermal pathways to the printed circuit board’s ground plane. A
heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.
8.0
FALL TIME
6.0
Y = 0.0414X + 2.0128
T
4.0
= T
AMB
+  PD  
CA

where:
2.0
0
0
CASE
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
• TCASE = Case temperature (measured on top surface
of package)
200
• TAMB = Ambient temperature °C
RISE AND FALL TIMES – ns
(0.694V TO 2.77V, 20% TO 80%)
Figure 39. Typical Output Rise/Fall Time (20% – 80%, VDDEXT = Max)
16.0
• PD = Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is shown
under Power Dissipation).
14.0
• CA = Value from Table 39.
Table 39. Airflow Over Package Versus CA
Y = 0.0773X + 1.4399
12.0
RISE TIME
10.0
Airflow (Linear Ft./Min.)
CA (°C/W)JC1
8.0
1
FALL TIME
6.0
= 6.8°C/W.
Y = 0.0417X + 1.8674
4.0
2.0
0
0
20
40
60
80
100 120 140
LOAD CAPACITANCE – pF
160
180
200
Figure 40. Typical Output Rise/Fall Time (20% – 80%, VDDEXT = Min)
Rev. C |
Page 55 of 60 |
January 2013
0
17.9
200
15.2
400
13.7
ADSP-21161N
225-BALL CSP_BGA BALL CONFIGURATIONS
Table 40. 225-Ball CSP_BGA Ball Assignments
Ball Name
NC
BMSTR
BMS
SPIDS
EBOOT
LBOOT
SCLK2
D3B
L0DAT4
L0ACK
L0DAT2
L1DAT6
L1CLK
L1DAT2
NC
FLAG10
RESET
FLAG8
D0A
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
L0DAT0
DATA39
DATA43
DATA41
IRQ2
ID1
ID2
ID0
VDDEXT
GND
GND
GND
GND
GND
VDDEXT
DATA26
DATA24
DATA25
DATA27
Ball Number
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
E13
E14
E15
J01
J02
J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13
J14
J15
Ball Name
TRST
TDI
RPBA
MOSI
FS0
SCLK1
D2B
D3A
L0DAT7
L0CLK
L0DAT1
L1DAT4
L1ACK
L1DAT0
RSTOUT1
FLAG5
FLAG7
FLAG9
FLAG6
VDDINT
GND
GND
GND
GND
GND
VDDINT
DATA37
DATA40
DATA38
DATA36
TIMEXP
ADDR22
ADDR20
ADDR23
VDDINT
GND
GND
GND
GND
GND
VDDINT
DATA22
DATA19
DATA21
DATA23
Ball Number
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
K13
K14
K15
Rev. C |
Ball Name
TMS
EMU
GND
SPICLK
D0B
D1A
D2A
FS2
FS3
L0DAT6
L1DAT7
L1DAT3
L1DAT1
DATA45
DATA47
FLAG1
FLAG2
FLAG4
FLAG3
VDDEXT
GND
GND
GND
GND
GND
VDDEXT
DATA34
DATA35
DATA33
DATA32
ADDR19
ADDR17
ADDR21
ADDR2
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
CAS
DATA20
DATA16
DATA18
Page 56 of 60 |
January 2013
Ball Number
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
G13
G14
G15
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
L13
L14
L15
Ball Name
TDO
TCK
FLAG11
MISO
SCLK0
D1B
FS1
VDDINT
SCLK3
L0DAT5
L0DAT3
L1DAT5
DATA42
DATA46
DATA44
FLAG0
IRQ0
VDDINT
IRQ1
VDDINT
GND
GND
GND
GND
GND
VDDINT
DATA29
DATA28
DATA30
DATA31
ADDR16
ADDR12
ADDR18
ADDR6
ADDR0
MS1
BR6
VDDEXT
WR
SDA10
RAS
ACK
DATA17
DMAG2
DMAG1
Ball Number
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
H13
H14
H15
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
M13
M14
M15
ADSP-21161N
Table 40. 225-Ball CSP_BGA Ball Assignments (Continued)
Ball Name
ADDR14
ADDR15
ADDR10
ADDR5
ADDR1
MS0
BR5
BR2
BRST
SDCKE
CS
CLK_CFG1
CLK_CFG0
AVDD
DMAR1
1
Ball Number
N01
N02
N03
N04
N05
N06
N07
N08
N09
N10
N11
N12
N13
N14
N15
Ball Name
ADDR13
ADDR9
ADDR8
ADDR4
MS2
SBTS
BR4
BR1
SDCLK1
SDCLK0
REDY
CLKIN
DQM
AGND
DMAR2
Ball Number
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
Ball Name
NC
ADDR11
ADDR7
ADDR3
MS3
PA
BR3
RD
CLKOUT
HBR
HBG
CLKDBL
XTAL
SDWE
NC
Ball Number
R01
R02
R03
R04
R05
R06
R07
R08
R09
R10
R11
R12
R13
R14
R15
RSTOUT exists only for silicon revisions 1.2 and greater. Leave this ball unconnected for silicon revisions 0.3, 1.0, and 1.1.
14
15
12
13
10
11
8
9
6
7
4
5
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
KEY:
VDDINT
GND*
AVDD
VDDEXT
AGND
SIGNAL
* USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL
PATHWAYS TO YOUR PRINTED CIRCUIT BOARD GROUND PLANE
Figure 41. 225-Ball CSP_BGA Ball Assignments (Bottom View, Summary)
Rev. C |
Page 57 of 60 |
January 2013
Ball Name
Ball Number
ADSP-21161N
OUTLINE DIMENSIONS
The ADSP-21161N comes in a 17 mm  17 mm, 225-ball
CSP_BGA package with 15 rows of balls.
A1 BALL
CORNER
17.20
17.00 SQ
16.80
A1 BALL
CORNER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
14.00
BSC SQ
D
E
F
G
H
1.00
BSC
J
K
L
M
N
P
R
0.50
REF
TOP VIEW
*1.85
1.71
1.40
DETAIL A
0.54
0.50
0.30
SEATING
PLANE
BOTTOM VIEW
*1.31
1.21
1.10
DETAIL A
0.70
0.60
0.50
BALL DIAMETER
COPLANARITY
0.20
*COMPLIANT TO JEDEC STANDARDS MO-192-AAF-2
WITH THE EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 42. 225-Ball CSP_BGA (BC-225-1)
SURFACE-MOUNT DESIGN
Table 41 is provided as an aid to PCB design. For industry standard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 41. BGA Data for Use with Surface-Mount Design
Package
225-Ball CSP_BGA (BC-225-1)
Ball Attach Type
Solder Mask Defined
Solder Mask Opening
0.40 mm diameter
Ball Pad Size
0.53 mm diameter
ORDERING GUIDE
Model1
ADSP-21161NKCA-100
ADSP-21161NCCA-100
ADSP-21161NKCAZ100
ADSP-21161NCCAZ100
ADSP-21161NYCAZ110
1
2
Temperature Range2
0C to 85C
–40C to +105C
0C to 85C
–40C to +105C
–40C to +125C
Instruction Rate
100 MHz
100 MHz
100 MHz
100 MHz
110 MHz
Z = RoHS Compliant Part.
Referenced temperature is case temperature.
Rev. C |
Page 58 of 60 |
January 2013
On-Chip
SRAM
1M bit
1M bit
1M bit
1M bit
1M bit
Package
Description
225-Ball CSP_BGA
225-Ball CSP_BGA
225-Ball CSP_BGA
225-Ball CSP_BGA
225-Ball CSP_BGA
Package
Option
BC-225-1
BC-225-1
BC-225-1
BC-225-1
BC-225-1
ADSP-21161N
Rev. C |
Page 59 of 60 |
January 2013
ADSP-21161N
© 2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02935-0-1/13 (C)
Rev. C |
Page 60 of 60 |
January 2013