AD ADXL343

Preliminary Technical Data
3-Axis, ±2 g/±4 g/±8 g/±16 g
Digital MEMS Accelerometer
ADXL343
FEATURES
GENERAL DESCRIPTION
Multipurpose accelerometer with 10- to 13-bit resolution for
use in a wide variety of applications
Digital output accessible via SPI (3- and 4-wire) and I2C
Built-in motion detection features make tap, double-tap,
activity, inactivity, and free-fall detection trivial
User-adjustable thresholds
Interrupts independently mappable to two interrupt pins
Low power operation down to 23 µA and embedded FIFO for
reducing overall system power
Wide supply voltage range: 2.0 V to 3.6 V
I/O voltage 1.7 V to VS
Wide operating temperature range (−40°C to +85°C)
10,000 g shock survival
Small, thin, Pb free, RoHS compliant 3 mm × 5 mm × 1 mm
LGA package
The ADXL343 is a versatile 3-axis, digital-output, low g MEMS
accelerometer. Selectable measurement range and bandwidth, and
configurable, built-in motion detection make it suitable for sensing
acceleration in a wide variety of applications. Robustness to
10,000 g of shock and a wide temperature range (−40°C to +85°C)
enable use of the accelerometer even in harsh environments.
The ADXL343 measures acceleration with high resolution (13-bit)
measurement at up to ±16 g. Digital output data is formatted as
16-bit twos complement and is accessible through either an SPI
(3- or 4-wire) or I2C digital interface. The ADXL343 can
measure the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion
or shock. Its high resolution (3.9 mg/LSB) enables measurement
of inclination changes less than 1.0°.
Several special sensing functions are provided. Activity and
inactivity sensing detect the presence or lack of motion. Tap
sensing detects single and double taps in any direction. Free-fall
sensing detects if the device is falling. These functions can be
mapped individually to either of two interrupt output pins.
APPLICATIONS
Handsets
Gaming and pointing devices
Hard disk drive (HDD) protection
An integrated memory management system with a 32-level first in,
first out (FIFO) buffer can be used to store data to minimize host
processor activity and lower overall system power consumption.
The ADXL343 is supplied in a small, thin, 3 mm × 5 mm × 1 mm,
14-terminal, plastic package.
FUNCTIONAL BLOCK DIAGRAM
VS
ADXL343
VDD I/O
POWER
MANAGEMENT
ADC
3-AXIS
SENSOR
DIGITAL
FILTER
32 LEVEL
FIFO
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
SDA/SDI/SDIO
SERIAL I/O
SDO/ALT
ADDRESS
SCL/SCLK
CS
GND
10627-001
SENSE
ELECTRONICS
Figure 1.
Rev. PrA
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
ADXL343
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1 Self-Test ....................................................................................... 20 Applications ....................................................................................... 1 Register Map ................................................................................... 21 General Description ......................................................................... 1 Register Definitions ................................................................... 22 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 26 Specifications..................................................................................... 3 Power Supply Decoupling ......................................................... 26 Absolute Maximum Ratings............................................................ 5 Mechanical Considerations for Mounting .............................. 26 Thermal Resistance ...................................................................... 5 Tap Detection .............................................................................. 26 Package Information .................................................................... 5 Threshold .................................................................................... 27 ESD Caution .................................................................................. 5 Link Mode ................................................................................... 27 Pin Configuration and Function Descriptions ............................. 6 Sleep Mode vs. Low Power Mode............................................. 28 Typical Performance Characteristics ............................................. 7 Offset Calibration ....................................................................... 28 Theory of Operation ...................................................................... 11 Using Self-Test ............................................................................ 29 Power Sequencing ...................................................................... 11 Data Formatting of Upper Data Rates ..................................... 30 Power Savings ............................................................................. 12 Noise Performance ..................................................................... 31 Serial Communications ................................................................. 13 Operation at Voltages Other Than 2.5 V ................................ 31 SPI ................................................................................................. 13 Offset Performance at Lowest Data Rates ............................... 32 I2C ................................................................................................. 16 Axes of Acceleration Sensitivity ............................................... 33 Interrupts ..................................................................................... 18 Layout and Design Recommendations ................................... 34 FIFO ............................................................................................. 19 Outline Dimensions ....................................................................... 35 Rev. PrA | Page 2 of 36
Preliminary Technical Data
ADXL343
SPECIFICATIONS
TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unless
otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter
SENSOR INPUT
Measurement Range
Nonlinearity
Inter-Axis Alignment Error
Cross-Axis Sensitivity 2
OUTPUT RESOLUTION
All g Ranges
±2 g Range
±4 g Range
±8 g Range
±16 g Range
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT
Sensitivity Deviation from Ideal
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity Change Due to Temperature
0 g OFFSET
0 g Output Deviation from Ideal, X-, Y-, Z-Axes
0 g Offset vs. Temperature for X-, Y-, Z-Axes
NOISE
X-, Y-, Z-Axes
OUTPUT DATA RATE AND BANDWIDTH
Output Data Rate (ODR) 3, 4, 5
SELF-TEST 6
Output Change in X-Axis
Output Change in Y-Axis
Output Change in Z-Axis
POWER SUPPLY
Operating Voltage Range (VS)
Interface Voltage Range (VDD I/O)
Supply Current
Standby Mode Leakage Current
Turn-On and Wake-Up Time 7
Test Conditions/Comments
Each axis
User selectable
Percentage of full scale
Min
Each axis
10-bit resolution
Full resolution
Full resolution
Full resolution
Full resolution
Each axis
All g ranges, full resolution
±2 g, 10-bit resolution
±4 g, 10-bit resolution
±8 g, 10-bit resolution
±16 g, 10-bit resolution
All g ranges
All g ranges, full resolution
±2 g, 10-bit resolution
±4 g, 10-bit resolution
±8 g, 10-bit resolution
±16 g, 10-bit resolution
Typ 1
Max
Unit
±2, ±4, ±8, ±16
±0.5
±0.1
±1
g
%
Degrees
%
10
10
11
12
13
Bits
Bits
Bits
Bits
Bits
256
256
128
64
32
±1.0
3.9
3.9
7.8
15.6
31.2
±0.01
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
%
mg/LSB
mg/LSB
mg/LSB
mg/LSB
mg/LSB
%/°C
±35
±0.8
mg
mg/°C
1.1
LSB rms
Each axis
ODR = 100 Hz for ±2 g, 10-bit resolution
or all g-ranges, full resolution
User selectable
0.1
3200
Hz
0.20
−2.10
0.30
2.10
−0.20
3.40
g
g
g
3.6
VS
V
V
µA
µA
µA
ms
2.0
1.7
ODR ≥ 100 Hz
ODR < 10 Hz
ODR = 3200 Hz
Rev. PrA | Page 3 of 36
2.5
1.8
140
30
0.1
1.4
ADXL343
Parameter
TEMPERATURE
Operating Temperature Range
WEIGHT
Device Weight
Preliminary Technical Data
Test Conditions/Comments
Min
Typ 1
−40
30
1
Max
Unit
+85
°C
mg
The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean ±1 σ, except for 0 g output and sensitivity,
which represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean ±1 σ.
Cross-axis sensitivity is defined as coupling between any two axes.
3
Bandwidth is the −3 dB frequency and is half the output data rate, bandwidth = ODR/2.
4
The output format for the 3200 Hz and 1600 Hz ODRs is different than the output format for the remaining ODRs. This difference is described in the Data Formatting of
Upper Data Rates section.
5
Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at
Lowest Data Rates section for details.
6
Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit =
0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). The part must be in normal power
operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly.
7
Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For
other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).
2
Rev. PrA | Page 4 of 36
Preliminary Technical Data
ADXL343
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Table 2.
All Other Pins
Output Short-Circuit Duration
(Any Pin to Ground)
Temperature Range
Powered
Storage
Rating
The information in Figure 2 and Table 4 provide details about
the package branding for the ADXL343.
10,000 g
10,000 g
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to VDD I/O + 0.3 V or 3.9 V,
whichever is less
−0.3 V to +3.9 V
Indefinite
−40°C to +105°C
−40°C to +105°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 3. Package Characteristics
Package Type
14-Terminal LGA
θJA
150°C/W
343B
#yww
v v v v
CNTY
θJC
85°C/W
Device Weight
30 mg
10627-102
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VS
VDD I/O
Digital Pins
Figure 2. Product Information on Package (Top View)
Table 4. Package Branding Information
Branding Key
343B
#
yww
vvvv
CNTY
ESD CAUTION
Rev. PrA | Page 5 of 36
Field Description
Part identifier for the ADXL343
RoHS-compliant designation
Date code
Factory lot code
Country of origin
ADXL343
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADXL343
TOP VIEW
(Not to Scale)
SCL/SCLK
VDD I/O
1
GND
2
RESERVED
3
14
13
SDA/SDI/SDIO
12
SDO/ALT ADDRESS
11
RESERVED
10
NC
9
INT2
8
INT1
+x
4
GND
5
VS
6
+y
+z
7
CS
NOTES
1. NC = NO INTERNAL CONNECTION.
10627-002
GND
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
VDD I/O
GND
RESERVED
GND
GND
VS
CS
INT1
INT2
NC
RESERVED
SDO/ALT ADDRESS
SDA/SDI/SDIO
SCL/SCLK
Description
Digital Interface Supply Voltage.
This pin must be connected to ground.
Reserved. This pin must be connected to VS or left open.
This pin must be connected to ground.
This pin must be connected to ground.
Supply Voltage.
Chip Select.
Interrupt 1 Output.
Interrupt 2 Output.
Not Internally Connected.
Reserved. This pin must be connected to ground or left open.
Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C).
Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).
Serial Communications Clock. SCL is the clock for I2C, and SCLK is the clock for SPI.
Rev. PrA | Page 6 of 36
Preliminary Technical Data
ADXL343
TYPICAL PERFORMANCE CHARACTERISTICS
20
150
N = 16
AVDD = DVDD = 2.5V
100
16
14
50
OUTPUT (mg)
PERCENT OF POPULATION (%)
18
12
10
8
0
–50
6
4
–100
–100
–50
0
50
ZERO g OFFSET (mg)
100
150
–150
–40
10627-206
0
–150
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 4. Zero g Offset at 25°C, VS = 2.5 V, All Axes
Figure 7. X-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
20
150
N = 16
AVDD = DVDD = 2.5V
18
100
16
14
50
OUTPUT (mg)
PERCENT OF POPULATION (%)
–20
10627-213
2
12
10
8
0
–50
6
4
–100
–100
–50
0
50
ZERO g OFFSET (mg)
100
150
–150
–40
10627-209
0
–150
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 5. Zero g Offset at 25°C, VS = 3.3 V, All Axes
10627-214
2
Figure 8. Y-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
30
150
100
20
50
15
0
10
–50
5
–100
0
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
2.0
–150
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 6. Zero g Offset Temperature Coefficient, VS = 2.5 V, All Axes
Figure 9. Z-Axis Zero g Offset vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V
Rev. PrA | Page 7 of 36
100
10627-215
OUTPUT (mg)
25
10627-210
PERCENT OF POPULATION (%)
N = 16
AVDD = DVDD = 2.5V
Preliminary Technical Data
55
280
50
275
45
270
35
30
25
20
15
265
260
255
250
245
10
240
5
235
0
230 234 238 242 246 250 254 258 262 266 270 274 278 282
SENSITIVITY (LSB/g)
230
–40
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. Sensitivity at 25°C, VS = 2.5 V, Full Resolution, All Axes
Figure 13. X-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution
40
280
275
35
270
30
SENSITIVITY (LSB/g)
25
20
15
265
260
255
250
245
10
240
5
235
–0.01
0
0.01
0.02
SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)
230
–40
10627-219
0
–0.02
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. Sensitivity Temperature Coefficient, VS = 2.5 V, All Axes
10627-223
PERCENT OF POPULATION (%)
–20
10627-222
SENSITIVITY (LSB/g)
40
10627-218
PERCENT OF POPULATION (%)
ADXL343
Figure 14. Y-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution
25
280
270
SENSITIVITY (LSB/g)
PERCENT OF POPULATION (%)
275
20
15
10
5
265
260
255
250
245
240
110
120
130
140
150
160
170
CURRENT CONSUMPTION (µA)
180
190
200
Figure 12. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V
Rev. PrA | Page 8 of 36
230
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 15. Z-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution
120
10627-224
100
10627-231
235
0
Preliminary Technical Data
ADXL343
60
280
PERCENT OF POPULATION (%)
275
SENSITIVITY (LSB/g)
270
265
260
255
250
245
240
50
40
30
20
10
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
10627-225
230
–40
0.2
0.5
0.8
1.1
1.4
1.7
2.0
SELF-TEST RESPONSE (g)
10627-228
235
Figure 19. X-Axis Self-Test Response at 25°C, VS = 2.5 V
Figure 16. X-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution
60
280
PERCENT OF POPULATION (%)
275
SENSITIVITY (LSB/g)
270
265
260
255
250
245
240
50
40
30
20
10
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
10627-226
230
–40
–0.2
–0.5
–0.8
–1.1
–1.4
–1.7
–2.0
SELF-TEST RESPONSE (g)
Figure 17. Y-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution
10627-229
235
Figure 20. Y-Axis Self-Test Response at 25°C, VS = 2.5 V
280
60
PERCENT OF POPULATION (%)
275
265
260
255
250
245
240
50
40
30
20
10
230
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
0
0.3
0.9
1.5
2.1
2.7
SELF-TEST RESPONSE (g)
3.3
Figure 21. Z-Axis Self-Test Response at 25°C, VS = 2.5 V
Figure 18. Z-Axis Sensitivity vs. Temperature—
Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution
Rev. PrA | Page 9 of 36
10627-230
235
10627-227
SENSITIVITY (LSB/g)
270
ADXL343
Preliminary Technical Data
160
200
120
SUPPLY CURRENT (µA)
CURRENT CONSUMPTION (µA)
140
100
80
60
40
150
100
50
1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200
OUTPUT DATA RATE (Hz)
Figure 22. Current Consumption vs. Output Data Rate at 25°C—10 Parts,
VS = 2.5 V
Rev. PrA | Page 10 of 36
0
2.0
2.4
2.8
3.2
SUPPLY VOLTAGE (V)
Figure 23. Supply Current vs. Supply Voltage, VS at 25°C
3.6
10627-233
0
10627-232
20
Preliminary Technical Data
ADXL343
THEORY OF OPERATION
The ADXL343 is a complete 3-axis acceleration measurement
system with a selectable measurement range of ±2 g, ±4 g, ±8 g,
or ±16 g. It measures both dynamic acceleration resulting from
motion or shock and static acceleration, such as gravity, that
allows the device to be used as a tilt sensor.
The sensor is a polysilicon surface-micromachined structure
built on top of a silicon wafer. Polysilicon springs suspend the
structure over the surface of the wafer and provide a resistance
against forces due to applied acceleration.
Deflection of the structure is measured using differential capacitors
that consist of independent fixed plates and plates attached to the
moving mass. Acceleration deflects the proof mass and unbalances
the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation
is used to determine the magnitude and polarity of the acceleration.
POWER SEQUENCING
Power can be applied to VS or VDD I/O in any sequence without
damaging the ADXL343. All possible power-on modes are
summarized in Table 6. The interface voltage level is set with
the interface supply voltage, VDD I/O, which must be present to
ensure that the ADXL343 does not create a conflict on the
communication bus. For single-supply operation, VDD I/O can be
the same as the main supply, VS. In a dual-supply application,
however, VDD I/O can differ from VS to accommodate the desired
interface voltage, as long as VS is greater than or equal to VDD I/O.
After VS is applied, the device enters standby mode, where power
consumption is minimized and the device waits for VDD I/O to be
applied and for the command to enter measurement mode to be
received. (This command can be initiated by setting the measure
bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In
addition, while the device is in standby mode, any register can be
written to or read from to configure the part. It is recommended
to configure the device in standby mode and then to enable
measurement mode. Clearing the measure bit returns the
device to the standby mode.
Table 6. Power Sequencing
Condition
Power Off
Bus Disabled
VS
Off
On
VDD I/O
Off
Off
Bus Enabled
Standby or Measurement
Off
On
On
On
Description
The device is completely off, but there is a potential for a communication bus conflict.
The device is on in standby mode, but communication is unavailable and creates a conflict on
the communication bus. The duration of this state should be minimized during power-up to
prevent a conflict.
No functions are available, but the device does not create a conflict on the communication bus.
At power-up, the device is in standby mode, awaiting a command to enter measurement
mode, and all sensor functions are off. After the device is instructed to enter measurement
mode, all sensor functions are available.
Rev. PrA | Page 11 of 36
ADXL343
Preliminary Technical Data
POWER SAVINGS
Table 8. Typical Current Consumption vs. Data Rate,
Low Power Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Power Modes
The ADXL343 automatically modulates its power consumption
in proportion to its output data rate, as outlined in Table 7. If
additional power savings is desired, a lower power mode is
available. In this mode, the internal sampling rate is reduced,
allowing for power savings in the 12.5 Hz to 400 Hz data rate
range at the expense of slightly greater noise. To enter low power
mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register
(Address 0x2C). The current consumption in low power mode
is shown in Table 8 for cases where there is an advantage to
using low power mode. Use of low power mode for a data rate
not shown in Table 8 does not provide any advantage over the same
data rate in normal power mode. Therefore, it is recommended
that only data rates shown in Table 8 are used in low power mode.
The current consumption values shown in Table 7 and Table 8
are for a VS of 2.5 V.
Table 7. Typical Current Consumption vs. Data Rate
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Output Data
Rate (Hz)
3200
1600
800
400
200
100
50
25
12.5
6.25
3.13
1.56
0.78
0.39
0.20
0.10
Bandwidth (Hz)
1600
800
400
200
100
50
25
12.5
6.25
3.13
1.56
0.78
0.39
0.20
0.10
0.05
Rate Code
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
IDD (µA)
140
90
140
140
140
140
90
60
50
45
40
34
23
23
23
23
Output Data
Rate (Hz)
400
200
100
50
25
12.5
Bandwidth (Hz)
200
100
50
25
12.5
6.25
Rate Code
1100
1011
1010
1001
1000
0111
IDD (µA)
90
60
50
45
40
34
Auto Sleep Mode
Additional power can be saved if theADXL343 automatically
switches to sleep mode during periods of inactivity. To enable
this feature, set the THRESH_INACT register (Address 0x25)
and the TIME_INACT register (Address 0x26) each to a value
that signifies inactivity (the appropriate value depends on the
application), and then set the AUTO_SLEEP bit (Bit D4) and the
link bit (Bit D5) in the POWER_CTL register (Address 0x2D).
Current consumption at the sub-12.5 Hz data rates that are
used in this mode is typically 23 µA for a VS of 2.5 V.
Standby Mode
For even lower power operation, standby mode can be used. In
standby mode, current consumption is reduced to 0.1 µA (typical).
In this mode, no measurements are made. Standby mode is
entered by clearing the measure bit (Bit D3) in the POWER_CTL
register (Address 0x2D). Placing the device into standby mode
preserves the contents of FIFO.
Rev. PrA | Page 12 of 36
Preliminary Technical Data
ADXL343
SERIAL COMMUNICATIONS
SPI
For SPI, either 3- or 4-wire configuration is possible, as shown in
the connection diagrams in Figure 24 and Figure 25. Clearing the
SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31)
selects 4-wire mode, whereas setting the SPI bit selects 3-wire
mode. The maximum SPI clock speed is 5 MHz with 100 pF
maximum loading, and the timing scheme follows clock polarity
(CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to
the ADXL343 before the clock polarity and phase of the host
processor are configured, the CS pin should be brought high
before changing the clock polarity and phase. When using 3-wire
SPI, it is recommended that the SDO pin be either pulled up to
VDD I/O or pulled down to GND via a 10 kΩ resistor.
CS
PROCESSOR
CS
SDIO
MOSI
SDO
MISO
SCLK
SCLK
10627-004
ADXL343
Figure 24. 3-Wire SPI Connection Diagram
PROCESSOR
CS
CS
SDI
MOSI
SDO
MISO
SCLK
SCLK
10627-003
ADXL343
Figure 25. 4-Wire SPI Connection Diagram
CS is the serial port enable line and is controlled by the SPI
master. This line must go low at the start of a transmission and
high at the end of a transmission, as shown in Figure 27. SCLK
is the serial port clock and is supplied by the SPI master. SCLK
should idle high during a period of no transmission. SDI and
SDO are the serial data input and output, respectively. Data is
updated on the falling edge of SCLK and should be sampled on
the rising edge of SCLK.
To read or write multiple bytes in a single transmission, the
multiple-byte bit, located after the R/W bit in the first byte transfer
(MB in Figure 27 to Figure 29), must be set. After the register
addressing and the first byte of data, each subsequent set of
clock pulses (eight clock pulses) causes the ADXL343 to point
to the next register for a read or write. This shifting continues
until the clock pulses cease and CS is deasserted. To perform reads or
writes on different, nonsequential registers, CS must be deasserted
between transmissions and the new register must be addressed
separately.
The timing diagram for 3-wire SPI reads or writes is shown
in Figure 29. The 4-wire equivalents for SPI writes and reads
are shown in Figure 27 and Figure 28, respectively. For correct
operation of the part, the logic thresholds and timing parameters
in Table 9 and Table 10 must be met at all times.
Use of the 3200 Hz and 1600 Hz output data rates is only
recommended with SPI communication rates greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only for communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate
above the recommended maximum may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
Preventing Bus Traffic Errors
The ADXL343 CS pin is used both for initiating SPI transactions and for enabling I2C mode. When the ADXL343 is used on
a SPI bus with multiple devices, its CS pin is held high while the
master communicates with the other devices. There may be
conditions where a SPI command transmitted to another device
looks like a valid I2C command. In this case, the ADXL343
interprets this as an attempt to communicate in I2C mode, and
may interfere with other bus traffic. Unless bus traffic can be
adequately controlled to assure such a condition never occurs,
it is recommended to add a logic gate in front of the SDI pin
as shown in Figure 26. This OR gate holds the SDA line high
when CS is high to prevent SPI bus traffic at the ADXL343
from appearing as an I2C start command. Note that this
recommendation applies only in cases where the ADXL343
is used on a SPI bus with multiple devices.
ADXL343
CS
PROCESSOR
CS
SDIO
MOSI
SDO
MISO
SCLK
SCLK
10627-104
I2C and SPI digital communications are available. In both cases,
the ADXL343 operates as a slave. I2C mode is enabled if the CS
pin is tied high to VDD I/O. The CS pin should always be tied high
to VDD I/O or be driven by an external controller because there is
no default mode if the CS pin is left unconnected. Therefore, not
taking these precautions may result in an inability to communicate
with the part. In SPI mode, the CS pin is controlled by the bus
master. In both SPI and I2C modes of operation, data transmitted
from the ADXL343 to the master device should be ignored
during writes to the ADXL343.
Figure 26. Recommended SPI Connection Diagram when Using Multiple SPI
Devices on a Single Bus
Rev. PrA | Page 13 of 36
ADXL343
Preliminary Technical Data
CS
tM
tSCLK
tDELAY
tS
tQUIET
tCS,DIS
SCLK
tHOLD
W
SDI
MB
A5
tSDO
X
SDO
A0
D7
ADDRESS BITS
X
D0
tDIS
DATA BITS
X
X
X
10627-017
tSETUP
X
Figure 27. SPI 4-Wire Write
CS
tM
tSCLK
tDELAY
tS
tCS,DIS
tQUIET
SCLK
tHOLD
R
SDI
MB
tSDO
X
SDO
X
X
A0
A5
tDIS
ADDRESS BITS
X
X
X
D0
D7
10627-018
tSETUP
DATA BITS
Figure 28. SPI 4-Wire Read
CS
tDELAY
tM
tSCLK
tS
tQUIET
tCS,DIS
SCLK
tSETUP
SDIO
tSDO
tHOLD
R/W
MB
A5
A0
ADDRESS BITS
D7
D0
DATA BITS
10627-019
SDO
NOTES
1. tSDO IS ONLY PRESENT DURING READS.
Figure 29. SPI 3-Wire Read/Write
Rev. PrA | Page 14 of 36
Preliminary Technical Data
ADXL343
Table 9. SPI Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
Pin Capacitance
1
Test Conditions
Min
Limit 1
Max
0.3 × VDD I/O
0.7 × VDD I/O
VIN = VDD I/O
VIN = 0 V
IOL = 10 mA
IOH = −4 mA
VOL = VOL, max
VOH = VOH, min
fIN = 1 MHz, VIN = 2.5 V
0.1
−0.1
0.2 × VDD I/O
0.8 × VDD I/O
10
−4
8
Limits based on characterization results, not production tested.
Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) 1
Parameter
fSCLK
tSCLK
tDELAY
tQUIET
tDIS
tCS,DIS
tS
tM
tSETUP
tHOLD
tSDO
tR 4
tF4
Min
Limit 2, 3
Max
5
200
5
5
10
150
0.3 × tSCLK
0.3 × tSCLK
5
5
40
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
SPI clock frequency
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
CS falling edge to SCLK falling edge
SCLK rising edge to CS rising edge
CS rising edge to SDO disabled
CS deassertion between SPI communications
SCLK low pulse width (space)
SCLK high pulse width (mark)
SDI valid before SCLK rising edge
SDI valid after SCLK rising edge
SCLK falling edge to SDO/SDIO output transition
SDO/SDIO output high to output low transition
SDO/SDIO output low to output high transition
The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3
The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
4
Output rise and fall times measured with capacitive load of 150 pF.
1
2
Rev. PrA | Page 15 of 36
Unit
V
V
µA
µA
V
V
mA
mA
pF
ADXL343
Preliminary Technical Data
I2C
Due to communication speed limitations, the maximum output
data rate when using 400 kHz I2C is 800 Hz and scales linearly
with a change in the I2C communication speed. For example,
using I2C at 100 kHz limits the maximum ODR to 200 Hz.
Operation at an output data rate above the recommended maximum may result in undesirable effect on the acceleration data,
including missing samples or additional noise.
With CS tied high to VDD I/O, the ADXL343 is in I2C mode,
requiring a simple 2-wire connection, as shown in Figure 30.
The ADXL343 conforms to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, available from NXP
Semiconductor. It supports standard (100 kHz) and fast (400 kHz)
data transfer modes if the bus parameters given in Table 11
and Table 12 are met. Single- or multiple-byte reads/writes are
supported, as shown in Figure 31. With the ALT ADDRESS pin
high, the 7-bit I2C address for the device is 0x1D, followed by
the R/W bit. This translates to 0x3A for a write and 0x3B for a
read. An alternate I2C address of 0x53 (followed by the R/W bit)
can be chosen by grounding the ALT ADDRESS pin (Pin 12).
This translates to 0xA6 for a write and 0xA7 for a read.
VDD I/O
ADXL343
RP
RP
PROCESSOR
CS
SDA
D IN/OUT
ALT ADDRESS
SCL
10627-008
There are no internal pull-up or pull-down resistors for any
unused pins; therefore, there is no known state or default state
for the CS or ALT ADDRESS pin if left floating or unconnected.
It is required that the CS pin be connected to VDD I/O and that
the ALT ADDRESS pin be connected to either VDD I/O or GND
when using I2C.
D OUT
Figure 30. I2C Connection Diagram (Address 0x53)
If other devices are connected to the same I2C bus, the nominal
operating voltage level of these other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary for
proper I2C operation. Refer to the UM10204 I2C-Bus Specification
and User Manual, Rev. 03—19 June 2007, when selecting pull-up
resistor values to ensure proper operation.
Table 11. I2C Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
Test Conditions
Min
Unit
0.3 × VDD I/O
V
V
µA
µA
0.7 × VDD I/O
VIN = VDD I/O
VIN = 0 V
0.1
−0.1
VDD I/O < 2 V, IOL = 3 mA
VDD I/O ≥ 2 V, IOL = 3 mA
VOL = VOL, max
fIN = 1 MHz, VIN = 2.5 V
Low Level Output Current (IOL)
Pin Capacitance
0.2 × VDD I/O
400
V
mV
mA
pF
3
8
Limits based on characterization results; not production tested.
SINGLE-BYTE WRITE
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
DATA
REGISTER ADDRESS
ACK
ACK
STOP
ACK
MULTIPLE-BYTE WRITE
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
DATA
REGISTER ADDRESS
ACK
ACK
DATA
STOP
ACK
ACK
SINGLE-BYTE READ
MASTER START
SLAVE ADDRESS + WRITE
SLAVE
START1
REGISTER ADDRESS
ACK
SLAVE ADDRESS + READ
ACK
NACK
ACK
DATA
ACK
DATA
STOP
MULTIPLE-BYTE READ
MASTER START
SLAVE
1THIS
SLAVE ADDRESS + WRITE
START1
REGISTER ADDRESS
ACK
ACK
SLAVE ADDRESS + READ
ACK
START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.
NOTES
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
Figure 31. I2C Device Addressing
Rev. PrA | Page 16 of 36
NACK
STOP
DATA
10627-033
1
Limit 1
Max
Preliminary Technical Data
ADXL343
Table 12. I2C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Parameter
fSCL
t1
t2
t3
t4
t5
t6 3, 4, 5, 6
t7
t8
t9
t10
Limit 1, 2
Max
400
Min
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
Unit
kHz
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
pF
0.9
300
0
t11
300
250
400
Cb
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus-free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving
tR, rise time of both SCL and SDA when receiving or transmitting
tF, fall time of SDA when receiving
tF, fall time of both SCL and SDA when transmitting
Capacitive load for each bus line
1
Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
All values referred to the VIH and the VIL levels given in Table 11.
3
t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge.
4
A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
5
The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal.
6
The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as
t6(max) = t3 − t10 − t5(min).
2
SDA
t3
t9
t10
t4
t11
SCL
t6
t2
t5
t7
REPEATED
START
CONDITION
Figure 32. I2C Timing Diagram
Rev. PrA | Page 17 of 36
t1
t8
STOP
CONDITION
10627-034
t4
START
CONDITION
ADXL343
Preliminary Technical Data
INTERRUPTS
The ADXL343 provides two output pins for driving interrupts:
INT1 and INT2. Both interrupt pins are push-pull, low impedance
pins with output specifications shown in Table 13. The default
configuration of the interrupt pins is active high. This can be
changed to active low by setting the INT_INVERT bit in the
DATA_FORMAT (Address 0x31) register. All functions can
be used simultaneously, with the only limiting feature being
that some functions may need to share interrupt pins.
Interrupts are enabled by setting the appropriate bit in the
INT_ENABLE register (Address 0x2E) and are mapped to
either the INT1 or INT2 pin based on the contents
of the INT_MAP register (Address 0x2F). When initially
configuring the interrupt pins, it is recommended that the
functions and interrupt mapping be done before enabling the
interrupts. When changing the configuration of an interrupt, it
is recommended that the interrupt be disabled first, by clearing
the bit corresponding to that function in the INT_ENABLE
register, and then the function be reconfigured before enabling
the interrupt again. Configuration of the functions while the
interrupts are disabled helps to prevent the accidental generation
of an interrupt before desired.
The interrupt functions are latched and cleared by either reading the
data registers (Address 0x32 to Address 0x37) until the interrupt
condition is no longer valid for the data-related interrupts or by
reading the INT_SOURCE register (Address 0x30) for the
remaining interrupts. This section describes the interrupts
that can be set in the INT_ENABLE register and monitored
in the INT_SOURCE register.
DATA_READY
The DATA_READY bit is set when new data is available and is
cleared when no new data is available.
SINGLE_TAP
The SINGLE_TAP bit is set when a single acceleration event
that is greater than the value in the THRESH_TAP register
(Address 0x1D) occurs for less time than is specified in the
DUR register (Address 0x21).
Table 13. Interrupt Pin Digital Output
Parameter
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
Pin Capacitance
Rise/Fall Time
Rise Time (tR) 2
Fall Time (tF) 3
1
2
3
Test Conditions
IOL = 300 µA
IOH = −150 µA
VOL = VOL, max
VOH = VOH, min
fIN = 1 MHz, VIN = 2.5 V
DOUBLE_TAP
The DOUBLE_TAP bit is set when two acceleration events
that are greater than the value in the THRESH_TAP register
(Address 0x1D) occur for less time than is specified in the DUR
register (Address 0x21), with the second tap starting after the
time specified by the latent register (Address 0x22) but within
the time specified in the window register (Address 0x23). See
the Tap Detection section for more details.
Activity
The activity bit is set when acceleration greater than the value stored
in the THRESH_ACT register (Address 0x24) is experienced on
any participating axis, set by the ACT_INACT_CTL register
(Address 0x27).
Inactivity
The inactivity bit is set when acceleration of less than the
value stored in the THRESH_INACT register (Address 0x25) is
experienced for more time than is specified in the TIME_INACT
register (Address 0x26) on all participating axes, as set by the
ACT_INACT_CTL register (Address 0x27). The maximum value
for TIME_INACT is 255 sec.
FREE_FALL
The FREE_FALL bit is set when acceleration of less than the
value stored in the THRESH_FF register (Address 0x28) is
experienced for more time than is specified in the TIME_FF
register (Address 0x29) on all axes (logical AND). The FREE_FALL
interrupt differs from the inactivity interrupt as follows: all axes
always participate and are logically AND’ed, the timer period is
much smaller (1.28 sec maximum), and the mode of operation is
always dc-coupled.
Watermark
The watermark bit is set when the number of samples in FIFO
equals the value stored in the samples bits (Register FIFO_CTL,
Address 0x38). The watermark bit is cleared automatically when
FIFO is read, and the content returns to a value below the value
stored in the samples bits.
Min
Limit 1
Max
0.2 × VDD I/O
−150
8
V
V
µA
µA
pF
210
150
ns
ns
0.8 × VDD I/O
300
CLOAD = 150 pF
CLOAD = 150 pF
Limits based on characterization results, not production tested.
Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin.
Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin.
Rev. PrA | Page 18 of 36
Unit
Preliminary Technical Data
ADXL343
Overrun
Trigger Mode
The overrun bit is set when new data replaces unread data.
The precise operation of the overrun function depends on the
FIFO mode. In bypass mode, the overrun bit is set when new data
replaces unread data in the DATAX, DATAY, and DATAZ registers
(Address 0x32 to Address 0x37). In all other modes, the overrun bit
is set when FIFO is filled. The overrun bit is automatically cleared
when the contents of FIFO are read.
In trigger mode, FIFO accumulates samples, holding the latest
32 samples from measurements of the x-, y-, and z-axes. After
a trigger event occurs and an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
FIFO keeps the last n samples (where n is the value specified by
the samples bits in the FIFO_CTL register) and then operates in
FIFO mode, collecting new samples only when FIFO is not full.
A delay of at least 5 µs should be present between the trigger event
occurring and the start of reading data from the FIFO to allow
the FIFO to discard and retain the necessary samples. Additional
trigger events cannot be recognized until the trigger mode is
reset. To reset the trigger mode, set the device to bypass mode
and then set the device back to trigger mode. Note that the FIFO
data should be read first because placing the device into bypass
mode clears FIFO.
FIFO
The ADXL343 contains an embedded memory management
system with a 32-level FIFO memory buffer that can be used to
minimize host processor burden. This buffer has four modes:
bypass, FIFO, stream, and trigger (see Table 22). Each mode is
selected by the settings of the FIFO_MODE bits (Bits[D7:D6])
in the FIFO_CTL register (Address 0x38).
If use of the FIFO is not desired, the FIFO should be placed in
bypass mode.
Bypass Mode
In bypass mode, FIFO is not operational and, therefore,
remains empty.
FIFO Mode
In FIFO mode, data from measurements of the x-, y-, and z-axes
are stored in FIFO. When the number of samples in FIFO equals
the level specified in the samples bits of the FIFO_CTL register
(Address 0x38), the watermark interrupt is set. FIFO continues
accumulating samples until it is full (32 samples from measurements
of the x-, y-, and z-axes) and then stops collecting data. After FIFO
stops collecting data, the device continues to operate; therefore,
features such as tap detection can be used after FIFO is full. The
watermark interrupt continues to occur until the number of
samples in FIFO is less than the value stored in the samples bits
of the FIFO_CTL register.
Stream Mode
In stream mode, data from measurements of the x-, y-, and zaxes are stored in FIFO. When the number of samples in FIFO
equals the level specified in the samples bits of the FIFO_CTL
register (Address 0x38), the watermark interrupt is set. FIFO
continues accumulating samples and holds the latest 32 samples
from measurements of the x-, y-, and z-axes, discarding older
data as new data arrives. The watermark interrupt continues
occurring until the number of samples in FIFO is less than the
value stored in the samples bits of the FIFO_CTL register.
Retrieving Data from FIFO
The FIFO data is read through the DATAX, DATAY, and DATAZ
registers (Address 0x32 to Address 0x37). When the FIFO is in
FIFO, stream, or trigger mode, reads to the DATAX, DATAY,
and DATAZ registers read data stored in the FIFO. Each time
data is read from the FIFO, the oldest x-, y-, and z-axes data are
placed into the DATAX, DATAY, and DATAZ registers.
If a single-byte read operation is performed, the remaining
bytes of data for the current FIFO sample are lost. Therefore, all
axes of interest should be read in a burst (or multiple-byte) read
operation. To ensure that the FIFO has completely popped (that
is, that new data has completely moved into the DATAX, DATAY,
and DATAZ registers), there must be at least 5 µs between the
end of reading the data registers and the start of a new read of
the FIFO or a read of the FIFO_STATUS register (Address 0x39).
The end of reading a data register is signified by the transition
from Register 0x37 to Register 0x38 or by the CS pin going high.
For SPI operation at 1.6 MHz or less, the register addressing
portion of the transmission is a sufficient delay to ensure that
the FIFO has completely popped. For SPI operation greater than
1.6 MHz, it is necessary to deassert the CS pin to ensure a total
delay of 5 µs; otherwise, the delay is not sufficient. The total delay
necessary for 5 MHz operation is at most 3.4 µs. This is not a
concern when using I2C mode because the communication rate is
low enough to ensure a sufficient delay between FIFO reads.
Rev. PrA | Page 19 of 36
ADXL343
Preliminary Technical Data
SELF-TEST
Table 14. Self-Test Output Scale Factors for Different Supply
Voltages, VS
The ADXL343 incorporates a self-test feature that effectively
tests its mechanical and electronic systems simultaneously.
When the self-test function is enabled (via the SELF_TEST bit
in the DATA_FORMAT register, Address 0x31), an electrostatic
force is exerted on the mechanical sensor. This electrostatic force
moves the mechanical sensing element in the same manner as
acceleration, and it is additive to the acceleration experienced
by the device. This added electrostatic force results in an output
change in the x-, y-, and z-axes. Because the electrostatic force
is proportional to VS2, the output change varies with VS. This
effect is shown in Figure 33. The scale factors shown in Table 14
can be used to adjust the expected self-test output limits for
different supply voltages, VS. The self-test feature of the
ADXL343 also exhibits a bimodal behavior. However, the limits
shown in Table 1 and Table 15 to Table 18 are valid for both
potential self-test values due to bimodality. Use of the self-test
feature at data rates less than 100 Hz or at 1600 Hz may yield
values outside these limits. Therefore, the part must be in normal
power operation (LOW_POWER bit = 0 in BW_RATE register,
Address 0x2C) and be placed into a data rate of 100 Hz through
800 Hz or 3200 Hz for the self-test function to operate correctly.
6
Axis
X
Y
Z
Z-Axis
0.8
1.00
1.47
1.69
Min
50
−540
75
Max
540
−50
875
Unit
LSB
LSB
LSB
Table 16. Self-Test Output in LSB for ±4 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
Min
25
−270
38
Max
270
−25
438
Unit
LSB
LSB
LSB
Table 17. Self-Test Output in LSB for ±8 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Min
12
−135
19
Max
135
−12
219
Unit
LSB
LSB
LSB
Table 18. Self-Test Output in LSB for ±16 g, 10-Bit Resolution
(TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
0
Axis
X
Y
Z
–2
X HIGH
X LOW
Y HIGH
Y LOW
Z HIGH
Z LOW
–6
2.0
2.5
3.3
3.6
VS (V)
10627-242
SELF-TEST SHIFT LIMIT (g)
2
X-Axis, Y-Axis
0.64
1.00
1.77
2.11
Table 15. Self-Test Output in LSB for ±2 g, 10-Bit or Full
Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)
Axis
X
Y
Z
4
–4
Supply Voltage, VS (V)
2.00
2.50
3.30
3.60
Figure 33. Self-Test Output Change Limits vs. Supply Voltage
Rev. PrA | Page 20 of 36
Min
6
−67
10
Max
67
−6
110
Unit
LSB
LSB
LSB
Preliminary Technical Data
ADXL343
REGISTER MAP
Table 19.
Address
Hex
Dec
0x00
0
0x01 to 0x1C
1 to 28
0x1D
29
0x1E
30
0x1F
31
0x20
32
0x21
33
0x22
34
0x23
35
0x24
36
0x25
37
0x26
38
0x27
39
0x28
40
0x29
41
0x2A
42
0x2B
43
0x2C
44
0x2D
45
0x2E
46
0x2F
47
0x30
48
0x31
49
0x32
50
0x33
51
0x34
52
0x35
53
0x36
54
0x37
55
0x38
56
0x39
57
Name
DEVID
Reserved
THRESH_TAP
OFSX
OFSY
OFSZ
DUR
Latent
Window
THRESH_ACT
THRESH_INACT
TIME_INACT
ACT_INACT_CTL
THRESH_FF
TIME_FF
TAP_AXES
ACT_TAP_STATUS
BW_RATE
POWER_CTL
INT_ENABLE
INT_MAP
INT_SOURCE
DATA_FORMAT
DATAX0
DATAX1
DATAY0
DATAY1
DATAZ0
DATAZ1
FIFO_CTL
FIFO_STATUS
Type
R
Reset Value
11100101
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R
R
R
R/W
R
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00001010
00000000
00000000
00000000
00000010
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Description
Device ID
Reserved; do not access
Tap threshold
X-axis offset
Y-axis offset
Z-axis offset
Tap duration
Tap latency
Tap window
Activity threshold
Inactivity threshold
Inactivity time
Axis enable control for activity and inactivity detection
Free-fall threshold
Free-fall time
Axis control for single tap/double tap
Source of single tap/double tap
Data rate and power mode control
Power-saving features control
Interrupt enable control
Interrupt mapping control
Source of interrupts
Data format control
X-Axis Data 0
X-Axis Data 1
Y-Axis Data 0
Y-Axis Data 1
Z-Axis Data 0
Z-Axis Data 1
FIFO control
FIFO status
Rev. PrA | Page 21 of 36
ADXL343
Preliminary Technical Data
Register 0x25—THRESH_INACT (Read/Write)
REGISTER DEFINITIONS
Register 0x00—DEVID (Read Only)
D7
1
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
The DEVID register holds a fixed device ID code of 0xE5 (345 octal).
Register 0x1D—THRESH_TAP (Read/Write)
The THRESH_TAP register is eight bits and holds the threshold
value for tap interrupts. The data format is unsigned, therefore,
the magnitude of the tap event is compared with the value
in THRESH_TAP for normal tap detection. The scale factor is
62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in
undesirable behavior if single tap/double tap interrupts are
enabled.
Register 0x1E, Register 0x1F, Register 0x20—OFSX,
OFSY, OFSZ (Read/Write)
The OFSX, OFSY, and OFSZ registers are each eight bits and
offer user-set offset adjustments in twos complement format
with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The
value stored in the offset registers is automatically added to the
acceleration data, and the resulting value is stored in the output
data registers. For additional information regarding offset
calibration and the use of the offset registers, refer to the Offset
Calibration section.
Register 0x21—DUR (Read/Write)
The DUR register is eight bits and contains an unsigned time
value representing the maximum time that an event must be
above the THRESH_TAP threshold to qualify as a tap event. The
scale factor is 625 µs/LSB. A value of 0 disables the single tap/
double tap functions.
Register 0x22—Latent (Read/Write)
The latent register is eight bits and contains an unsigned time
value representing the wait time from the detection of a tap
event to the start of the time window (defined by the window
register) during which a possible second tap event can be detected.
The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap
function.
Register 0x23—Window (Read/Write)
The window register is eight bits and contains an unsigned time
value representing the amount of time after the expiration of the
latency time (determined by the latent register) during which a
second valid tap can begin. The scale factor is 1.25 ms/LSB. A
value of 0 disables the double tap function.
Register 0x24—THRESH_ACT (Read/Write)
The THRESH_INACT register is eight bits and holds the threshold
value for detecting inactivity. The data format is unsigned,
therefore, the magnitude of the inactivity event is compared
with the value in the THRESH_INACT register. The scale factor
is 62.5 mg/LSB. A value of 0 may result in undesirable behavior
if the inactivity interrupt is enabled.
Register 0x26—TIME_INACT (Read/Write)
The TIME_INACT register is eight bits and contains an unsigned
time value representing the amount of time that acceleration
must be less than the value in the THRESH_INACT register for
inactivity to be declared. The scale factor is 1 sec/LSB. Unlike
the other interrupt functions, which use unfiltered data (see the
Threshold section), the inactivity function uses filtered output
data. At least one output sample must be generated for the
inactivity interrupt to be triggered. This results in the function
appearing unresponsive if the TIME_INACT register is set to a
value less than the time constant of the output data rate. A value
of 0 results in an interrupt when the output data is less than the
value in the THRESH_INACT register.
Register 0x27—ACT_INACT_CTL (Read/Write)
D7
ACT ac/dc
D3
INACT ac/dc
D6
ACT_X enable
D2
INACT_X enable
D5
ACT_Y enable
D1
INACT_Y enable
D4
ACT_Z enable
D0
INACT_Z enable
ACT AC/DC and INACT AC/DC Bits
A setting of 0 selects dc-coupled operation, and a setting of 1
enables ac-coupled operation. In dc-coupled operation, the
current acceleration magnitude is compared directly with
THRESH_ACT and THRESH_INACT to determine whether
activity or inactivity is detected.
In ac-coupled operation for activity detection, the acceleration
value at the start of activity detection is taken as a reference
value. New samples of acceleration are then compared to this
reference value, and if the magnitude of the difference exceeds
the THRESH_ACT value, the device triggers an activity interrupt.
Similarly, in ac-coupled operation for inactivity detection, a
reference value is used for comparison and is updated whenever
the device exceeds the inactivity threshold. After the reference
value is selected, the device compares the magnitude of the
difference between the reference value and the current acceleration
with THRESH_INACT. If the difference is less than the value in
THRESH_INACT for the time in TIME_INACT, the device is
considered inactive and the inactivity interrupt is triggered.
The THRESH_ACT register is eight bits and holds the threshold
value for detecting activity. The data format is unsigned,
therefore, the magnitude of the activity event is compared
with the value in the THRESH_ACT register. The scale factor
is 62.5 mg/LSB. A value of 0 may result in undesirable behavior
if the activity interrupt is enabled.
Rev. PrA | Page 22 of 36
Preliminary Technical Data
ADXL343
ACT_x Enable Bits and INACT_x Enable Bits
Asleep Bit
A setting of 1 enables x-, y-, or z-axis participation in detecting
activity or inactivity. A setting of 0 excludes the selected axis from
participation. If all axes are excluded, the function is disabled.
For activity detection, all participating axes are logically OR’ed,
causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactivity detection, all
participating axes are logically AND’ed, causing the inactivity
function to trigger only if all participating axes are below the
threshold for the specified time.
A setting of 1 in the asleep bit indicates that the part is
asleep, and a setting of 0 indicates that the part is not asleep.
This bit toggles only if the device is configured for auto sleep.
See the AUTO_SLEEP Bit section for more information on
autosleep mode.
Register 0x2C—BW_RATE (Read/Write)
D7
0
D6
0
D5
0
D4
LOW_POWER
D3
D2
D1
Rate
D0
Register 0x28—THRESH_FF (Read/Write)
LOW_POWER Bit
The THRESH_FF register is eight bits and holds the threshold
value, in unsigned format, for free-fall detection. The acceleration on
all axes is compared with the value in THRESH_FF to determine if
a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note
that a value of 0 mg may result in undesirable behavior if the freefall interrupt is enabled. Values between 300 mg and 600 mg
(0x05 to 0x09) are recommended.
A setting of 0 in the LOW_POWER bit selects normal operation,
and a setting of 1 selects reduced power operation, which has
somewhat higher noise (see the Power Modes section for details).
Register 0x29—TIME_FF (Read/Write)
The TIME_FF register is eight bits and stores an unsigned time
value representing the minimum time that the value of all axes
must be less than THRESH_FF to generate a free-fall interrupt.
The scale factor is 5 ms/LSB. A value of 0 may result in undesirable
behavior if the free-fall interrupt is enabled. Values between 100 ms
and 350 ms (0x14 to 0x46) are recommended.
Register 0x2A—TAP_AXES (Read/Write)
D7
0
D6
0
D5
0
D4
0
D3
Suppress
D2
TAP_X
enable
D1
TAP_Y
enable
D0
TAP_Z
enable
Suppress Bit
Setting the suppress bit suppresses double tap detection if
acceleration greater than the value in THRESH_TAP is present
between taps. See the Tap Detection section for more details.
TAP_x Enable Bits
A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z
enable bit enables x-, y-, or z-axis participation in tap detection.
A setting of 0 excludes the selected axis from participation in
tap detection.
Register 0x2B—ACT_TAP_STATUS (Read Only)
D7
0
D6
ACT_X
source
D5
ACT_Y
source
D4
ACT_Z
source
D3
Asleep
D2
TAP_X
source
D1
TAP_Y
source
D0
TAP_Z
source
ACT_x Source and TAP_x Source Bits
These bits indicate the first axis involved in a tap or activity
event. A setting of 1 corresponds to involvement in the event,
and a setting of 0 corresponds to no involvement. When new
data is available, these bits are not cleared but are overwritten by
the new data. The ACT_TAP_STATUS register should be read
before clearing the interrupt. Disabling an axis from participation
clears the corresponding source bit when the next activity or
single tap/double tap event occurs.
Rate Bits
These bits select the device bandwidth and output data rate (see
Table 7 and Table 8 for details). The default value is 0x0A, which
translates to a 100 Hz output data rate. An output data rate should
be selected that is appropriate for the communication protocol
and frequency selected. Selecting too high of an output data rate with
a low communication speed results in samples being discarded.
Register 0x2D—POWER_CTL (Read/Write)
D7
0
D6
0
D5
Link
D4
AUTO_SLEEP
D3
Measure
D2
Sleep
D1 D0
Wakeup
Link Bit
A setting of 1 in the link bit with both the activity and inactivity
functions enabled delays the start of the activity function until
inactivity is detected. After activity is detected, inactivity detection
begins, preventing the detection of activity. This bit serially links
the activity and inactivity functions. When this bit is set to 0,
the inactivity and activity functions are concurrent. Additional
information can be found in the Link Mode section.
When clearing the link bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the link bit is cleared
may have additional noise, especially if the device was asleep
when the bit was cleared.
AUTO_SLEEP Bit
If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables
the auto-sleep functionality. In this mode, the ADXL343 automatically switches to sleep mode if the inactivity function is
enabled and inactivity is detected (that is, when acceleration is
below the THRESH_INACT value for at least the time indicated
by TIME_INACT). If activity is also enabled, the ADXL343
automatically wakes up from sleep after detecting activity and
returns to operation at the output data rate set in the BW_RATE
register. A setting of 0 in the AUTO_SLEEP bit disables automatic
switching to sleep mode. See the description of the Sleep Bit in
this section for more information on sleep mode.
Rev. PrA | Page 23 of 36
ADXL343
Preliminary Technical Data
If the link bit is not set, the AUTO_SLEEP feature is disabled
and setting the AUTO_SLEEP bit does not have an impact on
device operation. Refer to the Link Bit section or the Link Mode
section for more information on utilization of the link feature.
When clearing the AUTO_SLEEP bit, it is recommended that the
part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that
the device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the AUTO_SLEEP
bit is cleared may have additional noise, especially if the device
was asleep when the bit was cleared.
Measure Bit
Sleep Bit
A setting of 0 in the sleep bit puts the part into the normal mode
of operation, and a setting of 1 places the part into sleep mode.
Sleep mode suppresses DATA_READY, stops transmission of data
to FIFO, and switches the sampling rate to one specified by the
wakeup bits. In sleep mode, only the activity function can be used.
When the DATA_READY interrupt is suppressed, the output
data registers (Register 0x32 to Register 0x37) are still updated
at the sampling rate set by the wakeup bits (D1:D0).
When clearing the sleep bit, it is recommended that the part be
placed into standby mode and then set back to measurement
mode with a subsequent write. This is done to ensure that the
device is properly biased if sleep mode is manually disabled;
otherwise, the first few samples of data after the sleep bit is
cleared may have additional noise, especially if the device was
asleep when the bit was cleared.
Wakeup Bits
These bits control the frequency of readings in sleep mode as
described in Table 20.
Table 20. Frequency of Readings in Sleep Mode
D1
0
0
1
1
D7
DATA_READY
D3
Inactivity
D6
SINGLE_TAP
D2
FREE_FALL
D5
DOUBLE_TAP
D1
Watermark
D4
Activity
D0
Overrun
Setting bits in this register to a value of 1 enables their respective
functions to generate interrupts, whereas a value of 0 prevents
the functions from generating interrupts. The DATA_READY,
watermark, and overrun bits enable only the interrupt output;
the functions are always enabled. It is recommended that interrupts
be configured before enabling their outputs.
Register 0x2F—INT_MAP (Read/Write)
A setting of 0 in the measure bit places the part into standby mode,
and a setting of 1 places the part into measurement mode. The
ADXL343 powers up in standby mode with minimum power
consumption.
Setting
D0
0
1
0
1
Register 0x2E—INT_ENABLE (Read/Write)
Frequency (Hz)
8
4
2
1
D7
DATA_READY
D3
Inactivity
D6
SINGLE_TAP
D2
FREE_FALL
D5
DOUBLE_TAP
D1
Watermark
D4
Activity
D0
Overrun
Any bits set to 0 in this register send their respective interrupts to
the INT1 pin, whereas bits set to 1 send their respective interrupts
to the INT2 pin. All selected interrupts for a given pin are OR’ed.
Register 0x30—INT_SOURCE (Read Only)
D7
DATA_READY
D3
Inactivity
D6
SINGLE_TAP
D2
FREE_FALL
D5
DOUBLE_TAP
D1
Watermark
D4
Activity
D0
Overrun
Bits set to 1 in this register indicate that their respective functions
have triggered an event, whereas a value of 0 indicates that the
corresponding event has not occurred. The DATA_READY,
watermark, and overrun bits are always set if the corresponding
events occur, regardless of the INT_ENABLE register settings,
and are cleared by reading data from the DATAX, DATAY, and
DATAZ registers. The DATA_READY and watermark bits may
require multiple reads, as indicated in the FIFO mode descriptions
in the FIFO section. Other bits, and the corresponding interrupts,
are cleared by reading the INT_SOURCE register.
Register 0x31—DATA_FORMAT (Read/Write)
D7
SELF_TEST
D6
SPI
D5
INT_INVERT
D4
0
D3
FULL_RES
D2
Justify
D1 D0
Range
The DATA_FORMAT register controls the presentation of data
to Register 0x32 through Register 0x37. All data, except that for
the ±16 g range, must be clipped to avoid rollover.
SELF_TEST Bit
A setting of 1 in the SELF_TEST bit applies a self-test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
SPI Bit
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.
Rev. PrA | Page 24 of 36
Preliminary Technical Data
ADXL343
INT_INVERT Bit
Table 22. FIFO Modes
A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.
Setting
D7 D6
0
0
0
1
Mode
Bypass
FIFO
1
0
Stream
1
1
Trigger
FULL_RES Bit
When this bit is set to a value of 1, the device is in full resolution
mode, where the output resolution increases with the g range
set by the range bits to maintain a 4 mg/LSB scale factor. When
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
the range bits determine the maximum g range and scale factor.
Justify Bit
A setting of 1 in the justify bit selects left-justified (MSB) mode,
and a setting of 0 selects right-justified mode with sign extension.
Function
FIFO is bypassed.
FIFO collects up to 32 values and then
stops collecting data, collecting new data
only when FIFO is not full.
FIFO holds the last 32 data values. When
FIFO is full, the oldest data is overwritten
with newer data.
When triggered by the trigger bit, FIFO
holds the last data samples before the
trigger event and then continues to collect
data until full. New data is collected only
when FIFO is not full.
Range Bits
Trigger Bit
These bits set the g range as described in Table 21.
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
Table 21. g Range Setting
D1
0
0
1
1
Setting
D0
0
1
0
1
Samples Bits
g Range
±2 g
±4 g
±8 g
±16 g
The function of these bits depends on the FIFO mode selected
(see Table 23). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE
register, regardless of which FIFO mode is selected. Undesirable
operation may occur if a value of 0 is used for the samples bits
when trigger mode is used.
Register 0x32 to Register 0x37—DATAX0, DATAX1,
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
Table 23. Samples Bits Functions
These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 and
Register 0x33 hold the output data for the x-axis, Register 0x34 and
Register 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis. The output
data is twos complement, with DATAx0 as the least significant
byte and DATAx1 as the most significant byte, where x represent X,
Y, or Z. The DATA_FORMAT register (Address 0x31) controls
the format of the data. It is recommended that a multiple-byte
read of all registers be performed to prevent a change in data
between reads of sequential registers.
D5
Trigger
D4
D3
D2
D1
Samples
Stream
Trigger
Samples Bits Function
None.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO samples are retained in
the FIFO buffer before a trigger event.
0x39—FIFO_STATUS (Read Only)
D7
FIFO_TRIG
D6
0
D5
D4
D3
D2
Entries
D1
D0
FIFO_TRIG Bit
Register 0x38—FIFO_CTL (Read/Write)
D7
D6
FIFO_MODE
FIFO Mode
Bypass
FIFO
D0
A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring,
and a 0 means that a FIFO trigger event has not occurred.
FIFO_MODE Bits
Entries Bits
These bits set the FIFO mode, as described in Table 22.
These bits report how many data values are stored in FIFO.
Access to collect the data from FIFO is provided through the
DATAX, DATAY, and DATAZ registers. FIFO reads must be
done in burst or multiple-byte mode because each FIFO level is
cleared after any read (single- or multiple-byte) of FIFO. FIFO
stores a maximum of 32 entries, which equates to a maximum
of 33 entries available at any given time because an additional
entry is available at the output filter of the device.
Rev. PrA | Page 25 of 36
ADXL343
Preliminary Technical Data
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
TAP DETECTION
A 1 µF tantalum capacitor (CS) at VS and a 0.1 µF ceramic capacitor
(CI/O) at VDD I/O placed close to the ADXL343 supply pins is
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead, no larger than 100 Ω, in series with VS
may be helpful. Additionally, increasing the bypass capacitance
on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic capacitor may also improve noise.
The tap interrupt function is capable of detecting either single
or double taps. The following parameters are shown in Figure 36
for a valid single and valid double tap event:
Care should be taken to ensure that the connection from the
ADXL343 ground to the power supply ground has low impedance
because noise transmitted through ground has an effect similar
to noise transmitted through VS. It is recommended that VS and
VDD I/O be separate supplies to minimize digital clocking noise
on the VS supply. If this is not possible, additional filtering of
the supplies, as previously mentioned, may be necessary.
VS
•
The tap detection threshold is defined by the THRESH_TAP
register (Address 0x1D).
The maximum tap duration time is defined by the DUR
register (Address 0x21).
The tap latency time is defined by the latent register
(Address 0x22) and is the waiting period from the end
of the first tap until the start of the time window, when a
second tap can be detected, which is determined by the
value in the window register (Address 0x23).
The interval after the latency time (set by the latent register) is
defined by the window register. Although a second tap must
begin after the latency time has expired, it need not finish
before the end of the time defined by the window register.
•
•
•
VDD I/O
CS
CIO
FIRST TAP
VS
XHI BW
SDA/SDI/SDIO
INT1 SDO/ALT ADDRESS
SCL/SCLK
INT2
CS
10627-016
GND
3- OR 4-WIRE
SPI OR I2C
INTERFACE
TIME LIMIT FOR
TAPS (DUR)
Figure 34. Application Diagram
The ADXL343 should be mounted on the PCB in a location
close to a hard mounting point of the PCB to the case. Mounting
the ADXL343 at an unsupported PCB location, as shown in
Figure 35, may result in large, apparent measurement errors
due to undampened PCB vibration. Locating the accelerometer
near a hard mounting point ensures that any PCB vibration at
the accelerometer is above the accelerometer’s mechanical sensor
resonant frequency and, therefore, effectively invisible to the
accelerometer. Multiple mounting points close to the sensor
and/or a thicker PCB also help to reduce the effect of system
resonance on the performance of the sensor.
LATENCY
TIME
(LATENT)
INTERRUPTS
MECHANICAL CONSIDERATIONS FOR MOUNTING
TIME WINDOW FOR
SECOND TAP (WINDOW)
SINGLE TAP
INTERRUPT
DOUBLE TAP
INTERRUPT
Figure 36. Tap Interrupt Function with Valid Single and Double Taps
If only the single tap function is in use, the single tap interrupt
is triggered when the acceleration goes below the threshold, as
long as DUR has not been exceeded. If both single and double
tap functions are in use, the single tap interrupt is triggered
when the double tap event has been either validated or
invalidated.
ACCELEROMETERS
10627-036
PCB
MOUNTING POINTS
THRESHOLD
(THRESH_TAP)
10627-037
ADXL343
INTERRUPT
CONTROL
SECOND TAP
VDD I/O
Figure 35. Incorrectly Placed Accelerometers
Rev. PrA | Page 26 of 36
Preliminary Technical Data
ADXL343
Several events can occur to invalidate the second tap of a double
tap event. First, if the suppress bit in the TAP_AXES register
(Address 0x2A) is set, any acceleration spike above the threshold
during the latency time (set by the latent register) invalidates
the double tap detection, as shown in Figure 37.
TIME LIMIT
FOR TAPS
(DUR)
LATENCY
TIME (LATENT)
TIME WINDOW FOR SECOND
TAP (WINDOW)
10627-038
XHI BW
INVALIDATES DOUBLE TAP IF
SUPRESS BIT SET
Figure 37. Double Tap Event Invalid Due to High g Event
When the Suppress Bit Is Set
A double tap event can also be invalidated if acceleration above
the threshold is detected at the start of the time window for the
second tap (set by the window register). This results in an invalid
double tap at the start of this window, as shown in Figure 38.
Additionally, a double tap event can be invalidated if an acceleration exceeds the time limit for taps (set by the DUR register),
resulting in an invalid double tap at the end of the DUR time
limit for the second tap event, also shown in Figure 38.
XHI BW
INVALIDATES DOUBLE TAP
AT START OF WINDOW
TIME LIMIT
FOR TAPS
(DUR)
TIME LIMIT
FOR TAPS
(DUR)
LATENCY
TIME
(LATENT)
TIME WINDOW FOR
SECOND TAP (WINDOW)
10627-039
XHI BW
Figure 38. Tap Interrupt Function with Invalid Double Taps
Every mechanical system has somewhat different single tap/
double tap responses based on the mechanical characteristics of
the system. Therefore, some experimentation with values for the
DUR, latent, window, and THRESH_TAP registers is required.
In general, a good starting point is to set the DUR register to a
value greater than 0x10 (10 ms), the latent register to a value greater
than 0x10 (20 ms), the window register to a value greater than
0x40 (80 ms), and the THRESH_TAP register to a value greater
than 0x30 (3 g). Setting a very low value in the latent, window, or
THRESH_TAP register may result in an unpredictable response
due to the accelerometer picking up echoes of the tap inputs.
After a tap interrupt has been received, the first axis to exceed
the THRESH_TAP level is reported in the ACT_TAP_STATUS
register (Address 0x2B). This register is never cleared but is
overwritten with new data.
THRESHOLD
The lower output data rates are achieved by decimating a common
sampling frequency inside the device. The activity, free-fall, and
single tap/double tap detection functions without improved tap
enabled are performed using undecimated data. Because the
bandwidth of the output data varies with the data rate and is
lower than the bandwidth of the undecimated data, the high
frequency and high g data that is used to determine activity,
free-fall, and single tap/double tap events may not be present
if the output of the accelerometer is examined. This may result
in functions triggering when acceleration data does not appear
to meet the conditions set by the user for the corresponding
function.
LINK MODE
TIME LIMIT
FOR TAPS
(DUR)
INVALIDATES
DOUBLE TAP AT
END OF DUR
Single taps, double taps, or both can be detected by setting the
respective bits in the INT_ENABLE register (Address 0x2E).
Control over participation of each of the three axes in single tap/
double tap detection is exerted by setting the appropriate bits in
the TAP_AXES register (Address 0x2A). For the double tap
function to operate, both the latent and window registers must
be set to a nonzero value.
The function of the link bit is to reduce the number of activity
interrupts that the processor must service by setting the device
to look for activity only after inactivity. For proper operation of
this feature, the processor must still respond to the activity and
inactivity interrupts by reading the INT_SOURCE register
(Address 0x30) and, therefore, clearing the interrupts. If an activity
interrupt is not cleared, the part cannot go into autosleep mode.
The asleep bit in the ACT_TAP_STATUS register (Address 0x2B)
indicates if the part is asleep.
Rev. PrA | Page 27 of 36
ADXL343
Preliminary Technical Data
SLEEP MODE VS. LOW POWER MODE
In applications where a low data rate and low power consumption
is desired (at the expense of noise performance), it is recommended
that low power mode be used. The use of low power mode preserves
the functionality of the DATA_READY interrupt and FIFO for
postprocessing of the acceleration data. Sleep mode, while
offering a low data rate and power consumption, is not intended
for data acquisition.
However, when sleep mode is used in conjunction with the
AUTO_SLEEP mode and the link mode, the part can automatically
switch to a low power, low sampling rate mode when inactivity
is detected. To prevent the generation of redundant inactivity
interrupts, the inactivity interrupt is automatically disabled
and activity is enabled. When the ADXL343 is in sleep mode, the
host processor can also be placed into sleep mode or low power
mode to save significant system power. When activity is detected,
the accelerometer automatically switches back to the original
data rate of the application and provides an activity interrupt
that can be used to wake up the host processor. Similar to when
inactivity occurs, detection of activity events is disabled and
inactivity is enabled.
OFFSET CALIBRATION
Accelerometers are mechanical structures containing elements
that are free to move. These moving parts can be very sensitive
to mechanical stresses, much more so than solid-state electronics.
The 0 g bias or offset is an important accelerometer metric because
it defines the baseline for measuring acceleration. Additional
stresses can be applied during assembly of a system containing
an accelerometer. These stresses can come from, but are not
limited to, component soldering, board stress during mounting,
and application of any compounds on or over the component. If
calibration is deemed necessary, it is recommended that calibration
be performed after system assembly to compensate for these effects.
A simple method of calibration is to measure the offset while
assuming that the sensitivity of the ADXL343 is as specified in
Table 1. The offset can then be automatically accounted for by
using the built-in offset registers. This results in the data acquired
from the DATA registers already compensating for any offset.
In a no-turn or single-point calibration scheme, the part is oriented
such that one axis, typically the z-axis, is in the 1 g field of gravity
and the remaining axes, typically the x- and y-axis, are in a 0 g
field. The output is then measured by taking the average of a
series of samples. The number of samples averaged is a choice of
the system designer, but a recommended starting point is 0.1 sec
worth of data for data rates of 100 Hz or greater. This corresponds
to 10 samples at the 100 Hz data rate. For data rates less than
100 Hz, it is recommended that at least 10 samples be averaged
together. These values are stored as X0g, Y0g, and Z+1g for the 0 g
measurements on the x- and y-axis and the 1 g measurement on
the z-axis, respectively.
The values measured for X0g and Y0g correspond to the x- and y-axis
offset, and compensation is done by subtracting those values from
the output of the accelerometer to obtain the actual acceleration:
XACTUAL = XMEAS − X0g
YACTUAL = YMEAS − Y0g
Because the z-axis measurement was done in a +1 g field, a no-turn
or single-point calibration scheme assumes an ideal sensitivity,
SZ for the z-axis. This is subtracted from Z+1g to attain the z-axis
offset, which is then subtracted from future measured values to
obtain the actual value:
Z0g = Z+1g − SZ
ZACTUAL = ZMEAS − Z0g
The ADXL343 can automatically compensate the output for offset
by using the offset registers (Register 0x1E, Register 0x1F, and
Register 0x20). These registers contain an 8-bit, twos complement
value that is automatically added to all measured acceleration
values, and the result is then placed into the DATA registers.
Because the value placed in an offset register is additive, a negative
value is placed into the register to eliminate a positive offset and
vice versa for a negative offset. The register has a scale factor of
15.6 mg/LSB and is independent of the selected g-range.
As an example, assume that the ADXL343 is placed into fullresolution mode with a sensitivity of typically 256 LSB/g. The
part is oriented such that the z-axis is in the field of gravity and
x-, y-, and z-axis outputs are measured as +10 LSB, −13 LSB,
and +9 LSB, respectively. Using the previous equations, X0g is
+10 LSB, Y0g is −13 LSB, and Z0g is +9 LSB. Each LSB of output
in full-resolution is 3.9 mg or one-quarter of an LSB of the
offset register. Because the offset register is additive, the 0 g
values are negated and rounded to the nearest LSB of the offset
register:
XOFFSET = −Round(10/4) = −3 LSB
YOFFSET = −Round(−13/4) = 3 LSB
ZOFFSET = −Round(9/4) = −2 LSB
These values are programmed into the OFSX, OFSY, and OFXZ
registers, respectively, as 0xFD, 0x03, and 0xFE. As with all
registers in the ADXL343, the offset registers do not retain the
value written into them when power is removed from the part.
Power-cycling the ADXL343 returns the offset registers to their
default value of 0x00.
Because the no-turn or single-point calibration method assumes an
ideal sensitivity in the z-axis, any error in the sensitivity results in
offset error. For instance, if the actual sensitivity was 250 LSB/g
in the previous example, the offset would be 15 LSB, not 9 LSB.
To help minimize this error, an additional measurement point
can be used with the z-axis in a 0 g field and the 0 g measurement
can be used in the ZACTUAL equation.
Rev. PrA | Page 28 of 36
Preliminary Technical Data
ADXL343
USING SELF-TEST
The self-test change is defined as the difference between the
acceleration output of an axis with self-test enabled and the
acceleration output of the same axis with self-test disabled (see
Endnote 4 of Table 1). This definition assumes that the sensor
does not move between these two measurements. If the sensor
moves, the additional shift, which is unrelated to self-test,
corrupts the test.
Proper configuration of the ADXL343 is also necessary for an
accurate self-test measurement. The part should be set with a
data rate of 100 Hz through 800 Hz, or 3200 Hz. This is done by
ensuring that a value of 0x0A through 0x0D, or 0x0F is written
into the rate bits (Bit D3 through Bit D0) in the BW_RATE
register (Address 0x2C). The part also must be placed into
normal power operation by ensuring the LOW_POWER bit in
the BW_RATE register is cleared (LOW_POWER bit = 0) for
accurate self-test measurements. It is recommended that the
part be set to full-resolution, 16 g mode to ensure that there is
sufficient dynamic range for the entire self-test shift. This is done
by setting Bit D3 of the DATA_FORMAT register (Address 0x31)
and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of
the DATA_FORMAT register (Address 0x31). This results in a high
dynamic range for measurement and a 3.9 mg/LSB scale factor.
After the part is configured for accurate self-test measurement,
several samples of x-, y-, and z-axis acceleration data should be
retrieved from the sensor and averaged together. The number
of samples averaged is a choice of the system designer, but a
recommended starting point is 0.1 sec worth of data for data
rates of 100 Hz or greater. This corresponds to 10 samples at
the 100 Hz data rate. For data rates less than 100 Hz, it is
recommended that at least 10 samples be averaged together. The
averaged values should be stored and labeled appropriately as
the self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF.
Next, self-test should be enabled by setting Bit D7 (SELF_TEST) of
the DATA_FORMAT register (Address 0x31). The output needs
some time (about four samples) to settle after enabling self-test.
After allowing the output to settle, several samples of the x-, y-,
and z-axis acceleration data should be taken again and averaged. It
is recommended that the same number of samples be taken for
this average as was previously taken. These averaged values should
again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be
disabled by clearing Bit D7 (SELF_TEST) of the DATA_FORMAT
register (Address 0x31).
With the stored values for self-test enabled and disabled, the
self-test change is as follows:
XST = XST_ON − XST_OFF
YST = YST_ON − YST_OFF
ZST = ZST_ON − ZST_OFF
Because the measured output for each axis is expressed in LSBs,
XST, YST, and ZST are also expressed in LSBs. These values can be
converted to g’s of acceleration by multiplying each value by the
3.9 mg/LSB scale factor, if configured for full-resolution mode.
Additionally, Table 15 through Table 18 correspond to the self-test
range converted to LSBs and can be compared with the measured
self-test change when operating at a VS of 2.5 V. For other voltages,
the minimum and maximum self-test output values should be
adjusted based on (multiplied by) the scale factors shown in
Table 14. If the part was placed into ±2 g, 10-bit or full-resolution
mode, the values listed in Table 15 should be used. Although
the fixed 10-bit mode or a range other than 16 g can be used, a
different set of values, as indicated in Table 16 through Table 18,
would need to be used. Using a range below 8 g may result in
insufficient dynamic range and should be considered when
selecting the range of operation for measuring self-test.
If the self-test change is within the valid range, the test is considered
successful. Generally, a part is considered to pass if the minimum
magnitude of change is achieved. However, a part that changes
by more than the maximum magnitude is not necessarily a failure.
Another effective method for using the self-test to verify accelerometer functionality is to toggle the self-test at a certain rate
and then perform an FFT on the output. The FFT should have a
corresponding tone at the frequency the self-test was toggled.
Using an FFT like this removes the dependency of the test on
supply voltage and on self-test magnitude, which can vary within
a rather wide range.
Rev. PrA | Page 29 of 36
ADXL343
Preliminary Technical Data
DATA FORMATTING OF UPPER DATA RATES
For a range of ±2 g, the LSB is Bit D6 of the DATAx0 register;
for ±4 g, Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the
DATAx0 register; and for ±16 g, Bit D3 of the DATAx0 register.
This is shown in Figure 40.
Formatting of output data at the 3200 Hz and 1600 Hz output
data rates changes depending on the mode of operation (fullresolution or fixed 10-bit) and the selected output range.
The use of 3200 Hz and 1600 Hz output data rates for fixed
10-bit operation in the ±4 g, ±8 g, and ±16 g output ranges
provides an LSB that is valid and that changes according to the
applied acceleration. Therefore, in these modes of operation,
Bit D0 is not always 0 when output data is right justified and
Bit D6 is not always 0 when output data is left justified.
Operation at any data rate of 800 Hz or lower also provides
a valid LSB in all ranges and modes that changes according
to the applied acceleration.
When using the 3200 Hz or 1600 Hz output data rates in fullresolution or ±2 g, 10-bit operation, the LSB of the output dataword is always 0. When data is right justified, this corresponds
to Bit D0 of the DATAx0 register, as shown in Figure 39. When
data is left justified and the part is operating in ±2 g, 10-bit mode,
the LSB of the output data-word is Bit D6 of the DATAx0 register.
In full-resolution operation when data is left justified, the location
of the LSB changes according to the selected output range.
DATAx1 REGISTER
DATAx0 REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
0
OUTPUT DATA-WORD FOR
±16g, FULL-RESOLUTION MODE.
OUTPUT DATA-WORD FOR ALL
10-BIT MODES AND THE ±2g,
FULL-RESOLUTION MODE.
10627-145
THE ±4g AND ±8g FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±2g
AND ±16g FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND
BIT D3 OF THE DATAX1 REGISTER FOR ±4g AND ±8g, RESPECTIVELY.
Figure 39. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Right Justified
DATAx1 REGISTER
DATAx0 REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
0
MSB FOR ALL MODES
OF OPERATION WHEN
LEFT JUSTIFIED.
LSB FOR ±2g, FULL-RESOLUTION
AND ±2g, 10-BIT MODES.
LSB FOR ±4g, FULL-RESOLUTION MODE.
LSB FOR ±8g, FULL-RESOLUTION MODE.
FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.
ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT
DATA IS LEFT JUSTIFIED.
10627-146
LSB FOR ±16g, FULL-RESOLUTION MODE.
Figure 40. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Left Justified
Rev. PrA | Page 30 of 36
Preliminary Technical Data
ADXL343
NOISE PERFORMANCE
10k
The trend of noise performance for both normal power and low
power modes of operation of the ADXL343 is shown in Figure 41.
Figure 42 shows the typical Allan deviation for the ADXL343.
The 1/f corner of the device, as shown in this figure, is very low,
allowing absolute resolution of approximately 100 µg (assuming
that there is sufficient integration time). Figure 42 also shows
that the noise density is 290 µg/√Hz for the x-axis and y-axis
and 430 µg/√Hz for the z-axis.
Figure 43 shows the typical noise performance trend of the
ADXL343 over supply voltage. The performance is normalized
to the tested and specified supply voltage, VS = 2.5 V. In general,
noise decreases as supply voltage is increased. It should be noted, as
shown in Figure 41, that the noise on the z-axis is typically higher
than on the x-axis and y-axis; therefore, while they change roughly
the same in percentage over supply voltage, the magnitude of change
on the z-axis is greater than the magnitude of change on the
x-axis and y-axis.
5.0
4.5
OUTPUT NOISE (LSB rms)
4.0
3.5
X-AXIS, LOW POWER
Y-AXIS, LOW POWER
Z-AXIS, LOW POWER
X-AXIS, NORMAL POWER
Y-AXIS, NORMAL POWER
Z-AXIS, NORMAL POWER
3.0
2.5
2.0
1.5
1.0
0
3.13 6.25 12.50 25
50 100 200 400
OUTPUT DATA RATE (Hz)
800 1600 3200
10627-250
0.5
Figure 41. Noise vs. Output Data Rate for Normal and Low Power Modes,
Full-Resolution (256 LSB/g)
100
10
0.01
1
0.1
100
10
AVERAGING PERIOD,
1k
10k
(s)
10627-251
ALLAN DEVIATION (µg)
1k
Figure 42. Root Allan Deviation
130
120
X-AXIS
Y-AXIS
Z-AXIS
110
100
90
80
70
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE, VS (V)
10627-252
For low power operation (LOW_POWER bit (D4) = 1 in the
BW_RATE register, Address 0x2C), the noise of the ADXL343
is constant for all valid data rates shown in Table 8. This value is
typically less than 1.8 LSB rms for the x- and y-axes and typically
less than 2.6LSB rms for the z-axis.
X-AXIS
Y-AXIS
Z-AXIS
PERCENTAGE OF NORMALIZED NOISE (%)
The specification of noise shown in Table 1 corresponds to
the typical noise performance of the ADXL343 in normal power
operation with an output data rate of 100 Hz (LOW_POWER bit
(D4) = 0, rate bits (D3:D0) = 0xA in the BW_RATE register,
Address 0x2C). For normal power operation at data rates below
100 Hz, the noise of the ADXL343 is equivalent to the noise at
100 Hz ODR in LSBs. For data rates greater than 100 Hz, the
noise increases roughly by a factor of √2 per doubling of the data
rate. For example, at 400 Hz ODR, the noise on the x- and y-axes
is typically less than 1.5 LSB rms, and the noise on the z-axis is
typically less than 2.2 LSB rms.
Figure 43. Normalized Noise vs. Supply Voltage, VS
OPERATION AT VOLTAGES OTHER THAN 2.5 V
The ADXL343 is tested and specified at a supply voltage of
VS = 2.5 V; however, it can be powered with VS as high as 3.6 V
or as low as 2.0 V. Some performance parameters change as the
supply voltage changes: offset, sensitivity, noise, self-test, and
supply current.
Due to slight changes in the electrostatic forces as supply voltage
is varied, the offset and sensitivity change slightly. When operating
at a supply voltage of VS = 3.3 V, the x- and y-axis offset is typically
25 mg higher than at Vs = 2.5 V operation. The z-axis is typically
20 mg lower when operating at a supply voltage of 3.3 V than when
operating at VS = 2.5 V. Sensitivity on the x- and y-axes typically
shifts from a nominal 256 LSB/g (full-resolution or ±2 g, 10-bit
operation) at VS = 2.5 V operation to 265 LSB/g when operating
with a supply voltage of 3.3 V. The z-axis sensitivity is unaffected by
a change in supply voltage and is the same at VS = 3.3 V operation
as it is at VS = 2.5 V operation. Simple linear interpolation can be
used to determine typical shifts in offset and sensitivity at other
supply voltages.
Rev. PrA | Page 31 of 36
ADXL343
Preliminary Technical Data
When using the lowest data rates, it is recommended that the
operating temperature range of the device be limited to provide
minimal offset shift across the operating temperature range.
Due to variability between parts, it is also recommended that
calibration over temperature be performed if any data rates
below 6.25 Hz are in use.
100
80
0.10Hz
0.20Hz
0.39Hz
0.78Hz
1.56Hz
3.13Hz
6.25Hz
60
40
0
25
45
55
65
75
85
TEMPERATURE (°C)
Figure 45. Typical Y-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V
140
120
100
80
0.10Hz
0.20Hz
0.39Hz
0.78Hz
1.56Hz
3.13Hz
6.25Hz
60
40
20
0
140
–20
25
120
NORMALIZED OUTPUT (LSB)
35
10627-057
20
35
45
55
65
TEMPERATURE (°C)
75
85
10627-058
The ADXL343 offers a large number of output data rates and
bandwidths, designed for a large range of applications. However,
at the lowest data rates, described as those data rates below 6.25 Hz,
the offset performance over temperature can vary significantly
from the remaining data rates. Figure 44, Figure 45, and Figure 46
show the typical offset performance of the ADXL343 over
temperature for the data rates of 6.25 Hz and lower. All plots
are normalized to the offset at 100 Hz output data rate; therefore,
a nonzero value corresponds to additional offset shift due to
temperature for that data rate.
120
NORMALIZED OUTPUT (LSB)
OFFSET PERFORMANCE AT LOWEST DATA RATES
140
NORMALIZED OUTPUT (LSB)
Changes in noise performance, self-test response, and supply
current are discussed elsewhere throughout the data sheet. For
noise performance, the Noise Performance section should be
reviewed. The Using Self-Test section discusses both the
operation of self-test over voltage, a square relationship with
supply voltage, as well as the conversion of the self-test response
in g’s to LSBs. Finally, Figure 23 shows the impact of supply
voltage on typical current consumption at a 100 Hz output data
rate, with all other output data rates following the same trend.
Figure 46. Typical Z-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V
100
80
0.10Hz
0.20Hz
0.39Hz
0.78Hz
1.56Hz
3.13Hz
6.25Hz
60
40
0
25
35
45
55
65
TEMPERATURE (°C)
75
85
10627-056
20
Figure 44. Typical X-Axis Output vs. Temperature at Lower Data Rates,
Normalized to 100 Hz Output Data Rate, VS = 2.5 V
Rev. PrA | Page 32 of 36
Preliminary Technical Data
ADXL343
AXES OF ACCELERATION SENSITIVITY
AZ
AX
10627-021
AY
Figure 47. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)
XOUT = 1g
YOUT = 0g
ZOUT = 0g
TOP
TOP
TOP
GRAVITY
XOUT = 0g
YOUT = 1g
ZOUT = 0g
XOUT = –1g
YOUT = 0g
ZOUT = 0g
XOUT = 0g
YOUT = 0g
ZOUT = 1g
Figure 48. Output Response vs. Orientation to Gravity
Rev. PrA | Page 33 of 36
XOUT = 0g
YOUT = 0g
ZOUT = –1g
10627-022
TOP
XOUT = 0g
YOUT = –1g
ZOUT = 0g
ADXL343
Preliminary Technical Data
LAYOUT AND DESIGN RECOMMENDATIONS
Figure 49 shows the recommended printed wiring board land pattern. Figure 50 and Table 24 provide details about the recommended
soldering profile.
3.3400
1.0500
0.5500
0.2500
3.0500
10627-014
5.3400
0.2500
1.1450
Figure 49. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters)
CRITICAL ZONE
TL TO TP
tP
TP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
10627-015
TEMPERATURE
RAMP-UP
t25°C TO PEAK
TIME
Figure 50. Recommended Soldering Profile
Table 24. Recommended Soldering Profile 1, 2
Profile Feature
Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time from TSMIN to TSMAX (tS)
TSMAX to TL Ramp-Up Rate
Liquid Temperature (TL)
Time Maintained Above TL (tL)
Peak Temperature (TP)
Time of Actual TP − 5°C (tP)
Ramp-Down Rate
Time 25°C to Peak Temperature
1
2
Sn63/Pb37
3°C/sec maximum
Condition
Pb-Free
3°C/sec maximum
100°C
150°C
60 sec to 120 sec
3°C/sec maximum
183°C
60 sec to 150 sec
240 + 0/−5°C
10 sec to 30 sec
6°C/sec maximum
6 minutes maximum
Based on JEDEC Standard J-STD-020D.1.
For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used.
Rev. PrA | Page 34 of 36
150°C
200°C
60 sec to 180 sec
3°C/sec maximum
217°C
60 sec to 150 sec
260 + 0/−5°C
20 sec to 40 sec
6°C/sec maximum
8 minutes maximum
Preliminary Technical Data
ADXL343
OUTLINE DIMENSIONS
PAD A1
CORNER
3.00
BSC
0.49
BOTTOM VIEW
13
14
0.813 × 0.50
1
0.80
BSC
5.00
BSC
0.50
8
7
6
TOP VIEW
END VIEW
1.01
0.79
0.74
0.69
0.49
1.50
03-16-2010-A
1.00
0.95
0.85
SEATING
PLANE
Figure 51. 14-Terminal Land Grid Array [LGA]
(CC-14-1)
Solder Terminations Finish Is Au over Ni
Dimensions shown in millimeters
Rev. PrA | Page 35 of 36
ADXL343
Preliminary Technical Data
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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PR10627-0-5/12(PrA)
Rev. PrA | Page 36 of 36