AVAGO AFCT-701SDDZ 10gb/1gb ethernet, 1310nm sfp transceiver Datasheet

AFCT-701SDDZ
10Gb/1Gb Ethernet, 1310nm
SFP+ Transceiver
Data Sheet
Description
The Avago AFCT-701SDDZ transceiver is part of a family of SFP+ products. This transceiver utilizes Avago’s
1310nm DFB and PIN Detector technology to provide an
IEEE 10Gb Ethernet design compliant with the 10GBASELR standard and allows for the operation at 1.25GBd for
Gigabit Ethernet Applications. The AFCT-701SDDZ transceiver has the signal and the chassis SFP grounds tied
together to enhance the EMI shielding performance of
the module, providing extra margin that is particularly
useful in higher density applications. The design is based
on the new electrical and mechanical specification enhancements to the well known SFP specifications developed by the SFF Committee. These specifications are
referred to as SFP+ to recognize these enhancements to
previous SFP specifications used for lower speed products. Avago Technologies is an active participant in the
SFF Committee specification development activities.
Related Products
x AFBR-703SDDZ SFP+ 10Gb/1Gb Gigabit Ethernet
10GBASE-SR transceiver for operation in OM3 MMF
link applications with link length up to 300 meters
x AFCT-701SDZ(AFCT-701ASDZ) SFP+ 10 Gigabit
Ethernet 10GBASE-LR transceiver with case
temperature 0-70 qC (0-85 qC) for operation in SMF
link applications with link lengths up to 10 Km.
DDZ
AFCT-701S
Features
x Avago 1310nm Distributed Feedback (DFB) source
and Transmitter Optical Subassembly technology
x Avago PIN detector and Receiver Optical Subassembly
technology
x Typical power dissipation 850mW
x Full digital diagnostic management interface
x Avago SFP+ package design enables equipment EMI
performance in high port density applications with
margin to Class B limits
x Flexibility in data rate selection through either
hardware or software control
Specifications
x Optical interface specifications per IEEE 802.3ae
10GBASE-LR
x Compliant to the transmitter extinction ratio and
the receiver sensitivity specs per IEEE 802.3 Gigabit
Ethernet (1.25GBd) 1000BASE-LX
x Electrical interface specifications per SFF Committee
SFF 8431 Specifications for Enhanced 8.5 and 10
Gigabit Small Form Factor Pluggable Module “SFP+”
x Management interface specifications per SFF Committee SFF 8431 and SFF 8472 Diagnostic Monitoring
Interface for Optical Transceivers
x AFBR-707SDZ SFP+ 10 Gigabit Ethernet 10GBASELRM transceiver for 220 meter operation in all MMF
link applications including OM1 and OM2 legacy fiber
cables and new high bandwidth OM3 fiber cables.
x Mechanical specifications per SFF Committee SFF
8432 Improved Pluggable Formfactor “IPF”
x AFCT-5016Z SFP+ Evaluation Board The purpose of
this SFP+ evaluation board is to provide the designer
with a convenient means for evaluating SFP+ fiber
optic transceivers.
x Compliant to Restriction on Hazardous Substances
(RoHS) per EU and China requirements
x LC Duplex optical connector interface confirming to
ANSI TIA/EA 604-10 (FOCIS 10A)
x Compliant to halogen free requirement
x Class 1 Eye safe per requirements of IEC 60825-1/
CDRH
Description, continued
Installation
Compliance Prediction
The AFCT-701SDDZ transceiver package is compliant
with the SFF 8432 Improved Pluggable Formfactor housing specification for the SFP+. It can be installed in any
INF-8074 or SFF-8431/2 compliant Small Form Pluggable
(SFP) port regardless of host equipment operating status
The AFCT-701SDDZ is hot-pluggable, allowing the module to be installed while the host system is operating and
on-line. Upon insertion, the transceiver housing makes
initial contact with the host board SFP cage, mitigating
potential damage due to Electro-Static Discharge (ESD).
Compliance prediction is the ability to determine if an
optical transceiver is operating within its operating and
environmental requirements. AFCT-701SDDZ devices
provide real-time access to transceiver internal supply
voltage and temperature, allowing a host to identify
potential component compliance issues. Received
optical power is also available to assess compliance of
a cable plant and remote transmitter. When operating
out of requirements, the link cannot guarantee error free
transmission.
By selecting TX rate select to 1.25 Gbps operation, the TX
module performance complies with the extinction ratio
and output power level in the 1000BASE-LX specifications.
Fault Isolation
The rate select can be done through either the hardware
pins or the software access to the A2h page of EEPROM
map. The user can refer to the Appendix for details of
rate select.
The fault isolation feature allows a host to quickly pinpoint the location of a link failure, minimizing downtime. For optical links, the ability to identify a fault at a
local device, remote device or cable plant is crucial to
speeding service of an installation. AFCT-701SDDZ realtime monitors of Tx_Bias, Tx_Power, Vcc, Temperature
and Rx_Power can be used to assess local transceiver
current operating conditions. In addition, status flags
TX_DISABLE and Rx Loss of Signal (LOS) are mirrored in
memory and available via the two-wire serial interface.
Digital Diagnostic Interface and Serial Identification
Component Monitoring
The two-wire interface protocol and signaling detail are
based on SFF-8431. Conventional EEPROM memory,
bytes 0-255 at memory address 0xA0, is organized in
compliance with SFF-8431. New digital diagnostic information, bytes 0-255 at memory address 0xA2, is
compliant to SFF-8472. The new diagnostic information
provides the opportunity for Predictive Failure Identification, Compliance Prediction, Fault Isolation and Component Monitoring.
Component evaluation is a more casual use of the AFCT701SDDZ real-time monitors of Tx_Bias, Tx_Power, Vcc,
Temperature and Rx_Power. Potential uses are as debugging aids for system installation and design, and
transceiver parametric evaluation for factory or field
qualification. For example, temperature per module can
be observed in high density applications to facilitate
thermal evaluation of blades, PCI cards and systems.
Likewise RX performance complies with the sensitivity
performance in the 1000BASE-LX by selecting RX rate
select to 1.25 Gbps operation.
Predictive Failure Identification
The AFCT-701SDDZ predictive failure feature allows a
host to identify potential link problems before system
performance is impacted. Prior identification of link
problems enables a host to service an application via
“fail over” to a redundant link or replace a suspect device, maintaining system uptime in the process. For applications where ultra-high system uptime is required, a
digital SFP provides a means to monitor two real-time
laser metrics associated with laser degradation and predicting failure: average laser bias current (Tx_Bias) and
average laser optical power (Tx_Power).
2
OPTICAL INTERFACE
ELECTRICAL INTERFACE
RECEIVER
LIGHT FROM FIBER
AMPLIFICATION
& QUANTIZATION
PHOTO-DETECTOR
RD+ (RECEIVE DATA)
RD– (RECEIVE DATA)
RX_LOS
RS0
RS1
CONTROLLER & MEMORY
SDA
SCL
MOD-ABS
TRANSMITTER
LIGHT TO FIBER
VCSEL
TX_DISABLE
LASER
DRIVER &
SAFETY
CIRCUITRY
TD+ (TRANSMIT DATA)
TD– (TRANSMIT DATA)
TX_FAULT
Figure 1. Transceiver functional diagram
Transmitter Section
Transmit Fault (TX_FAULT)
The transmitter section includes the Transmitter Optical
Sub-Assembly (TOSA) and laser driver circuitry. The
TOSA, containing an Avago designed and manufactured
1310 nm DFB light source, is located at the optical interface and mates with the LC optical connector. The TOSA
is driven by an IC which uses the incoming differential
high speed logic signal to modulate the laser diode
driver current. This Tx laser driver circuit regulates the
optical power at a level within the specified range.
A catastrophic laser fault will activate the transmitter
signal, TX_FAULT, and disable the laser. This signal is
an open collector output (pull-up required on the host
board). A low signal indicates normal laser operation and
a high signal indicates a fault. A fault is defined as laser
power below or above the specified IEEE 802.3ae specified min/max range. The TX_FAULT will be latched high
when a laser fault occurs and is cleared by toggling the
TX_DISABLE input or power cycling the transceiver. The
transmitter fault condition can also be monitored via the
two-wire serial interface (address A2, byte 110, bit 2).
Transmit Disable (TX_DISABLE)
The AFCT-701SDDZ accepts an LVTTL compatible transmit disable control signal input which shuts down the
transmitter optical output. A high signal implements
this function while a low signal allows normal transceiver
operation. In the event of a fault (e.g. eye safety circuit
activated), cycling this control signal resets the module
as depicted in Figure 5. An internal pull up resistor disables the transceiver transmitter until the host pulls the
input low. TX_DISABLE can also be asserted via the twowire interface (address A2h, byte 110, bit 6) and monitored (address A2h, byte 110, bit 7).
The contents of A2h, byte 110, bit 6 are logic OR’d with
hardware TX_DISABLE (contact 3) to control transmitter
operation. The normal behavior of this feature is to reset
a TX disabled transceiver to TX enabled when it is power
cycled or hot-plugged.
3
Receiver Section
Caution
The receiver section includes the Receiver Optical SubAssembly (ROSA) and the amplification/quantization
circuitry. The ROSA, containing a PIN photodiode and
custom transimpedance amplifier, is located at the optical interface and mates with the LC optical connector.
The ROSA output is fed to a custom IC that provides
post-amplification and quantization.
The post-amp IC also includes transition detection circuitry which monitors the AC level of incoming optical
signals and provides a LVTTL/CMOS compatible status
signal to the host. A high status signal indicates loss of
modulated signal, indicating link failures such as broken
fiber or failed transmitter. Rx_LOS can also be monitored
via the two-wire serial interface (address A2h, byte 110,
bit 1).
There are no user serviceable parts nor maintenance
requirements for the AFCT-701SDDZ. All mechanical
adjustments are made at the factory prior to shipment.
Tampering with, modifying, misusing or improperly handling the AFCT-701SDDZ will void the product warranty.
It may also result in improper operation and possibly
overstress the laser source. Performance degradation or
device failure may result. Connection of the AFCT-701
SDDZ to a light source not compliant with IEEE Std.
802.3ae Clause 52 and SFF-8341 specifications, operating above maximum operating conditions or in a manner inconsistent with it’s design and function may result
in exposure to hazardous light radiation and may constitute an act of modifying or manufacturing a laser product. Persons performing such an act are required by law
to recertify and re-identify the laser product under the
provisions of U.S. 21 CFR (Subchapter J) and TUV.
Functional Data I/O
Customer Manufacturing Processes
The AFCT-701SDDZ interfaces with the host circuit board
through the twenty contact SFP+ electrical connector.
See Table 2 for contact descriptions. The module edge
connector is shown in Figure 3.
This module is pluggable and is not designed for aqueous wash, IR reflow, or wave soldering processes.
Receiver Loss of Signal (Rx_LOS)
The AFCT-701SDDZ high speed transmit and receive interfaces require SFF-8431 compliant signal lines on the
host board. To simplify board requirements, biasing resistors and AC coupling capacitors are incorporated into
the SFP+ transceiver module (per SFF-8431) and hence
are not required on the host board. The TX_DISABLE,
TX_FAULT and RX_LOS signals require LVTTL signals on
the host board (per SFF-8431) if used. If an application
does not take advantage of these functions, care must
be taken to ground TX_DISABLE to enable normal operation.
Figure 2 depicts the recommended interface circuit to
link the AFCT-701SDDZ to supporting physical layer ICs.
Timing for the dedicated SFP+ control signals implemented in the transceiver is shown in Figure 5.
Application Support
An Evaluation Kit and Reference Designs are available to
assist in evaluation of the AFCT-701SDDZ. Please contact
your local Field Sales representative for availability and
ordering details.
4
Ordering Information
Please contact your local field sales engineer or one of
Avago Technologies franchised distributors for ordering information. For technical information, please visit
Avago Technologies’ WEB page at www.avagotech.com.
For information related to SFF Committee documentation visit www.sffcommittee.org.
Regulatory Compliance
Electromagnetic Interference (EMI)
The AFCT-701SDDZ complies with all applicable laws
and regulations as detailed in Table 1. Certification level
is dependent on the overall configuration of the host
equipment. The transceiver performance is offered as a
figure of merit to assist the designer.
Equipment incorporating 10 gigabit transceivers is
typically subject to regulation by the FCC in the United
States, CENELEC EN55022 (CISPR 22) in Europe and VCCI
in Japan. The AFCT-701SDDZ enables equipment compliance to these standards detailed in Table 1. The metal
housing and shielded design of the AFCT-701SDDZ minimizes the EMI challenge facing the equipment designer.
For superior EMI performance it is recommended that
equipment designs utilize SFP+ cages per SFF 8432.
Electrostatic Discharge (ESD)
The AFCT-701SDDZ is compatible with ESD levels found
in typical manufacturing and operating environments
as described in Table 1. In the normal handling and
operation of optical transceivers, ESD is of concern in
two circumstances.
The first case is during handling of the transceiver prior to insertion into an SFP compliant cage. To protect
the device, it’s important to use normal ESD handling
pre-cautions. These include use of grounded wrist
straps, work-benches and floor wherever a transceiver is
handled.
The second case to consider is static discharges to the
exterior of the host equipment chassis after installation.
If the optical interface is exposed to the exterior of host
equipment cabinet, the transceiver may be subject to
system level ESD requirements.
RF Immunity (Susceptibility)
Due to its shielded design, the EMI immunity of the
AFCT-701SDDZ exceeds typical industry standards.
Eye Safety
The AFCT-701SDDZ provides Class 1 (single fault
tolerant) eye safety by design and has been tested for
compliance with the requirements listed in Table 1. The
eye safety circuit continuously monitors the optical
output power level and will disable the transmitter upon
detecting a condition beyond the scope of Class 1 certification Such conditions can be due to inputs from the
host board (Vcc fluctuation, unbalanced code) or a fault
within the transceiver. US CDRH and EU TUV certificates
are listed in table 1.
Flammability
The AFCT-701SDDZ optical transceiver is made of metal
and high strength, heat resistant, chemical resistant and
UL 94V-0 flame retardant plastic.
5
Table 1. Regulatory Compliance
Feature
Test Method
Performance
Electrostatic Discharge (ESD)
to the Electrical Contacts
MIL-STD883C Method 3015.4
JEDEC DESD22-A11-4-B
Class 1 (> 1KV) for high speed I/O pins
Class 1 (> 2KV) for all other pins
Electrostatic Discharge (ESD)
to the Duplex LC Receptacle
IEC 61000-4-2
Typically, no damage occurs with 25 kV when
the duplex LC connector receptacle is
contacted by a Human Body Model probe.
Life Traffic ESD Immunity
IEC 61000-4-2
10 contacts of 8 kV on the electrical faceplate
with device inserted into a panel.
Life Traffic ESD Immunity
IEC 61000-4-2
Air discharge of 15 kV (min.) contact to
connector without damage.
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC EN55022 Class B
(CISPR 22A)
VCCI Class 1
System margins are dependent on customer
board and chassis design.
RF Immunity
IEC 61000-4-3
Typically shows no measurable effect from a 10
V/m field swept from 80MHz to 1 GHz
Laser Eye Safety and
Equipment Type Testing
US FDA CDRH AEL Class 1
US21 CFR, Subchapter J per
Paragraphs 1002.10 and 1002.12
CDRH Accession No. 9521220-158
Pending Completion
BAUART
¨
GEPRUFT
¨
TUV
Rheinland
Product Safety
TYPE
APPROVED
(IEC) EN60825-1: 1994 + A11 + A2
(IEC) EN60825-2: 1994 + A1
(IEC) EN60950: 1992 + A1 + A2 + A3
+ A4 + A11
Component Recognition
Underwriters Laboratories and Canadian
Standards Association Joint Component
Recognition for Information Technology
Equipment including Electrical Business
Equipment
UL file E173874
RoHS Compliance
RoHS Directive 2002/95/EC and
it’s amendment directives 6/6
SGS Test Report No. LPC1/00895/08
CTS ref. CTS/08-0238/Avago
6
VccT
VeeT
10 kΩ
TX_DISABLE
TX_DISABLE
TX_FAULT
TX_FAULT
TD+
0.1 μF
100 Ω
TD–
0.1 μF
4.7 k to 10 kΩ
4.7uH
Host
Vcc
0 .1μF
DCR=0.15
22μF
LASER DRIVER
VccT
0 .1μF
0.5Ω
PROTOCOL IC
SERDES IC
VccR
4.7uH
.
0 .1μF
4.7 k to
10 kΩ
DCR=0.15
22μF
VccR
VccR
0 .1μF
.
50 Ω
0.5Ω
50 Ω
0.1 μF
RD+
100 Ω
RD–
0.1 μF
RX_LOS
LOSS OF SIGNAL
RS0
RS1
VccHost
VccHTWI
VeeR
4.7 k to 10 kΩ
MODULE DETECT
SCL
SDA
Figure 2. Typical application configuration
7
1.1 k to 8 kΩ
POST AMPLIFIER
1.1 k to 8 kΩ
MOD_ABS
SCL
SDA
Table 2. Contact Description
Contact Symbol
Function/Description
Notes
1
VeeT
Transmitter Signal Ground
Note 1
2
TX_FAULT
Transmitter Fault (LVTTL-O) – High indicates a fault condition
Note 2
3
TX_DISABLE
Transmitter Disable (LVTTL-I) – High or open disables the transmitter
Note 3
4
SDA
Two Wire Serial Interface Data Line (LVCMOS – I/O)
(same as MOD-DEF2 in INF-8074)
Note 4
Two Wire Serial Interface Clock Line (LVCMOS – I/O)
(same as MOD-DEF1 in INF-8074)
Note 4
5
SCL
6
MOD_ABS
Module Absent (Output), connected to VeeT or VeeR in the module
Note 5
7
RS0
Rate Select 0 - RS0=Lo for 1000BASE-LX, RS0=Hi for 10GBASE-LR
Note 6
8
RX_LOS
Receiver Loss of Signal (LVTTL-O)
Note 2
9
RS1
Rate Select 1 - RS1=Lo for 1000BASE-LX, RS1=Hi for 10GBASE-LR
Note 6
10
VeeR
Receiver Signal Ground
Note 1
11
VeeR
Receiver Signal Ground
Note 1
12
RD-
Receiver Data Out Inverted (CML-O)
13
RD+
Receiver Data Out (CML-O)
14
VeeR
Receiver Signal Ground
15
VccR
Receiver Power + 3.3 V
16
VccT
Transmitter Power + 3.3 V
17
VeeT
Transmitter Signal Ground
18
TD+
Transmitter Data In (CML-I)
19
TD-
Transmitter Data In Inverted (CML-I)
20
VeeT
Transmitter Signal Ground
Notes:
1. The module signal grounds are isolated from the module case.
2. This is an open collector/drain output that on the host board requires a 4.7 k: to 10 k: pullup resistor to VccHost. See Figure 2.
3. This input is internally biased high with a 4.7 k: to 10 k: pullup resistor to VccT.
4. Two-Wire Serial interface clock and data lines require an external pullup resistor dependent on the capacitance load.
5. This is a ground return that on the host board requires a 4.7 k: to 10 k: pullup resistor to VccHost.
6. Refer to the Appendix for detailed operation of RS0 and RS1.
10
11
BOTTOM OF
BOARD AS
VIEWED FROM
TOP THROUGH
BOARD
TOWARD
HOST
1
Figure 3. Module edge connector contacts
8
TOP VIEW
OF BOARD
20
Note 1
Note 1
Table 3. Absolute Maximum Ratings
Stress in excess of any of the individual Absolute Maximum Ratings can cause immediate catastrophic damage to the
module even if all other parameters are within Recommended Operating Conditions. It should not be assumed that
limiting values of more than one parameter can be applied concurrently. Exposure to any of the Absolute Maximum
Ratings for extended periods can adversely affect reliability.
Parameter
Symbol
Minimum
Maximum
Unit
Storage Temperature
TS
-40
100
C
Case Operating Temperature
TC
-40
100
C
Relative Humidity
RH
5
95
%
Supply Voltage
VccT, VccR
-0.3
3.8
V
-0.5
Vcc+0.5
V
Low Speed Input Voltage
Two-Wire Interface Input Voltage
-0.5
Vcc+0.5
V
High Speed Input Voltage, Single Ended
-0.3
Vcc+0.5
V
2.5
V
20
mA
1.5
dBm
High Speed Input Voltage, Differential
Low Speed Output Current
-20
Optical Receiver Input Average Power
Notes
Note 1
Note:
1. The module supply voltages, VccT and VccR must not differ by more than 0.5 V or damage to the device may occur.
Table 4. Recommended Operating Conditions
Recommended Operating Conditions specify parameters for which the electrical and optical characteristics hold unless otherwise noted. Optical and electrical charactristics are not defined for operation outside the Recommended
Operating Conditions, reliability is not implied and damage to the module may occur for such operation over an
extended period of time.
Parameter
Symbol
Minimum
Maximum
Unit
Notes
Case Operating Temperature
TC
0
70
°C
Note 1
Module Supply Voltage
VccT, VccR
3.135
3.465
V
10.311
10.313
GBd
Note 3
66
mVp-p
Note 2
Signal Rate
1000BASE-LX (1.25GBd Typical)
Power Supply Noise Tolerance
including Ripple
Tx Input Single Ended DC
Voltage Tolerance (Ref VeeT)
V
-0.3
4.0
V
Rx Output Single Ended Voltage Tolerance
V
-0.3
4.0
V
Notes:
1. Ambient operating temperature limits are based on the Case Operating Temperature limits and are subject to the host system thermal design.
See Figure 6 for the module Tc reference point.
2. The Power Supply Filter (PSF) and resulting Power Supply Noise Tolerance (PSNT) are specified in the SFF 8431 MSA. The PSNT value applies over
the range from 10Hz to 10MHz.
3. For 10GBASE-LR
9
Table 5. Low Speed Signal Electrical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Typical values are for Tc = 40°C. VccT and VccR = 3.3 V.
Parameter
Symbol
Module Supply Current
Typical
Maximum
Unit
Notes
ICC
258
289
mA
Note 1
Power Dissipation
PDISS
850
1000
mW
TX_FAULT, RX_LOS
IOH
- 50
+ 37.5
PA
VOL
- 0.3
0.4
V
VIH
2.0
VccT + 0.3
V
VIL
-0.3
0.8
V
TX_DISABLE
Minimum
Note 2
Note 3
Notes:
1. Supply current includes both VccT and VccR connections.
2. Measured with a 4.7 k: load to VccHost.
3. TX_DISABLE has an internal 4.7 k: to 10 k: pull-up to VccT
Table 6. High Speed Signal Electrical Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
Symbol
Minimum
Tx Input Differential Voltage, |(TD +) - (TD-)|
VI
180
Tx Input AC Common Mode Voltage Tolerance
Typical
Maximum
Unit
Notes
700
mV
Note 1
15
mV(RMS)
Tx Input Differential S-parameter (100 : Ref.)
SDD11
Note 3
dB
0.01-11.1 GHz
Tx Input Reflected Differential to
Common Mode Conversion (25 : Ref.)
SCD11
-10
dB
0.01-11.1 GHz
Rx Output Differential Voltage, |(RD +) - (RD-)|
Vo
850
mV
Note 2
Rx Output Termination Mismatch @ 1MHz
'Zm
5
%
7.5
mV(RMS)
300
Rx Output AC Common Mode Voltage
28
Note 5
Rx Output Output Rise and Fall Time
(20% to 80%)
tr, tf
ps
Rx Output Total Jitter
TJ
0.70
0.332
Ulp-p
UIp-p
Rx Output 99% Jitter
DJ
0.42
Ulp-p
Rx Output Differential S-parameter (100 : Ref.)
SDD22
Note 4
dB
0.01-11.1 GHz
Rx Output Common Mode Reflection
Coefficient (25 : Ref.)
SCC22
-6
-3
dB
dB
0.01-2.5 GHz
2.5-11.1 GHz
Receiver Output Eye Mask
Notes:
1. Internally AC coupled and terminated (100 Ohm differential).
2. Internally AC coupled but requires an external load termination (100 Ohm differential).
3. Reflection Coefficient given by equation SDD11(dB)=Max(-12 + 2*SQRT(f ) -6.3+13Log10(f/5.5)), with f in GHz.
4. Differential Output S-parameter given by equation SDD22(dB)= Max(-12 + 2*SQRT(f ) -6.3+13Log10(f/5.5)), with f in GHz.
5. The RMS value is measured by calculating the standard deviation of the histogram for one UI of the common mode signal.
6. TJ conditions per SFF-8431
10
Note 6, 10GBd
1.25GBd
See Figure 4a
1.40
1.0
NORMALIZED AMPLITUDE
ABSOLUTE AMPLITUDE - mV
425
150
0
-150
0.75
0.73
0.5
0.28
0.25
0
-425
-0.40
0.35
0
0
1.0
0.65
NORMALIZED TIME (UNIT INTERVAL)
Figure 4a. 10GBd Receiver Electrical Optical Eye Mask Definition
0.25 0.40 0.45 0.55 0.60 0.75
1
NORMALIZED TIME (UNIT INTERVAL)
Figure 4b. 10GBd Transmitter Optical Eye Mask Definition
Table 7. Two-Wire Interface Electrical Characteristics
Parameter
Symbol
Minimum
Maximum
Unit
Host Vcc Range
VccHTWI
3.135
3.465
V
SCL and SDA
VOL
0.0
0.40
V
VOH
VccHTWI - 0.5
VccHTWI + 0.3
V
VIL
-0.3
VccT*0.3
V
VIH
VccT*0.7
VccT + 0.5
V
Input Current on the
SCL and SDA Contacts
Il
-10
10
μA
Capacitance on SCL
and SDA Contacts
Ci[2]
14
pF
Total bus capacitance
for SCL and for SDA
Cb[3]
100
pF
At 400 kHz, 3.0 k: Rp, max
At 100 kHz, 8.0 k: Rp, max
290
pF
At 400 kHz, 1.1 k:Rp, max
At 100 kHz, 2.75 k: Rp, max
SCL and SDA
Conditions
Rp[1] pulled to VccHTWI,
measured at host side of
connector
Notes:
1. Rp is the pull up resistor. Active bus termination may be used by the host in place of a pullup resistor. Pull ups can be connected to various
power supplies, however the host board design shall ensure that no module contact has voltage exceeding VccT or VccR by 0.5 V nor requires
the module to sink more than 3.0 mA current.
2. Ci is the capacitance looking into the module SCL and SDA contacts
3. Cb is the total bus capacitance on the SCL or SDA bus.
11
Table 8a. Optical Specifications
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
Minimum
Typical
Maximum
Units
Notes
dBm
1
0.5
dBm
1
-30
dBm
1
dB
1
3.2
dB
1
1355
nm
Transmitter
Laser OMA output power
-5.2
Laser mean output power
-8.2
Laser off power
Extinction ratio
3.5
Transmitter and dispersion penalty (TDP)
Center Wavelength
1260
Side Mode Suppression Ratio - SMSR
30
dB
RIN12OMA
-128
dB/Hz
1
Optical Return Loss Tolerance
12
dB
1
Transmitter Output Eye Mask
1, See Figure 4b
Receiver
Stressed sensitivity (OMA)
-10.3
dBm
Receive sensitivity (OMA)
-12.6
dBm
Receive Power (Pave) Overload
0.5
dBm
1, 2
1
Receive Electrical 3dB Upper Cutoff Frequency
12.3
GHz
Reflectance
-12
dB
1
1355
nm
1
-17
dBm
3
3
Center Wavelength
1260
RX_LOS (OMA) De-Assert
RX_LOS (OMA) Assert
-30
dBm
RX_LOS (OMA) Hysteresis
0.5
dB
Vertical eye closure penalty
2.2
dB
2
Stressed eye jitter
0.3
UI p-p
2
General Specification Considerations (Notes):
1. IEEE 802.3ae Clause 52 compliant.
2. Vertical eye closure and stressed eye jitter are test conditions for stressed sensitivity (OMA) measurements
3. Loss of Signal (LOS) detection responds only to OMA and the indicator will respond unpredictably with the application of unmodulated optical
power.
12
Table 8b. 1.25GBd Optical Characteristics
Parameter
Symbol
Minimum
Output Optical Power (Average)
Pout
-9.5
Optical Extinction Ratio
ER
9
Total Jitter
(TP1 to TP2 Contribution)
TJ
Typical
Maximum
Unit
-3
dBm
Transmitter
dB
227
ps
0.284
UI
1355
nm
RMS Spectral Width
4
nm
Laser Off Power
-30
dBm
RIN (max)
-120
dB/Hz
Receiver Sensitivity
(Average Optical Input Power)
-19
dBm
Stressed Receiver Sensitivity
-14.4
dBm
266
ps
0.332
UI
Center Wavelength
1260
Receiver
Total Jitter
(TP3 to TP4 Contributed 1.25GBd)
TJ
Average Receive Power (max)
-3
Return Loss (min)
dBm
12
dB
LOS De-Assert
PD
-20
LOS Assert
PA
-30
dBm
Hysteresis
PD-PA
0.5
dB
Receive Electrical 3dB Upper Cutoff Frequency
Wavelength
13
2.5
1260
dBm
4
GHz
1355
nm
Notes
Table 9. Control Functions: Low Speed Signals Timing Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
Symbol
Maximum
Unit
Notes
TX_DISABLE Assert Time
t_off
Minimum
100
Ps
Note 1 , Fig. 5
TX_DISABLE Negate Time
t_on
2
ms
Note 2 , Fig. 5
Time to initialize, including reset of TX_FAULT
t_init
300
ms
Note 3 , Fig. 5
TX_FAULT Assert Time
t_fault
1000
Ps
Note 4 , Fig. 5
TX_DISABLE to Reset
t_reset
Ps
Note 5 , Fig. 5
10
RX_LOS Assert Time
t_los_on
100
Ps
Note 6 , Fig. 5
RX_LOS Deassert Time
t_los_off
100
Ps
Note 7 , Fig. 5
Rate Select Time
t_rate
40
ms
Notes:
1. Time from rising edge of TX_DISABLE to when the optical output falls below 10% of nominal. A 10 ms interval between assertions of
TX_DISABLE is required.
2. Time from falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal.
3. Time from power on or falling edge of TX_DISABLE to when the modulated optical output rises above 90% of nominal and the Two-Wire
interface is available.
4. From power on or negation of TX_FAULT using TX_DISABLE.
5. Time TX_DISABLE must be held high to reset the laser fault shutdown circuitry.
6. Time from loss of optical signal to Rx_LOS Assertion.
7. Time from valid optical signal to Rx_LOS De-Assertion.
Table 10. Control Functions: Two-Wire Interface Timing Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
Symbol
TX_DISABLE Assert Time
TX_DISABLE Negate Time
TX_FAULT Assert Time
Minimum
Maximum
Unit
Notes
t_off_twi
100
ms
Note 1
t_on_twi
100
ms
Note 2
t_fault_twi
100
ms
Note 3
Rx_LOS Assert Time
t_loss_on_twi
100
ms
Note 4
Rx_LOS Deassert Time
t_loss_off_twi
100
ms
Note 5
Analog parameter data ready
t_data
1000
ms
Note 6
Two-Wire Interface Ready
t_serial
300
ms
Note 7
Complete Single or Sequential Write up to 4 Byte
t_write
40
ms
Note 8
Complete Sequential Write of 5-8 Byte
t_write
80
ms
Note 8
Two-Wire Interface Clock Rate
f_serial_clock
400
kHz
Note 8
Time bus free before new
transmission can start
t_buf
Ps
Note 9
20
Notes:
1. Time from two-wire interface assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the optical output falls below 10% of nominal. Measured
from falling clock edge after stop bit of write transaction.
2. Time from two-wire interface de-assertion of TX_DISABLE (A2h, byte 110, bit 6) to when the modulated optical output rises above 90% of
nominal.
3. Time from fault to two-wire interface TX_FAULT (A2h, byte 110, bit 2) asserted.
4. Time for two-wire interface assertion of Rx_LOS (A2h, byte 110, bit 1) from loss of optical signal.
5. Time for two-wire interface de-assertion of Rx_LOS (A2h, byte 110, bit 1) from presence of valid optical signal.
6. From power on to data ready bit asserted (A2h, byte 110, bit 0). Data ready indicates analog monitoring circuitry is functional.
7. Time from power on until module is ready for data transmission over the two-wire interface (reads or writes over A0h and A2h).
8. Operation of the Two Wire Serial Interface at rtes beyond 100kHz requires the use of clock stretching techniques.
9. Between STOP and START. See SFF 8431 Section 4.3
14
Table 11. Transceiver Digital Diagnostic Monitor (Real Time Sense) Characteristics
The following characteristics are defined over the Recommended Operating Conditions unless otherwise noted.
Parameter
Symbol
Min.
Units
Notes
Transceiver Internal Temperature
TINT
±3.0
°C
Temperature is measured internal to the transceiver.
Valid from = -10°C to 85°C case temperature.
Transceiver Internal Supply
Voltage
VINT
±0.1
V
Supply voltage is measured internal to the transceiver
and can, with less accuracy, be correlated to
voltage at the VccT contact. Valid over 3.3 V ± 10%.
Transmitter Laser DC Bias Current
IINT
±10
%
IINT accuracy is better than ±10% of the nominal value.
Transmitted Average Optical
Output Power
PT
±3.0
dB
Average Power coupled into 9/125 μm single-mode
fiber. Valid from151 PW to 1120 PW.
Received Average Optical Input
Power
PR
±3.0
dB
Average Power coupled from 9/125 μm single-mode
fiber. Valid from 25 PW to 1120 PW.
VCCT, VCCR > 2.97 V
VCCT, VCCR > 2.97 V
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_init
t_init
t-init: TX DISABLE NEGATED
t-init: TX DISABLE ASSERTED
VCCT, VCCR > 2.97 V
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
INSERTION
t_off
t_init
t-init: TX DISABLE NEGATED, MODULE HOT PLUGGED
t_on
t-off & t-on: TX DISABLE ASSERTED THEN NEGATED
OCCURANCE OF FAULT
OCCURANCE OF FAULT
TX_FAULT
TX_FAULT
TX_DISABLE
TX_DISABLE
TRANSMITTED SIGNAL
TRANSMITTED SIGNAL
t_fault
* SFP SHALL CLEAR TX_FAULT IN
< t_init IF THE FAILURE IS TRANSIENT
t-fault: TX FAULT OCCURED
t_reset
t_init*
t-reset: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL RECOVERED
OCCURANCE OF FAULT
TX_FAULT
LOS
TRANSMITTED SIGNAL
* SFP SHALL CLEAR TX_FAULT IN
< t_init IF THE FAILURE IS TRANSIENT
t_reset
t_fault
t_loss_on
t_init*
t-fault: TX DISABLE ASSERTED THEN NEGATED, TX SIGNAL NOT RECOVERED
t-los-on & t-los-off
Figure 5. Transceiver timing diagrams (module installed and power applied except where noted)
15
OCCURANCE
OF LOSS
OPTICAL SIGNAL
TX_DISABLE
t_loss_off
Table 12. EEPROM Serial ID Memory Contents – Conventional SFP Memory (Address A0h)
Byte #
Decimal
Data
Hex
Notes
Byte #
Decimal
Data
Hex
Notes
0
03
SFP physical device
37
00
Hex Byte of Vendor OUI[1]
1
04
SFP function defined by serial ID only
38
17
Hex Byte of Vendor OUI[1]
2
07
LC optical connector
39
6A
Hex Byte of Vendor OUI[1]
3
20
10GBASE-LR
40
41
“A” - Vendor Part Number ASCII character
4
00
41
46
“F” - Vendor Part Number ASCII character
5
00
6
02
7
42
43
“C” - Vendor Part Number ASCII character
43
54
“T” - Vendor Part Number ASCII character
00
44
2D
“-” - Vendor Part Number ASCII character
8
00
45
37
“7” - Vendor Part Number ASCII character
9
00
46
30
“0” - Vendor Part Number ASCII character
10
00
47
31
“1” - Vendor Part Number ASCII character
11
06
64B/66B
48
53
“S” - Vendor Part Number ASCII character
12
67
10312.5 Mbit/sec nominal bit rate (10.3125
Gbit/s)
49
44
“D” - Vendor Part Number ASCII character
13
00
Unspecified
50
44
“D” - Vendor Part Number ASCII character
14
0A
10GBASE-LR 10km
51
5A
“Z” - Vendor Part Number ASCII character
15
64
10GBASE-LR 10km
52
20
“ ” - Vendor Part Number ASCII character
16
00
53
20
“ ” - Vendor Part Number ASCII character
17
00
54
20
“ ” - Vendor Part Number ASCII character
18
00
55
20
“ ” - Vendor Part Number ASCII character
19
00
56
20
“ ” - Vendor Part Number ASCII character
20
41
“A” - Vendor Name ASCII character
57
20
“ ” - Vendor Part Number ASCII character
21
56
“V” - Vendor Name ASCII character
58
20
“ ” - Vendor Part Number ASCII character
22
41
“A” - Vendor Name ASCII character
59
20
“ ” - Vendor Part Number ASCII character
23
47
“G” - Vendor Name ASCII character
60
05
Hex Byte of Laser Wavelength[2]
24
4F
“O” - Vendor Name ASCII character
61
1E
Hex Byte of Laser Wavelength[2]
25
20
“ ” - Vendor Name ASCII character
62
00
26
20
“ ” - Vendor Name ASCII character
63
27
20
“ ” - Vendor Name ASCII character
64
00
Receiver limiting output. 1 Watt power
class.
28
20
“ ” - Vendor Name ASCII character
65
3A
Hardware SFP TX_DISABLE, TX_FAULT,
RX_LOS & RATE_SELECT
29
20
“ ” - Vendor Name ASCII character
66
00
30
20
“ ” - Vendor Name ASCII character
67
00
31
20
“ ” - Vendor Name ASCII character
68-83
Vendor Serial Number ASCII characters[4]
32
20
“ ” - Vendor Name ASCII character
84-91
Vendor Date Code ASCII characters[5]
1000BASE-LX
Checksum for Bytes 0-62[3]
33
20
“ ” - Vendor Name ASCII character
92
68
Digital Diagnostics, Internal Cal, Rx Pwr Avg
34
20
“ ” - Vendor Name ASCII character
93
FA
A/W, Soft SFP TX_DISABLE, TX_FAULT,
RX_LOS, & RATE_SELECT
35
20
“ ” - Vendor Name ASCII character
94
03
SFF-8472 Compliance to revision 10.2
36
00
Checksum for Bytes 64-94[3]
95
96 - 255
00
Notes:
1. The IEEE Organizationally Unique Identifier (OUI) assigned to Avago Technologies is 00-17-6A (3 bytes of hex)..
2. Laser wavelength is represented in 16 unsigned bits.
3. Addresses 63 and 95 are checksums calculated (per SFF-8472) and stored prior to product shipment.
4. Addresses 68-83 specify the AFCT-701SDDZ ASCII serial number and will vary on a per unit basis.
5. Addresses 84-91 specify the AFCT-701SDDZ ASCII date code and will vary on a per date code basis.
16
Table 13. EEPROM Serial ID Memory Contents – Enhanced Feature Set Memory (Address A2h)
Byte #
Decimal
Notes
Byte #
Decimal
Notes
Byte #
Decimal
Notes
0
Temp H Alarm MSB[1]
26
Tx Pwr L Alarm MSB[4]
104
Real Time Rx Pwr MSB[5]
1
Temp H Alarm LSB[1]
27
Tx Pwr L Alarm LSB[4]
105
Real Time Rx Pwr LSB[5]
2
Temp L Alarm MSB[1]
28
Tx Pwr H Warning MSB[4]
106
Reserved
3
Temp L Alarm LSB[1]
29
Tx Pwr H Warning LSB[4]
107
Reserved
4
Temp H Warning MSB[1]
30
Tx Pwr L Warning MSB[4]
108
Reserved
5
Temp H Warning LSB[1]
31
Tx Pwr L Warning LSB[4]
109
Reserved
6
Temp L Warning MSB[1]
32
Rx Pwr H Alarm MSB[5]
110
Status/Control
- See Table 14
7
Temp L Warning LSB[1]
33
Rx Pwr H Alarm LSB[5]
111
Reserved
8
Vcc H Alarm MSB[2]
34
Rx Pwr L Alarm MSB[5]
112
Flag Bits - See Table 15
9
Vcc H Alarm LSB[2]
35
Rx Pwr L Alarm LSB[5]
113
Flag Bits - See Table 15
10
Vcc L Alarm MSB[2]
36
Rx Pwr H Warning MSB[5]
114
Reserved
11
Vcc L Alarm LSB[2]
37
Rx Pwr H Warning LSB[5]
115
Reserved
12
Vcc H Warning MSB[2]
38
Rx Pwr L Warning MSB[5]
116
Flag Bits - See Table 15
13
Vcc H Warning LSB[2]
39
Rx Pwr L Warning LSB[5]
117
Flag Bits - See Table 15
14
Vcc L Warning MSB[2]
40-55
Reserved
118
Extended Control/Status
byte. See Table 16
15
Vcc L Warning LSB[2]
56-94
External Calibration Constants[6]
119-127
Reserved
16
Tx Bias H Alarm MSB[3]
95
Checksum for Bytes 0-94[7]
128-247
Customer Writeable
17
Tx Bias H Alarm LSB[3]
96
Real Time Temperature MSB[1]
248-255
Vendor Specific
18
Tx Bias L Alarm MSB[3]
97
Real Time Temperature LSB[1]
19
Tx Bias L Alarm LSB[3]
98
Real Time Vcc MSB[2]
20
Tx Bias H Warning MSB[3]
99
Real Time Vcc LS[2]
21
Tx Bias H Warning LSB[3]
100
Real Time Tx Bias MSB[3]
22
Tx Bias L Warning MSB[3]
101
Real Time Tx Bias LSB[3]
23
Tx Bias L Warning LSB[3]
102
Real Time Tx Power MSB[4]
24
Tx Pwr H Alarm MSB[4]
103
Real Time Tx Power LSB[4]
25
Tx Pwr H Alarm LSB[4]
Notes:
1. Temperature (Temp) is decoded as a 16 bit signed twos compliment integer in increments of 1/256°C.
2. Supply Voltage (Vcc) is decoded as a 16 bit unsigned integer in increments of 100 PV.
3. Laser bias current (Tx Bias) is decoded as a 16 bit unsigned integer in increments of 2 PA.
4. Transmitted average optical power (Tx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 PW.
5. Received average optical power (Rx Pwr) is decoded as a 16 bit unsigned integer in increments of 0.1 PW.
6. Bytes 56-94 are not intended for use with AFCT-701SDDZ, but have been set to default values per SFF-8472.
7. Byte 95 is a checksum calculated (per SFF-8472) and stored prior to product shipment.
17
Table 14. EEPROM Serial ID Memory Contents – Soft Commands (Address A2h, Byte 110)
Bit #
Status/
Control Name
Description
Notes
7
TX_ DISABLE State
Digital state of SFP TX_ DISABLE Input (1 = TX_DISABLE asserted)
Note 1
6
Soft TX_ DISABLE
Read/write bit for changing digital state of TX_DISABLE function
Note 1, 2
5
Reserved
4
Reserved
3
Soft RS0 Select
Read/write bit that allows software RX rate control.
Writing ‘1’ selects full speed RX operation. Power on default is logic zero/low.
This bit is OR’d with the hardware RS0 pin value (see Appendix).
2
TX_FAULT State
Digital state of the SFP TX_FAULT Output (1 = TX_FAULT asserted)
Note 1
1
RX_LOS State
Digital state of the SFP RX_LOS Output (1 = RX_LOS asserted)
Note 1
0
Data Ready (Bar)
Indicates transceiver is powered and real time sense data is ready. (0 = Ready)
Notes:
1. The response time for soft commands of the AFCT-701SDDZ is 100 msec as specified by SFF-8472.
2. Bit 6 is logic OR’d with the SFP TX_DISABLE input on contact 3; either asserted will disable the SFP+ transmitter.
Table 15. EEPROM Serial ID Memory Contents – Alarms and Warnings (Address A2h, Bytes 112, 113, 116, 117)
Byte
Bit
Flag Bit Name Description
112
7
Temp High Alarm
Set when transceiver internal temperature exceeds high alarm threshold
6
Temp Low Alarm
Set when transceiver internal temperature exceeds low alarm threshold
5
Vcc High Alarm
Set when transceiver internal supply voltage exceeds high alarm threshold
4
Vcc Low Alarm
Set when transceiver internal supply voltage exceeds low alarm threshold
3
Tx Bias High Alarm
Set when transceiver laser bias current exceeds high alarm threshold
2
Tx Bias Low Alarm
Set when transceiver laser bias current exceeds low alarm threshold
1
Tx Power High Alarm
Set when transmitted average optical power exceeds high alarm threshold
113
116
117
18
0
Tx Power Low Alarm
Set when transmitted average optical power exceeds low alarm threshold
7
Rx Power High Alarm
Set when received average optical power exceeds high alarm threshold
6
Rx Power Low Alarm
Set when received average optical power exceeds low alarm threshold
0-5
Reserved
7
Temp High Warning
Set when transceiver internal temperature exceeds high warning threshold
6
Temp Low Warning
Set when transceiver internal temperature exceeds low warning threshold
5
Vcc High Warning
Set when transceiver internal supply voltage exceeds high warning threshold
4
Vcc Low Warning
Set when transceiver internal supply voltage exceeds low warning threshold
3
Tx Bias High Warning
Set when transceiver laser bias current exceeds high warning threshold
2
Tx Bias Low Warning
Set when transceiver laser bias current exceeds low warning threshold
1
Tx Power High Warning
Set when transmitted average optical power exceeds high warning threshold
0
Tx Power Low Warning
Set when transmitted average optical power exceeds low warning threshold
7
Rx Power High Warning
Set when received average optical power exceeds high warning threshold
6
Rx Power Low Warning
Set when received average optical power exceeds low warning threshold
0-5
Reserved
Table 16. EEPROM Serial ID Memory Contents - Extended Control/Status (Address A2h, Byte 118)
Bit #
Status/
Control Name
Description
Notes
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Soft RS1 Select
Read/write bit that allows software Tx rate control. Writing '1' selects full speed
Tx operation. Power on default is logic zero/low. This bit is OR'd with the hardware RS1 pin value (see Appendix).
1
2
Reserved
1
Class2 Operation State
Value=0. Power class2 operation is not active.
0
Power Class Select
Has no effect.
Notes:
1. The response time for soft commands of the AFCT-701SDDZ is 100ms as specified by SFF-8472.
9.7
TCASE REFERENCE POINT
47.5
13.4 ±0.1
13.6
13.7
0.82 UNCOMPRESSED
12.27
8.5 ±0.1
LATCH COLOR
BLUE: 10GBASELR
0.69 UNCOMPRESSED
6.25
14.9 UNCOMPRESSED
TX
Figure 6. Module drawing
19
RX
Appendix: Rate Select Control
RX and TX rates can be independently controlled by either hardware input pins or via register writes. Module electrical input pins 7 and 9 are used to select RX and TX rate respectively. Status of each logic level is reflected to register
byte 110 bit 4 and 5 on address A2h as shown in the diagram below. RX and TX rates can also be controlled by register
writes to byte 110 bit 3 and 118 bit 3. Power on default of these bits are logic low. Hardware and software control
inputs are OR’d to allow flexible control.
RS0 RX Rate Select control flow
RS1 TX Rate Select control flow
Hardware
Input
Software
Input
Hardware
Input
Software
Input
RS0 (PIN7) Voltage
"1"...V>2.0
"0"...V<0.8
A2h, byte 110
Bit 3
RS1 (PIN9) Voltage
"1"...V>2.0
"0"...V<0.8
A2h, byte 118
Bit 3
A2h, byte 110
Bit 4
A2h, byte 110
Bit 5
OR
OR
RX Rate
Control
RS0 Control Input
TX Rate
Control
RS1 Control Input
Hardware
Software
RX
Operation
0
0
1.25G
0
0
1.25G
0
1
10G
0
1
10G
1
0
10G
1
0
10G
1
1
10G
1
1
10G
For product information and a complete list of distributors, please go to our website:
Hardware
Software
TX
Operation
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-1965EN - January 18, 2011