ASAHI KASEI [AK2500B] AK2500B DS3/STS-1 Analog Line Receiver GENERAL DESCRIPTION FEATURE The AK2500B is a DSP based line receiver. It provides the analog receive line interface functions for a 44.736 MHz DS3 or 51.84 MHz STS-1 interface. The device operates from a single +3.3 Volt supply and is transparent to the framing format. - “Robust” DSP based line receiver - AK2500B Provides Complete Analog Line Receiver for DS3 and STS-1 Applications - Provides Line Equalization, and Clock and Data Recovery Functions APPLICATIONS PACKAGE - 24 pin SOP - Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX3 cross connect. - Interfacing customer premises equipment to a line. BLOCK DIAGRAM RLOL TREF BREF IREF EXCLK CLOCK RCLK RECOVERY RPDATA DATA GAIN and LINE RNDATA RECOVERY EQUALIZATION RIN VDDA VSSA LOS VDDD LOGIC VSSD VDDC VSSC LOSTHR MS0005-E-00 RLOS MODE2 -1- MODE1 RESET 1999/12 ASAHI KASEI [AK2500B] PIN LOCATION 24 PIN SOP Package IREF 1 24 MODE2 2 23 MODE1 RLOL 3 22 VSSA RIN 4 21 VSSA VDDA 5 20 VSSC VDDA 6 19 RPDATA RESET 7 18 RNDATA BREF 8 17 RCLK TREF 9 16 VDDC VSSA 10 15 VDDA VSSD 11 14 VDDD RLOS 12 13 EXCLK LOSTHR MS0005-E-00 AK2500B -2- 1999/12 ASAHI KASEI [AK2500B] PIN CONDITION No. Maximum AC load Minimum DC load Status on Reset Pin Name I/O Pin Type 1 IREF O Analog 2 LOSTHR I Analog 3 RLOL O CMOS 4 RIN I Analog Note 2 5 VDDA - 6 VDDA - 7 RESET I CMOS Note 3 8 BREF O Analog 9 TREF O Analog 10 VSSA - 11 VSSD - 12 RLOS O CMOS 13 EXCLK I CMOS 14 VDDD - 15 VDDA - 16 VDDC - 17 RCLK O 18 RNDATA 19 Remarks Note 1 15pF “H” 15pF “H” CMOS 15pF “L” O CMOS 15pF “L” RPDATA O CMOS 15pF “L” 20 VSSC - 21 VSSA - 22 VSSA - 23 MODE1 I Analog 24 MODE2 I Analog Note: 1)External resister 4.9 kohm is connected between IREF and VSS. 2)Input impedance of RIN is more than 5kohm. 3)Pulled up to VDD with internal register. (typical 50k ohm) MS0005-E-00 -3- 1999/12 ASAHI KASEI [AK2500B] PIN DESCRIPTION No. Pin Name I/O 1 IREF O 2 LOSTHR I 3 RLOL O 4 RIN I 5 VDDA - 6 VDDA - 7 RESET I 8 BREF O 9 TREF O 10 VSSA - 11 VSSD - 12 RLOS O 13 EXCLK I 14 VDDD - Ground for the digital part. 0 volts. Receive Loss-of-Signal. This pin is set high on loss of the incoming signal at RIN. External Reference Clock. A valid DS3 or STS-1 clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD/2 levels, must be 40% - 60%. The EXCLK frequency determines the operating frequency of the device. Power Supply for the digital part. +3.3 volts 15 VDDA - Power Supply for the analog part. +3.3 volts. 16 VDDC - Power Supply for the output buffer. +3.3 volts. 17 RCLK O Recovered Clock. 18 RNDATA O Receive Negative Data. 19 RPDATA O Receive Positive Data. 20 VSSC - Ground for the output buffer. 0 volts. 21 VSSA - 22 VSSA - 23 MODE1 I 24 MODE2 I MS0005-E-00 Function Current reference output determined by the external resister. External resistance 4.9 kohm(+/-1%) should be connected between this pin and VSSA. Loss of Signal Threshold Control The voltage forced on this pin controls the input loss-of-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD at LOSTHR (see Table 6). Receive PLL Loss-of-Lock Active High alarm. If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High. Receive Input Unbalanced analog receive input. The B3ZS receive signal is input to this pins. Data and clock are recovered and output on RPDATA, RNDATA and RCLK. Power Supply for the analog part. +3.3 volts. Active low RESET. Pulled up to VDD with internal resister. Bottom voltage reference level output. An external capacitor (0.1uF±20%) should be connected between this pin and VSSA. Top voltage reference level output. An external capacitor (0.1uF±20%) should be connected between this pin and VSSA. Ground for the analog part. 0 volts. Ground for the analog part. 0 volts. Mode Control. Equalizer enable/bypass mode, Test mode are selectable as shown in Table 4. -4- 1999/12 ASAHI KASEI [AK2500B] FUNCTIONAL DESCRIPTION The AK2500B provides the basic receiver functions of a high-speed line card as shown in Fig.7. The receiver extracts data and clock from a B3ZS coded signal and outputs clock and synchronized data. Signal Requirements Pulse characteristics are specified at the DSX-3. Table 1. DS3 Interface Specification Parameter Specification Line Rate 44.736Mbps±20ppm Line Code B3ZS Test Load 75Ω±5% Standards GR-499-CORE , ANSI T1-102 , T1.404 Table 2. STS-1 Interface Specification Parameter Specification Line Rate 51.840Mbps±20ppm Line Code B3ZS Test Load 75Ω±5% Standards GR-253-CORE , ANSI T1-102 Equalization The incoming data may have the loss of cable and/or flat. Cable type and length from the cross-connect are specified as shown in Table 3. Equalizer compensates appropriately for a nominal DSX-3/STS-1 pulse as attenuated by 0 - 450 feet of 728A cable. Table 3. DS3/STS-1 Cable Specification Parameter Specification Cable Type Type 728A coaxial cable (or equivalent) Cable Length 0 – 450 feet (from DSX-3 point) MS0005-E-00 -5- 1999/12 ASAHI KASEI [AK2500B] Equalizer Bypass If the incoming signal is attenuated by flat loss only (zero cable loss), the internal equalizer should be bypassed with MODE1=1, MODE2=1. (See Table 4) The level of the incoming signal should satisfy the RIN input range (50mVpk - 1000mVpk for DS3/STS-1). Table 4. Mode Control MODE2 (pin24) MODE1 (pin23) 0 0 OPEN 1 1 Function Equalizer Enable TEST MODE (Factory use only) Equalizer Bypass DSX-3 (1)Cable loss 0 - 450feet + Flat loss Cable Flat Loss 0 - 450feet 0 - 6dB AK2500B MODE2 MODE1 0 0 Equalizer enable Flat Loss (2)Flat loss only Transmitter Monitoring circuit AK2500B MODE2 MODE1 1 1 Equalizer bypass Fig. 1 AK2500B Application Clock Acquisition If a valid input signal is assumed to be already present at the analog input, the maximum time between the application of device power and error-free operation is typically 20 ms. Table 5. PLL Lock Acquisition Time (TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V) Power up Input data restore MS0005-E-00 Conditions Power : Off -> On Input data : Valid Power : On Input data : Loss -> Valid -6- min typ Max 20 1.0 Units ms 5.0 ms 1999/12 ASAHI KASEI [AK2500B] Output Jitter Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Jitter Transfer Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Jitter Tolerance Compliance with GR-499-CORE, GR-253-CORE, ITU-T G.752, G.824 Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Loss-of-Lock Detection If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High. External Reference Clock An external reference clock EXCLK is used to set the frequency of the PLL. The frequency of EXCLK should be within the ideal clock±100ppm. Reset AK2500B/01B goes into RESET status if RESET input is low. Output pins status is as follows during the low input on RESET . RLOS, RLOL : High RPDATA, RNDATA, RCLK : Low MS0005-E-00 -7- 1999/12 ASAHI KASEI [AK2500B] Loss of Signal This device detects the loss of signal by analog and digital methods. RLOS goes high if either the analog or digital loss has detected. Analog Loss of Signal(ALOS) Analog loss detector operates as follows. - Analog loss detector monitors the peak level of the incoming signal. - If the peak level falls below Alarm set threshold as shown in Table 6, output pins status is as follows. RLOS : High RPDATA: Low RNDATA: Low RCLK : Recovered from EXCLK Table 6. Analog Loss-of-Signal thresholds LOSTHR Clear Alarm Level Set Alarm Level Voltage Min. Upper Threshold Max. Upper Threshold Min. Lower Threshold Max. Lower Threshold Units GND 71 125 59 105 mV VDD/2 56 99 47 83 mV VDD 45 79 37 66 mV Notes: - Set Alarm Level is 0.5dB lower than Clear Alarm Level - Measured with PN20 pattern, 450ft cable loss, flat loss MS0005-E-00 -8- 1999/12 ASAHI KASEI [AK2500B] Digital Loss of Signal(DLOS) Digital loss detector operates as follows. - A digital loss detector monitors consecutive 0s and 1s density in recovered data. - RLOS is set high if 175±5 consecutive 0s is detected. - RPDATA,RNDATA are set low if ALOS is detected. - RLOS is set low if 33% 1s density (58 1s in 175 consecutive bits) and no consecutive 100 bits of 0s are detected. Normal Operation RCLK : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS : Low 175 +/- 5 bits of consecutive 0s in the incoming data DLOS RCLK 175bits of the incoming data includes the following data. 1) 58bits of 1s (33% 1s density) 2) No 100bits of consecutive 0s : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS Peak level of the incoming data : High Set Alarm Threshold < Level Peak level of the incoming data Clear Alarm Threshold > Level ALOS RCLK : Recovered from EXCLK RPDATA : Low RNDATA : Low RLOS : High Fig. 2 Loss of Signal state diagram MS0005-E-00 -9- 1999/12 ASAHI KASEI [AK2500B] ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units DC Supply (referenced to GND) (Note 1) V+ -0.3 4.6 V Input Voltage, Any Pin Vin GND-0.3 (V+)+0.3 V Input Current, Any Pin (Note 2) Iin - 10 mA Ambient Operating Temperature TA -40 85 °C Storage Temperature tstg -65 150 °C Power Dissipation PD - 1 W WARNING: Operation at or beyond these limits may result in permanent damage to the device. operation is not guaranteed at these extremes. Note; 1.GND=VSSA=VSSC=VSSD=0V 2.Transient currents of up to 100 mA will not cause SCR latch up. Normal RECOMMENDED OPERATING CONDITIONS Parameter DC Supply (referenced to GND) Ambient Operating Temperature Symbol Condition Min Typ Max Units V+ 3.0 3.3 3.6 V TA -40 25 85 °C - 95 100 105 110 mA mA 44.736 - 100ppm 44.736 44.736 + 100ppm MHz 51.84 - 100ppm 51.84 51.84 + 100ppm MHz Supply Current: DS3 STS-1 IS PN20 PN20 EXCLK Frequency DS3 STS-1 MS0005-E-00 - 10 - 1999/12 ASAHI KASEI [AK2500B] ANALOG SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V) Parameter Condition Jitter Transfer 3dB Bandwidth with repetitive 100 pattern (Note 4) Peaking Min Typ Max Units - 205 - kHz - 0.05 0.1 dB Jitter Tolerance 5kHz 10kHz 60kHz 300kHz 1MHz (Including cable loss) (Note 4, 5) 18 8 1.5 0.4 0.3 Signal Noise Immunity (Note 6) UIpp UIpp UIpp UIpp UIpp - 11 - dB - 1.4 - nsp-p - 1.8 - nsp-p Output Clock Duty Cycle (Note4) 45 - 55 % Receiver Input Range 50 - 1000 mVpk DLOS detection 170 175 180 bits 8 bits Output Jitter with Jitter-Free Input (Note4) All one's pattern Repetitive 1000 pattern RIN to RPDATA Delay Time Note; 4. Measured with repetitive input at nominal DSX-3 level with (V+)=3.3V, TA=25°C 5. Typical performance is shown in Fig. 3. 6. Measured with sinusoidal noise, peak amplitude of noise is 11dB down from peak amplitude of signal. The noise frequency is 22MHz±22kHz(DS3), 26MHz±26kHz(STS-1). 100 3.2k, 14UIpp G.752 GR-499 Category II Jitter Amplitude [UIpp] 10 AK2500B Typical performance GR-499 Category I 1 300k, 0.3UIpp 0.1 0.05UIpp 0.01 0.01 0.1 1 10 100 1000 10000 Jitter Frequency [kHz] Fig. 3 Jitter Tolerance(STS-1) MS0005-E-00 - 11 - 1999/12 ASAHI KASEI [AK2500B] DS3 SWITCHING SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ ) Parameter RCLK Pulse Width (Note 10, 11) EXCLK Duty Cycle (EXCLK Min Rise/Fall time : 5ns) Symbol Min Typ Max Units tpwh tpwl 10.1 10.1 11.177 11.177 12.2 12.2 ns ns tpwh1 40 - 60 % Rise Time, RCLK (Note 11) tr - - 3.5 ns Fall Time, RCLK (Note 11) tf - - 3.5 ns Delay time from RCLK rising to RDATA(Note 12) tdcrd 0 - 3.5 ns Setup time from RCLK falling to RDATA(Note 12) tscrd 5.0 - - ns Hold time from RCLK falling to RDATA(Note 12) thcrd 8.4 - - ns STS-1 SWITCHING SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ ) Parameter Symbol Min Typ Max RCLK Pulse Width tpwh tpwl 8.7 8.7 9.645 9.645 10.6 10.6 ns ns tpwh1/tpw 40 - 60 % (Note 11, 13) EXCLK Duty Cycle(EXCLK Min Rise/Fall time : 5ns) Units Rise Time, RCLK (Note 11) tr - - 3.5 ns Fall Time, RCLK (Note 11) tf - - 3.5 ns Delay time from RCLK rising to RDATA(Note 12) tdcrd 0 - 3.5 ns Setup time from RCLK falling to RDATA(Note 12) tscrd 5.0 - - ns Hold time from RCLK falling to RDATA(Note 12) thcrd 7.0 ns Note; 10. Assumes PLL is locked to 44.736 MHz signal. 11. The sum of the pulse widths must always meet the frequency specifications. 12. At max load of 10 pF. 13. Assumes PLL is locked to 51.84 MHz signal. DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; V+ = 3.3V±0.3V; GND = 0V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (Note 14) VIH (V+) x 0.7 - (V+) V Low-Level Input Voltage (Note 14) VIL GND - 0.5 V High-Level Output Voltage(Note 15,16) IOUT=-40uA VOH (V+) x 0.8 - (V+) V Low-Level Output Voltage IOUT=1.6mA (Note 15), 0.4mA (Note 16) VOL GND - 0.4 V ±10 uA Input Leakage Current (Note 17) Note; 14. Pins RESET 15. Pins RCLK, RPDATA, RNDATA MS0005-E-00 16. Pins RLOS, RLOL 17. Except RESET - 12 - 1999/12 ASAHI KASEI [AK2500B] tr tf 90% 90% 10% RCLK 10% Fig. 4 Signal Rise and Fall Characteristics t pwh RCLK t pwl t dcrd RPDATA RNDATA t scrd t hcrd Fig. 5 Recovered Clock and Data Switching Characteristics t pwh1 VDD/2 EXCLK t pw Fig. 6 EXCLK Duty Cycle Requirements MS0005-E-00 - 13 - 1999/12 ASAHI KASEI [AK2500B] Application Circuit Example 17 FRAMER B3ZS CODER/ DECODER 19 18 RCLK 0.01uF RIN RPDATA COAX 4 RNDATA 75ohm AK2500B CLOCK SOURCE 13 EXCLK VDDC VDDA CONTROL LOGIC 3 RLOL 12 RLOS VDDD 2 LOSTHR 24 MODE2 23 MODE1 7 VSSD VSSA RESET VSSC BREF TREF 8 9 0.1uF Fig. 7 16 3.3V 5, 6, 15 14 0.1uF 11 0.1uF 0.1uF 10, 21, 22 20 IREF 1 0.1uF 4.9kohm Application circuit example Board Layout Consideratons The recommended power supply de-coupling circuit is illustrated in Figure 7. Good quality high-frequency, low lead-inductance capacitors should be used. If the performance of Jitter Tolerance or S/X is not good, please try to use smaller de-coupling capacitors such as 0.01uF. These performances are affected by the power supply noise which depends on the customer’s board circuit and layout. All capacitors should be as close to the device as possible. MS0005-E-00 - 14 - 1999/12 ASAHI KASEI [AK2500B] Marking (1)Pin #1 indication (2)Date Code: 7digits XXXXYZZ (3)Marketing Code: AK2500B (4)Country of Origin: JAPAN (5)Asahi Kasei Logo AKM AK2500B XXXXYZZ JAPAN MS0005-E-00 - 15 - 1999/12 ASAHI KASEI [AK2500B] Outline Dimensions MS0005-E-00 - 16 - 1999/12 ASAHI KASEI [AK2500B] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0005-E-00 - 17 - 1999/12